MC9328MX21 MOTOROLA | Alldatasheet
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Technical content
© Freescale Semiconductor, Inc., 2004. All rights reserved. Freescale Semiconductor Product Preview This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. MC9328MX21/D Rev. 1.1, 09/29/2004 MC9328MX21
Package Information
(MAPBGA–289) Ordering Information: See Table 1 on page 4
1 Introduction
Freescales i.MX family of microprocessors has demonstrated leadership in the portable handheld market. Building on the success of the MX (Media Extensions) series, the i.MX21 (MC9328MX21) provides a leap in performance with an ARM926EJ-S microprocessor core that provides native security and accelerated Java support in addition to highly integrated system functions. The i.MX products specifically address the needs of the smartphone and portable product markets with their intelligent integrated peripherals, advanced processor core, and power management capabilities. The i.MX21 features the advanced and power-efficient ARM926EJ-S core operating at speeds up to 266 MHz and is part of a growing family of Smart Speed products that offer high performance processing optimized for lowest power consumption. On-chip modules such as a video accelerator module, LCD controller, USB On-The- Go, CMOS sensor interface, and two synchronous serial interfaces offer designers a rich suite of peripherals that can enhance any product seeking to provide a rich MC9328MX21
Contents
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information encryption, and secure software downloads. Bluetooth and expansion options are provided through PCMCIA/CF, USB, and MMC/SD host controllers. The i.MX21 is packaged in a 289-pin MAPBGA. Figure 1. i.MX21 Functional Block Diagram
MC9328MX21 Product Preview, Rev. 1.1 Freescale Semiconductor 3
1.1 Conventions
This document uses the following conventions: OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET. Logic level one is a voltage that corresponds to Boolean true (1) state. Logic level zero is a voltage that corresponds to Boolean false (0) state. T o set a bit or bits means to establish logic level one. T o clear a bit or bits means to establish logic level zero. A signal is an electronic construct whose state conveys or changes in state convey information. A pin is an external physical connection. The same pin can be used to connect a number of signals. Asserted means that a discrete signal is in active logic state. Active low signals change from logic level one to logic level zero. Active high signals change from logic level zero to logic level one. Negated means that an asserted discrete signal changes logic state. Active low signals change from logic level zero to logic level one. Active high signals change from logic level one to logic level zero. LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and high bytes or words are spelled out. Numbers preceded by a percent sign (%) are bi nary. Numbers preceded by a dollar sign ($) or 0x are hexadecimal.
1.2 Target Applications
The i.MX21 is targeted for advanced information appliances, smart phones, Web browsers, digital MP3 audio players, handheld computers based on the popular Palm OS platform, and messaging applications.
1.3 Reference Documentation
The following documents are required for a complete description of the i.MX21 and are necessary to design properly with the device. Especially for those not familiar with the ARM926EJ-S processor or previous DragonBall products, the following documents are helpful when used in conjunction with this manual. ARM Architecture Reference Manual (ARM Ltd., order number ARM DDI 0100) ARM7TDMI Data Sheet (ARM Ltd., order number ARM DDI 0029) ARM920T Technical Reference Manual (ARM Ltd., order number ARM DDI 0151C) MC9328MX21 Product Brief (order number MC9328MX21P/D) MC9328MX21 Reference Manual (order number MC9328MX21RM/D) MC9328MX1 Product Brief (order number MC9328MX1P/D) MC9328MX1 Data Sheet (order number MC9328MX1/D) MC9328MX1 Reference Manual (order number MC9328MX1RM/D) The Freescale manuals are available on the Freescale Semiconductor Web site at http://www.freescale.com. These documents may be downloaded directly from the Freescale Web site, or printed versions may be ordered. The ARM Ltd. documentation is available from http://www.arm.com.
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1.4 Ordering Information
Table 1 provides ordering information for the i.MX21.
1.5 Features
description of i.MX21 features. Table 1. i.MX21 Ordering Information
2 Signal Descriptions
Table 2. i.MX21 Signal Descriptions
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[1:0] is selected. DTACK is multiplexed with CS4. on-going burst sequence and initiate a new (long first access) burst sequence. BCLK Clock signal sent to external synchronous memories (such as burst flash) during burst mode. also shared with the PCMCIA PC_WE. DTACK DTACK signal—External input data acknowledge signal, multiplexed with CS4 . determined by the settings of these pins. MA [11:0] SDRAM address signals. MA[9:0] are multiplexed with address signals A[10:1]. corresponds to D[23:16], DQM1 corresponds to D[15:8], and DQM0 corresponds to D[7:0]. by programming the Function Multiplexing Control Register in the System Control chapter. by programming the Function Multiplexing Control Register in the System Control chapter. Table 2. i.MX21 Signal Descriptions (Continued)
oscillator circuit is shut down. EXT_48M This is a special factory test signal. To ensure proper operation, connect this signal to ground. EXT_266M This is a special factory test signal. To ensure proper operation, connect this signal to ground. modules (except the reset module, SDRAMC module, and the clock control module) are reset. from the following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out. an external RC circuit designed to detect a power-up event. OSC26M_TEST This is a special factory test signal. To ensure proper operation, leave this signal as a no connect. WKGD Battery indicator input used to qualify the walk-up process. Also multiplexed with TIN. TRST Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller. TDO Serial Output for test instructions and data. Changes on the falling edge of TCK. TDI Serial Input for test instructions and data. Sampled on the rising edge of TCK. TCK Test Clock to synchronize test logic and control register access through the JTAG port. multiplexed with OWIRE, hence utilizing OWIRE will render RTCK unusable and vice versa.
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BMI_RXF_FULL and BMI_WAIT of the BMI. LSCLK Shift Clock. This signal is multiplexed with the BMI_CLK_CS from BMI. OE_ACD Alternate Crystal Direction/Output Enable. SPL_SPR Sampling start signal for left and right scanning. This signal is multiplexed with the SLCDC1_CLK. signal). This signal is multiplexed with the SLCDC1_RS. is multiplexed with SLCDC1_D0. are SPL_SPR and SD2_CLK signals of LCDC and SD2, respectively. locations. These are PS and SD2_CMD signals of LCDC and SD2, respectively. locations. These are CLS and SD2_D3 signals of LCDC and SD2, respectively. inactive when a parallel data interface is used.
alternate muxing of these signals are available on some of the USB OTG and USBH1 signals. with SSI3_RXD signal from SSI3. multiplexed with LD[15:0] and SLCDC_DAT[15:0]. BMI_CLK_CS BMI bidirectional clock or chip select signal.This signal is multiplexed with LSCLK of LCDC. write and negated for read.This signal is muxed with LD[17] of LCDC. driven high when BMI is slave.This signal is multiplexed with CONTRAST signal of LCDC. value.This signal is muxed with VSYNC of the LCDC. EXT_DMAREQ External DMA Request input signal. This signal is multiplexed with CSPI1_RDY. EXT_DMAGRANT External DMA Grant output signal. This signal is multiplexed with LD[16]. NF_CE NAND Flash Chip Enable output signal. This signal is multiplexed with PC_CE1 of PCMCIA. NF_WP NAND Flash Write Protect output signal. This signal is multiplexed with PC_CE2 of PCMCIA. NF_RE NAND Flash Read Enable output signal. This signal is multiplexed with PC_RW of PCMCIA.
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NF_WE NAND Flash Write Enable output signal. This signal is multiplexed with and PC_BVD2 of PCMCIA. NF_RB NAND Flash Ready Busy input signal. This signal is multiplexed with PC_RST of PCMCIA. A[15:13]. NF_IO[7:0] signals are multiplexed with several PCMCIA signals. PC_A[25:0] PCMCIA Address signals. These signals are multiplexed with A[25:0]. PC_D[15:0] PCMCIA Data input and output signals. These signals are multiplexed with D[15:0]. PC_CD1 PCMCIA Card Detect1 input signal. This signal is multiplexed with NFIO[7] signal of NF. PC_CD2 PCMCIA Card Detect2 input signal. This signal is multiplexed with NFIO[6] signal of NF. PC_RST PCMCIA Reset output signal. This signal is multiplexed with NFRB signal of NF. cycles. This signal is multiplexed with NFALE signal of NF. PC_WE PCMCIA Memory Write Enable output signal asserted during common or attribute memory cycles. This signal is shared with RW of the EIM. PC_SPKOUT PCMCIA Speaker Out output signal. This signal is multiplexed with PWMO signal. PC_REG PCMCIA Register Select output signal. This signal is shared with EB2 of EIM. PC_CE1 PCMCIA Card Enable1 output signal. This signal is multiplexed with NFCE signal of NF. PC_CE2 PCMCIA Card Enable2 output signal. This signal is multiplexed with NFWP signal of NF. PC_IORD PCMCIA IO Read output signal. This signal is shared with EB3 of EIM. PC_IOWR PCMCIA IO Write output signal. This signal is shared with OE signal of EIM. PC_WP PCMCIA Write Protect input signal. This signal is multiplexed with NFIO[3] signal of NF. multiplexed with NFCLE signal of NF. access and negated low for write access. This signal is multiplexed with NFRE signal of NF. PC_PWRON PCMCIA input signal to indicate that the card power has been applied and stabilized.
CSPI1_SS[2:0] Slave Select (Selectable polarity) signal. CSPI1_SS2 is also multiplexed with USBG_RXDAT. CSPI1_RDY Serial Data Ready signal. Also multiplexed with EXT_DMAREQ. CSPI2_MOSI Master Out/Slave In signal. This signal is multiplexed with USBH2_TXDP signal of USB OTG. CSPI2_MISO Master In/Slave Out signal. This signal is multiplexed with USBH2_TXDM signal of USB OTG. CSPI3_MOSI Master Out/Slave In signal. This signal is multiplexed with SD1_CMD. CSPI3_MISO Master In/Slave Out signal. This signal is multiplexed with SD1_D0. CSPI3_SS Slave Select (Selectable polarity) signal multiplexed with SD1_D3. CSPI3_SCLK Serial Clock signal. This signal is multiplexed with SD1_CLK. Clock, and Reset Controller module. TOUT2 Timer Output signal from General Purpose Timer1 (GPT2). This signal is multiplexed with PWMO. TOUT3 Timer Output signal from General Purpose Timer1 (GPT3). This signal is multiplexed with PWMO. USB_BYP USB Bypass input active low signal. USBG_RXDP USB OTG Receive Data Plus input signal. This signal is muxed with SLCDC1_DAT15. USBG_RXDM USB OTG Receive Data Minus input signal. This signal is muxed with SLCDC1_DAT14. USBG_TXDP USB OTG Transmit Data Plus output signal. This signal is muxed with SLCDC1_DAT13. USBG_TXDM USB OTG Transmit Data Minus output signal. This signal is muxed with SLCDC1_DAT12. USBG_RXDAT USB OTG Transceiver differential data receive signal. Multiplexed with CSPI1_SS2. USBG_OE USB OTG Output Enable signal. This signal is muxed with SLCDC1_DAT11.
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USBG_ON USB OTG Transceiver ON output signal. This signal is muxed with SLCDC1_DAT9. USBG_TXR_INT signal of USB OTG. This signal is muxed with SLCDC1_DAT10. USBH1_RXDAT USB Host1 Transceiver differential data receive signal. Multiplexed with USBH1_FS. USBH1_OE USB Host1 Output Enable signal. This signal is muxed with SLCDC1_DAT2. SLCDC1_DAT1 and USBH1_RXDAT. USBH_ON USB Host transceiver ON output signal. This signal is muxed with SLCDC1_DAT0. USBH2_RXDP USB Host2 Receive Data Plus input signal. This signal is multiplexed with CSPI2_SS[1] of CSPI2. USBH2_OE USB Host2 Output Enable signal. This signal is multiplexed with CSPI2_SCLK of CSPI2. USBH2_FS USB Host2 Full Speed output signal. This signal is multiplexed with CSPI2_SS[0] of CSPI2. USBG_SCL USB OTG I2C Clock Output signal. This signal is multiplexed with SLCDC1_DAT8. USBG_SDA USB OTG I2C Data Input/Output signal. This signal is multiplexed with SLCDC1_DAT7. USBG_TXR_INT USB OTG transceiver Interrupt input. Multiplexed with USBG_FS. added. This signal is multiplexed with CSPI3_MOSI. SD1_CLK SD Output Clock. This signal is multiplexed with CSPI3_SCLK.
pull-up, via the Pull-up enable register, a 50 K–69K external pull up resistor must be added. SD1_D[3] is muxed with CSPI3_SS while SD1_D[0] is muxed with CSPI3_MISO. SD2_CLK SD Output Clock signal. This signal is multiplexed with SLCDC1_CLK signal from SLCDC1. SLCDC_D0 signals from SLCDC1. UART2_RXD Receive Data input signal. This signal is multiplexed with KP_ROW6 signal from KPP. UART2_TXD Transmit Data output signal. This signal is multiplexed with KP_COL6 signal from KPP. UART2_RTS Request to Send input signal. This signal is multiplexed with KP_ROW7 signal from KPP. UART2_CTS Clear to Send output signal. This signal is multiplexed with KP_COL7 signal from KPP. UART3_RXD Receive Data input signal. This signal is multiplexed with IR_RXD from FIRI. UART3_TXD Transmit Data output signal. This signal is multiplexed with IR_TXD from FIRI. UART4_RXD Receive Data input signal which is multiplexed with USBH1_RXDP and USBH1_TXDP. UART4_TXD Transmit Data output signal which is multiplexed with USBH1_TXDM. UART4_RTS Request to Send input signal which is multiplexed with USBH1_FS and USBH1_RXDP. UART4_CTS Clear to Send output signal which is multiplexed with USBH1_TXDP and USBH1_RXDM. SSI1_MCLK SSI1 master clock. Multiplexed with TOUT. SSI2_CLK Serial clock signal which is output in master or input in slave.
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SSI2_FS Frame Sync signal which is output in master and input in slave. SSI2_MCLK SSI2 master clock. Multiplexed with TOUT. SAP_CLK Serial clock signal which is output in master or input in slave. SAP_FS Frame Sync signal which is output in master and input in slave. OWIRE One wire input and output signal. This signal is multiplexed with JTAG RTCK. TOUT3 of the General Purpose Timer module. multiplexing) to choose which signal KP_COL6 is available. NVDD Noisy Supply for the I/O pins. There are six (6) I/O voltage rings, NVDD1 through NVDD6.
3 Specifications
This section contains the electrical specifications and timing diagrams for the i.MX21 processor.
3.1 Maximum Ratings
Table 3 provides information on maximum ratings.
3.2 Recommended Operating Range
pairs of VDD and VSS power supply and return pins. QVDD, QVDDx, and QVSS pins are used for internal logic. to the enclosed I/O pads. This design allows different peripheral supply voltage levels in a system. AVDD pins from other VDD pins. For more information about I/O pads grouping per VDD, please refer to Table 4 on page 15. Table 3. Maximum Ratings Table 4. Recommended Operating Range
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3.3 DC Electrical Characteristics
Table 5 contains both maximum and minimum DC characteristics of the i.MX21. Table 5. Maximum and Minimum DC Characteristics Table 4. Recommended Operating Range (Continued)
3.4 AC Electrical Characteristics
timing is measured at 30 pF loading. Table 6. Tri-State Signal Timing Table 7. 32k/26M Oscillator Signal Timing Table 8. CLKO Rise/Fall Time (at 30pF Loaded)
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3.5 DPLL Timing Specifications
predivider and Tdck is the output double clock period. Table 9. DPLL Specifications
3.6 Reset Module
NVDD2-6 before QVDD is powered up to prevent forward biasing. Figure 2. Timing Relationship with POR
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Figure 3. Timing Relationship with RESET_IN Table 10. Reset Module Timing Parameter Table
1 Width of input POWER_ON_RESET 800 – 800 – ms
2 Width of internal POWER_ON_RESET
5 Width of external hard-reset RESET_IN 4 – 4 – Cycles of
3.7 External DMA Request and Grant
request will initiate one DMA burst. the External DMA Grant signal is asserted with the initiation of the DMA burst. per source select register setting). REN and CEN bit of this channel are set. External DMA Request is asserted. the external request becomes low for the next consecutive burst, if another DMA request signal is asserted. request is de-asserted immediately after sensing grant signal active. Figure 4. Assertion of DMA External Grant Signal signal active such that a new burst is not initiated. Figure 5. Safe Maximum Timings for External Request De-Assertion NOTE: Assuming in worst case the data is read/written from/to External device as per the above waveform.
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3.8 BMI Interface Timing Diagram
3.8.1 Connecting BMI to ATI MMD Devices
3.8.1.1 ATI MMD Devices Drive the BMI_CLK/CS
happens, the new coming data is ignored.
3.8.1.1.1 MMD Read BMI Timing
Figure 6 shows the MMD read BMI timing when the MMD drives clock. Table 11. DMA External Request and Grant Timing Parameter Table
Figure 6. MMD (ATI) Drives Clock, MMD Read BMI Timing Note: All the timings assume that the hclk is running at 133 MHz. Note: The MIN period of the 1T is assumed that MMD latch data at falling edge. are slow pads and it max frequency can only up to 18Mhz, the max clock frequency can only up to 36 MHz.
3.8.1.1.2 MMD Write BMI Timing
BMI_CLK/CS BMI checks the BMI_WRITE logic level to determine if the current cycle is a write cycle. Table 12. MMD Read BMI Timing Table when MMD Drives Clock
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Figure 7. MMD (ATI) Drives Clock, MMD Write BMI Timing Note: All timings assume that the hclk is running at 133 MHz. Note: At this mode, the maximum frequency of the BMI_CLK/CS can be up to 36 MHz (doubles as maximum data pad speed).
3.8.1.2 BMI Drives the BMI_CLK/CS
issue a write cycle (MMD write BMI).
3.8.1.3 MMD Read BMI Timing
MMD devices can latch the data on each falling edge of BMI_CLK/CS. will drive BMI_CLK/CS out once the BMI_WRITE is changed from low to high. Table 13. MMD Write BMI Timing
Figure 8. BMI Drives Clock, MMD Read BMI Timing Note: In this mode, the max frequency of the BMI_CLK/CS can be up to 36Mhz(double as max data pad speed). Note: The BMI_CLK/CS can only be divided by 2,4,8,16 from HCLK.
3.8.1.4 MMD Write BMI Timing
Figure on page 26 shows the MMD write BMI timing when BMI drives BMI_CLK/CS. MMD still has data to write after the first operation completed. latch the last data using the internal clock. BMI_WRITE signal can not be negated when the WRITE operation is proceeding. Table 14. MMD Read BMI Timing Table when BMI Drives Clock
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Figure 9. BMI Drives Clock, MMD Write BMI Timing data pad speed) if BMI latch data at the next rising edge. Note: Tds1 is the receive data setup time when BMI latch data at the falling edge. Note: Tds2 is the receive data setup time when BMI latch data at the next rising edge.
3.8.2 Connecting BMI to Exte rnal Bus Master Devices
CS is logic low and BMI_WRITE is logic high. Each rising edge of BMI_CLK/CS will determine if data should be latched to RxFIFO from the data bus. Table 15. MMD Write BMI Timing Table when BMI Drives Clock
Figure 10. Memory Interface Slave Mode, External Bus Master Read/Write to BMI Timing Note: All the timings are assumed that the hclk is running at 133 MHz.
3.8.3 Connecting BMI to External Bus Slave Devices
write cycles are continuously generated when TxFIFO is not emptied. cannot begin until this read cycle complete. Table 16. External Bus Master Read/Write to BMI Timing Table
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3.8.3.1 Memory Interface Master Mode Without WAIT Signal
shows the BMI timing when the WAIT bit is cleared. Figure 11. Memory Interface Master Mode, BMI Read/Write to External Slave Device Timing without Wait
3.8.3.2 Memory Interface Master Mode with WAIT Signal
sampling a logic high BMI_WAIT signal. Figure 12 shows the BMI write timing when the WAIT bit is set.
Figure 12. Memory Interface Master Mode, BMI Write to External Slave Device Timing with Wait Signal without WAIT signal. So the BMI_READ will be asserted at least for 1+WS Int_Clk period. Figure 13. Memory Interface Master Mode, BMI Read to External Slave Device Timing with Wait Signal
3.9 SPI Timing Diagrams
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Figure 14. Master SPI Timing Diagram Using SPI_RDY Edge Trigger Figure 15. Master SPI Timing Diagram Using SPI_RDY Level Trigger Figure 16. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger Figure 17. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT Figure 18. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge
3.10 LCD Controller
Figure 19. SCLK to LD Timing Diagram Table 17. Timing Parameter Table for Figure 14 through Figure 18
1 SPI_RDY to SS output low 2T 1
- T = CSPI system clock period (PERCLK2).
3 Last SCLK edge to SS output high 2·Tsclk – ns
- WAIT = Number of bit clocks (SCLK) or 32.768 KHz clocks per Sample Period Control
Table 18. LCDC SCLK Timing Parameter Table The pixel clock is equal to LCDC_CLK / (PCD + 1). When it is in CSTN, TFT or monochrome mode with bus width = 1, SCLK is equal to the pixel clock. When it is in monochrome with other bus width settings, SCLK is equal to the pixel clock divided by bus width. The polarity of SCLK and LD can also be programmed. Maximum frequency of SCLK is HCLK / 3 for TFT and CSTN, otherwise LD output will be incorrect.
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Figure 20. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing Table 19. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing VSYN, HSYN and OE can be programmed as active high or active low. In Figure 20, all 3 signals are active low. XMAX is defined in number of pixels in one line.
Figure 21. Sharp TFT Panel Timing Table 20. Sharp TFT Panel Timing Falling of SPL/SPR aligns with first LD of line. Falling of PS aligns with rising edge of CLS. REV toggles in every HSYN period.
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Figure 22. Non-TFT Mode Panel Timing Table 21. Non-TFT Mode Panel Timing Ts is the SCLK period while Tpix is the pixel clock period. When it is in CSTN mode or monochrome mode with bus width = 1, T3 = Tpix = Ts. When it is in monochrome mode with bus width = 2, 4, and 8, T3 = 1, 2 and 4 Tpix respectively.
3.11 Smart LCD Controller
Figure 23. SLCDC Serial Transfer Timing
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Figure 24. SLCDC Parallel Transfers Timing Table 22. SLCDC Serial Transfer Timing
3.12 Multimedia Card/Secure Digital Host Controller
SD module (inner system) and the application (user programming). Figure 25. Chip-Select Read Cycle Timing Diagram Table 23. SLCDC Parallel Transfers Timing Table 24. SDHC Bus Timing Parameter Table
1 CLK frequency at Data transfer Mode (PP) 110/30 cards 0 25/5 0 25/5 MHz
2 CLK frequency at Identification Mode 2 0 400 0 400 KHz
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3.12.1 Command Response Timing on MMC/SD Bus
Figure 30 are defined in Table 25.
7 Output delay time 3 0 16 0 14 ns
Table 25. State Signal Parameters for Figure 26 through Figure 30 Table 24. SDHC Bus Timing Parameter Table (Continued)
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Figure 28. Timing Diagrams at Data Read to multiple block mode, with the flow terminated by a stop transmission command.
Figure 29. Timing Diagrams at Data Write different scenarios on the bus.
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Figure 30. Stop Transmission During Different Scenarios Table 26. Timing Values for Figure 26 through Figure 30 Stop transmission received after last data block. Card becomes busy programming. Stop transmission received after last data block. Card becomes busy programming.
3.12.2 SDIO-IRQ and ReadWait Service Handling
continues until the source is removed (SD_DAT[1] returns to its high level). Figure 31. SDIO IRQ Timing Diagram Table 26. Timing Values for Figure 26 through Figure 30 (Continued)
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Figure 32. SDIO ReadWait Timing Diagram
3.13 NAND-Flash Controller Interface
The timing diagrams Figure 33 through Figure 36shows the timing of the NAND Flash controller. Figure 33. Command Latch Cycle Timing
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Figure 36. Output Data Latch Cycle Timing Note: The data shown in Figure 36 is generated using the NAND Flash device and sampled with IPP_FLASH_CLK. Table 27. Timing Characteristics
3.14 Pulse-Width Modulator
available at the pulse-width modulator output (PWMO) external pin. Figure 37. PWM Output Timing Diagram Table 28. PWM Output Timing Parameter Table
1 System CLK frequency 1 04 504 5 M H z
Table 27. Timing Characteristics (Continued)
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3.15 SDRAM Memory Controller
timings related to the SDRAMC module in the i.MX21. Figure 38. SDRAM Read Cycle Timing Diagram Table 28. PWM Output Timing Parameter Table (Continued) Note: CKE is high during the read/write cycle.
Table 29. SDRAM Timing Parameter Table
5 SDRAM access time (CL = 1) – – – – ns
6 Data out hold time
7 Data out high-impedance time (CL = 3) – tHZ
- tHZ = SDRAM data out high-impedance time, external SDRAM memory device dependent parameter.
7 Data out high-impedance time (CL = 2) – tHZ
7 Data out high-impedance time (CL = 1) – – – – ns
8 Active to read/write command period (RC = 1) tRCD
- tRCD = SDRAM clock cycle time. The tRCD setting can be found in the i.MX21 reference manual.
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Figure 39. SDRAM Write Cycle Timing Diagram Table 30. SDRAM Write Timing Parameter Table
6 Precharge cycle period
7 Active to read/write command delay t RCD
Figure 40. SDRAM Refresh Timing Diagram
- Precharge cycle timing is included in the write timing diagram.
- tRP and tRCD = SDRAM clock cycle time. These settings can be found in the i.MX21 reference manual.
Table 31. SDRAM Refresh Timing Parameter Table Table 30. SDRAM Write Timing Parameter Table (Continued)
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Figure 41. SDRAM Self-Refresh Cycle Timing Diagram
3.16 Synchronous Serial Interface
6 Precharge cycle period t
7 Auto precharge command period t RC
- tRP and tRC = SDRAM clock cycle time. These settings can be found in the i.MX21 reference manual.
Table 31. SDRAM Refresh Timing Parameter Table (Continued)
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Figure 44. SSI Transmitter External Clock Timing Diagram Figure 45. SSI Receiver External Clock Timing Diagram Table 32. SSI to SAP Ports Timing Parameter Table
14 SRXD hold time after (Rx) CK low 0 – 0 – ns
Table 32. SSI to SAP Ports Timing Parameter Table (Continued)
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30 SRXD hole time after (Rx) CK low 0 – 0 – ns
32 SRXD hold after (Tx) CK falling 0 – 0 – ns
34 SRXD hold after (Tx) CK falling 0 – 0 – ns
- All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. Table 33. SSI to SSI1 Ports Timing Parameter Table
Table 33. SSI to SSI1 Ports Timing Parameter Table (Continued)
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- All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. Table 34. SSI to SSI2 Ports Timing Parameter Table
- All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. Table 34. SSI to SSI2 Ports Timing Parameter Table (Continued)
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Table 35. SSI to SSI3 Ports Timing Parameter Table
3.17.1 Reset Sequence with Reset Pulse Presence Pulse
The timing diagram for this sequence is shown in Figure 46.
- All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. Table 35. SSI to SSI3 Ports Timing Parameter Table (Continued)
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Figure 46. 1-Wire Initialization The reset pulse begins the initialization sequence and it is initiated when the RPP control register bit is set. to determine if at least one DS2502 is connected. Software will determine if more than one DS2502 exists. a zero, then no device was found.
3.17.2 Write 0
Figure 47. Write 0 Timing complete, the WR0 register will be auto cleared.
3.17.3 Write 1/Read Data
the 1 generated by the bus master (one-wire). completed. After a Read, the control register RDST bit is set to the value of the read.
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the main clock is an exact integer multiple of 1 MHz, then the generated frequency will be exactly 1 MHz. A main clock frequency below 10 MHz might cause a misbehavior of the module.
3.18 USB On-The-Go
covers the transfer modes and how they work from the ground up. all times, there is no end-of-transfer. Table 37. System Clock Requirements
Figure 50. USB Timing Diagram for Data Transfer to USB Transceiver (TX) Table 38. USB Timing Parameter Table for Data Transfer to USB Transceiver (TX)
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Figure 51. USB Timing Diagram for Data Transfer from USB Transceiver (RX) Data Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP. Figure 52. USB Timing Diagram for Data Transfer from USB Transceiver (I2C) Table 39. USB Timing Parameter Table for Data Transfer from USB Transceiver (RX)
3.19 External Interface Module (EIM)
in Figure 53, and Table 41 on page 68 defines the parameters of signals. Table 40. USB Timing Parameter Table for Data Transfer from USB Transceiver (I2C)
1 Hold time (repeated) START condition 188 – ns
2 Data hold time 0 188 ns
3 Data setup time 88 – ns
4 HIGH period of the SCL clock 500 – ns
5 LOW period of the SCL clock 500 – ns
6 Setup time for STOP condition 185 – ns
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Figure 53. EIM Bus Timing Diagram Table 41. EIM Bus Timing Parameters
3.19.1 EIM External Bus Timing Diagrams
The following timing diagrams show the timing of accesses to memory or a peripheral.
- Clock refers to the system clock signal, HCLK, generated from the System DPLL
Table 41. EIM Bus Timing Parameters (Continued)
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Figure 54. WSC = 1, A.HALF/E.HALF
Figure 55. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF
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Figure 56. WSC = 1, OEA = 1, A.WORD/E.HALF
Figure 57. WSC = 1, WEA = 1, WEN = 1, A.WORD/E.HALF
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Figure 58. WSC = 3, OEA = 2, A.WORD/E.HALF
Figure 59. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF
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Figure 60. WSC = 3, OEA = 4, A.WORD/E.HALF
Figure 61. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF
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Figure 62. WSC = 3, OEN = 2, A.WORD/E.HALF
Figure 63. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF
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Figure 64. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
Figure 65. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF
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Figure 66. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF
Figure 67. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF
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Figure 68. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF
Figure 69. WSC = 3, CSA = 1, A.HALF/E.HALF
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Figure 70. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF
Figure 71. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF
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Figure 72. WSC = 3, SYNC = 1, A.HALF/E.HALF
Figure 73. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD
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Figure 74. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF
Figure 75. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF
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Figure 76. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF
3.20 DTACK Mode Memory Access Timing Diagrams
to generate different HCLK frequencies.
MC9328MX21 Product Preview, Rev. 1.1 Freescale Semiconductor 93 There are two modes of operation for the DTACK input signal: rising edge detection or level sensitive detection with a programmable insensitivity time. DTACK is only used during external asynchronous data transfers, thus the SYNC bit in the chip select control registers must be cleared. During edge detection mode, the EIM will terminate an external data transfer following the detection of the DTACK signals rising edge, so long as it occurs within the 1024 HCLK cycle time. Edge detection mode is used for devices that follow the PCMCIA standard. Note that DTACK rising edge detection mode can only be used for CS[5] operations. To configure CS[5] for DTACK rising edge detection, the following bits must be programmed in the Chip Select 5 Control Register and EIM Configuration Register: WSC bit field set to 0x3F and CSA (or CSN) set to 1 or greater in the Chip Select 5 Control Register AGE bit set in the EIM Configuration Register Other bits such as DSZ, OEA, OEN, and so on, may be set according to system and timing requirements of the external device. The requirement of setting CSA or CSN is required to allow the EIM to wait for the rising edge of DTACK during back-to-back external transfers, such as during DMA transfers or an internal 32-bit access through an external 16-bit data port. During level sensitive detection, the EIM will first hold off sampling the DTACK signal for at least 2 HCLK cycles, and up to 5 HCLK cycles as programmed by the DCT bits in the Chip Select Control Register. After this insensitivity time, the EIM will sample DTACK and if it detects that DTACK is logic high, it will continue the data transfer at the programmed number of wait states. However, if the EIM detects that DTACK is logic low, it will wait until DTACK goes to logic high to continue the access, so long as this occurs within the 1024 HCLK cycle time. If at anytime during an external data transfer DTACK goes to logic low, the EIM will wait until DTACK returns to logic high to resume the data transfer. Level detection is often used for asynchronous devices such graphic controller chips. Level detection may be used with any chip select except CS[4] as it is multiplexed with the DTACK signal. To configure a chip select for DTACK level sensitive detection, the following bits must be programmed in the Chip Select Control Register and EIM Configuration Register: EW bit set, WSC set to > 1, and CSN set to < 3 in the Chip Select Control Register BCD/DCT set to desired insensitivity time in th e Chip Select Control Register. The insensitivity time is dictated by the external devices timing requirements. AGE bit cleared in the EIM Configuration Register Other bits such as DSZ, OEA, OEN, and so on, may be set according to system and timing requirements of the external device. The waveforms in the following section provide examples of the DTACK signal operation.
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3.20.1 DTACK Example Waveforms: Internal ARM AHB Word
Figure 77. DTACK Edge Triggered Read Access, WSC=3F, OEA=8, OEN=5, AGE=1.
Figure 78. DTACK Level Sensitive Sequential Read Accesses, WSC=2, EW=1, DCT=1, AGE=0
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Figure 79. DTACK Level Sensitive Sequential Write Accesses, WSC=2, EW=1, RWA=1, RWN=1,
3.21 I 2C Module
Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP. Figure 80. Definition of Bus Timing for I2C
3.22 CMOS Sensor Interface
and a 16 × 32 statistic data FIFO.
3.22.1 Gated Clock Mode
Section 3.22.3, Calculation of Pixel Clock Rise/Fall Time, on page 101. Table 42. I2C Bus Timing Parameter Table
2 Data hold time
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Figure 81. Sensor Output Data on Pixel Clock Falling Edge Figure 82. Sensor Output Data on Pixel Clock Rising Edge Table 43. Gated Clock Mode Timing Parameters
3.22.2 Non-Gated Clock Mode
located in Section 3.22.3, Calculation of Pixel Clock Rise/Fall Time, on page 101.
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Figure 83. Sensor Output Data on Pixel Clock Falling Edge Figure 84. Sensor Output Data on Pixel Clock Rising Edge Table 44. Non-Gated Clock Mode Parameters
3.22.3 Calculation of Pixel Clock Rise/Fall Time
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns. Table 44. Non-Gated Clock Mode Parameters (Continued)
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4 Pin-Out and Package Information
Table 45. i.MX21 Pin Assignments
4.1 MAPBGA Package Dimensions
Figure 85. i.MX21 MAPBGA Mechanical Drawing
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4.2 MAPBGA Package Dimensions
Figure 86. i.MX21 MAPBGA Mechanical Drawing
MC9328MX21 Product Preview, Rev. 1.1 Freescale Semiconductor 105
5 Document Revision History
This revision, Rev. 1.1, updates the functional block diagram, Figure 1 on page 2.
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