MC9328MX21_06 FREESCALE | Alldatasheet
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© Freescale Semiconductor, Inc., 2005, 2006. All rights reserved. Freescale Semiconductor Data Sheet: Technical Data Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Document Number: MC9328MX21 Rev. 3.1, 07/2006 MC9328MX21
Package Information
(MAPBGA–289) Ordering Information: See Table 1 on page 3
1 Introduction
Freescale’s i.MX family of microprocessors has demonstrated leadership in the portable handheld market. Building on the success of the MX (Media Extensions) series, the i.MX21 (MC9328MX21) provides a leap in performance with an ARM926EJ-S microprocessor core that provides accelerated Java support in addition to highly integrated system functions. The i.MX21 device specifically addresses the needs of the smartphone and portable product markets with intelligent integrated peripherals, advanced processor core, and power management capabilities. Thei.MX21 features the advanced and power-efficient ARM926EJ-S core operating at speeds up to 266 MHz and is part of a growing family of Smart Speed products that offer high performance processing optimized for lowest power consumption. On-chip modules such as a video accelerator module, LCD controller, USB On-The- Go, 1-Wire ® interface, CMOS sensor interface, and synchronous serial interfaces offer designers a rich suite of peripherals that can enhance many products seeking to provide a rich multimedia experience. MC9328MX21
266 MHz
Contents
4 Pin Assignment and Package Information 95
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Bluetooth and expansion options are provided through PCMCIA/CF, USB, and MMC/SD host controllers. The device is packaged in a 289-pin MAPBGA. Figure 1. i.MX21 Functional Block Diagram
1.1 Conventions
- OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.
- Logic level one is a voltage that corresponds to Boolean true (1) state.
- Logic level zero is a voltage that corresponds to Boolean false (0) state.
- T o set a bit or bits means to establish logic level one.
- T o clear a bit or bits means to establish logic level zero.
- A signal is an electronic construct whose state conveys or changes in state convey information. Connectivity ARM9 Platform System Control Enhanced Multimedia Accelerator (eMMA) Standard System I/O Memory Interface ARM926EJ-S Internal Control Clock Management I2C UART x 4 1-WIRE IrDA USB OTG/ 2 Hosts SDRAMC EIM/BMI NFC i.MX21 CSPI x 3 Human Interface Audio Mux SSI x 2 JTAG/MultiICE System Boot Timers x 3 WDOG RTC DMAC GPIO PWM SLCD Controller Keypad D Cache I Cache MAX MMU Bus Control Memory Control Pre- and Post- Processing Video Accelerator Memory Expansion MMC/SD x 2 PCMCIA/CF LCD Controller CSI
- A pin is an external physical connection. The same pin can be used to connect a number of signals.
- Asserted means that a discrete signal is in active logic state. — Active low signals change from logic level one to logic level zero. — Active high signals change from logic level zero to logic level one.
- Negated means that an asserted discrete signal changes logic state. — Active low signals change from logic level zero to logic level one. — Active high signals change from logic level one to logic level zero.
- LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and high bytes or words are spelled out.
- Numbers preceded by a percent sign (%) are bi nary. Numbers preceded by a dollar sign ($) or 0x are hexadecimal.
1.2 Target Applications
audio players, handheld computers based on the popular Palm OS platform, and messaging applications.
1.3 Reference Documentation
following documents are helpful when used in conjunction with this manual.
1.4 Ordering Information
Table 1 provides ordering information for the device. Table 1. Ordering Information
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1.5 Features
brief description of i.MX21 features.
- ARM926EJ-S Core Complex
- enhanced Multimedia Accelerator (eMMA)
- Display and Video Modules — LCD Controller (LCDC) — Smart LCD Controller (SLCDC) — CMOS Sensor Interface (CSI)
- Bus Master Interface (BMI)
- Wireless Connectivity — Fast Infra-Red Interface (FIRI)
- Wired Connectivity — USB On-The-Go (USBOTG) Controller — Four Universal Asynchronous Receiver/Transmitters (UARTx) — Three Configurable Serial Peripheral Interfaces (CSPI x) for High Speed Data Transfer — Inter-IC (I 2C) Bus Module — Two Synchronous Serial Interfac es (SSI) with Inter-IC Sound (I2S) — Digital Audio Mux — One-Wire Controller — Keypad Interface
- Memory Expansion and I/O Card Support — Two Multimedia Card and Secure Dig ital (MMC/SD) Host Controller Modules
- Memory Interface — External Interface Module (EIM) — SDRAM Controller (SDRAMC) — NAND Flash Controller (NFC) — PCMCIA/CF Interface
- Standard System Resources — Clock Generation Module (C GM) and Power Control Module — Three General-Purpose 32-Bit Counters/Timers — Watchdog Timer — Real-Time Clock/Sampling Timer (RTC) — Pulse-Width Modulator (PWM) Module — Direct Memory Access Controller (DMAC) — General-Purpose I/O (GPIO) Ports — Debug Capability MC9328MX21CVK 289-lead MAPBGA 0.65mm, 14mm x 14mm Lead-free -40 °C–85°C MC9328MX21CVM 289-lead MAPBGA 0.8mm, 17mm x 17mm Lead-free -40 °C–85°C
Table 1. Ordering Information (Continued)
2 Signal Descriptions
- CLKMODE[1:0]: To ensure proper opera tion, leave these signals as no connects.
- OSC26M_TEST: To ensure proper opera tion, leave this signal as no connect.
- EXT_48M: To ensure proper operati on, connect this signal to ground.
- EXT_266M: To ensure proper operati on, connect this signal to ground.
- TEST_WB[2:0]: These signals are also multiple xed with GPIO PORT E as well as alternate keypad signals. If not utilizing these signals for GPIO functionality or for their other multiplexed function, then configure as GPIO input with pull up enabled, and leave as a no connect.
- TEST_WB[4:3]: To ensure proper opera tion, leave these signals as no connects.
Table 2. i.MX21 Signal Descriptions EB1 Byte Strobe—Active low external enable byte signal that controls D [23:16], shared with SDRAM DQM1. OE Memory Output Enable—Active low output enables external data bus, shared with PCMCIA PC_IOWR. selected. DTACK is multiplexed with CS4. going burst sequence and initiate a new (long first access) burst sequence. BCLK Clock signal sent to external synchronous memories (such as burst flash) during burst mode. shared with the PCMCIA PC_WE. DTACK DTACK signal—External input data acknowledge signal, multiplexed with CS4 .
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high, terminate with a 1 KΩ resistor to VDDA. Do not change the state of these inputs after power-up. Boot 3 should always be tied to logic low. MA [11:0] SDRAM address signals. MA[9:0] are multiplexed with address signals A[10:1]. corresponds to D[23:16], DQM1 corresponds to D[15:8], and DQM0 corresponds to D[7:0]. programming the Function Multiplexing Control Register in the System Control chapter. programming the Function Multiplexing Control Register in the System Control chapter. RAS SDRAM Row Address Select signal. signal switching from GND to VDDA. XTAL26M Oscillator output to external crystal. When using an external signal source, float this output. wave signal switching from GND to QVDD5. XTAL32K Oscillator output to external crystal. When using an external signal source, float this output. EXT_48M This is a special factory test signal. To ensure proper operation, connect this signal to ground. EXT_266M This is a special factory test signal. To ensure proper operation, connect this signal to ground. (except the reset module, SDRAMC module, and the clock control module) are reset. following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out. external RC circuit designed to detect a power-up event. Table 2. i.MX21 Signal Descriptions (Continued)
CLKMODE[1:0] These are special factory test signals. To ensure proper operation, leave these signals as no connects. OSC26M_TEST This is a special factory test signal. To ensure proper operation, leave this signal as a no connect. functions, then configure as GPIO input with pull-up enabled, and leave as a no connect. TEST_WB[4:3] These are special factory test signals. To ensure proper operation, leave these signals as no connects. WKGD Battery indicator input used to qualify the walk-up process. Also multiplexed with TIN. For termination recommendations, see the Table “JTAG pinouts” in the Multi-ICE® User Guide from ARM® Limited. TRST Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller. TDO Serial Output for test instructions and data. Changes on the falling edge of TCK. TDI Serial Input for test instructions and data. Sampled on the rising edge of TCK. TCK Test Clock to synchronize test logic and control register access through the JTAG port. with 1-Wire, therefore using 1-Wire renders RTCK unusable and vice versa. of BMI. LD[16] is multiplexed with BMI_READ_REQ of BMI and EXT_DMAGRANT. LSCLK Shift Clock. This signal is multiplexed with the BMI_CLK_CS from BMI. OE_ACD Alternate Crystal Direction/Output Enable. SPL_SPR Sampling start signal for left and right scanning. This signal is multiplexed with the SLCDC1_CLK.
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signal is multiplexed with the SLCDC1_RS. SPL_SPR and SD2_CLK signals of LCDC and SD2, respectively. SLCDC1_CS SLCDC Chip Select output signal. This signal is multiplexed and available at 2 alternate signal locations. These are PS and SD2_CMD signals of LCDC and SD2, respectively. locations. These are CLS and SD2_D3 signals of LCDC and SD2, respectively. SLCDC1_D0 SLCDC serial data output signal. This signal is multiplexed and available at 2 alternate signal locations. parallel data interface is used. alternate muxing of these signals are available on some of the USB OTG and USBH1 signals. multiplexed with LD[15:0] and SLCDC_DAT[15:0]. BMI_CLK_CS BMI bidirectional clock or chip select signal.This signal is multiplexed with LSCLK of LCDC. negated for read.This signal is muxed with LD[17] of LCDC. when BMI is slave.This signal is multiplexed with CONTRAST signal of LCDC. signal is muxed with VSYNC of the LCDC.
EXT_DMAREQ External DMA Request input signal. This signal is multiplexed with CSPI1_RDY. NF_CLE NAND Flash Command Latch Enable output signal. Multiplexed with PC_POE of PCMCIA. NF_CE NAND Flash Chip Enable output signal. This signal is multiplexed with PC_CE1 of PCMCIA. NF_WP NAND Flash Write Protect output signal. This signal is multiplexed with PC_CE2 of PCMCIA. NF_ALE NAND Flash Address Latch Enable output signal. This signal is multiplexed with PC_OE of PCMCIA. NF_RE NAND Flash Read Enable output signal. This signal is multiplexed with PC_RW of PCMCIA. NF_WE NAND Flash Write Enable output signal. This signal is multiplexed with and PC_BVD2 of PCMCIA. NF_RB NAND Flash Ready Busy input signal. This signal is multiplexed with PC_RST of PCMCIA. A[15:13]. NF_IO[7:0] signals are multiplexed with several PCMCIA signals. PC_A[25:0] PCMCIA Address signals. These signals are multiplexed with A[25:0]. PC_D[15:0] PCMCIA Data input and output signals. These signals are multiplexed with D[15:0]. PC_CD1 PCMCIA Card Detect1 input signal. This signal is multiplexed with NFIO[7] signal of NF . PC_CD2 PCMCIA Card Detect2 input signal. This signal is multiplexed with NFIO[6] signal of NF . PC_WAIT PCMCIA Wait input signal to extend current access. This signal is multiplexed with NFIO[5] signal of NF . PC_READY PCMCIA Ready input signal indicates card is ready for access. Multiplexed with NFIO[4] signal of NF . PC_RST PCMCIA Reset output signal. This signal is multiplexed with NFRB signal of NF . PC_OE PCMCIA Memory Read Enable output signal asserted during common or attribute memory read cycles. This signal is multiplexed with NFALE signal of NF . signal is shared with RW of the EIM. PC_VS1 PCMCIA Voltage Sense1 input signal. This signal is multiplexed with NFIO[2] signal of NF . PC_VS2 PCMCIA Voltage Sense2 input signal. This signal is multiplexed with NFIO[1] signal of NF . PC_BVD1 PCMCIA Battery Voltage Detect1 input signal. This signal is multiplexed with NFIO[0] signal of NF . PC_BVD2 PCMCIA Battery Voltage Detect2 input signal. This signal is multiplexed with NF_WE signal of NF . PC_SPKOUT PCMCIA Speaker Out output signal. This signal is multiplexed with PWMO signal. PC_REG PCMCIA Register Select output signal. This signal is shared with EB2 of EIM. PC_CE1 PCMCIA Card Enable1 output signal. This signal is multiplexed with NFCE signal of NF . PC_CE2 PCMCIA Card Enable2 output signal. This signal is multiplexed with NFWP signal of NF . PC_IORD PCMCIA IO Read output signal. This signal is shared with EB3 of EIM. PC_IOWR PCMCIA IO Write output signal. This signal is shared with OE signal of EIM. PC_WP PCMCIA Write Protect input signal. This signal is multiplexed with NFIO[3] signal of NF .
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multiplexed with NFCLE signal of NF . access and negated low for write access. This signal is multiplexed with NFRE signal of NF . PC_PWRON PCMCIA input signal to indicate that the card power has been applied and stabilized. CSPI1_SS1 is multiplexed with EXT_DMAGRANT. CSPI1_RDY Serial Data Ready signal. Also multiplexed with EXT_DMAREQ. CSPI2_MOSI Master Out/Slave In signal. This signal is multiplexed with USBH2_TXDP signal of USB OTG. CSPI2_MISO Master In/Slave Out signal. This signal is multiplexed with USBH2_TXDM signal of USB OTG. CSPI3_MOSI Master Out/Slave In signal. This signal is multiplexed with SD1_CMD. CSPI3_MISO Master In/Slave Out signal. This signal is multiplexed with SD1_D0. CSPI3_SS Slave Select (Selectable polarity) signal multiplexed with SD1_D3. CSPI3_SCLK Serial Clock signal. This signal is multiplexed with SD1_CLK. and SYS_CLK2 signal of SSI1 and SSI2. The pin name of this signal is simply TOUT. TOUT2 Timer Output signal from General Purpose Timer1 (GPT2). This signal is multiplexed with PWMO. TOUT3 Timer Output signal from General Purpose Timer1 (GPT3). This signal is multiplexed with PWMO. USB_BYP USB Bypass input active low signal. This signal can only be used for USB function, not for GPIO. USB_OC USB Over current input signal. This signal can only be used for USB function, not for GPIO. USBG_RXDP USB OTG Receive Data Plus input signal. This signal is muxed with SLCDC1_DAT15. USBG_RXDM USB OTG Receive Data Minus input signal. This signal is muxed with SLCDC1_DAT14. USBG_TXDP USB OTG Transmit Data Plus output signal. This signal is muxed with SLCDC1_DAT13. USBG_TXDM USB OTG Transmit Data Minus output signal. This signal is muxed with SLCDC1_DAT12. USBG_RXDAT USB OTG Transceiver differential data receive signal. Multiplexed with CSPI1_SS2.
USBG_OE USB OTG Output Enable signal. This signal is muxed with SLCDC1_DAT11. USBG_ON USB OTG Transceiver ON output signal. This signal is muxed with SLCDC1_DAT9. signal of USB OTG. This signal is muxed with SLCDC1_DAT10. by programming the Function Multiplexing Control Register in the System Control chapter. an alternative multiplex for UART4_CTS. by programming the Function Multiplexing Control Register in the System Control chapter. USBH1_TXDM USB Host1 Transmit Data Minus output signal. Multiplexed with UART4_TXD and SLCDC1_DAT3. USBH1_RXDAT USB Host1 Transceiver differential data receive signal. Multiplexed with USBH1_FS. USBH1_OE USB Host1 Output Enable signal. This signal is muxed with SLCDC1_DAT2. USBH_ON USB Host transceiver ON output signal. This signal is muxed with SLCDC1_DAT0. USBH2_RXDP USB Host2 Receive Data Plus input signal. This signal is multiplexed with CSPI2_SS[1] of CSPI2. USBH2_RXDM USB Host2 Receive Data Minus input signal. This signal is multiplexed with CSPI2_SS[2] of CSPI2. USBH2_TXDP USB Host2 Transmit Data Plus output signal. This signal is multiplexed with CSPI2_MOSI of CSPI2. USBH2_TXDM USB Host2 Transmit Data Minus output signal. This signal is multiplexed with CSPI2_MISO of CSPI2. USBH2_OE USB Host2 Output Enable signal. This signal is multiplexed with CSPI2_SCLK of CSPI2. USBH2_FS USB Host2 Full Speed output signal. This signal is multiplexed with CSPI2_SS[0] of CSPI2. USBG_SCL USB OTG I2C Clock input/output signal. This signal is multiplexed with SLCDC1_DAT8. USBG_SDA USB OTG I2C Data input/output signal. This signal is multiplexed with SLCDC1_DAT7. USBG_TXR_INT USB OTG transceiver interrupt input. Multiplexed with USBG_FS. multiplexed with CSPI3_MOSI. SD1_CLK SD Output Clock. This signal is multiplexed with CSPI3_SCLK. with CSPI3_SS while SD1_D[0] is muxed with CSPI3_MISO. SD2_CMD SD Command bidirectional signal. This signal is multiplexed with SLCDC1_CS signal from SLCDC1. SD2_CLK SD Output Clock signal. This signal is multiplexed with SLCDC1_CLK signal from SLCDC1.
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UART2_RXD Receive Data input signal. This signal is multiplexed with KP_ROW6 signal from KPP . UART2_TXD Transmit Data output signal. This signal is multiplexed with KP_COL6 signal from KPP . UART2_RTS Request to Send input signal. This signal is multiplexed with KP_ROW7 signal from KPP . UART2_CTS Clear to Send output signal. This signal is multiplexed with KP_COL7 signal from KPP . UART3_RXD Receive Data input signal. This signal is multiplexed with IR_RXD from FIRI. UART3_TXD Transmit Data output signal. This signal is multiplexed with IR_TXD from FIRI. UART4_RXD Receive Data input signal which is multiplexed with USBH1_RXDP and USBH1_TXDP . UART4_TXD Transmit Data output signal which is multiplexed with USBH1_TXDM. UART4_RTS Request to Send input signal which is multiplexed with USBH1_FS and USBH1_RXDP . UART4_CTS Clear to Send output signal which is multiplexed with USBH1_TXDP and USBH1_RXDM. SYS_CLK1 SSI1 master clock. Multiplexed with TOUT. SSI2_CLK Serial clock signal which is output in master or input in slave. SSI2_FS Frame Sync signal which is output in master and input in slave. SYS_CLK2 SSI2 master clock. Multiplexed with TOUT. SSI3_FS Frame Sync signal which is output in master and input in slave. Multiplexed with SLCDC2_D0. SAP_CLK Serial clock signal which is output in master or input in slave. SAP_FS Frame Sync signal which is output in master and input in slave.
OWIRE 1-Wire input and output signal. This signal is multiplexed with JTAG RTCK. of the General Purpose Timer module. PF[16] Dedicated GPIO. When unused, program this signal as an input with the on-chip pull-up resistor enabled. the alternate signal multiplexing) to choose which signals KP_ROW6 and KP_ROW7 are available. NVDD Noisy Supply for the I/O pins. There are six (6) I/O voltages, NVDD1 through NVDD6.
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3 Specifications
This section contains the electrical specifications and timing diagrams for the i.MX21 processor.
3.1 Maximum Ratings
Table 3 provides the maximum ratings. maximum-rated conditions for extended periods may affect device reliability.
3.2 Recommended Operating Range
enclosed I/O pads. This design allows different peripheral supply voltage levels in a system. the VDDA pins from other VDD pins. For more information about I/O pads grouping per VDD, please refer to Table 4. Table 3. Maximum Ratings
- VDD is the supply voltage associated with the input. See Signal Multiplexing Scheme table in the reference manual.
3 Storage Temperature Range T storage -55 150 oC
Table 4. 266 MHz Recommended Operating Range
3.3 DC Electrical Characteristics
Table 5 contains the DC characteristics of the i.MX21. Table 6 shows the input and output capacitance for the device. Table 5. DC Characteristics
- Data labeled Typical is not guaranteed, but is intended as an indication of the IC's potential performance.
- For DSCR definition refer to the System Control chapter in the reference manual.
Table 6. Input/Output Capacitance
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Table 7 shows the power consumption for the device.
3.4 AC Electrical Characteristics
with an operating supply voltage from VDD min to VDD max under an operating temperature from TL to TH. to the reference manual’s System Control Chapter for details on drive strength settings. other signals required to meet 133 MHz timing. taken to minimize parasitic capacitance of associated printed circuit board traces. Table 7. Power Consumption 1 Run Current QVDD = QVDDX = 1.65V, NVDD1 = 1.8V. NVDD2 through NVDD6 = VDDA = 3.1V. Core = 266 MHz, System = 133 MHz. 2 Sleep Current Standby current with Well Biasing System enabled.
- TA = 70°C for suffixes VK, VM, DVK, DVM, and SVK. TA = 85°C for suffixes CVK, CVM, and SCVK.
Table 8. Loading Guidelines for Fast IO Signals to Achieve 133MHz Operation
3.5 DPLL Timing Specifications
predivider and Tdck is the output double clock period. Table 9. 32k/26M Oscillator Signal Timing Table 10. CLKO Rise/Fall Time (at 30pF Loaded) Table 11. DPLL Specifications
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3.6 Reset Module
Figure 3. Be aware that NVDD must ramp up to at least 1.7V for NVDD1 and 2.7V for NVDD2-6 before QVDD is powered up to prevent forward biasing. Figure 2. Timing Relationship with POR Figure 3. Timing Relationship with RESET_IN
3.7 External DMA Request and Grant
request the DMAC for data transfer. device using the External DMA request should keep its request asserted until it is serviced by the DMAC. One External DMA request will initiate one DMA burst. are true, the External DMA Grant signal is asserted with the initiation of the DMA burst.
- The DMA channel for which the DMA burst is ongoing has request source as external DMA Request (as per source select register setting).
- REN and CEN bit of this channel are set.
- External DMA Request is asserted. After the grant is asserted, the External DMA request will not be sampled until completion of the DMA burst. As the external request is synchronized, the request synchronization will not be done during this period. The priority of the external request becomes low for the next consecutive burst, if another DMA request signal is asserted. Worst case—that is, the smallest burst (1 byt e read/write) timing diagrams are shown in Figure 4 and
Figure 5. Minimum and maximum timings for the External request and External grant signals are present DMA request is de-asserted immediately after sensing grant signal active. Table 12. Reset Module Timing Parameters
1 Width of input POWER_ON_RESET 800 – 800 – ms
2 Width of internal POWER_ON_RESET
5 Width of external hard-reset RESET_IN 4–4– C y c l e s o f C L K 3 2
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Figure 4. Assertion of DMA External Grant Signal sensing grant signal active such that a new burst is not initiated. Figure 5. Safe Maximum Timings for External Request De-Assertion
3.8 BMI Interface Timing Diagram
3.8.1 Connecting BMI to ATI MMD Devices
3.8.1.1 ATI MMD Devices Drive the BMI_CLK/CS
Table 13. DMA External Request and Grant Timing Parameters NOTE: Assuming in worst case the data is read/written from/to External device as per the above waveform.
happens, the new coming data is ignored.
3.8.1.1.1 MMD Read BMI Timing
Figure 6 shows the MMD read BMI timing when the MMD drives clock. Figure 6. MMD (ATI) Drives Clock, MMD Read BMI Timing Note: All the timings assume that the hclk is running at 133 MHz. Note: The MIN period of the 1T is assumed that MMD latch data at falling edge. are slow pads and it max frequency can only up to 18MHz, the max clock frequency can only up to 36 MHz. Table 14. MMD Read BMI Timing Table when MMD Drives Clock
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3.8.1.1.2 MMD Write BMI Timing
WRITE is logic low, it latches data into the RxFIFO on each falling edge of BMI_CLK/CS signal. Figure 7. MMD (ATI) Drives Clock, MMD Write BMI Timing Note: All timings assume that the hclk is running at 133 MHz. Note: At this mode, the maximum frequency of the BMI_CLK/CS can be up to 36 MHz (doubles as maximum data pad speed).
3.8.1.2 BMI Drives the BMI_CLK/CS
issue a write cycle (MMD write BMI).
3.8.1.3 MMD Read BMI Timing
can latch the data on each falling edge of BMI_CLK/CS. will drive BMI_CLK/CS out once the BMI_WRITE is changed from low to high. Table 15. MMD Write BMI Timing
Figure 8. BMI Drives Clock, MMD Read BMI Timing Note: In this mode, the max frequency of the BMI_CLK/CS can be up to 36MHz (double as max data pad speed). Note: The BMI_CLK/CS can only be divided by 2,4,8,16 from HCLK.
3.8.1.4 MMD Write BMI Timing
Figure 9 shows the MMD write BMI timing when BMI drives BMI_CLK/CS. MMD still has data to write after the first operation completed. latch the last data using the internal clock. BMI_WRITE signal can not be negated when the WRITE operation is proceeding. Table 16. MMD Read BMI Timing Table when BMI Drives Clock
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Figure 9. BMI Drives Clock, MMD Write BMI Timing data pad speed) if BMI latch data at the next rising edge. Note: Tds1 is the receive data setup time when BMI latch data at the falling edge. Note: Tds2 is the receive data setup time when BMI latch data at the next rising edge.
3.8.2 Connecting BMI to Exte rnal Bus Master Devices
CS is logic low and BMI_WRITE is logic high. Each rising edge of BMI_CLK/CS will determine if data should be latched to RxFIFO from the data bus. Table 17. MMD Write BMI Timing Table when BMI Drives Clock
Figure 10. Memory Interface Slave Mode, External Bus Master Read/Write to BMI Timing Note: All the timings are assumed that the hclk is running at 133 MHz.
3.8.3 Connecting BMI to External Bus Slave Devices
write cycles are continuously generated when TxFIFO is not emptied. cannot begin until this read cycle complete. Table 18. External Bus Master Read/Write to BMI Timing Table
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3.8.3.1 Memory Interface Master Mode Without WAIT Signal
shows the BMI timing when the WAIT bit is cleared. Figure 11. Memory Interface Master Mode, BMI Read/Write to External Slave Device Timing without Wait
3.8.3.2 Memory Interface Master Mode with WAIT Signal
sampling a logic high BMI_WAIT signal. Figure 12 shows the BMI write timing when the WAIT bit is set.
Figure 12. Memory Interface Master Mode, BMI Write to External Slave Device Timing with Wait Signal without WAIT signal. So the BMI_READ will be asserted at least for 1+WS Int_Clk period. Figure 13. Memory Interface Master Mode, BMI Read to External Slave Device Timing with Wait Signal
3.9 CSPI Timing Diagrams
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as well as to increment the data FIFO. Figure 14. Master CSPI Timing Diagram Using SPI_RDY Edge Trigger Figure 15. Master CSPI Timing Diagram Using SPI_RDY Level Trigger Figure 16. Master CSPI Timing Diagram Ignore SPI_RDY Level Trigger Figure 17. Slave CSPI Timing Diagram FIFO Advanced by BIT COUNT Figure 18. Slave CSPI Timing Diagram FIFO Advanced by SS Rising Edge
3.10 LCD Controller
Figure 19. SCLK to LD Timing Diagram Table 19. Timing Parameters for Figure 14 through Figure 18
1 SPI_RDY to SS output low 2T 1
- T = CSPI system clock period (PERCLK2).
3 Last SCLK edge to SS output high 2·Tsclk – ns
- WAIT = Number of bit clocks (SCLK) or 32.768 kHz clocks per Sample Period Control
Table 20. LCDC SCLK Timing Parameters The pixel clock is equal to LCDC_CLK / (PCD + 1). When it is in CSTN, TFT or monochrome mode with bus width = 1, SCLK is equal to the pixel clock. When it is in monochrome with other bus width settings, SCLK is equal to the pixel clock divided by bus width. The polarity of SCLK and LD can also be programmed. Maximum frequency of SCLK is HCLK / 3 for TFT and CSTN, otherwise LD output will be incorrect.
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Figure 20. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing Table 21. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing VSYN, HSYN and OE can be programmed as active high or active low. In Figure 20, all 3 signals are active low. XMAX is defined in number of pixels in one line.
Figure 21. Sharp TFT Panel Timing Table 22. Sharp TFT Panel Timing Falling of SPL/SPR aligns with first LD of line. Falling of PS aligns with rising edge of CLS. REV toggles in every HSYN period.
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Figure 22. Non-TFT Mode Panel Timing Table 23. Non-TFT Mode Panel Timing Ts is the SCLK period while Tpix is the pixel clock period. When it is in CSTN mode or monochrome mode with bus width = 1, T3 = Tpix = Ts. When it is in monochrome mode with bus width = 2, 4, and 8, T3 = 1, 2 and 4 Tpix respectively.
3.11 Smart LCD Controller
Figure 23. SLCDC Serial Transfer Timing
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Figure 24. SLCDC Parallel Transfers Timing Table 24. SLCDC Serial Transfer Timing Table 25. SLCDC Parallel Transfers Timing
3.12 Multimedia Card/Secure Digital Host Controller
SD module (inner system) and the application (user programming). Figure 25. Chip-Select Read Cycle Timing Diagram Table 26. SDHC Bus Timing Parameters
1 CLK frequency at Data transfer Mode (PP) 1— 10/30 cards
2 CLK frequency at Identification Mode 2
7 Output delay time 3 0 16 0 14 ns
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3.12.1 Command Response Timing on MMC/SD Bus
Figure 30 are defined in Table 27. Figure 26. Timing Diagrams at Identification Mode responding card. The other two diagrams show the separating periods NRC and NCC. Table 27. State Signal Parameters for Figure 26 through Figure 30
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Figure 28. Timing Diagrams at Data Read block mode, with the flow terminated by a stop transmission command.
Figure 29. Timing Diagrams at Data Write different scenarios on the bus.
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Figure 30. Stop Transmission During Different Scenarios Table 28. Timing Values for Figure 26 through Figure 30 Stop transmission received after last data block. Card becomes busy programming. Stop transmission received after last data block. Card becomes busy programming.
3.12.2 SDIO-IRQ and ReadWait Service Handling
continues until the source is removed (SD_DAT[1] returns to its high level). Figure 31. SDIO IRQ Timing Diagram Figure 32. SDIO ReadWait Timing Diagram Table 28. Timing Values for Figure 26 through Figure 30 (Continued)
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3.13 External Memory Interface (EMI) Electricals
3.13.1 NAND-Flash Controller (NFC) Interface
which drives the CPU clock (FCLK) that is fed through the NFCDIV block to generate the NFC clock. 66 MHz. It should also be noted that the default NFC clock on power up is 16.63 MHz. Figure 33. Command Latch Cycle Timing DIagram
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Table 29. NFC Target Timing Parameters1,2
- High is defined as 80% of signal value and low is defined as 20% of signal value. All timings are listed according to this NFC
clock frequency (multiples of NFC clock period) except NF16, which is not NFC clock related.
- The read data is generated by the NAND Flash device and sampled with the internal NFC clock.
22.17 MHz
33.25 MHz
3.14 Pulse-Width Modulator
available at the pulse-width modulator output (PWMO) external pin. Figure 37. PWM Output Timing Diagram Table 30. PWM Output Timing Parameters
1 System CLK frequency 1
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3.15 SDRAM Memory Controller
to the SDRAMC module in the i.MX21. Figure 38. SDRAM Read Cycle Timing Diagram Table 31. SDRAM Read Cycle Timing Parameter Note: CKE is high during the read/write cycle.
Figure 39. SDRAM Write Cycle Timing Diagram
5 SDRAM access time (CL = 1) – – – – ns
6 Data out hold time
7 Data out high-impedance time (CL = 3) – t HZ
7 Data out high-impedance time (CL = 2) – t HZ
7 Data out high-impedance time (CL = 1) – – – – ns
8 Active to read/write command period (RC = 1) t
- tHZ = SDRAM data out high-impedance time, external SDRAM memory device dependent parameter.
- tRCD = SDRAM clock cycle time. The tRCD setting can be found in the i.MX21 reference manual.
Table 31. SDRAM Read Cycle Timing Parameter (Continued)
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Figure 40. SDRAM Refresh Timing Diagram Table 32. SDRAM Write Cycle Timing Parameter
6 Precharge cycle period
- Precharge cycle timing is included in the write timing diagram.
- tRP and tRCD = SDRAM clock cycle time. These settings can be found in the i.MX21 reference manual.
7 Active to read/write command delay t RCD
Figure 41. SDRAM Self-Refresh Cycle Timing Diagram Table 33. SDRAM Refresh Timing Parameters
6 Precharge cycle period t
- tRP and tRC = SDRAM clock cycle time. These settings can be found in the i.MX21 reference manual.
7 Auto precharge command period t RC
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3.16 Synchronous Serial Interface
mode, the transmitter and receiver each have their own clock and frame synchronization signals. are shown in Figure 42 through Figure 45. communicate with a wide variety of devices. The SSI can be connected to 4 set of ports, SAP, SSI1, SSI2 and SSI3. Figure 42. SSI Transmitter Internal Clock Timing Diagram Note: SRXD input in synchronous mode only.
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Table 34. SSI to SAP Ports Timing Parameters
14 SRXD hold time after (Rx) CK low 0 – 0 – ns
30 SRXD hole time after (Rx) CK low 0 – 0 – ns
32 SRXD hold after (Tx) CK falling 0 – 0 – ns
34 SRXD hold after (Tx) CK falling 0 – 0 – ns
- All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. Table 35. SSI to SSI1 Ports Timing Parameters Table 34. SSI to SAP Ports Timing Parameters (Continued)
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- All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. Table 36. SSI to SSI2 Ports Timing Parameters Table 35. SSI to SSI1 Ports Timing Parameters (Continued)
- All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. Table 36. SSI to SSI2 Ports Timing Parameters (Continued)
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Table 37. SSI to SSI3 Ports Timing Parameters
3.17.1 Reset Sequence with Reset Pulse Presence Pulse
The timing diagram for this sequence is shown in Figure 46. Figure 46. 1-Wire Initialization The reset pulse begins the initialization sequence and it is initiated when the RPP control register bit is set. to determine if at least one DS2502 is connected. Software will determine if more than one DS2502 exists.
- All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. Table 37. SSI to SSI3 Ports Timing Parameters (Continued)
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a zero, then no device was found.
3.17.2 Write 0
Figure 47. Write 0 Timing complete, the WR0 register will be auto cleared.
3.17.3 Write 1/Read Data
the 1 generated by the bus master (one-wire). completed. After a Read, the control register RDST bit is set to the value of the read. Figure 48. Write 1 Timing
Figure 49. Read Timing The precision of the generated clock is very important to get a proper behavior of the one-wire module. This module is based on a state machine which undertakes actions at defined times. The most stringent constraint is 0.0645 as a relative time imprecision. The Figure 39 gathers relative time precision for different main clock frequencies. the main clock is an exact integer multiple of 1 MHz, then the generated frequency will be exactly 1 MHz. A main clock frequency below 10 MHz might cause a misbehavior of the module. Table 38. System Timing Requirements Table 39. System Clock Requirements
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3.18 USB On-The-Go
covers the transfer modes and how they work from the ground up. all times, there is no end-of-transfer. Figure 50. USB Timing Diagram for Data Transfer to USB Transceiver (TX) Table 40. USB Timing Parameters for Data Transfer to USB Transceiver (TX)
Figure 51. USB Timing Diagram for Data Transfer from USB Transceiver (RX) Data Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP. Figure 52. USB Timing Diagram for Data Transfer from USB Transceiver (I2C) Table 41. USB Timing Parameters for Data Transfer from USB Transceiver (RX) Table 42. USB Timing Parameters for Data Transfer from USB Transceiver (I2C)
1 Hold time (repeated) START condition 188 – ns
2 Data hold time 0 188 ns
3 Data setup time 88 – ns
4 HIGH period of the SCL clock 500 – ns
5 LOW period of the SCL clock 500 – ns
6 Setup time for STOP condition 185 – ns
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3.19 External Interface Module (EIM)
in Figure 53, and Table 43 defines the parameters of signals. Figure 53. EIM Bus Timing Diagram
Table 43. EIM Bus Timing Parameters
0.1 V Unit
- Clock refers to the system clock signal, HCLK, generated from the System DPLL
11 Burst Clock (BCLK) cycle time 15 – – 15 – – ns
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3.19.1 EIM External Bus Timing Diagrams
The following timing diagrams show the timing of accesses to memory or a peripheral. Figure 54. WSC = 1, A.HALF/E.HALF Note: Signals listed with lower case letters are internal to the device.
Figure 55. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF Note: Signals listed with lower case letters are internal to the device.
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Figure 56. WSC = 1, OEA = 1, A.WORD/E.HALF Note: Signals listed with lower case letters are internal to the device.
Figure 57. WSC = 1, WEA = 1, WEN = 1, A.WORD/E.HALF Note: Signals listed with lower case letters are internal to the device.
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Figure 58. WSC = 3, OEA = 2, A.WORD/E.HALF Note: Signals listed with lower case letters are internal to the device.
Figure 59. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF Note: Signals listed with lower case letters are internal to the device.
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Figure 60. WSC = 3, OEA = 4, A.WORD/E.HALF Note: Signals listed with lower case letters are internal to the device.
Figure 61. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF Note: Signals listed with lower case letters are internal to the device.
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Figure 62. WSC = 3, OEN = 2, A.WORD/E.HALF Note: Signals listed with lower case letters are internal to the device.
Figure 63. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF Note: Signals listed with lower case letters are internal to the device.
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Figure 64. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF Note: Signals listed with lower case letters are internal to the device.
Figure 65. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF Note: Signals listed with lower case letters are internal to the device.
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Figure 66. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF Note: Signals listed with lower case letters are internal to the device.
Figure 67. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF Note: Signals listed with lower case letters are internal to the device.
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Figure 68. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF Note: Signals listed with lower case letters are internal to the device.
Figure 69. WSC = 3, CSA = 1, A.HALF/E.HALF Note: Signals listed with lower case letters are internal to the device.
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Figure 70. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF Note: Signals listed with lower case letters are internal to the device.
Figure 71. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF Note: Signals listed with lower case letters are internal to the device.
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Figure 72. WSC = 3, SYNC = 1, A.HALF/E.HALF Note: Signals listed with lower case letters are internal to the device.
Figure 73. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD Note: Signals listed with lower case letters are internal to the device.
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Figure 74. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF Note: Signals listed with lower case letters are internal to the device.
Figure 75. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF Note: Signals listed with lower case letters are internal to the device.
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Figure 76. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF Note: Signals listed with lower case letters are internal to the device.
MC9328MX21 Technical Data, Rev. 3.1 Freescale Semiconductor 87
3.20 DTACK Mode Memory Access Timing Diagrams
When enabled, the DTACK input signal is used to externally terminate a data transfer. For DTACK enabled operations, a bus time-out monitor generates a bus error when an external bus cycle is not terminated by the DTACK input signal after 1024 HCLK clock cycles have elapsed, where HCLK is the internal system clock driven from the PLL module. For a 133 MHz HCLK setting, this time equates to 7.7 μs. Refer to the Section 3.5, “DPLL Timing Specifications” for more information on how to generate different HCLK frequencies. There are two modes of operation for the DTACK input signal: rising edge detection or level sensitive detection with a programmable insensitivity time. DTACK is only used during external asynchronous data transfers, thus the SYNC bit in the chip select control registers must be cleared. During edge detection mode, the EIM will terminate an external data transfer following the detection of the DTACK signal’s rising edge, so long as it occurs within the 1024 HCLK cycle time. Edge detection mode is used for devices that follow the PCMCIA standard. Note that DTACK rising edge detection mode can only be used for CS[5] operations. To configure CS[5] for DTACK rising edge detection, the following bits must be programmed in the Chip Select 5 Control Register and EIM Configuration Register:
- WSC bit field set to 0x3F and CSA (or CSN) set to 1 or greater in the Chip Select 5 Control Register
- AGE bit set in the EIM Configuration Register Other bits such as DSZ, OEA, OEN, and so on, may be set according to system and timing requirements of the external device. The requirement of setting CSA or CSN is required to allow the EIM to wait for the rising edge of DTACK during back-to-back external transfers, such as during DMA transfers or an internal 32-bit access through an external 16-bit data port. During level sensitive detection, the EIM will first hold off sampling the DTACK signal for at least 2 HCLK cycles, and up to 5 HCLK cycles as programmed by the DCT bits in the Chip Select Control Register. After this insensitivity time, the EIM will sample DTACK and if it detects that DTACK is logic high, it will continue the data transfer at the programmed number of wait states. However, if the EIM detects that DTACK is logic low, it will wait until DTACK goes to logic high to continue the access, so long as this occurs within the 1024 HCLK cycle time. If at anytime during an external data transfer DTACK goes to logic low, the EIM will wait until DTACK returns to logic high to resume the data transfer. Level detection is often used for asynchronous devices such graphic controller chips. Level detection may be used with any chip select except CS[4] as it is multiplexed with the DTACK signal. To configure a chip select for DTACK level sensitive detection, the following bits must be programmed in the Chip Select Control Register and EIM Configuration Register:
- EW bit set, WSC set to > 1, and CSN set to < 3 in the Chip Select Control Register
- BCD/DCT set to desired “insensitivity time” in the Ch ip Select Control Register. The “insensitivity time” is dictated by the external device’s timing requirements.
- AGE bit cleared in the EIM Configuration Register Other bits such as DSZ, OEA, OEN, and so on, may be set according to system and timing requirements of the external device. The waveforms in the following section provide examples of the DTACK signal operation.
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3.20.1 DTACK Example Waveforms: Inte rnal ARM AHB Word Accesses to
Figure 77. DTACK Edge Triggered Read Access, WSC=3F, OEA=8, OEN=5, AGE=1.
Figure 78. DTACK Level Sensitive Sequential Read Accesses, WSC=2, EW=1, DCT=1, AGE=0 (Example of
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Figure 79. DTACK Level Sensitive Sequential Write Accesses, WSC=2, EW=1, RWA=1, RWN=1, DCT=1,
3.21 I 2C Module
Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP. Figure 80. Definition of Bus Timing for I2C
3.22 CMOS Sensor Interface
3.22.1 Gated Clock Mode
Table 44. I2C Bus Timing Parameters
2 Data hold time
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Figure 81. Sensor Output Data on Pixel Clock Falling Edge Figure 82. Sensor Output Data on Pixel Clock Rising Edge Table 45. Gated Clock Mode Timing Parameters
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
3.22.2 Non-Gated Clock Mode
Figure 83. Sensor Output Data on Pixel Clock Falling Edge
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Figure 84. Sensor Output Data on Pixel Clock Rising Edge
3.22.3 Calculation of Pixel Clock Rise/Fall Time
- max rise time allowed = (pos itive duty cycle - hold time)
- max fall time allowed = (nega tive duty cycle - setup time) In most of case, duty cycle is 50 / 50, therefore:
- max rise time = (period / 2 - hold time)
- max fall time = (period / 2 - setup time) For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns. positive duty cycle = 10 / 2 = 5ns ≥ max rise time allowed = 5 - 1 = 4ns negative duty cycle = 10 / 2 = 5ns ≥ max fall time allowed = 5 - 1 = 4ns Falling-edge latch data
- max fall time allowed = (nega tive duty cycle - hold time)
- max rise time allowed = (pos itive duty cycle - setup time)
Table 46. Non-Gated Clock Mode Parameters1
- HCLK = AHB System Clock, THCLK = Period of HCLK
4 Pin Assignment and Package Information
Table 47. i.MX21 Pin Assignment
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4.1 MAPBGA Package Dimensions
Figure 85 illustrates the MAPBGA 14 mm × 14 mm × 1.41 mm package, which has 0.65 mm ball pitch. Figure 85. i.MX21 MAPBGA Mechanical Drawing
4.2 MAPBGA Package Dimensions
Figure 86. i.MX21 MAPBGA Mechanical Drawing
81829 Muenchen, Germany
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including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. negligent regarding the design or manufacture of the part. © Freescale Semiconductor, Inc. 2005, 2006. All rights reserved.
5 Document Revision History
Table 48 provides the document changes for the MC9328MX21 Rev. 3.1. Table 48. Document Revision History Page 10 Removed table referenceing Tri-State™ signal timing.