MC9328MX1 FREESCALE | Alldatasheet
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© Freescale Semiconductor, Inc., 2004. All rights reserved. This document contains information on a new product. Specifications and information herein are subject to change without notice. Freescale Semiconductor Advance Information MC9328MX1/D Rev. 4, 08/2004 MC9328MX1
Package Information
(MAPBGA–256)
Ordering Information
1 Introduction
Motorolas i.MX family of microprocessors has demonstrated leadership in the portable handheld market. Continuing this legacy, the i.MX series provides a leap in performance with an ARM9 microprocessor core and highly integrated system functions. The i.MX products specifically address the requirements of the personal, portable product market by providing intelligent integrated peripherals, an advanced processor core, and power management capabilities. The new MC9328MX1 features the advanced and power- efficient ARM920T core that operates at speeds up to 200 MHz. Integrated modules, which include an LCD controller, static RAM, USB support, an A/D converter (with touch panel control), and an MMC/SD host controller, support a suite of peripherals to enhance any product seeking to provide a rich multimedia experience. In addition, the MC9328MX1 is the first Bluetooth technology-ready applications processor. It is packaged in a 256-pin Mold Array Process-Ball Grid Array (MAPBGA). Figure 1 on page 2 shows the functional block diagram of the MC9328MX1. MC9328MX1/D Rev. 3.0, 12/2003 MC9328MX1 (i.MX1) Integrated Portable System Processor
Contents
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Figure 1. MC9328MX1 Functional Block Diagram
1.1 Conventions
OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET. Logic level one is a voltage that corresponds to Boolean true (1) state. Logic level zero is a voltage that corresponds to Boolean false (0) state. T o set a bit or bits means to establish logic level one. T o clear a bit or bits means to establish logic level zero. A signal is an electronic construct whose state conveys or changes in state convey information. A pin is an external physical connection. The same pin can be used to connect a number of signals. Asserted means that a discrete signal is in active logic state. Active low signals change from logic level one to logic level zero. Active high signals change from logic level zero to logic level one. Negated means that an asserted discrete signal changes logic state. Active low signals change from logic level zero to logic level one. Active high signals change from logic level one to logic level zero. high bytes or words are spelled out.
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 3
1.2 Features
To support a wide variety of applications, the MC9328MX1 provides a robust array of features, including the following: ARM920T Microprocessor Core AHB to IP Bus Interfaces (AIPIs) External Interface Module (EIM) SDRAM Controller (SDRAMC) DPLL Clock and Powe r Control Module Three Universal Asynchronous Receiver/Transmitters (UART 1 UART 2 and UART 3) Two Serial Periphera l Interfaces (SPI) Two General-Purpose 32-bit Counters/Timers Watchdog Timer Real-Time Clock/Sampling Timer (RTC) LCD Controller (LCDC) Pulse-Width Modulation (PWM) Module Universal Serial Bus (USB) Device Multimedia Card and Secure Digita l (MMC/SD) Host Controller Module Memory Stick® Host Controller (MSHC) SmartCard Interf ace Module (SIM) Direct Memory Access Controller (DMAC) Two Synchronous Serial Interfaces and Inter-IC Sound (SSI 1 and SSI 2/I 2S) Module Inter-IC (I 2C) Bus Module V i d e o P o r t General-Purpose I/O (GPIO) Ports Bootstrap Mode Analog Signal Processing (ASP) Module Bluetooth Accelerator (BTA) Multimedia Accelerator (MMA) 256-pin MAPBGA Package
1.3 Target Applications
The MC9328MX1 is targeted for advanced information appliances, smart phones, Web browsers, digital MP3 audio players, handheld computers based on the popular Palm OS platform, and messaging applications such as Motorola's wireless cellular products, including the AccompliTM 008 GSM/GPRS interactive communicator.
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1.4 Document Revision History
and not stylistic or grammatical changes.
1.5 Product Documentation
products, the following documents are helpful when used in conjunction with this manual. Table 1. MC9328MX1 Data Sheet Revision History Throughout Clarified instances where BCLK signal is burst clock. Table 4 on page 14 Maximum Ratings table replaced. Added “Important” note regarding no software support for the BTA.
1.6 Ordering Information
Table 2 provides ordering information for the 256-lead mold array process ball grid array (MAPBGA) package. Table 2. MC9328MX1 Ordering Information
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2 Signals and Connections
grouped by the internal module that they are connected to. Table 3. Signal Names and Descriptions the Function Multiplexing Control Register (FMCR). By default CSD [1:0] is selected. on-going burst sequence and initiate a new (long first access) burst sequence. BCLK (burst clock) Clock signal sent to external synchronous memories (such as burst flash) during burst mode. input signal by external DRAM. reset is determined by the settings of these pins. SDBA [4:0] SDRAM/SyncFlash non-interleave mode bank address multiplexed with address signals A [15:11]. These signals are logically equivalent to core address p_addr [25:21] in SDRAM/SyncFlash cycles.
are selectable by programming the system control register. used as SyncFlash boot chip select by properly configuring BOOT [3:0] input pins. modules (except the reset module and the clock control module) are reset. the following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out. generated by an external RC circuit designed to detect a power-up event. TRST Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller. TDO Serial Output for test instructions and data. Changes on the falling edge of TCK. TDI Serial Input for test instructions and data. Sampled on the rising edge of TCK. Table 3. Signal Names and Descriptions (Continued)
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TCK Test Clock to synchronize test logic and control register access through the JTAG port. ETMTRACESYNC ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode. ETMTRACECLK ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode. ETMTRACEPKT [7:0] ETM packet signals which are multiplex with ECB, LBA, BCLK (burst clock), PA17, A [19:16]. ETMTRACEPKT [7:0] are selected in ETM mode. LD [15:0] LCD Data Bus—All LCD signals are driven low after reset and when LCD is off. FLM/VSYNC Frame Sync or Vsync—This signal also serves as the clock signal output for gate. driver (dedicated signal SPS for Sharp panel HR-TFT). CONTRAST This signal is used to control the LCD bias voltage as contrast control. SPL_SPR Program horizontal scan direction (Sharp panel dedicated signal).
PS Control signal output for source driver (Sharp panel dedicated signal). CLS Start signal output for gate driver. This signal is invert version of PS (Sharp panel dedicated signal). REV Signal for common electrode driving signal preparation (Sharp panel dedicated signal). (IOMUX),” for information on how to bring this signal to the assigned pin. (IOMUX),” for information on how to bring this signal to the assigned pin. (IOMUX),” for information on how to bring this signal to the assigned pin. (IOMUX),” for information on how to bring this signal to the assigned pin.
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Pull-up enable register, a 4.7K–69K external pull up resistor must be added. enable register, a 50 K–69K external pull up resistor must be added. purposes, not for use in application mode.
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TRISTATE Sets all I/O pins to tristate; Can be used for flash loading and is pulled low for normal operations.
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3 Specifications
This section contains the electrical specifications and timing diagrams for the MC9328MX1 processor.
3.1 Maximum Ratings
page 15 or the DC Characteristics table. Table 4. Maximum Ratings1
- Voltages referenced to Vss and BTRFGND, wh ich are both tied to the same potential.
- A typical application with 30 pads simultaneously switch ing assumes the GPIO toggling and instruction fetches from
the ARM core-that is, 7x GPIO, 15x Data bus, and 8x Address bus.
- A worst-case application with 70 pads simultaneously s witching assumes the GPIO toggling and instruction fetches
max 5mA is consumed for OSC pads, with each toggle GPIO consuming 4mA.
3.2 Recommended Operating Range
multiple pairs of VDD and VSS power supply and return pins. QVDD and QVSS pins are used for internal logic. to the enclosed I/O pads. This design allows different peripheral supply voltage levels in a system. AVDD pins from other VDD pins. Bluetooth pins can be used as general purpose I/O pins and BTRFVDD can be used as other NVDD pins. For more information about I/O pads grouping per VDD, please refer to Table 3 on page 6.
3.3 Power Sequence Requirements
application note AN2537 on the i.MX website page.
3.4 DC Electrical Characteristics
Table 6 contains both maximum and minimum DC characteristics of the MC9328MX1. Table 5. Recommended Operating Range 1
- Voltages referenced to Vss and BTRFGND, wh ich are both tied to the same potential.
150 MHz)
200 MHz)
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Table 6. Maximum and Minimum DC Characteristics Power Performance of MC9328MX1.
3.5 AC Electrical Characteristics
from VDD min to VDD max under an operating temperature from TL to TH. All timing is measured at 30 pF loading. Table 7. Tri-State Signal Timing Table 8. 32k/16M Oscillator Signal Timing Table 9. CLKO Rise/Fall Time (at 30pF Loaded)
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3.6 Embedded Trace Macrocell
and a 1 into the read/write bit. Figure 2. Figure 2. Trace Port Timing Diagram Table 10. Trace Port Timing Diagram Parameter Table
1 CLK frequency 0 85 0 100 MHz
3.7 DPLL Timing Specifications
and Tdck is the output double clock period. Table 11. DPLL Specifications
300 T ref
270 T ref
400 T ref
370 T ref
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3.8 Reset Module
The timing relationships of the Reset module with the POR and RESET_IN are shown in Figure 3 and Figure 4. Figure 3. Timing Relationship with POR
Figure 4. Timing Relationship with RESET_IN Table 12. Reset Module Timing Parameter Table
1 Width of input POWER_ON_RESET note1
- POR width is dependent on the 32 or 32.768 kHz cryst al oscillator start-up time. Design margin should
allow for crystal toleranc e, i.MX chip variations, temperature impact, and supply voltage influence. 400 ms to 1.2 seconds for this type of crystal. be ignored in calculating timing for the start-up process.
2 Width of internal POWER_ON_RESET
5 Width of external hard-reset RESET_IN 4 – 4 – Cycles of
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3.9 External Interface Module
Figure 5, and Table 13 defines the parameters of signals. Figure 5. EIM Bus Timing Diagram Table 13. EIM Bus Timing Parameter Table
- Clock refers to the system clock signal , HCLK, generated from the System DPLL
Table 13. EIM Bus Timing Parameter Table (Continued)
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3.9.1 DTACK Signal Description
function when the external DTACK signal is used for data acknowledgement.
3.9.2 DTACK Signal Timing
measure for this figure are found in the associated tables.
3.9.2.1 DTACK READ Cycle without DMA
Figure 6. DTACK READ Cycle without DMA Table 14. Parameters for Read Cycle, WSC = 111111, DTACK_SEL=0, HKCL=96MHz
4 D T A C K asserted after CS5 asserted 1019T ns
3.9.2.2 DTACK Read Cycle DMA Enabled
Figure 7. DTACK Read Cycle DMA Enabled
6 Data hold timing after OE negated 0 ns
7 Data ready after DTACK asserted 0 T ns
10 DTACK
- DTACK assert means DTACK become low level.
- T is the system clock period. (For 96MHz system clock)
- OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur
only when EBC bit in CS5L register is clear.
- Address becomes valid and CS asserts at the start of read access cycle.
- The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
Table 14. Parameters for Read Cycle, WSC = 111111, DTACK_SEL=0, HKCL=96MHz (Continued)
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Table 15. Parameters for Read Cycle WSC = 111111, DTACK_SEL=0, HCLK=96MHz
5 D T A C K asserted after CS5 asserted 1019T ns
7 Data hold timing after OE negated 0 ns
8 Data ready after DTACK is asserted T ns
11 DTACK
- DTACK assert mean DTACK become low.
- T is the system clock period. (For 96MHz system clock)
when EBC bit in CS5L register is clear.
- Address becomes valid and CS asserts at the start of read access cycle.
- The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
3.9.2.3 DTACK Write Cycle without DMA
Figure 8. DTACK Write Cycle without DMA Table 16. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HKCL=96MHz
6 D T A C K asserted after CS5 asserted 1019T ns
9 Data ready after CS5 is asserted T ns
11 DTACK pulse width 1T 3T ns
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3.9.2.4 DTACK Write Cycle DMA Enabled
Figure 9. DTACK Write Cycle DMA Enabled
- DTACK assert mean DTACK become low.
- T is the system clock period. (For 96MHz system clock)
- CS5 assertion can be controlled by CSA bits. EB assertion can also be programmed by WEA bits in the CS5L register.
- Address becomes valid and RW asserts at the start of write access cycle.
- The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
Table 17. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HCLK=96MHz
1 C S 5 assertion time See note 2 ns
Table 16. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HKCL=96MHz (Continued)
10 CS deactive to next CS active T ns
12 DTACK pulse width 1T 3T ns
- DTACK assert mean DTACK become low.
- T is the system clock period. (For 96MHz system clock)
- CS5 assertion can be controlled by CSA bits. EB assertion also can be programmed by WEA bits in the CS5L register.
- Address becomes valid and RW asserts at the start of write access cycle.
4.The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state. Table 17. Parameters for Write Cycle WSC = 111111, DTACK_SEL=0, HCLK=96MHz (Continued)
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3.9.3 EIM External Bus Timing
The following timing diagrams show the timing of accesses to memory or a peripheral. Figure 10. WSC = 1, A.HALF/E.HALF
Figure 11. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF
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Figure 12. WSC = 1, OEA = 1, A.WORD/E.HALF
Figure 13. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
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Figure 14. WSC = 3, OEA = 2, A.WORD/E.HALF
Figure 15. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF
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Figure 16. WSC = 3, OEA = 4, A.WORD/E.HALF
Figure 17. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF
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Figure 18. WSC = 3, OEN = 2, A.WORD/E.HALF
Figure 19. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF
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Figure 20. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF
Figure 21. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF
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Figure 22. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF
Figure 23. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF
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Figure 24. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF
Figure 25. WSC = 3, CSA = 1, A.HALF/E.HALF
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Figure 26. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF
Figure 27. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF
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Figure 28. WSC = 3, SYNC = 1, A.HALF/E.HALF
Figure 29. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD
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Figure 30. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF
Figure 31. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF
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Figure 32. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF
Figure 33. SCLK to LD Timing Diagram
3.9.4 Non-TFT Panel Timing
Figure 34. Non-TFT Panel Timing Table 18. LCDC SCLK Timing
1 SCLK to LD valid – 3 ns
Table 19. Non TFT Panel Timing Diagram
MC9328MX1 Advance Information, Rev. 4
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VSYN, HSYN and SCLK can be programmed as active high or active low. In the above timing diagram, all these 3 signals are active high. Ts is the shift clock period. Ts = Tpix * (panel data bus width). Tpix is the pixel clock period which equals LCDC_CLK period * (PCD + 1). Maximum frequency of LCDC_CLK is 48 MHz, which is controlled by Peripheral Clock Divider Register. Maximum frequency of SCLK is HCLK / 5, otherwise LD output will be wrong.
3.10 Pen ADC Specifications
The specifications for the pen ADC are shown in Table 20 through Table 22.
3.11 ASP Touch Panel Controller
parameters and their corresponding measuring conditions are mentioned as well.
3.11.1 Electrical Specifications
Test conditions: Temperature = 25º C, QVDD = 1800mV. Table 20. Pen ADC System Performance
- Tested under input = 0~1.8V at 25°C
Table 21. Pen ADC Test Conditions Table 22. Pen ADC Absolute Rating
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Note that QVDD should be 1800mV.
3.11.2 Gain Calculations
Figure 35. Gain Calculations Where V is input, S is output, G is the slope, and C is the y-intercept. Table 23. ASP Touch Panel Controller Electrical Spec
3.11.3 Offset Calculations
Figure 36. Offset Calculations Where V is input, S is output, G is the slope, and C is the y-intercept.
3.11.4 Gain Error Calculations
Gain error calculations are made using the information in this section. Figure 37. Gain Error Calculations allowed. This occurs when the sample at 1800mV has just reached the ceiling of the 16-bit range, 65535.
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3.12 Bluet ooth Accelerator
Bluetooth chip interfaced to a UART is recommended. The Bluetooth Accelerator (BTA) radio interface supports the Motorola Radio, MC13180 using an SPI interface. Figure 39 on page 59, and the associated parameters shown in Table 24 and Table 25 on page 59. Figure 38. Motorola MC13180 Data Bus Timing Diagram Table 24. Motorola MC13180 Data Bus Timing Parameter Table
1 FrameSync setup time relati ve to BT CLK rising edge1 –4– n s
2 FrameSync hold time relative to BT CLK rising edge 1 –1 2– n s
Figure 39. SPI Interface Timing Diagram Using Motorola MC13180
3 Receive Data setup time relative to BT CLK rising edge 1 –6– n s
4 Receive Data hold time rela tive to BT CLK rising edge1 –1 3– n s
7 BT CLK duty cycle 40 – 60 %
8 Transmit Data hold time relative to RXTX_EN falling edge 4 – 10 µs
- Please refer to Motorola 2.4 GHz RF Transceiv er Module (MC13180) Technical Data documentation.
- The setup and hold times of RX_TX_EN can be adjusted by programming Time_A_B register
(0x00216050) and RF_Status (0x0021605C) registers. Table 25. SPI Interface Timing Parameter Table Using Motorola MC13180
1 SPI_EN setup time relative to rising edge of SPI_CLK 15 – ns
2 Transmit data delay time relative to rising edge of SPI_CLK 0 15 ns
3 Transmit data hold time relative to rising edge of SPI_EN 0 15 ns
4 SPI_CLK rise time 0 25 ns
5 SPI_CLK fall time 0 25 ns
6 SPI_EN hold time relative to falling edge of SPI_CLK 15 – ns
Table 24. Motorola MC13180 Data Bus Timing Parameter Table (Continued)
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3.13 SPI Timing Diagrams
two control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY signal (input). load data out to the internal data shift registers, as well as to increment the data FIFO. Figure 40. Master SPI Timing Diagram Using SPI_RDY Edge Trigger Figure 41. Master SPI Timing Diagram Using SPI_RDY Level Trigger
7 Receive data setup time relative to falling edge of SPI_CLK 1 15 – ns
8 Receive data hold time relative to falling edge of SPI_CLK 1 15 – ns
9 SPI_CLK frequency, 50% duty cycle required 1 –2 0 M H z
- The SPI_CLK clock frequency and duty cycle, setup and hold times of receive data can be set by
programming SPI_Control (0x00216138) register together with system clock. Table 25. SPI Interface Timing Parameter Table Using Motorola MC13180 (Continued)
Figure 42. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger Figure 43. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT Figure 44. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge Table 26. Timing Parameter Table for Figure 40 through Figure 44
1 SPI_RDY to SS output low 2T 1
- T = CSPI system clock period (PERCLK2).
3 Last SCLK edge to SS output high 2·Tsclk – ns
- WAIT = Number of bit clocks (SCLK) or 32.768 KHz clocks per Sample
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3.14 LCD Controller
with various display configurations, refer to the LCD controller chapter of the MC9328MX1 Reference Manual. Figure 45. SCLK to LD Timing Diagram Figure 46. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing Diagram Table 27. LCDC SCLK Timing Parameter Table
1 SCLK to LD valid – 2 ns
Table 28. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing Table
22 T s
11 T s
Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns. VSYN, HSYN and OE can be programmed as active high or active low. In Figure 46, all 3 signals are active low. The polarity of SCLK and LD[15:0] can also be programmed. For T9 non-display region, VSYN is non-active. It is used as an reference. XMAX is defined in pixels.
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3.15 Multimedia Card/Secu re Digital Host Controller
the application (user programming). Figure 47. Chip-Select Read Cycle Timing Diagram Table 29. SDHC Bus Timing Parameter Table
1 CLK frequency at Data transfer Mode (PP) 110/30 cards
2 CLK frequency at Identification Mode 2
7 Output delay time 3 01 6 0 1 4 n s
3.15.1 Command Response Timing on MMC/SD Bus
clock cycles as illustrated in Figure 48. The symbols for Figure 48 through Figure 52 are defined in Table 30. Figure 48. Timing Diagrams at Identification Mode two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the responding card. The other two diagrams show the separating periods NRC and NCC. Table 30. State Signal Parameters for Figure 48 through Figure 52
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Figure 49. Timing Diagrams at Data Transfer Mode
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Figure 51. Timing Diagrams at Data Write
Figure 52. Stop Transmission During Different Scenarios Stop transmission received after last data block. Card becomes busy programming. Stop transmission received after last data block. Card becomes busy programming.
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3.15.2 SDIO-IRQ and ReadWait Service Handling
is removed (SD_DAT[1] returns to its high level). status of the attached card. The interrupt period only happens at the boundary of each block (512 bytes). Figure 53. SDIO IRQ Timing Diagram back to the data transfer operation and all counter and status values are resumed as access continues. Table 31. Timing Values for Figure 48 through Figure 52
Figure 54. SDIO ReadWait Timing Diagram
3.16 Memory Stick Host Controller
attribute and transfer direction. BS0 is the INT transfer state, and during this state no packet transmissions occur. are automatically repeated to avoid a bus collision on the SDIO.
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Figure 55. MSHC Signal Timing Diagram Table 32. MSHC Signal Timing Parameter Table
1 MS_SCLKI frequency – 25 MHz
2 MS_SCLKI high pulse width 20 – ns
3 MS_SCLKI low pulse width 20 – ns
4 MS_SCLKI rise time – 3 ns
5 MS_SCLKI fall time – 3 ns
6 MS_SCLKO frequency
7 MS_SCLKO high pulse width 1 20 – ns
8 MS_SCLKO low pulse width 1 15 – ns
9 MS_SCLKO rise time 1 –5 n s
10 MS_SCLKO fall time 1 –5 n s
3.17 Pulse-Width Modulator
width modulator output (PWMO) external pin. Figure 56. PWM Output Timing Diagram
11 MS_BS delay time 1 –3 n s
12 MS_SDIO output delay time 1,2 –3 n s
13 MS_SDIO input setup time for MS_SCLKO rising edge (RED bit = 0) 3 18 – ns
14 MS_SDIO input hold time for MS_SCLKO rising edge (RED bit = 0) 3 0– n s
15 MS_SDIO input setup time for MS_SCLKO falling edge (RED bit = 1) 4 23 – ns
16 MS_SDIO input hold time for MS_SCLKO falling edge (RED bit = 1) 4 0– n s
- Loading capacitor condition is less than or equal to 30pF.
- An external resistor (100 ~ 200 ohm) should be inserted in series to provide current control on the MS_SDIO pin,
- If the MSC2[RED] bit = 0, MSHC samples MS _SDIO input data at MS_SCLKO rising edge.
- If the MSC2[RED] bit = 1, MSHC samples MS_SDIO input data at MS_SCLKO falling edge.
Table 33. PWM Output Timing Parameter Table
1 System CLK frequency 1 08 70 1 0 0 M H z
Table 32. MSHC Signal Timing Parameter Table (Continued)
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3.18 SDRAM Memory Controller
written. SyncFlash does not support burst writes, therefore a Burst Terminate command is not required. memory on the low order 8 data bits following the CAS latency. Table 33. PWM Output Timing Parameter Table (Continued)
Figure 57. SDRAM/SyncFlash Read Cycle Timing Diagram Table 34. SDRAM Timing Parameter Table
2 SDRAM clock low-level width 6–4– n s
Note: CKE is high during the read/write cycle.
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5 SDRAM access time (CL = 1) – 22 – 22 ns
7 Data out high-impedance time (CL = 1) – 22 – 22 ns
8 Active to read/write command period (RC = 1) t
- t RCD = SDRAM clock cycle time. The tRCD setting can be found in the MC9328MX1 reference manual.
Table 34. SDRAM Timing Parameter Table (Continued)
Figure 58. SDRAM/SyncFlash Write Cycle Timing Diagram Table 35. SDRAM Write Timing Parameter Table
6 Precharge cycle period
7 Active to read/write command delay tRCD
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Figure 59. SDRAM Refresh Timing Diagram
- Precharge cycle timing is incl uded in the write timing diagram.
- t RP and tRCD = SDRAM clock cycle time. These settings can be found in the MC9328MX1 reference
Table 36. SDRAM Refresh Timing Parameter Table Table 35. SDRAM Write Timing Parameter Table (Continued)
Figure 60. SDRAM Self-Refresh Cycle Timing Diagram
6 Precharge cycle period t
7 Auto precharge command period tRC
- t RP and t RC = SDRAM clock cycle time. These settings can be found in the MC9328MX1 reference
Table 36. SDRAM Refresh Timing Parameter Table (Continued)
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3.19 USB Device Port
how they work from the ground up. Figure 61. USB Device Timing Diagram for Data Transfer to USB Transceiver (TX) Table 37. USB Device Timing Parameter Table for Data Transfer to USB Transceiver (TX)
Figure 62. USB Device Timing Diagram for Data Transfer from USB Transceiver (RX) Table 38. USB Device Timing Parameter Table for Data Transfer from USB Transceiver (RX) Table 37. USB Device Timing Parameter Table for Data Transfer to USB Transceiver (TX) (Continued)
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3.20 I 2C Module
Slave Acknowledge, Data, Data Acknowledge, and STOP. Figure 63. Definition of Bus Timing for I2C
3.21 Synchronous Serial Interface
clock timing diagrams are shown in Figure 65 through Figure 67 on page 84. distinctions result in the basic operating modes that allow the SSI to communicate with a wide variety of devices. Table 39. I2C Bus Timing Parameter Table
1 Hold time (repeated) START condition 182 – 160 – ns
2 Data hold time 01 7 101 5 0 n s
4 HIGH period of the SCL clock 80 – 120 – ns
5 LOW period of the SCL clock 480 – 320 – ns
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Figure 66. SSI Transmitter External Clock Timing Diagram Figure 67. SSI Receiver External Clock Timing Diagram Table 40. SSI 1 Timing Parameter Table Note: SRXD Input in Synchronous mode only.
10 STCK high to STXD valid from high
14 SRXD hold time after SRCK low 0 – 0 – ns
18 STCK high to STFS (bl) high
26 STCK high to STXD valid from high
Table 40. SSI 1 Timing Parameter Table (Continued)
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30 SRXD hole time after SRCK low 0 – 0 – ns
32 SRXD hold after STCK falling 0 – 0 – ns
34 SRXD hold after STCK falling 0 – 0 – ns
- All the timings for the SSI are given for a non-inve rted serial clock polarity (TSCKP/RSCKP = 0) and a
STFS/SRFS shown in the tables and in the figures.
- There are 2 sets of I/O signals for the SSI module. They are from Port C primary function (PC3 – PC8)
module (CRM). By default, the input are selected from Port C primary function.
- bl = bit length; wl = word length.
Table 41. SSI 2 Timing Parameter Table
Table 41. SSI 2 Timing Parameter Table (Continued)
88 Freescale Semiconductor
3.22 CMOS Sensor Interface
generation, a status register, interface logic, a 32 × 32 image data receive FIFO, and a 16 × 32 statistic data FIFO.
3.22.1 Gated Clock Mode
edge. The parameters for the timing diagrams are listed in Table 42 on page 89.
- All the timings for both SSI modules are given for a non-inverted serial clock polarity (TSCKP/RSCKP =
STFS/SRFS shown in the tables and in the figures.
- There is one set of I/O signals for the SSI2 module. They are from Port C alternate function (PC19 –
PC24). When SSI signals are configured as outputs, they can be viewed at Port C alternate function a. in the Clock controller module (CRM). By default, the input is selected from Port C alternate function.
- bl = bit length; wl = word length
90 Freescale Semiconductor
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
3.22.2 Non-Gated Clock Mode
edge. The parameters for the timing diagrams are listed in Table 43 on page 91. Table 42. Gated Clock Mode Timing Parameters (Continued)
92 Freescale Semiconductor
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns. Table 43. Non-Gated Clock Mode Parameters (Continued)
4 Pin-Out and Package Information
Table 44. MC9328MX1 BGA Pin Assignments
94 Freescale Semiconductor
4.1 MAPBGA Package Dimensions
pads. The device designator for the MAPBGA package is VH. Figure 72. MC9328MX1 MAPBGA Mechanical Drawing
MC9328MX1 Advance Information, Rev. 4 Freescale Semiconductor 95 NOTES
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