MC92501

MC92501 MOTOROLA | Alldatasheet

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SEMICONDUCTOR TECHNICAL DATA Advance Information ATM Cell Processor The ATM Cell Processor (MC92501) is an Asynchronous Transfer Mode (ATM) layer device composed of dedicated high-performance ingress and egress cell processors combined with UTOPIA Level 2-compliant physical (PHY) and switch interface ports (see Block Diagram). The MC92501 is a second generation ATM cell processor in MotorolaÕs 92500 series. This document provides information on the new features offered by the second generation ATM cell processor. This document, combined with MC92500/D, provides the complete speciÞcation for the ATM cell processor. New Features of the MC92501: ¥ Implements ATM Layer Functions for Broadband ISDN According to ATM Forum UNI 4.0 and TM 4.0 SpeciÞcations, ITU Recommendations, and Bellcore Recommendations ¥ Provides ABR Relative Rate Marking and EFCI Marking According to TM 4.0 ¥ Selective Discard CLP = 1 (or CLP = 0+1) Flow on Selected Connections ¥ UTOPIA Level 2 PHY Interface and UTOPIA ATM Layer Interface ¥ Supports Both Partial Packet Discard (PPD) and Early Packet Discard (EPD) ¥ Change ABR RM Cell Priority ¥ Support for CLP Transparency Existing MC92500 Features: ¥ Full-Duplex Operation at Data Rates up to 155 Mbit/sec ¥ Performs Internal VPI and VCI Address Compression for up to 64K VCs ¥ CLP-Aware Peak, Average, and Burst-Length Policing with Programmable Tag/Drop Action Per Policer ¥ Supports up to 16 Physical Links Using Dedicated Ingress/Egress MultiPHY Control Signals ¥ Each Physical Link Can Be ConÞgured as Either a UNI or NNI Port ¥ Supports Multicast, Multiport Address Translation ¥ Maintains Both Virtual Connection and Physical Link Counters on Both Ingress and Egress Cell Flows ¥ Provides a Flexible 32-Bit External Memory Port for Context Management ¥ Automated AIS, RDI, CC, and Loopback Functions with Performance Monitoring Block Test on All 64K Connections ¥ Programmable 32-Bit Microprocessor Interface Supporting Big-Endian or Little-Endian Bus Formats ¥ Bidirectional UPC or NPC Design with up to Four Leaky Buckets Per Connection ¥ Supports a Programmable Number of Additional Switch Overhead Parameters Allowing Adaptation to Any Switch Routing Header Format ¥ Provides Per-Link Cell Counters in Both Directions This document contains information on a new product. SpeciÞcations and information herein are subject to change without notice. MC92501

ORDERING INFORMATION

© Motorola, Inc. 1998 REV 1.2 2/98 TN98020500

REPRESENTATIVE BLOCK DIAGRAM INGRESS CELL PROCESSOR VP and VC Address Translation NPC/UPC Cell Counting OAM Operations Add Switch Parameters Microprocessor Cell Insertion/Extraction UTOPIA IF INGRESS PHY IF CRC Check (OAM) MultiPHY Support INGRESS SWITCH IF CRC Generation Independent Clock EGRESS PHY IF CRC Gen (OAM) MultiPHY Support EGRESS CELL PROCESSOR Multicast Translation Cell Counting OAM Operations Address Translation Microprocessor Cell Insertion/Extraction EGRESS SWITCH IF Extract Overhead CRC Check Independent Clock MICROPROCESSOR IF Cell Insertion Cell Extraction ConÞg Registers Maintenance Access UTOPIA IF INTERNAL SCAN FMC GENERATIONEXT MEMORY IFEXTERNAL MEMORY IF MICRO- PROCESSOR IF UTOPIA IF UTOPIA IF

TABLE OF CONTENTS (CONTINUED)

block or packet is transferred. input port to the output port based on the switchÕs routing table. destination port, based on the switchÕs routing table. side of the switch fabric into PHY layer and ATM layer tasks. the cell level and are independent of the physical medium. Figure 1. MC92501 in an ATM Network Application

SECTION 2. FUNCTIONAL DESCRIPTION 2.1. System Functional Description A serial transmission link operating at up to 155.52 Mbit/sec (PHY) is coupled to the MC92501 via a byte-based interface. The transmission link timing is adapted to the MC92501 and switch timing by means of internal cell buffers. A common clock supplies both the PHY IF and MC92501. The host microprocessor initializes and provides real-time control information to the data-ßow chips (PHY IF and MC92501) using slave accesses. The MC92501 operates in conjunction with an external connection memory, which provides one context entry for each active connection. The entry consists of two types of context parameters: static and dynamic. The static parameters are loaded into the context memory when the VC is established, and are valid for the duration of that connection. The static parameters include trafÞc descriptors, OAM ßags, and ATM switch parameters. The dynamic context parameters include cell counters, UPC/NPC Þelds, and OAM parameters. The dynamic parameters can be modiÞed while a particular connection is being processed. The microprocessor can access the external memory through the MC92501 to collect trafÞc statistics and to update the OAM parameters. During normal cell processing, the MC92501 has exclusive access to the external memory and maintains external memory coherency. At user-programmable intervals, the MC92501 provides the microprocessor with a Òmaintenance slot.Ó During this time, cell processing is halted and control of the external memory bus is relinquished. The break in cell processing is made possible by the difference between the MC92501 cell- processing rate and the line rate. The microprocessor can use the maintenance slot for any of the following tasks: ¥ Connection setup and tear down ¥ Statistics collection ¥ Updating OAM parameters of active connection The microprocessor is responsible for the external memory coherency during the maintenance interval. 2.2. MC92501 Functional Description MC92501 General Features: ¥ Implements ATM layer functions for broadband ISDN according to CCITT recommendations, ATM Forum UNI 4.0 and TM 4.0 speciÞcations, and ITU and Bellcore recommendations. ¥ Provides 155 Mbit/sec throughput capacity and is physical layer independent. ¥ Optionally supports up to 16 physical links. ¥ Optionally conÞgured as a User Network Interface (UNI) or Network Node Interface (NNI) on a per-link basis. ¥ Provides Available Bit RateÐRelative Rate (ABRÐRR) marking and EFCI marking according to TM 4.0. ¥ Supports advanced discard policies such as Selective Discard, Partial Packet Discard (PPD), Early Packet Discard (EPD), and Limited Early Packet Discard (Limited EPD). ¥ Operates in conjunction with an external memory (up to

16 MB) to provide context management for up to 64K virtual

connections. ¥ Provides cell counter coherency on a per-connection basis by maintaining redundant copies of the counter tables and dynamically switching between them. ¥ Provides per-link cell counters in both directions. ¥ Provides per-connection Usage Parameter Control (UPC) or Network Parameter Control (NPC) using a leaky bucket design with up to four buckets per connection. ¥ Provides support for Operation, Administration, and Maintenance (OAM) Continuity Check function for all connections. ¥ Supports Virtual Path (VP) and Virtual Channel (VC) level alarm surveillance, OAM fault management loopback test, and OAM performance monitoring on all connections. ¥ Interfaces with either big-endian or little-endian microprocessors. ¥ Supports cell insertion into the cell streams using direct access registers which may be written by the microprocessor or by a DMA device. ¥ Supports copying cells from the cell streams using direct access registers which may be read by the microprocessor or by a DMA device. ¥ Supports multicast operation. 2.3. First Generation Features The MC92501 is a second generation ATM cell processor that enhances the MC92500 (Þrst generation) functionality. The MC92501 is backwards-compatible and pin- compatible with the MC92500. This document describes the second generation enhancements and is meant to supplement the MC92500 speciÞcation. The MC92500 speciÞcation can be ordered from the Motorola Literature Center by requesting document MC92500/D.

SECTION 4. SELECTIVE DISCARD ATM Forum TM 4.0 deÞnes procedures according to which cells can be discarded by network elements. A switching element may discard cells belonging to selected connections or cells whose CLP = 1 in case of congestion. This function is called selective discard and it is implemented by the MC92501. Selective discard is enabled by the ICNGÑGlobal Ingress Congestion NotiÞcation bit in the Ingress Processing Control Register (IPLR). Selective discard can be enabled on a per-connection basis by the ISDMÑIngress Selective Discard Operation Mode Þeld in the Common Parameters Extension Word. This Þeld determines whether selective discard is enabled and whether selective discard is performed on CLP = 1 or on CLP = 0+1 trafÞc. Selective discard can be enabled globally by the IPCVÑIngress Enable bit in the ATMC CFB ConÞguration Register (ACR).

or by setting the PTI Þeld in the cellÕs header to Ò110BÓ. overhead of cells which are received from the switch fabric. ¥ Provides different priority to RM cells. ¥ The cell belongs to a VC connection and its PTI = 6. Figure 9. RM Cell Fields

Figure 11. Cell Marking Scheme global register, cellÕs overhead, or context bit. case it will mark egress BRM cells. global register, cellÕs overhead, and context memory.

location of this bit in the overhead is programmable using the EEBYÑEFS Byte Location bit and the EEBIÑEFS Bit Location bit in the Egress Switch Overhead Information Register 1 (ESOIR1). This bit is enabled by the EEASÑGlobal EFS Enable bit in the Egress Switch Interface ConÞguration Register (ESWCR). The MC92501 can be programmed that in such a case it will mark egress FRM cells or perform EFCI marking. 5.4.2.3. Egress Flow Status from Context Memory The switch fabric can notify the MC92501 that it should mark cells because of the egress ßow status of connection #n by setting the EFSÑOverhead Egress Flow Status bit in the overhead of egress cells belonging to that connection. (See Section 5.4.2.2 for details on enabling of EFSÑOverhead Egress Flow Status bit and its location.) When the MC92501 receives that cell, it copies the bit into the CEFSÑConnection Egress Flow Status bit in the Common Parameters Extension Word of connection #n. The MC92501 can be programmed that in such a case it will mark ingress BRM cells. 5.4.2.4. Logic of Egress Flow Status The egress ßow status equals 1 if: EAME = 1 OR EFS = 1 and EEAS = 1 and egress = 1 OR CEFS = 1 and EEAS = 1 and ingress = 1 Where: EAME = Global Egress ABR Mark Enable EFS = Overhead Egress Flow Status EEAS = Global EFS Enable CEFS = Connection EFS Enable Egress = Programmed Overhead Egress Bit Ingress = Programmed Overhead Ingress Bit 5.4.3. Ingress ABR Marking Bits The MC92501 can mark cells as a result of either ingress ßow status or egress ßow status. In the case where ingress ßow status is asserted, the MC92501 can perform one or more of the following: ¥ Set CI bit in an ingress FRM cell Ñ when the ISFCEÑ Global Ingress Set FRM CI Enable bit in the Ingress Processing ConÞguration Register (IPCR) is set. ¥ Set NI bit in an ingress FRM cell Ñ when the ISFNEÑ Global Ingress Set FRM NI Enable bit in the IPCR is set. ¥ Set PTI[1] bit in an ingress cell whose PTI[2] = 0 Ñ when the ISPEÑGlobal Ingress Set PTI Enable bit in the IPCR is set. In the case where egress ßow status is asserted, the MC92501 can perform one or more the following: ¥ Set CI bit in an ingress BRM cell Ñ when the ISBCEÑ Global Ingress Set BRM CI Enable bit in the IPCR is set. ¥ Set NI bit in an ingress BRM cell Ñ when the ISBNEÑ Global Ingress Set BRM NI Enable bit in the IPCR is set. All cell marking on the ingress is enabled on a per- connection basis by the CIMEÑConnection Ingress Marking Enable bit in the Common Parameters Extension Word. 5.4.3.1. Logic of Ingress ABR Marking Bits The CI bit is set if: FRM cell and CIME = 1 and ingress ßow status = 1 and ISFCE = 1 OR BRM cell and CIME = 1 and egress ßow status = 1 and ISBCE = 1 The NI bit is set if: FRM cell and CIME = 1 and ingress ßow status = 1 and ISFNE = 1 OR BRM cell and CIME = = 1 and egress ßow status = 1 and ISBNE = 1 The PTI[1] bit is set if: PTI[2] = 0 and CIME = 1 and ingress ßow status = 1 and ISPE = 1 Where: CIME = Connections Ingress Marking Enable FRM Cell = Cell marked as FRM cell BRM Cell = Cell marked as BRM cell Ingress Flow Status = Set as deÞned in Section 5.4.1.4 Egress Flow Status = Set as deÞned in Section 5.4.2.4 ISFCE = Global Ingress Set FRM CI Enable ISFNE = Global Ingress Set FRM NI Enable ISPE = Global Ingress Set PTI Enable ISBCE = Global Ingress Set BRM CI Enable ISBNE = Global Ingress Set BRM NI Enable 5.4.4. Egress ABR Marking Bits The MC92501 can mark cells as a result of either ingress ßow status or egress ßow status. In the case where egress ßow status is asserted, the MC92501 can perform one or more of the following: ¥ Set CI bit in an egress FRM cell Ñ when the ESFCEÑ Global Egress Set FRM CI Enable bit in the Egress Processing ConÞguration Register (EPCR) is set. ¥ Set NI bit in an egress FRM cell Ñ when the ESFNEÑ Global Egress Set FRM NI Enable bit in the EPCR is set. ¥ Set PTI[1] bit in an egress cell whose PTI[2] = 0 Ñ when the ESPEÑGlobal Egress Set PTI Enable bit in the EPCR is set. In the case where ingress ßow status is asserted, the MC92501 can perform one or more the following: ¥ Set CI bit in an egress BRM cell Ñ when the ESBCEÑ Global Egress Set BRM CI Enable bit in the EPCR is set. ¥ Set NI bit in an egress BRM cell Ñ when the ESBNEÑ Global Egress Set BRM NI Enable bit in the EPCR is set. All cell marking on the egress is enabled on a per- connection basis by the CEMEÑConnection Egress Marking Enable bit in the Common Parameters Extension Word.

susceptible to discarding in case of congestion. overhead and assigns 0 to the header CLP . considers the cell as if it has CLP = 0. Figure 16. CLP Transparency with a CLP Significant Switch Fabric the Ingress Switch Interface ConÞguration Register (ISWCR). Overhead Information Register 1 (ESOIR1).

1. If a cell belongs to a connection which supports CLP transparency (the ICTEÑIngress CLP Transparency Enable bit

overhead and assigns the ICTVÑIngress CLP Transparency Value bit to the header CLP .

1. If the CIFSÑConnection Ingress Flow Status bit is set then the MC92501 reconstructs the header CLP from the

EOCLPÑEgress Overhead CLP bit in the cellÕs overhead.

is not performed during maintenance. External Memory Access Busy bit in the IAAR register. then may read the data from the IADR register. an external address compression device. use the maintenance cell slot for this purpose. Table 1. Indirect Access Fields

MDCÑMDTACK Drive Control is set. backwards compatibility is maintained. accesses are always performed regardless of these signals. Table 2. Host Interface Fields

SECTION 9. EGRESS OVERHEAD MANIPULATION The MC92501 supports the following features: ¥ The size of the ECI Þeld used by the egress cell processing block can be programmed by writing to the ECESÑEgress Cell Processing Block ECI Size Þeld in the Egress Overhead Manipulation Register (EGOMR). ¥ The size of the MTTS Þeld used by the egress cell processing block can be programmed by writing to the ECTSÑEgress Cell Processing Block MTTS Size Þeld in the EGOMR. ¥ The M bit used by the egress cell processing block can be either the M bit which was extracted from the cellÕs overhead, the logical not of the M bit which was extracted from the cellÕs overhead, or 1 or 0 by programming the ECMSÑEgress Cell Processing Block M Bit Source Þeld in the EGOMR. ¥ In ECI on Header mode, the ECI is extracted from the ATM cell header. The header VPI Þeld size can be programmed to either 12 bits or 8 bits using the VPSÑVPI Size in ECI on Header Mode bit of the Egress Switch Interface ConÞguration Register (ESWCR).

This section describes the registers which were added or modiÞed for the MC92501. Table 3 contains all the registers which were added and their addresses. The following registers have been updated. The Þelds that have been added are in bold. insertion bandwidth. Insertion rate is controlled by the insertion leaky bucket. The FQFE bit has been added. When FQF and FQFE are set, an interrupt is generated. Table 3. General Register List Register Group Register Name Mnemonic ADD (25:0) Ref.

The AMRV Þeld has been updated. The MRV Þeld has been updated. The following registers have been added. This bit notiÞes the MC92501 whether there is congestion in the ingress ßow. See Section 4. marking if enabled. See Section 5.4.1. marking if enabled. See Section 5.4.2. Table 4. Values of ATMC CFB Revision Fields Table 5. Values of the MC92501 Revision Fields

00000000000000 ICNG IAME

000000000000000 EAME

11.3.3. Indirect External Memory Access Address Register (IAAR) This register contains the address, width, and busy bit for accessing the MC92501 external memory or the external memory device. Refer to Section 7 for details. The register has the following structure: IABÑIndirect External Memory Access Busy This bit indicates that indirect external memory access mechanism is busy. 0 = Indirect access mechanism is free and therefore indirect external memory access data register can be accessed. 1 = Indirect access mechanism is busy and therefore indirect access data register should not be accessed. IADÑIndirect External Memory Access DIR This bit indicates indirect access direction. 0 = Indirect write access 1 = Indirect read access IAWÑIndirect External Memory Access Size This bit indicates the size of the access. 0 = 32 bits 1 = 16 bits IAASÑIndirect External Memory Access Address Space This Þeld indicates the accessed address space. 00 = Reserved 01 = External address compression device 10 = Non-destructive external memory 11 = Reserved IAAÑIndirect External Memory Access Address This Þeld indicates bits 23:1 of the address within the address space speciÞed in the IAASÑIndirect External Memory Access Address Space Þeld. 11.3.4. Indirect External Memory Access Data Register (IADR) This register contains the data which should be written to the external memory in case of an indirect write access or the data that was last read from external memory in case of an indirect read access. Refer to Section 7 for details. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IAB IAD IAW 0 0 0 IAAS IAA 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 IAA 0

11.4. Configuration Register The following registers have been updated. The Þelds that have been added are in bold. 11.4.1. Ingress Processing Configuration Register (IPCR) IGCTEÑGlobal Ingress CLP Transparency Enable This bit enables CLP transparency function on the ingress. See Section 6 for details. ICCRÑIngress Check CRC on RM Cells This bit determines whether the CRC of RM cells that are received in the ingress is checked. 0 = The CRC of RM cells that are recevied in the ingress is not checked. 1 = The CRC of RM cells that are received in the ingress is checked and if it is not okay, then the cell is removed and can be copied to the microprocessor. IRCRÑIngress Recalculate CRC on RM Cells This bit determines whether the CRC of ingress RM cells is recalculated. 0 = The CRC of ingress RM cells is not recalculated. 1 = The CRC of ingress RM cells is recalculated. ISFCEÑGlobal Ingress Set FRM CI Enable This bit enables setting CI bit in forward RM cells received in ingress. See Section 5.4.3 for details. 0 = Setting CI bit in forward RM cells received in ingress is disabled. 1 = Setting CI bit in forward RM cells received in ingress is enabled. ISFNEÑGlobal Ingress Set FRM NI Enable This bit enables setting NI bit in forward RM cells received in ingress. See Section 5.4.3 for details. 0 = Setting NI bit in forward RM cells received in ingress is disabled. 1 = Setting NI bit in forward RM cells received in ingress is enabled. ISPEÑGlobal Ingress Set PTI Enable This bit enables setting PTI[1] bit in cells with PTI[2] = 0 which are received in ingress. See Section 5.4.3 for details. 0 = Setting PTI[1] bit in cells with PTI[2] = 0 which are received in ingress is disabled. 1 = Setting PTI[1] bit in cells with PTI[2] = 0 which are received in ingress is enabled. ISBCEÑGlobal Ingress Set BRM CI Enable This bit enables setting CI bit in backward RM cells received in ingress. See Section 5.4.3 for details. 0 = Setting CI bit in backward RM cells received in ingress is disabled. 1 = Setting CI bit in backward RM cells received in ingress is enabled. ISBNEÑGlobal Ingress Set BRM NI Enable This bit enables setting NI bit in backward RM cells received in ingress. See Section 5.4.3 for details. 0 = Setting NI bit in backward RM cells received in ingress is disabled. 1 = Setting NI bit in backward RM cells received in ingress is enabled. IROEÑIngress RM Overlay Enable This bit enables updating switch parameter words in the case of RM cells. See Section 5.5 for details. IPCVÑIngress Features Enable This bit should be set when the following features are used: packet-based UPC, selective discard, and CLP transparency. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

00000000 IGCTE ICCR IRCR ISFCE ISFNE ISPE ISBCE ISBNE

1 5 1 4 1 3 1 2 1 1 1 0 9876543210 IPCC 0 IGZC IUHC IIP IROE 0 IBCC IPCV IAPE IACE

11.4.2. Egress Processing Configuration Register (EPCR) EGCTEÑGlobal Egress CLP Transparency Enable This bit enables CLP transparency function on the egress. See Section 6 for details. ECCRÑEgress Check CRC on RM Cells This bit determines whether the CRC of RM cells that are received in the egress is checked. 0 = The CRC of RM cells that are recevied in the egress is not checked. 1 = The CRC of RM cells that are received in the egress is checked and if it is not okay, then the cell is removed and can be copied to the microprocessor. ERCRÑEgress Recalculate CRC on RM Cells This bit determines whether the CRC of egress RM cells is recalculated. 0 = The CRC of egress RM cells is not recalculated. 1 = The CRC of egress RM cells is recalculated. ESFCEÑGlobal Egress Set FRM CI Enable This bit enables setting CI bit in forward RM cells received in egress. See Section 5.4.2. 0 = Setting CI bit in forward RM cells received in egress is disabled. 1 = Setting CI bit in forward RM cells received in egress is enabled. ESFNEÑGlobal Egress Set FRM NI Enable This bit enables setting NI bit in forward RM cells received in egress. See Section 5.4.2. 0 = Setting NI bit in forward RM cells received in egress is disabled. 1 = Setting NI bit in forward RM cells received in egress is enabled. ESPEÑGlobal Egress Set PTI Enable This bit enables setting PTI[1] bit in cells with PTI[2] = 0 which are received in egress. See Section 5.4.2. 0 = Setting PTI[1] bit in cells with PTI[2] = 0 which are received in egress is disabled. 1 = Setting PTI[1] bit in cells with PTI[2] = 0 which are received in egress is enabled. ESBCEÑGlobal Egress Set BRM CI Enable This bit enables setting CI bit in backward RM cells received in egress. See Section 5.4.2. 0 = Setting CI bit in backward RM cells received in egress is disabled. 1 = Setting CI bit in backward RM cells received in egress is enabled. ESBNEÑGlobal Egress Set BRM NI Enable This bit enables setting NI bit in backward RM cells received in egress. See Section 5.4.2. 0 = Setting NI bit in backward RM cells received in egress is disabled. 1 = Setting NI bit in backward RM cells received in egress is enabled. EPCCÑEgress Policing Counters Control This Þeld determines which counters appear in the Policing Counters Table if egress UPC is enabled. (The UPCFÑUPC Flow bit in the ACR is set.) It also determines the size of each record in the table. 000 = The policing table does not exist. 001 = The policing table contains three counters and one reserved long word: DSCD0, DSCD1, TAG, Reserved. 010 = The policing table contains three counters: DSCD0, DSCD1, TAG. 011 = The policing table contains two counters: DSCD, TAG. 100 = The policing table contains one counter: TAG. 101 = The policing table contains one counter: DSCD. 110 = Reserved 111 = Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

00000000 EGCTE ECCR ERCR ESFCE ESFNE ESPE ESBCE ESBNE

1 5 1 4 1 3 1 2 1 1 1 0 9876543210 EPCC 000 EIP 0 0 EBCC EPCV RGFC 0 0

EIPÑEgress Insertion Priority This bit determines the priority between inserted/generated cells and egress received cells. Note that insertion is always limited by the leaky bucket mechanism. 0 = Inserted/generated cellsÕ priority is higher than egress received cells. 1 = Egress received cellsÕ priority is higher than inserted/generated cells. EPCVÑEgress Features Enable This bit should be set when the reset EFCI feature is activated. See Section 5.6. 11.4.3. ATMC CFB Configuration Register (ACR) VPRPÑVP RM Cell PTI This bit determines whether a cell is a VP RM cell only if its PTI = 6. 0 = A cell is a VP RM cell if and only if it belongs to a VP connection, its VCI = 6, and its PTI = 6. 1 = A cell is a VP RM cell if and only if it belongs to a VP connection and its VCI = 6. CRRPÑVC RM Cell Removal Point This bit determines whether a VC cell whose PTI = 6 or 7 is removed at the OAM termination point, or whether its removal is subjected to the per-connection enable bits for PTI = 6 or PTI = 7. 0 = A VC cell whose PTI = 6 or 7 is removed at the OAM termination point as deÞned by the EEOTÑEgress End-to-End OAM Termination bit in the egress and by the IEOTÑIngress End-to-End OAM Termination bit in the ingress. 1 = A VC cell is removed at the egress if the EP6RÑEgress PTI 6 Remove bit is set and its PTI = 6 or if the EP7RÑEgress PTI 7 Remove bit is set and its PTI = 7. A VC cell is removed at the ingress if the IP6RÑIngress PTI 6 Remove bit is set and its PTI = 6 or if the IP7RÑIngress PTI 7 Remove bit is set and its PTI = 7. PMACÑPM on All Connections This bit determines whether the OAM performance monitoring test can be done on all connections or on 64 connections. 0 = Performance monitoring can be done only on 64 selected connections. 1 = Performance monitoring can be done on all connections. UPCFÑUPC Flow This bit determines whether the UPC is active in the ingress ßow or in the egress ßow. 0 = The UPC is active in the ingress ßow. 1 = The UPC is active in the egress ßow. 11.4.4. Egress Switch Interface Configuration Register (ESWCR) EIASÑGlobal IFS Enable This bit enables the MC92501 to use theIFSÑOverhead Ingress Flow Status bit in the egress switch overhead. See Section 5.4.1 for details. 0 = The IFSÑOverhead Ingress Flow Status bit is not deÞned in the egress overhead Þelds so it cannot trigger ABR cell marking. 1 = The IFSÑOverhead Ingress Flow Status bit is deÞned in the egress overhead Þelds and is used by the MC92501 for marking cells. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ATC SPC COMC INPC EGPC DVTC FLGC OAMC VPRP FTM CRRP PMAC 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 UPCF 000000000000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 EIAS EEAS VPS 0 0 IHAF 0 ESFC EFE MTSE EATD ELNS ESPC ESPR EPLP ESHF 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 ESNB 0 IMSB ILSB

EEASÑGlobal EFS Enable This bit enables the MC92501 to use the EFSÑOverhead Egress Flow Status bit in the egress switch overhead. See Section 5.4.2 for details. 0 = The EFSÑOverhead Egress Flow Status bit is not deÞned in the egress overhead Þelds so it cannot trigger ABR cell marking. 1 = The EFSÑOverhead Egress Flow Status bit is deÞned in the egress overhead Þelds and is used by the MC92501 for marking cells. VPSÑVPI Size in ECI on Header Mode This bit determines the size of the VPI Þeld for ECI on Header mode (IHAF = 1). See Section 9 for details. 0 = VPI size is 12 bits 1 = VPI size is 8 bits 11.4.5. Egress Switch Overhead Information Register 0 (ESOIR0) This register name was ESOIR on MC92500. The following deÞnition is changed: MTBI-MTTS Bit Location This Þeld indicates the location of the MTTS Þeld within the byte speciÞed by the MTBY -MTTS Byte Location Þeld. 0 = MTTS equals the value that resides in bits 7:5 of the byte pointed to by the MTBY -MTTS Byte Location Þeld. 1 = MTTS equals the value that resides in bits 7:6 of the byte pointed to by the MTBY -MTTS Byte Location Þeld. 2 = MTTS equals the value that resides in bit 7 of the byte pointed to by the MTBY -MTTS Byte Location Þeld. 3 = MTTS equals the value that resides in bits 3:0 of the byte pointed to by the MTBY -MTTS Byte Location Þeld. 4 = MTTS equals the value that resides in bits 4:1 of the byte pointed to by the MTBY -MTTS Byte Location Þeld. 5 = MTTS equals the value that resides in bits 5:2 of the byte pointed to by the MTBY -MTTS Byte Location Þeld. 6 = MTTS equals the value that resides in bits 6:3 of the byte pointed to by the MTBY -MTTS Byte Location Þeld. 7 = MTTS equals the value that resides in bits 7:4 of the byte pointed to by the MTBY -MTTS Byte Location Þeld. Note that this deÞnition is backwards-compatible to the deÞnition in MC92500. 11.4.6. Microprocessor Configuration Register (MPCONR) WSSMÑWord Select Signals Mode This bit deÞnes the functionality of the MP Word Write Enable High / Address 1 (MWSH/A1) and the MP Word Write Enable Low / SIZE (MWSL/SIZE) signals. See Section 8.1.3 for details. 0 = MWSH/A1 functions as MWSH-word write enable high and MWSL/SIZE functions as MWSL-word write enable low. 1 = MWSH/A1 functions as A1 and MWSL/SIZE functions as SIZE. RQ0ÑMREQ0 Signal Functionality This Þeld deÞnes the functionality of the MP Request 0 (MREQ0) signal. See Section 8.1.2 for details. 00 = Cell in request 01 = Cell in request 10 = Cell out request 11 = External memory request RQ1ÑMREQ1 Signal Functionality This Þeld deÞnes the functionality of the MP Request 1 (MREQ1) signal. See Section 8.1.2 for details. 00 = Cell out request 01 = Cell in request 10 = Cell out request 11 = External memory request 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DO 0 0 0 WSSM 00 RQ0 0 RQ1 0 RQ2 1 5 1 4 1 3 1 2 1 1 1 0 9876543210

00 MDC 0 DDDS 0 DDGR 0 DDEM 0 DDCI 0 DDCE

RQ2ÑMREQ2 Signal Functionality This Þeld deÞnes the functionality of the MP Request 2 (MREQ2) signal. See Section 8.1.2 for details. 00 = External memory request 01 = Cell in request 10 = Cell out request 11 = External memory request MDCÑMDTACK Drive Control This bit determines which MDTACK signals are driven. 0 = MDT ACK0 is driven and MDTACK1 is not driven. 1 = Both MDTACK0 and MDTACK1 are driven. 11.4.7. Maintenance Configuration Register (MACONR) The MSDR Þeld is expanded from 6 bits to 9 bits. The maximum value for the MSDR is therefore 511 instead of 63. This means that the maintenance request signals can be asserted as much as 511 clocks (or 8 cell processing slots) before the CM bit. 11.4.8. Ingress PHY Configuration Register (IPHCR) IUMÑIngress UTOPIA Mode This bit deÞnes the UTOPIA level mode of the ingress PHY . See Section 10. 0 = UTOPIA Level 1 1 = UTOPIA Level 2 11.4.9. Egress PHY Configuration Register (EPHCR) EUMÑEgress UTOPIA Mode This bit deÞnes the UTOPIA level mode of the egress PHY . See Section 10. 0 = UTOPIA Level 1 1 = UTOPIA Level 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0000000000000000 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 MSDR 0 MSIR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0000000000000000 1 5 1 4 1 3 1 2 1 1 1 0 9876543210

00000000000 IUM INVPD IPOM IPPR IPLP

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0000000000000000 1 5 1 4 1 3 1 2 1 1 1 0 9876543210

00000000000 EUM EPFC EPOM ECGE EGIC

11.4.10. MC92501 General Configuration Register (GCR) CMPCÑContext Parameters Extension Table Control This bit determines the existence of the Context Parameters Extension Table in external memory. See Section 12.1 for details. 0 = The Common Parameters Table does not exist. 1 = The Common Parameters Table exists. 11.4.11. Egress Switch Overhead Information Register 1 (ESOIR1) This register determines the location of the overhead information in the data structure received from the switch. The register has the following structure: EOBYÑEOCLP Byte Location This Þeld contains the byte number of the switch data structure in which the EOCLPÑEgress Overhead CLP bit in the cellÕs overhead. The byte on which STXSOC is asserted is byte number 0. See Section 6 for details. EOBIÑEOCLP Bit Location This Þeld contains the number of the EOCLPÑEgress Overhead CLP bit in the cellÕs overhead. The most signiÞcant bit is number 7, and the least signiÞcant bit is number 0. See Section 6 for details. EIBYÑIFS Byte Location This Þeld contains the byte number of the switch data structure in which the IFSÑOverhead Ingress Flow Status bit can be EIBIÑIFS Bit Location This Þeld contains the number of the IFSÑOverhead Ingress Flow Status bit within the byte speciÞed by the EEBYÑEFS Byte EEBYÑEFS Byte Location This Þeld contains the byte number of the switch data structure in which the EFSÑOverhead Egress Flow Status bit can be EEBIÑEFS Bit Location This Þeld contains the number of the EFSÑOverhead Egress Flow Status bit within the byte speciÞed by the EIBYÑIFS Byte 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

000000000000000 PHIDC

1 5 1 4 1 3 1 2 1 1 1 0 9876543210

000000000 CMPC 0 0 ILCC 0 0 ELCC

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

00000000 EOBY EOBI

1 5 1 4 1 3 1 2 1 1 1 0 9876543210 EIBY EIBI EEBY EEBI

11.4.12. RM Overlay Register (RMOR) This register contains all the parameters which are related to RM cell overlay. Refer to Section 5.5 for details. The register has the following structure: IBOEÑIngress BRM Overlay Enable This bit determines whether the MC92501 overlays the ROFÑRM Overlay Þeld on the switch parameters for ingress backward RM cells. 0 = Switch parameters are not overlayed when a backward RM cell is received in the ingress. 1 = Switch parameters are overlayed when a backward RM cell is received in the ingress. IFOEÑIngress FRM Overlay Enable This bit determines whether the MC92501 overlays the ROFÑRM Overlay Þeld on the switch parameters for ingress forward RM cells. 0 = Switch parameters are not overlayed when a forward RM cell is received in the ingress. 1 = Switch parameters are overlayed when a forward RM cell is received in the ingress. ROLÑRM Overlay Location This Þeld contains the number of the switch parameters byte which should be overlayed. ROMÑRM Overlay Mask This Þeld contains the byte mask which serves for overlaying the ROFÑRM Overlay Þeld over the ingress switch parameters byte. ROFÑRM Overlay This Þeld contains the byte which is overlayed on the ingress switch parameters byte. Each bit in this Þeld is overlayed on the corresponding bit in the ingress switch parameters only if it is enabled by the corresponding bit in the ROMÑRM Overlay Mask Þeld. 11.4.13. CLP Transparency Overlay Register (CTOR) This register contains the location of the IOCLPÑIngress Overhead CLP bit in the ingress switch parameters. See Section 6 for details. The register has the following structure: OCBLÑIOCLP Byte Location This Þeld contains the byte number within the switch parameter word on which the IOCLPÑIngress Overhead CLP bit is located. The most signiÞcant byte is number 0, and the least signiÞcant byte is number 3. OCBIÑIOCLP Bit Location This Þeld contains the number of the IOCLPÑIngress Overhead CLP bit within the byte speciÞed by the OCBLÑIOCLP Byte Location Þeld. The most signiÞcant bit is number 7, and the least signiÞcant bit is number 0. 11.4.14. Context Parameters Extension Table Pointer Register (CPETP) This register contains the pointer to the Þrst word of the Context Parameters Extension Table. The pointer is in units of 256 bytes. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IBOE IFOE 00 ROL ROM 1 5 1 4 1 3 1 2 1 1 1 0 9876543210

00000000 ROF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0000000000000000 1 5 1 4 1 3 1 2 1 1 1 0 9876543210

000000000 OCBI OCBL

3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 CEPTP 00

11.4.15. Egress Overhead Manipulation Register (EGOMR) This register contains Þelds for manipulating egress overhead Þelds. See Section 9 for details. ECMSÑ Egress Cell Processing Block M Bit Source This Þeld contains the source for the M bit which is used by the egress cell processing block. 00 = The M bit used by the egress cell processing block is taken from the M bit which is extracted from the switch cell data structure. 01 = The M bit used by the egress cell processing block is taken from the logical NOT of the M bit which is extracted from the switch cell data structure. 10 = The M bit used by the egress cell processing block is 0. 11 = The M bit used by the egress cell processing block is 1. ECTSÑ Egress Cell Processing Block MTTS Size This Þeld contains the size of the MTTS Þeld which is used by the egress cell processing block. 0 = The MTTS Þeld which is used by the egress cell processing block is the MTTS Þeld, which is extracted from the switch cell data structure. 1 = The MTTS Þeld which is used by the egress cell processing block is the least signiÞcant bit of the MTTS Þeld, which is extracted from the switch cell data structure. 2 = The MTTS Þeld which is used by the egress cell processing block is the two least signiÞcant bits of the MTTS Þeld, which are extracted from the switch cell data structure. 3 = The MTTS Þeld which is used by the egress cell processing block is the three least signiÞcant bits of the MTTS Þeld, which are extracted from the switch cell data structure. ECESÑ Egress Cell Processing Block ECI Size This Þeld contains the size of the ECI Þeld which is used by the egress cell processing block. 0 = The ECI Þeld which is used by the egress cell processing block is the ECI Þeld, which is extracted from the switch cell data structure. 1 = Reserved 2 = Reserved 3 = Reserved 4 = Reserved 5 = Reserved 6 = The ECI Þeld which is used by the egress cell processing block is the six least signiÞcant bits of the ECI Þeld, which are extracted from the switch cell data structure. 7 = The ECI Þeld which is used by the egress cell processing block is the seven least signiÞcant bits of the ECI Þeld, which are extracted from the switch cell data structure. 8 = The ECI Þeld which is used by the egress cell processing block is the eight least signiÞcant bits of the ECI Þeld, which are extracted from the switch cell data structure. 9 = The ECI Þeld which is used by the egress cell processing block is the nine least signiÞcant bits of the ECI Þeld, which are extracted from the switch cell data structure. 10 = The ECI Þeld which is used by the egress cell processing block is the 10 least signiÞcant bits of the ECI Þeld, which are extracted from the switch cell data structure. 11 = The ECI Þeld which is used by the egress cell processing block is the 11 least signiÞcant bits of the ECI Þeld, which are extracted from the switch cell data structure. 12 = The ECI Þeld which is used by the egress cell processing block is the 12 least signiÞcant bits of the ECI Þeld, which are extracted from the switch cell data structure. 13 = The ECI Þeld which is used by the egress cell processing block is the 13 least signiÞcant bits of the ECI Þeld, which are extracted from the switch cell data structure. 14 = The ECI Þeld which is used by the egress cell processing block is the 14 least signiÞcant bits of the ECI Þeld, which are extracted from the switch cell data structure. 15 = The ECI Þeld which is used by the egress cell processing block is the 15 least signiÞcant bits of the ECI Þeld, which are extracted from the switch cell data structure. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0000000000000000 1 5 1 4 1 3 1 2 1 1 1 0 9876543210

00000000 ECMS ECTS ECES

SECTION 12. EXTERNAL MEMORY DESCRIPTION The following table has been added. 12.1. Context Parameters Extension Table Each context Parameters Extension Table record contains one word, the Common Parameters Extension Word. 12.1.1. Common Parameters Extension Word BKPT[21:12]ÑBucket Pointer[21:12] When VPAP-VP on all connections, this Þeld contains bits 21 to 12 of the bucket point. When VPAP-VP on all connections is reset, this Þeld is reserved and should be 0. CIFSÑConnection Ingress Flow Status The MC92501 copies the IFSÑOverhead Ingress Flow Status bit to this bit. This bit is used by the ingress processing block CEFSÑConnection Egress Flow Status The MC92501 copies the EFSÑOverhead Egress Flow Status bit to this bit. This bit is used by the ingress processing block ECTEÑEgress CLP Transparency Enable This bit determines whether CLP should be copied from the EOCLPÑEgress Overhead CLP bit in the cellÕs overhead bit to the cell header. See Section 6 for details. 0 = CLP should not be copied from the switch overhead to the cell header. 1 = CLP should be copied from the switch overhead to the cell header. CEMEÑConnection Egress Marking Enable This bit enables marking of cells which are received in the egress. See Section 5.4.2. 0 = Marking of cells which are received in the egress is disabled. 1 = Marking of cells which are received in the egress is enabled. IPDVÑIngress Packet Discard Variables This Þeld is accessed only by the MC92501. EREFÑEgress Reset EFCI This bit determines if PTI[1] of an egress cell is to be reset. 0 = PTI[1] of an egress cell is not reset. 1 = PTI[1] of an egress cell is to be reset. ISDMÑIngress Selective Discard Operation Mode This Þeld determines the selective discard operation mode. See Section 3. 00 = No selective discard. 01 = Reserved. 10 = Selective discard on CLP = 1 ßow. 11 = Selective discard on CLP = 0+1 ßow. UOMÑUPC Operation Mode This Þeld determines the UPC operation mode. 00 = Cell-based UPC 01 = Partial Packet Discard (PPD). See Section 3.3 for details. 10 = Early Packet Discard (EPD). See Section 3.4 for details. 11 = Limited EPD. SeeSection 3.5 for details. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BKPT[21:12] 0 0 CIFS CEFS ECTE CEME 1 5 1 4 1 3 1 2 1 1 1 0 9876543210

0 PDV 0 0 EREF 0 ISDM UOM 0 ICTV ICTE CIME

ICTVÑIngress CLP Transparency Value This bit determines the value that should be written to a cellÕs header if the ICTEÑIngress CLP Transparency Enable bit is set. See Section 6 for details. ICTEÑIngress CLP Transparency Enable This bit determines whether CLP should be copied to the IOCLPÑIngress Overhead CLP bit and whether the ICTVÑIngress CLP Transparency Value bit should be written to the cell header CLP . See Section 6 for details. 0 = The ingress header CLP bit is not touched. 1 = CLP should be copied from the cell header to the ingress switch parameters. The ICTVÑIngress CLP Transparency Value bit should be written to the cell header CLP . CIMEÑConnection Ingress Marking Enable This bit enables marking of cells which are received in the ingress. See Section 5.4.3 for details. 0 = Marking of cells which are received in the ingress is disabled. 1 = Marking of cells which are received in the ingress is enabled. 12.2. CONTEXT PARAMETERS TABLE Some bits have been added, and some bit deÞnitons have been updated in the Egress Parameters Word and the Ingress Parameters Word. These bits are in bold. 12.2.1. Egress Parameters EP6RÑEgress PTI 6 Remove When this bit is set and the CRRP-VC RM cell removal point is set, then an egress cell whose PTI = 6 is removed, provided that the connection is a VC connection. EP7RÑEgress PTI 7 Remove When this bit is set and the RRP-RM cell removal point is set, then an egress cell whose PTI = 7 is removed, provided that the connection is a VC connection. EEOTÑEgress End-to-End OAM Termination When this bit is set, the egress ßow is treated as the terminating point of the OAM end-to-end cell ßow for the connection. Additionally, if the CRRPÑVC RM Cell Removal Point bit is reset, then cells with PTI = 6 or 7 are removed at this point. 12.2.2. Ingress Parameters: IP6RÑIngress PTI 6 Remove When this bit is set and the RRP-RM Cell Removal Point is set, then an ingress cell whose PTI = 6 is removed, provided that the connection is a VC connection. IP7RÑIngress PTI 7 Remove When this bit is set and the RRP-RM Cell Removal Point is set, then an ingress cell whose PTI = 7 is removed, provided that the connection is a VC connection. IEOTÑIngress End-to-End OAM Termination When this bit is set, the ingress ßow is treated as the terminating point of the OAM end-to-end cell ßow for the connection. Additionally, if the CRRPÑVC RM Cell Removal Point bit is reset, then cells which belong to a VC connection and whose PTI = 6 or 7 are removed at this point. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ECIV EVPC EEOT ESOT ESOO Rsvd ECAS ECRD ECOT ECAO ECSF ECEF ECSB ECEB Rsvd Rsvd 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 ESAI ESRD ESCS ESCE ECA ERA EP6C EP7C EVRE EP6R EP7R Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ICIV IVPC IEOT ISOT ISOO Rsvd ICAS ICRD ICOT ICAO ICSF ICEF ICSB ICEB Rsvd Rsvd 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 ISAI ISRD ISCS ISCE ICA IRA IP6C IP7C IVRE IP6R IP7R Reserved UDT

12.2.3. Common Parameters The size and the location of some of the Þelds is changed according to PMAC-PM on all connections. When VPAP-VP on all connections is reset, the structure of the common parameters is the structure of the MC92500. When PMAC-PM on all connections is set, the structure is as follows: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IOPV EOPV OAM_ptr[5:0] NBK BKT_PTR(21:16) 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 BKT_ptr(15:0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IOPV EOPV NBK BKT_PTR(11:00) 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 OAM_Ptr(15:0)

SECTION 13. DATA STRUCTURES This section presents the data structures which where added or updated. 13.1. General Fields 13.1.1. Reason The deÞnition of Reason 01001 is changed: ÒA CRC error was detectedÓ instead of ÒA CRC error was detected (OAM cells only)Ó.

SECTION 14. SIGNAL DESCRIPTION The following are the pins which have been added or whose deÞnition has been changed. 14.1. Microproccessor Signals (MP) The following signal deÞnitions have been updated. The MC92500 MDT ACK signal is renamed to MP Data Acknowledge0 (MDT ACK0) and the MP Data Acknowledge0 (MDTACK1) signal has been added. MP Data Acknowledge0 (MDTACK0), MP Data Acknowledge1 (MDTACK1) MDTACK0 and MDT ACK1 are three-state output signals used to indicate when the data on MDATA is valid during a read access from the MC92501. At the end of each access, these signals are actively pulled up and then released. The user may program the MC92501 not to drive these signals during certain types of accesses. See Section 11.4.6 for details. These signals are active low and the outputs are asynchronous to the MCLK. MP Cell Request Options MREQ0 , MREQ1, and MREQ2 signals replace MCIREQ , MCOREQ, and EMMREQ, respectively. Each of the MREQ[n] signals are programmable to one of the following options: 1. MP Cell In Request MREQ[n] is an output signal that can be used by an external DMA device as a control line indicating when to start a new cell insertion cycle into the MC92501. It is asserted whenever the cell insertion register array is available to be written. This signal is active low, and the output is on the falling edge of MCLK. 2. MP Cell Out Request MREQ[n] is an output signal that may be used by an external DMA device as a control line indicating when to start a new cell extraction cycle from the MC92501. It is asserted whenever the cell extraction register array is available to be read. The microprocessor control register (MPCTLR) contains the number of maintenance accesses performed in a single maintenance slot. It is active low, and the output is on the falling edge of MCLK. 3. External Memory Maintenance Request MREQ[n] is an output signal that can be asserted a programmable number of clock cycles before the start of an external memory maintenance cycle (see Section 11.4.7). It is negated after a programmable number of maintenance accesses have been performed. It is active low, and the output is on the falling edge of MCLK. MP Request 0 (MREQ0 This output signal can be programmed to one of the above three options. Its default value is the Þrst option: MP Cell In Request (MCIREQ MP Request 1 (MREQ1) This output signal can be programmed to one of the above three options. Its default value is the second option: MP Cell Out Request (MCOREQ MP Request 2 (MREQ2) This output signal can be programmed to one of the above three options. Its default value is the third option: External Memory Maintenance Request (EMMREQ NOTE The default values of MREQ0 , MREQ1 , and MREQ2 signals are MCIREQ , MCOREQ , and EMMREQ, respectively. These default values make the MC92501 backwards-compatible with the MC92500. MP Word Write Enable High / Address 1 (MWSH /A1) This input signal can be programmed by the WSSMÑWord Select Signals Mode bit to one of the following modes: 1. Write-Enable Mode: This signal indicates that the high word is being written. During a maintenance write access, the value detected on MWSH /A1 is driven on the appropriate EMBSH signal. During the read access, the EMBSH signal is always asserted. This signal is active low. 2. Add1-Size Mode: This signal serves as address 1 during a maintenance write access. During a read access, this signal is ignored. This signal is sampled by the MC92501 on the falling edge of MCLK. MP Word Write Enable Low / SIZE (MWSL /SIZE) This input signal can be programmed by the WSSMÑWord Select Signals Mode bit to one of the following modes: 1. Write-Enable Mode: This signal indicates that the low word is being written. During a maintenance write access, the value detected on MWSL /SIZE is driven on the appropriate EMBSL signal. During the read access, the EMBSL signal is always asserted. This signal is active low. 2. Add1-Size Mode: This signal indicates the size of the maintenance write access which is either 32-bit or 16-bit access. During a read access, this signal is ignored and the access width is 32 bits. This signal is sampled by the MC92501 on the falling edge of MCLK. NOTE All cell extraction register, cell insertion register, and general register accesses are long-word (32- bit) accesses, so both MWSH /A1 and MWSL / SIZE should be asserted low for these write accesses when write-enable mode is selected.

14.2. Ingress PHY Signals The deÞnition of RXPHYID0-3 has been updated. The RXADDR4 signal has been added. Receive PHY ID 0-3/Receive Address 0-3 (RXPHYID0ÐRXPHYID3/RXADDR0ÐRXADDR3) This bus has two modes depending on the IUMÑIngress UTOPIA Mode bit of the Ingress PHY ConÞguration Register (IPHCR): ¥ In UTOPIA Level 1 Ñ The RXPHYID0ÐRXPHYID3 input bus indicates the ID number of the PHY device currently transferring data to the MC92501. If only a single PHY de- vice is supported, this bus should be tied low. This bus is sampled along with the Þrst octet of each cell. ¥ In UTOPIA Level 2 Ñ The RXADD0ÐRXADDR3 output bus that indicates the four least signiÞcant bits of the ID number of the PHY device which is being polled or selected by the MC92501. See Section 10 for details. Receive Address 4 (RXADDR4) This signal is an output signal that indicates the most signiÞcant bit of the ID number of the PHY device which is being polled or selected by the MC92501. See Section 10 for details. 14.3. Egress PHY Signals The TXPHYID0-3 deÞnition has been updated and renamed to TXPH. TXPHYIDV/TXADDR4 signal replaces TXPHYID V signal of the MC92500. Transmit PHY ID 0-3 / Transmit Address 0-3 (TXPHYID0ÐTXPHYID3/TXADDR0ÐTXADDR3) This bus has two modes depending on the EUMÑEgress UTOPIA Mode bit: ¥ In UTOPIA Level 1 Ñ The TXPHYID0ÐTXPHYID3 output bus indicates the ID number of the PHY device to which either the current cell or the next cell is directed. The func- tionality is controlled by the MC92500 General ConÞgura- tion Register (GCR). ¥ In UTOPIA Level 2 Ñ The TXADDR0ÐTXADDR3 output bus indicates the four less signiÞcant bits of the ID number of the PHY device which is being polled or selected by the MC92501. See Section 10 for details. Transmit Next PHY ID Valid/Transmit Address 4 (TXPHYID V/TXADDR4) This bit has two modes depending on the EUMÑEgress UTOPIA Mode bit: ¥ In UTOPIA Level 1 Ñ The TXPHYIDV output signal, when low, indicates that TXPHYID (when conÞgured as the next cellÕs ID) is valid. If TXPHYID is conÞgured to refer to the current cell, TXPHYIDV is not used. ¥ In UTOPIA Level 2 Ñ The TXADDR4 output signal indi- cates the most signiÞcant bit of the ID number of the PHY device which is being polled or selected by the MC92501. See Section 10 for details.

Table 6. Boundary Scan Bit DeÞnition

SECTION 16. ELECTRICAL CHARACTERISTICS 16.1. Electrical Specification for Clocks and Interfaces Electrical speciÞcations for the clocks, microprocessor interface timing, PHY interface timing, switch interface timing, and external memory interface timing are identical to the MC92500. Please refer to document MC92500/D for speciÞc values. 16.2. DC Electrical Characteristics ABSOLUTE MAXIMUM RATINGS (See Note) NOTE: Maximum ratings are those values beyond which damage to the device may occur. RECOMMENDED OPERATING CONDITIONS (To Guarantee Functionality) NOTES: 1. All parameters are characterized for dc conditions after thermal equilibrium has been established. 2. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). 3. All input, bidirectional, and MDT ACK are 5 V tolerant. 4. SRXDATAx, SRXSOC, SRXPRTY , TDO three-state outputs must be constrained to 0 £ Vout < VDD in High-Z state. PRELIMINARY DC ELECTRICAL CHARACTERISTICS (TA = 0 to 70°C) VDD = 3.3 V ± 0.3 V *Inputs may be modiÞed to include pull resistors at any time. Symbol Parameter Value/Value Range Unit VDD DC Supply Voltage - 0.5 to 3.8 V Vin3 DC Input Voltage (5 V Tolerant) - 0.5 to 5.8 V Vout3,4 DC Output Voltage - 0.5 to V DD +0.5 V I DC Current Drain per Pin, Any Single Input or Output ± 50 mA I DC Current Drain V DD and VSS Pins ± 100 mA Tstg Storage Temperature - 65 to 150 °C TL Lead Temperature (10-Second Soldering) 300 °C Parameter Symbol Min Max Unit DC Supply Voltage, VDD = 3.3 V (Nominal) V DD 3.0 3.6 V Input Voltage (5 V Tolerant) V in4 0 5.5 V Commercial Operating Temperature T A 07 0 °C Symbol Parameter Condition Min Max Unit VIH TTL Inputs (5 V Tolerant) 2.2 5.5 V VIL TTL Inputs (5 V Tolerant) - 0.3 0.8 V Iin Input Leakage Current, No Pull Resistor V in = VDD or VSS - 5 5 mA With Pullup Resistor* - 50 - 5 With Pulldown Resistor* 55 0 IOH Output High Current, LVTTL Output Type Outputs: EACEN, EMWR, EMADDx, EMBSHx, EMBSLx VDD = Min, VOH Min = 0.8 VDD - 24 Ñ mA Output High Current, LVTTL Output Type Outputs: All Other Outputs - 4 Ñ IOL Output Low Current, LVTTL Output Type Outputs: EACEN, EMWR, EMADDx, EMBSHx, EMBSLx VDD = Min, VOL Max = 0.4 V 24 Ñ mA Output Low Current, LVTTL Output Type Outputs: All Other Outputs IOZ Output Leakage Current, Three-State Output Output = High Impedence, Vout = VDD or VSS - 10 10 mA IDDQ Max Quiescent Supply Current I out = 0 mA Vin = VDD or VSS TBD TBD mA IDD Max Dynamic Supply Current Nominal Load Capacitance, ACLK = 25.6 MHz, MCLK = 33 MHz TBD TBD mA Ci Input Capacitance (TTL) 8p F This device contains protection circuitry to guard against damage due to high static voltages or electric Þelds. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-imped- ance circuit. For proper operation it is recom- mended that Vin and Vout be constrained to 0 (Vin, Vout) £ 5.5 V. Unused outputs must always be tied to an ap- propriate logic voltage level (e.g., either V SS or VDD). Unused outputs must be left open.

SECTION 17. PACKAGING INFORMATION 17.1. Additional Pins The following pins have been added: D14 Ñ MP Data Acknowledge0 (MDTACK1), and C15 Ñ Receive Address 4 (RXADDR4). These pins do not appear on the MC92500. 17.2. Pin Assignment Pack- age Pin Signal Name Pack- age Pin Signal Name Pack- age Pin Signal Name Pack- age Pin Signal Name Pack- age Pin Signal Name Pack- age Pin Signal Name C3 TESTOUT A8 MSEL A14 SRXDATA:0 E17 RXDATA:3 J19 EMDATA:18 R19 EMADD:23 A2 ACLK D9 MREQ:0 B14 SRXCLK C20 RXDATA:2 J20 EMDATA:17 P17 EMADD:22 B2 TESTSEL C9 MREQ:1 C14 SRXCLAV D19 RXDATA:1 K17 EMDATA:16 R18 EMADD:21 D5 MADD:17 B9 MDTACK0 A15 SRXSOC E18 RXDATA:0 K18 EMDATA:15 T20 EMADD:20 A3 MADD:16 A9 MINT B15 SRXPRTY D20 EMDATA:31 K19 EMDATA:14 T19 EMADD:19 B4 MADD:15 D10 MREQ:2 D14 MDTACK1 E19 EMDATA:30 K20 EMDATA:13 U20 EMADD:18 C5 MADD:14 C10 MCLK C15 RXADDR4 F18 EMDATA:29 L20 EMDATA:12 V20 EMADD:17 A4 MADD:13 B10 MWR A16 RXSOC G17 EMDATA:28 L18 EMDATA:11 T17 EMADD:16 B5 MADD:12 A10 MWSH/A1 B16 RXENB E20 EMDATA:27 L19 EMDATA:10 U18 EMADD:15 C6 MADD:11 A11 MWSL/SIZE C16 RXEMPTY F19 EMDATA:26 M20 EMDATA:9 U19 EMADD:14 D7 MADD:10 C11 MDS A17 RXPHYID:3 G18 EMDATA:25 M19 EMDATA:8 V18 EMADD:13 A5 MADD:9 B11 SRXENB A18 RXPHYID:2 F20 EMDATA:24 M18 EMDATA:7 Y19 EMADD:12 B6 MADD:8 A12 SRXDATA:7 D16 RXPHYID:1 G19 EMDATA:23 M17 EMDATA:6 W18 EMADD:11 C7 MADD:7 B12 SRXDATA:6 C17 RXPHYID:0 G20 EMDATA:22 N20 EMDATA:5 V17 EMADD:10 A6 MADD:6 C12 SRXDATA:5 B17 RXPRTY H18 EMDATA:21 N19 EMDATA:4 U16 EMADD:9 B7 MADD:5 D12 SRXDATA:4 C18 RXDATA:7 H19 EMDATA:20 N18 EMDATA:3 Y18 EMADD:8 A7 MADD:4 A13 SRXDATA:3 B20 RXDATA:6 H20 EMDATA:19 P20 EMDATA:2 W17 EMADD:7 C8 MADD:3 B13 SRXDATA:2 C19 RXDATA:5 J17 EACEN P19 EMDATA:1 Y17 EMADD:6 B8 MADD:2 C13 SRXDATA:1 D18 RXDATA:4 J18 EMWR R20 EMDATA:0 W16 EMADD:5 V15 EMADD:4 W10 TDO U5 TXPRTY P1 MDATA:25 H2 MDATA:5 U14 EMADD:3 Y9 TDI V4 TXSOC N3 MDATA:24 H3 MDATA:4 Y16 EMADD:2 W9 ENID W4 TXDATA:7 N2 MDATA:23 G1 MDATA:3 W15 N/C V9 STXCLK V3 TXDATA:6 N1 MDATA:22 G2 MDATA:2 Y15 EMBSH:0 U9 STXCLAV W1 TXDATA:5 M4 MDATA:21 G3 MDATA:1 W14 EMBSH:1 Y8 STXSOC V2 TXDATA:4 M3 MDATA:20 F1 MDATA:0 Y14 EMBSH:2 W8 STXPRTY U3 TXDATA:3 M2 MDATA:19 F2 MADD:25 V13 EMBSH:3 V8 STXDATA:7 T4 TXDATA:2 M1 MDATA:18 G4 MADD:24 W13 N/C Y7 STXDATA:6 V1 TXDATA:1 L4 MDATA:17 F3 MADD:23 Y13 EMBSL:0 W7 STXDATA:5 U2 TXDATA:0 L3 MDATA:16 E1 MADD:22 U12 EMBSL:1 V7 STXDATA:4 T3 TXPHYID:3 L2 MDATA:15 E2 MADD:21 V12 EMBSL:2 Y6 STXDATA:3 U1 TXPHYID:2 L1 MDATA:14 E3 MADD:20 W12 EMBSL:3 W6 STXDATA:2 T2 TXPHYID:1 K1 MDATA:13 D1 MADD:19 Y12 N/C U7 STXDATA:1 R3 TXPHYID:0 K3 MDATA:12 C1 MADD:18 U11 AMODE:1 V6 STXDATA:0 P4 MDATA:31 K2 MDATA:11 D2 VCOCTL V11 AMODE:0 Y5 STXENB T1 MDATA:30 J1 MDATA:10 W11 ARST W5 TXENB R2 MDATA:29 J2 MDATA:9 Y11 TCK V5 TXFULL P3 MDATA:28 J3 MDATA:8 Y10 TRST Y4 TXCCLR R1 MDATA:27 J4 MDATA:7 V10 TMS Y3 TXPHYIDV/ TXADDR4 P2 MDATA:26 H1 MDATA:6

17.3. 256-Lead GTBGA Outline /C0068/C0073/C0077/C0077/C0073/C0078 /C0077/C0065/C0088 /C0077/C0073/C0076/C0076/C0073/C0077/C0069/C0084/C0069/C0082/C0083 /C0065/C0045/C0045/C0045/C0050/C0046/C0056/C0051 /C0065/C0049/C0048/C0046/C0053/C0048 /C0048/C0046/C0055/C0048 /C0065/C0050/C0048/C0046/C0053/C0054/C0082/C0069/C0070 /C0065/C0051/C0049/C0046/C0049/C0053 /C0049/C0046/C0052/C0057 /C0098/C0048/C0046/C0054/C0053 /C0048/C0046/C0056/C0053 /C0068/C0050/C0055/C0046/C0048/C0048/C0066/C0083/C0067 /C0069/C0050/C0055/C0046/C0048/C0048/C0066/C0083/C0067 /C0101/C0049/C0046/C0050/C0055/C0066/C0083/C0067 /C0070/C0049/C0055/C0046/C0055/C0056 /C0050/C0052/C0046/C0048/C0048 /C0071/C0049/C0055/C0046/C0055/C0056 /C0050/C0052/C0046/C0048/C0048 /C0082/C0049/C0050/C0046/C0053/C0048/C0082/C0069/C0070 /C0082/C0050/C0048/C0046/C0052/C0048 /C0050/C0046/C0053/C0048 /C0078/C0079/C0084/C0069/C0083/C0058 /C0049/C0046 /C0068/C0073/C0077/C0069/C0078/C0083/C0073/C0079/C0078/C0083 /C0065/C0082/C0069 /C0073/C0078 /C0077/C0073/C0076/C0076/C0073/C0077/C0069/C0084/C0069/C0082/C0083/C0046 /C0050/C0046 /C0073/C0078/C0084/C0069/C0082/C0080/C0082/C0069/C0084 /C0068/C0073/C0077/C0069/C0078/C0083/C0073/C0079/C0078/C0083 /C0065/C0078/C0068 /C0084/C0079/C0076/C0069/C0082/C0065/C0078/C0067/C0069/C0083 /C0080/C0069/C0082/C0065/C0083/C0077/C0069/C0089/C0049/C0052/C0046/C0053/C0077/C0044/C0049/C0057/C0057/C0052/C0046 /C0051/C0046 /C0068/C0073/C0077/C0069/C0078/C0083/C0073/C0079/C0078 /C0098 /C0073/C0083 /C0077/C0069/C0065/C0083/C0085/C0082/C0069/C0068 /C0065/C0084 /C0084/C0072/C0069 /C0077/C0065/C0088/C0073/C0077/C0085/C0077 /C0083/C0079/C0076/C0068/C0069/C0082 /C0066/C0065/C0076/C0076 /C0068/C0073/C0065/C0077/C0069/C0084/C0069/C0082/C0044 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076 /C0084/C0079 /C0068/C0065/C0084/C0085/C0077 /C0080/C0076/C0065/C0078/C0069 /C0090/C0046 /C0052/C0046 /C0068/C0065/C0084/C0085/C0077 /C0090 /C0040/C0083/C0069/C0065/C0084/C0073/C0078/C0071 /C0080/C0076/C0065/C0078/C0069/C0041 /C0073/C0083 /C0068/C0069/C0070/C0073/C0078/C0069/C0068 /C0066/C0089 /C0084/C0072/C0069 /C0083/C0080/C0072/C0069/C0082/C0073/C0067/C0065/C0076 /C0067/C0082/C0079/C0087/C0078/C0083 /C0079/C0070 /C0084/C0072/C0069 /C0083/C0079/C0076/C0068/C0069/C0082 /C0066/C0065/C0076/C0076/C0083/C0046 /C0053/C0046 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076/C0073/C0083/C0077 /C0082/C0069/C0081/C0085/C0073/C0082/C0069/C0077/C0069/C0078/C0084 /C0065/C0080/C0080/C0076/C0073/C0069/C0083 /C0084/C0079 /C0090/C0079/C0078/C0069 /C0084 /C0079/C0078/C0076/C0089/C0046 /C0080/C0065/C0082/C0065/C0076/C0076/C0069/C0076/C0073/C0083/C0077 /C0082/C0069/C0081/C0085/C0073/C0082/C0069/C0077/C0069/C0078/C0084 /C0083/C0072/C0065/C0076/C0076 /C0069/C0088/C0067/C0076/C0085/C0068/C0069 /C0065/C0078/C0089 /C0069/C0070/C0070/C0069/C0067/C0084 /C0079/C0070 /C0076/C0065/C0083/C0069/C0082 /C0077/C0065/C0082/C0075 /C0079/C0078 /C0084/C0079/C0080/C0083/C0085/C0082/C0070/C0065/C0067/C0069 /C0079/C0070 /C0080 /C0065/C0067/C0075/C0065/C0071/C0069/C0046 M M DETAIL K Z /C0048/C0046/C0049/C0053 /C0090 /C0048/C0046/C0051/C0053 /C0090 A A1A3 R14X E Y X /C0048/C0046/C0050/C0048 F G R24X /C0049/C0050/C0046/C0055/C0056 /C0083/C0081/C0085/C0065/C0082/C0069 D /C0090/C0079/C0078/C0069/C0084 /C0049/C0053 b256X e19X VIEW M±M /C0088/C0048/C0046/C0051/C0048 /C0089/C0090 /C0048/C0046/C0049/C0048/C0090 /C0065 /C0066 /C0067 /C0053/C0049 DETAIL K ROTATED 90 CLOCKWISE/C0095 /C0068 /C0069 /C0070 /C0071 /C0072 /C0074 /C0075 /C0076 /C0077 /C0078 /C0080 /C0082 /C0084 /C0085 /C0086 /C0087 /C0089 /C0050/C0048 S e19X S /C0082/C0049/C0048/C0046/C0054/C0051/C0053/C0066/C0083/C0067 PACKAGE DIMENSIONS GLOB-TOP BALL GRID ARRAY (GTBGA) PACKAGE GC SUFFIX CASE 1208-01

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