MC88PL117 MOTOROLA | Alldatasheet

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/C0077/C0079/C0084/C0079/C0082/C0079/C0076/C0065 SEMICONDUCTOR TECHNICAL DATA 1 REV 4 Motorola, Inc. 1997 /C0078/C0111/C0116 /C0082/C0101/C0099/C0111/C0109/C0109/C0101/C0110/C0100/C0101/C0100 /C0102/C0111/C0114 /C0078/C0101/C0119 /C0068/C0101/C0115/C0105/C0103/C0110/C0115 /C0067/C0077/C0079/C0083 /C0080/C0076/C0076 /C0067/C0108/C0111/C0099/C0107 /C0068/C0114/C0105/C0118/C0101/C0114 /C0080/C0114/C0111/C0103/C0114/C0097/C0109/C0109/C0097/C0098/C0108/C0101 /C0070/C0114/C0101/C0113/C0117/C0101/C0110/C0099/C0121/C0044 /C0076/C0111/C0119 /C0083/C0107/C0101/C0119/C0044 /C0072/C0105/C0103/C0104 /C0070/C0097/C0110/C0045/C0079/C0117/C0116 The MC88PL117 utilizes proven phase–locked loop clock driver technology to create a large fan–out, multiple frequency and phase, low skew clock driver. The 88PL117 provides the clock frequencies necessary to drive systems using the PowerPC 601 microprocessor and the Pentium microprocessor (see applications section for details). A total of 14 high current, matched impedance outputs are available in 8 programmable output frequency and phase configurations. Output frequencies are referenced to a system frequency, Q, and are available at 2X, 1X, and 1/2X the Q frequency. Four programmable input frequency multiplication ratios can be programmed to provide outputs at 1X, 2X, and 4X the system frequency Q. Details on the programmable configurations can be found in the applications section of this data sheet.

  • Clock Driver for PowerPC 601 and Pentium Microprocessors
  • 14 programmable outputs
  • Maximum output–to–output skew of 500ps for a single frequency
  • Maximum output–to–output skew of 500ps for multiple frequencies
  • fMAX of 2X_Q = 120MHz
  • One output with programmable phase capability
  • ±36mA DC current outputs drive 50Ω transmission lines
  • A lock indicator output (LOCK) goes high when steady–state phase–lock is achieved
  • OE/MR 3–state control
  • Dedicated feedback output
  • Two selectable clock inputs
  • PLL enable pin for testability
  • Dynamic Switch Between SYNC Inputs One output (QFEED) is dedicated for feedback. It is located physically close to the FEEDBACK input pin to minimize the feedback line length. External delay (increased wire length) or logic can be inserted in the feedback path if necessary. Proper termination of the feedback line is necessary for any line length over one inch. One output is provided with up to eight selectable 1/8 or 1/4 period (45° or 90°) delay increments. Three control pins, ∅ 2, ∅ 1 and ∅ 0, program the eight increments; the increment/phase shift positions are shown in Table 3. in the applications section. All outputs can be 3–stated (high impedance) during board–level testing with the OE/MR pin; the QFEED and LOCK outputs will not be 3–stated, which allows the 88PL117 to remain in a phase–locked condition. Correct phase and frequency coherency will be guaranteed one to two cycles after bringing the OE/MR pin high. The PLL_EN pin disables the PLL and gates the SYNC input signal directly into the internal clock distribution network to provide low frequency testability. Two selectable SYNC inputs (SYNC0 and SYNC1) are provided for clock redundancy or ease of testability. The device is guaranteed to lock to the new SYNC input when the REF_SEL input is switched dynamically. A phase–lock indicator output (LOCK) stays low when the part is out of lock (start–up, etc.) and goes high when steady–state phase–lock is achieved. The lock indicator circuitry works reliably for VCO frequencies down to 55MHz. For VCO frequencies less than 55MHz, no guarantees are offered for the lock indicator output. The MC88PL117 VCO is capable of operating at frequencies higher than the output divider and feedback structures are able to follow. When the VCO is in the mode described above, it is referred to as “runaway” and the device will not lock. The condition usually occurs at power–up. To avoid runaway, it is recommended that the device be fully powered before a sync signal is applied. PowerPC is a trademark of International Business Machines Corporation. /C0077/C0067/C0056/C0056/C0080/C0076/C0049/C0049/C0055 CMOS PLL CLOCK DRIVER FN SUFFIX 52–LEAD PLASTIC LEADLESS CHIP CARRIER (PLCC) CASE 778–02

BR1333 — Rev 6 Pinout: 52–Lead PLCC (Top View) QFEED VCC FEEDBACK GND AV CC FIL AGND GND Q13 VCC Q12 REF_SEL SYNC1 MULT0 MULT1 GND VCC GND VCC ∅ 0 ∅ 1 ∅ 2 SYNC033 DV DD32 DGND31 Q ∅30 Q1129 VCC28 Q1027 GND26 Q925 VCC24 Q823 GND22 PLL_EN21 47LOCK 48OE/MR 49Q0 50VCC 51Q1 52GND 2VCC 3Q3 4GND 5OPT0 6OPT1 7OPT2 MC88PL117

BR1333 — Rev 6

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MC88PL117 Block Diagram (Logical Representation) Q0DQ R Q13DQ R QFEEDDQ R Q ∅DQ R LOCK INDICATOR CIRCUITRY PFD CH PUMP VCO SYNC0 SYNC1 REF_SEL Disable FEEDBACK PLL_EN EXTERNAL FILTER PIN OUTPUT FREQUENCY AND PHASE CONTROL LOGIC OPT2 OPT1 OPT0 FEEDBACK LOGIC PHASE DELAY LOGIC ∅ 2 ∅ 1 ∅ 0 MULT1 MULT0 POWER–ON RESET OE/MR LOCK

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Figure 5. Output Frequency Configuration 5 Figure 6. Output Frequency Configuration 6

  1. IOL and IOH are 12mA and –12mA respectively for the LOCK output.
  2. The PLL_EN input pin is not guaranteed to meet this specification.
  3. Maximum test duration is 2.0ms, one output loaded at a time.
  4. Specification value for IOZ is preliminary, will be finalized upon ‘MC’ status.

BR1333 — Rev 6 PRELIMINARY AC ELECTRICAL CHARACTERISTICS (TA = 0 to 70°C, VCC = 5.0V ±5%) Target Specifications Symbol Parameter Min Max Unit Condition tskewr Output–to–Output Skew (Same Frequency, Coincident Rising Edges) 500 ps 50Ω Load2 tskewrall Output–to–Output Skew (Any Frequency, Coincident Rising Edges, Q0–Q13, QFEED) 500 ps 50Ω Load2 tskewp Part–to–Part Skew1 1.0 ns 50Ω Load2 tr/tf Output Rise/Fall Time (0.8 to 2.0V) 0.15 1.0 ns 50Ω Load2 tPULSE Output Pulse Width, All Outputs2 (Measured at VCC /2) 0.5tCYCLE – 0.5 0.5tCYCLE + 0.5 ns 50Ω Load2 tpd SYNC Input to f SYNC =15MHz FEEDBACK Delay f SYNC =20MHz fSYNC =25MHz fSYNC =30MHz –200 –200 –100 400 400 500 600 ps Feedback=Q,Q/2 fSYNC =15MHz –50 550 Feedback=Q/4 JitterCC Cycle–to–Cycle Jitter (Clock Period Stability) ±250 ps fMAX Maximum Output Frequency for 2X_Q Outputs 8 120 MHz 50Ω Load2 fMAX Maximum Output Frequency for Q Outputs 4 60 MHz 50Ω Load2 fMAX Maximum Output Frequency for Q/2 Outputs 2 30 MHz 50Ω Load2 tskew∅ Phase Accuracy of Q∅ versus Q or Q/2 Phase Offset – 750Phase Offset + 250 ps 1. This assumes that each device is running off of the same clock source with zero skew between clock source signals. A small amount of negative offset may be present between SYNC and FEEDBACK (tPD Spec). 2. 50Ω load terminated to VCC /2.

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TABLE 1. PROGRAMMABLE OUTPUT CONFIGURATIONS (Q is system reference frequency)

1 L L L 2 12 0

2 L L H 2 4 8

3 L H L 4 10 0

4 L H H 0 14 0

5 H L L 0 7 7

6 H H H 2 12 0

TABLE 2. PROGRAMMABLE INPUT FREQUENCY MODES (Multiplication factors)

1 L L Q/4

2 L H Q/2

3 H H Q

TABLE 3. Q∅ PROGRAMMABLE PHASE INCREMENTS FOR Q AND Q/2 OUTPUTS

  1. Valid for output configurations 1, 3, 4, 6, 8
  2. Valid for output configurations 2, 5, 7

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Figure 11. MPC601 2X_PCLK Input Termination Scheme Figure 12. Recommended Loop Filter and Analog Isolation Scheme

1 Figure 12 shows a loop filter and analog isolation scheme

can cause undesirable voltage transients at the FIL pin. same as a standard bypass capacitor.

2 In addition to the bypass capacitors used in the analog

be tied as close to the package as possible.

BR1333 — Rev 6 OUTLINE DIMENSIONS FN SUFFIX PLASTIC PACKAGE CASE 778-02 ISSUE C –L– Y BRK W D D V 52 1 NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). B U Z X VIEW D–D H K F VIEW S M0.007 (0.18) L–M ST SN M0.007 (0.18) L–M ST SN 0.004 (0.100) –T– SEATING PLANE M0.007 (0.18) L–M ST SN M0.007 (0.18) L–M ST SNA R G C Z J E VIEW S –M– –N– DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.785 0.795 19.94 20.19 B 0.785 0.795 19.94 20.19 C 0.165 0.180 4.20 4.57 E 0.090 0.110 2.29 2.79 F 0.013 0.019 0.33 0.48 G 0.050 BSC 1.27 BSC H 0.026 0.032 0.66 0.81 R 0.750 0.756 19.05 19.20 U 0.750 0.756 19.05 19.20 V 0.042 0.048 1.07 1.21 W 0.042 0.048 1.07 1.21 X 0.042 0.056 1.07 1.42 Z 2 10 2 10 G1 0.710 0.730 18.04 18.54 /C0095/C0095/C0095/C0095 M0.007 (0.18) L–M ST SN M0.007 (0.18) L–M ST SN S0.010 (0.25) L–M ST SN S0.010 (0.25) L–M ST SN

BR1333 — Rev 6

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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution;JAPAN : Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, P.O. Box 5405; Denver, Colorado 80217. 303–675–2140 or 1–800–441–24473–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 INTERNET : http://Design–NET.com 51 Ting Kok R oad, Tai Po, N.T., Hong Kong. 852–26629298 MC88PL117/D◊