MC88LV926 IDT | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 11
Technical content
Features
- 2X_Q Output Meets All Requiremen ts of the 50 and 66 MHz 68060 Microprocessor PCLK Input Specifications
- Low Voltage 3.3 V V CC
- Three Outputs (Q0–Q2) with Output–Output Skew <500 ps
- CLKEN Output for Half Speed Bus Applications
- The Phase Variation from Part-to-Part Between SYNC and the ‘Q' Outputs Is Less than 600 ps (Derived from the TPD Specification, Which Defines the Part-to-Part Skew)
- SYNC Input Frequency Range from 5.0 MHz to 2X_Q F Max/4
- All Outputs Have ± 36 mA Drive (Equal High and Low) CMOS Levels
- Can Drive Either CMOS or TTL Inputs. All Inputs Are TTL-Level Compatible with VCC = 3.3 V
- Test Mode Pin (PLL_EN) Provided for Low Frequency Testing
- 20-Lead SOIC Pb-Free Package Available Three ‘Q' outputs (Q0-Q2) are provided with less than 500 ps skew between their rising edges. A 2X_Q output runs at twice the ‘Q' output frequency. The 2X_Q output is ideal for 68060 systems which require a 2X processor clock input, and it meets the tight duty cycle spec of the 50 and 66 MHz 68060. The QCLKEN output is designed to drive the CLKEN input of the 68060 when the bus logic runs at half of the microprocessor clock rate. The QCLKEN output is skewed relative to the 2X_Q output to ensure that CLKEN setup and hold times of the 68060 are satisfied. A Q/2 frequency is fed back internally, providing a fixed 2X multiplication from the ‘Q' outputs to the SYNC input. Since the feedback is done internally (no external feedback pin is provided) the input/output frequency relationships are fixed. The Q3 output provides an inverted clock output to allow flexibility in the clock tree design. In normal phase-locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the 88LV926 in a static ‘test mode'. In this mode there is no frequency limitation on the input clock, which is necessary for a low frequency board test environment. The RST_OUT(LOCK) pin doubles as a phase-lock indicator. When the RST_IN pin is held high, the open drain RST_OUT pin will be pulled actively low until phase-lock is achieved. When phase-lock occurs, the RST_OUT(LOCK) is released and a pull- up resistor will pull the signal high. To give a processor reset signal, the RST_IN pin is toggled low, and the RST_OUT(LOCK) pin will stay low for 1024 cycles of the ‘Q' output frequency after the RST_IN pin is brought back high. Description of the RST_IN/RST_OUT(LOCK) Functionality The RST_IN and RST_OUT(LOCK) pins provide a 68030/040/060 processor reset function, with the RST_OUT pin also acting as a lock indicator. If the RST_IN pin is held high during system power-up, the RST_OUT pin will be in the low state until steady state phase/frequency lock to the input reference is achieved. 1024 ‘Q' output cycles after phase-lock is achieved the RST_OUT(LOCK) pin will go into a high impedance state, allowing it to be pulled high by an external pull-up resistor (see the AC/ DC specs for the characteristics of the RST_OUT(LOCK) pin). If the RST_IN pin is held low during power-up, the RST_OUT(LOCK) pin will remain low. MC88LV926 LOW SKEW CMOS PLL
68080 CLOCK DRIVER
20-LEAD PLASTIC SOIC PACKAGE CASE 751D-06 EG SUFFIX 20-LEAD PLASTIC SOIC PACKAGE Pb-FREE PACKAGE CASE 751D-06 DATA SHEET MC88LV926 IDT™ Low Skew CMOS PLL 68060 Clock Driver Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MC88LV926 Low Skew CMOS PLL 68060 Clock Driver
2 Freescale Semiconductor
Figure 1. Pinout: 20-Lead Wide SOIC Package (Top View) values (see Figure 7) the lock time is approximately 10ms. back high 1024 cycles after the RST_IN pin goes high. Table 1. Capacitance and Power Specifications
- Value at V CC = 3.3 V TBD
Table 2. Maximum Ratings(1)
- Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions. Table 3. Recommended Operating Conditions Table 4. DC Characteristics (TA = 0°C to 70°C; VCC = 3.3 V ± 0.3 V)(1)
- The MC88LV926 can also be operated from a 3.3V supply. V OH output levels will vary 1:1 with VCC, input levels and current specs will be
unchanged, except VIH; when VCC > 4.0 volts, VIH minimum level is 2.7 volts.
- I OL is +12mA for the RST_OUT output.
- Maximum test duration 2.0ms, one output loaded at a time.
- The PLL_EN input pin is not guaranteed to meet this specification.
4 Freescale Semiconductor
Figure 2. MC88LV926 Logic Block Diagram Table 5. Sync Input Timing Requirements
- When V CC > 4.0 volts, Maximum SYNC Input Period is 125 ns.
NOTE: Maximum Operating Frequency is guaranteed with the 88LV926 in a phase-locked condition. Table 6. Frequency Specifications (TA = 0°C to 70°C; VCC = 3.3 V ± 0.3 V
33 MHz
Table 7. AC Characteristics (TA = 0°C to 70°C; VCC = 3.3V ± 0.3V
- These specifications are not tested, they are guaranteed by stat istical characterization. See Application Note 1 for a discussion of this
- Under equally loaded conditions and at a fixed temperature and voltage.
- Guaranteed that QCLKEN will meet the setup and hold time requirement of the 68060.
- With V CC fully powered–on: tCLOCK Max is with C1 = 0.1 μF; tLOCK Min is with C1 = 0.01 μF.
- Specification is valid onl y when the PLL_EN pin is low.
- See Application Notes, Note 4 for the distribution in time of each output referenced to SYNC.
6 Freescale Semiconductor
- Statistical characterization techniques were used to
varied to create a 14 cell designed experimental matrix. tested specifications limits.
- A 470 K Ω or 1 MΩ resistor tied to either Analog V
ensure no jitter is present on the MC88LV926 outputs. SYNC input and the Q0 output, measured at the pins. 1.5 V. See Figure 3 for a graphical description. Figure 3. Depiction of the Fixed SYNC to Q0 Offset (tPD) Which Is Present Figure 4. RST_OUT Test Circuit
1 MΩ or 470 K Ω
1 MΩ or 470 KΩ
Figure 5. Logical Representation of the MC88LV926 With Input/Output Frequency Relationships Figure 6. Output/Input Switching Waveforms and Timing Relationships
- The t PD spec includes the full temperature range from
specification limits, the tPD spec window will be reduced.
- The RST _OUT pin is an open drain N–Channel output.
resistor is used as a pull-up as shown in Figure 3.
12.5 MHz
66 MHz P–Clock
- The MC88LV926 aligns rising edges of the outputs and th e SYNC input, therefore the SYNC input does not require a
- All skew specs are measured between the V CC/2 crossing point of the appropriate output edges. All skews are specified
as “windows”, not as a ± deviation around a center point.
8 Freescale Semiconductor
- Figure 7 shows a loop filter and analog isolation
cause undesirable voltage transients at the RC1 pin. should not occur at the 88LV926's digital VCC supply. can occur in a high frequency, high speed digital system. same as a standard bypass capacitor.
40 MHz, the 470 K resistor provides the correct amount
resistor should be used (instead of 470 K).
- In addition to the bypass capacitors used in the analog
Figure 7. Recommended Loop Filter and Analog Isolation Scheme for the MC88LV926
6 Analog Loop Filter/VCO Section
A separate Analog power suppy is not necessary and should not be used. MC88LV926 in a normal digital environment. NOTE: Further loop optimization may occur.
Figure 8. Typical MC88LV926/MC68060 System Configuration
16.67 MHz
Advanced Clock Drivers Devices
10 Freescale Semiconductor
7.6 7.4 12.95 12.65 0.25 0.10 2.65 2.35 10.55 10.05 B T AM0.25 B 20X SEATING PLANE 0.1 T M0.25 T A B 20X 18X 0.49 0.35 1.27
0.75 X45˚
0.25 AA 0.32 0.23 1.0 0.4 7˚ NOTES: DIMENSIONS ARE IN MILLIMETERS. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. DATUMS A AND B TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE INTER-LEAD FLASH OR PROTRUSIONS. INTER-LEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE WIDTH TO EXCEED 0.62 MM. SECTION A-A MC88LV926 Low Skew CMOS PLL 68060 Clock Driver NETCOM IDT™ Low Skew CMOS PLL 68060 Clock Driver Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MC88LV926
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA XX-XXXX-XXXXX Corporate Headquarters Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Asia Pacific and Japan Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria Singapore 238877 +65 6 887 5505 Europe IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support netcom@idt.com 480-763-2056 Innovate with IDT and accelerate your future networks. Contact: www.IDT.com PART NUMBERS INSERT PRODUCT NAME AND DOCUMENT TITLE NETCOM MPC92459
900 MHz Low Voltage LVDS Clock Synthesizer NETCOM
Low Skew CMOS PLL 68060 Clock Driver NETCOM