MC88LV915T MOTOROLA | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 11

Technical content

Features

  • Five Outputs (Q0–Q4) with Output–Output Skew < 500 ps each being phase and frequency locked to the SYNC input
  • The phase variation from part–to–part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPD specification, which defines the part–to–part skew)
  • Input/Output phase–locked frequency ratios of 1:2, 1:1, and 2:1 are available
  • Input frequency range from 5MHz – 2X_Q FMAX spec.
  • Additional outputs available at 2X and +2 the system “Q” frequency. Also a Q (180° phase shift) output available
  • All outputs have ±36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs are TTL–level compatible. ±88mA IOL /IOH specifications guarantee 50Ω transmission line switching on the incident edge
  • Test Mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes. All outputs can go into high impedance (3–state) for board test purposes
  • Lock Indicator (LOCK) accuracy indicates a phase–locked state Yield Surface Modeling and YSM are trademarks of Motorola, Inc. /C0077/C0067/C0056/C0056/C0076/C0086/C0057/C0049/C0053/C0084 LOW SKEW CMOS PLL CLOCK DRIVER

BR1333 — Rev 6 PLL_ENGNDQ1VCCQ0GNDFREQ_SEL LOCK GND VCC GND Q/2 RC1 GND(AN) VCC (AN) SYNC[1] SYNC[0] REF_SEL FEEDBACK 2X_QOE /RST VCC VCCQ4Q5 GND 1911 18171612 13 14 15 26272843 21 Pinout: 28–Lead PLCC (Top View) Reference clock input Reference clock input Chooses reference between sync[0] & Sync[1] Doubles VCO Internal Frequency (low) Feedback input to phase detector Input for external RC network Clock output (locked to sync) Inverse of clock output 2 x clock output (Q) frequency (synchronous) Clock output(Q) frequency ÷ 2 (synchronous) Indicates phase lock has been achieved (high when locked) Output Enable/Asynchronous reset (active low) Disables phase–lock for low freq. testing Power and ground pins (note pins 8, 10 are “analog” supply pins for internal PLL only) Input Input Input Input Input Input Output Output Output Output Output Input Input PIN SUMMARY SYNC[0] SYNC[1] REF_SEL FREQ_SEL FEEDBACK RC1 Q(0–4) 2x_Q Q/2 LOCK OE /RST PLL_EN VCC ,GND Pin Name Num I/O Function FN SUFFIX PLASTIC PLCC CASE 776–02

BR1333 — Rev 6

3 MOTOROLA

M U X M U X MUX PLL_EN R R R R R R R OE /RST FEEDBACK Q/2Q CP D Q CP D Q CP D EXTERNAL REC NETWORK (RC1 Pin) REF_SEL SYNC (1) SYNC (0) CHARGE PUMP/LOOP FILTER DIVIDE BY TWO Q3Q CP D 2x_Q Q CP D Q CP D Q Q CP D (÷1) (÷2) FREQ_SEL OSCILLATOR VOLTAGE CONTROLLEDPHASE/FREQ. DETECTOR LOCK

BR1333 — Rev 6 MAXIMUM RATINGS* Symbol Parameter Limits Unit VCC , AVCC DC Supply Voltage Referenced to GND –0.5 to 7.0 V Vin DC Input Voltage (Referenced to GND) –0.5 to VCC +0.5 V Vout DC Output Voltage (Referenced to GND) –0.5 to VCC +0.5 V Iin DC Input Current, Per Pin ±20 mA Iout DC Output Sink/Source Current, Per Pin ±50 mA ICC DC V CC or GND Current Per Output Pin ±50 mA Tstg Storage Temperature –65 to +150 °C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Limits Unit VCC Supply Voltage 3.3 ±0.3 V Vin DC Input Voltage 0 to VCC V Vout DC Output Voltage 0 to VCC V TA Ambient Operating Temperature 0 to 70 °C ESD Static Discharge Voltage > 1000 V DC CHARACTERISTICS (TA = 0°C to 70°C; VCC = 3.3V ± 0.3V) Symbol Parameter VCC Guaranteed Limits Unit Condition VIH Minimum High Level Input Voltage 3.0 3.3 2.0 2.0 V VOUT = 0.1V or VCC – 0.1V VIL Minimum Low Level Input Voltage 3.0 3.3 0.8 0.8 V VOUT = 0.1V or VCC – 0.1V VOH Minimum High Level Output Voltage 3.0 3.3 2.4 2.7 V VIN = VIH or VIL IOH = –24mA VOL Minimum Low Level Output Voltage 3.0 3.3 0.44 0.44 V VIN = VIH or VIL IOH = 24mA IIN Maximum Input Leakage Current 3.6 ±1.0 µA VI = VCC , GND ICCT Maximum ICC /Input 3.6 2.0 mA VI = VCC – 2.1V IOLD Minimum Dynamic3 Output Current 3.6 +50 mA VOLD = 1.25V IOHD 3.6 –50 mA VOHD =2.35V ICC Maximum Quiescent Supply Current 3.6 TBD µA VI = VCC , GND 1. IOL is +12mA for the RST_OUT output. 2. The PLL_EN input pin is not guaranteed to meet this specification. 3. Maximum test duration 2.0ms, one output loaded at a time. SYNC INPUT TIMING REQUIREMENTS Symbol Parameter Minimum Maximum Unit tRISE/FALL SYNC Input Rise/Fall Time, SYNC Input From 0.8V to 2.0V — 5.0 ns tCYCLE , SYNC Input Input Clock Period SYNC Input f2X_Q /C03244 100 ns Duty Cycle Duty Cycle, SYNC Input 50% ± 25%

BR1333 — Rev 6

5 MOTOROLA

FREQUENCY SPECIFICATIONS (TA = 0°C to 70°C; VCC = 3.3V ± 0.3V) Symbol Parameter Guaranteed Minimum Unit Fmax (2X_Q) Maximum Operating Frequency, 2X_Q Output 100 MHz Fmax (‘Q’) Maximum Operating Frequency, Q0–Q3 Outputs

50 MHz

NOTE: Maximum Operating Frequency is guaranteed with the 88LV926 in a phase–locked condition. AC CHARACTERISTICS (TA =0° C to +70° C, VCC = 3.3V ±0.3V, Load = 50Ω Terminated to VCC /2) Symbol Parameter Min Max Unit Condition tRISE/FALL Outputs Rise/Fall Time, All Outputs (Between 0.8 to 2.0V) 0.5 2.0 ns Into a 50Ω Load Terminated to VCC /2 tPULSE WIDTH (Q0–Q4, Q5, Q/2) Output Pulse Width: Q0, Q1, Q2, Q3, Q4, Q5, Q/2 @ VCC /2 0.5tCYCLE – 0.51 0.5tCYCLE + 0.51 ns Into a 50Ω Load Terminated to VCC /2 tPULSE WIDTH (2X_Q Output) Output Pulse Width: 40MHz 2X_Q @ 1.5V 66MHz 80MHz 100MHz 0.5tCYCLE – 1.5 0.5tCYCLE – 1.0 0.5tCYCLE – 1.0 0.5tCYCLE – 1.0 0.5tCYCLE + 0.5 0.5tCYCLE + 0.5 0.5tCYCLE + 0.5 0.5tCYCLE + 0.5 ns Into a 50Ω Load Terminated to VCC /2 tCYCLE (2x_Q Output) Cycle–to–Cycle Variation 40MHz 2x_Q @ VCC /2 66MHz 80MHz 100MHz tCYCLE – 600ps tCYCLE – 300ps tCYCLE – 300ps tCYCLE – 400ps tCYCLE + 600ps tCYCLE + 300ps tCYCLE + 300ps tCYCLE + 400ps tPD 2 SYNC Feedback (With 1MΩ from RC1 to An VCC ) ns SYNC Feedback SYNC Input to Feedback Delay 66MHz (Measured at SYNC0 or 1 and 80MHz FEEDBACK Input Pins) 100MHz –1.65 –1.45 –1.25 –1.05 –0.85 –0.65 tSKEWr 3 (Rising) See Note 4 Output–to–Output Skew Between Out- puts Q0–Q4, Q/2 (Rising Edges Only) — 500 ps All Outputs Into a Matched 50Ω Load Terminated to VCC /2 tSKEWf 3 (Falling) Output–to–Output Skew Between Out- puts Q0–Q4 (Falling Edges Only) — 750 ps All Outputs Into a Matched 50Ω Load Terminated to VCC /2 tSKEWall3 Output–to–Output Skew 2X_Q, Q/2, Q0–Q4 Rising, Q5 Falling — 750 ps All Outputs Into a Matched 50Ω Load Terminated to VCC /2 tLOCK 4 Time Required to Acquire Phase–Lock From Time SYNC Input Signal is Received 1.0 10 ms Also Time to LOCK Indicator High tPZL 5 Output Enable Time OE/RST to 2X_Q, Q0–Q4, Q5, and Q/2 3.0 14 ns Measured With the PLL_EN Pin Low tPHZ ,tPLZ 5 Output Disable Time OE/RST to 2X_Q, Q0–Q4, Q5, and Q/2 3.0 14 ns Measured With the PLL_EN Pin Low 1. TCYCLE in this spec is 1/Frequency at which the particular output is running. 2. The TPD specification’s min/max values may shift closer to zero if a larger pullup resistor is used. 3. Under equally loaded conditions and at a fixed temperature and voltage. 4. With VCC fully powered–on, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1µF, tLOCK minimum is with C1 = 0.01µF. 5. The tPZL , tPHZ , tPLZ minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is reached.

  • The MC88LV915T aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does not require a 50% duty cycle.
  • All skew specs are measured between the VCC /2 crossing point of the appropriate output edges.All skews are specified as ‘windows’, not as a ± deviation around a center point.
  • If a “Q” output is connected to the FEEDBACK input (this situation is not shown), the “Q” output frequency would match the SYNC input frequency, the 2X_Q output would run at twice the SYNC frequency, and the Q/2 output would run at half the SYNC frequency. Timing Notes: (These waveforms represent the hook–up configuration of Figure 2a on page 7) FEEDBACK INPUT SYNC INPUT (SYNC[1] or SYNC[0])

Figure 1. Output/Input Switching Waveforms and Timing Diagrams

BR1333 — Rev 6

7 MOTOROLA

Figure 2c. Wiring Diagram and Frequency Relationships with 2X_Q Output Feed Back Figure 2b. Wiring Diagram and Frequency Relationships With Q4 Output Feed Back Figure 2a. Wiring Diagram and Frequency Relationships With Q/2 Output Feed Back Allowable Input Frequency Range: 20MHz to (2X_Q FMAX Spec) (for FREQ_SEL HIGH) 10MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL LOW) Allowable Input Frequency Range: 10MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL HIGH) 5MHz to (2X_Q FMAX Spec)/4 (for FREQ_SEL LOW) In this application, the 2X_Q output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of 2X_Q and SYNC, thus the 2X_Q frequency will equal the SYNC frequency. The Q/2 output will always run at 1/4 the 2X_Q fre- quency, and the “Q” outputs will run at 1/2 the 2X_Q frequency. 2:1 Input to “Q” Output Frequency Relationship In this application, the Q4 output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of Q4 and SYNC, thus the Q4 frequency (and the rest of the “Q” outputs) will equal the SYNC frequency. The Q/2 output will al- ways run at 1/2 the “Q” frequency, and the 2X_Q output will run at 2X the “Q” frequency. 1:1 Input to “Q” Output Frequency Relationship Allowable Input Frequency Range: 5MHz to (2X_Q FMAX Spec)/4 (for FREQ_SEL HIGH) 2.5MHz to (2X_Q FMAX Spec)/8 (for FREQ_SEL LOW) In this application, the Q/2 output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of Q/2 and SYNC, thus the Q/2 frequency will equal the SYNC frequency. The “Q” outputs (Q0–Q4, Q5 ) will always run at 2X the Q/2 frequency, and the 2X_Q output will run at 4X the Q/2 frequency. 1:2 Input to “Q” Output Frequency Relationship 50MHz FEEDBACK SIGNAL 25MHz FEEDBACK SIGNAL 25MHz SIGNAL 25MHz SIGNAL 100MHz FEEDBACK SIGNAL 2X_Q ANALOG V CC CRYSTAL OSCILLATOR 100MHz INPUT HIGH LOW HIGH HIGH PLL_ENFQ_SEL Q0 Q1 Q/2 RST FEEDBACK REF_SEL SYNC[0] ANALOG GND RC1 MC88LV915T EXTERNAL LOOP FILTER 100MHz SIGNAL 2X_Q ANALOG V CC CRYSTAL OSCILLATOR 50MHZ INPUT HIGH LOW HIGH HIGH PLL_ENFQ_SEL Q0 Q1 Q/2 RST FEEDBACK REF_SEL SYNC[0] ANALOG GND RC1 MC88LV915T EXTERNAL LOOP FILTER 100MHz SIGNAL 2X_Q ANALOG V CC 50MHz “Q” CLOCK OUTPUTS CRYSTAL OSCILLATOR 25MHz INPUT HIGH LOW HIGH HIGH PLL_ENFQ_SEL Q0 Q1 Q/2 Q4RST FEEDBACK REF_SEL SYNC[0] ANALOG GND RC1 MC88LV915T EXTERNAL LOOP FILTER 50MHz “Q” CLOCK OUTPUTS 50MHz “Q” CLOCK OUTPUTS Note: If the OE/RST input is active, a pull–up or pull–down re- sistor isn’t necessary at the FEEDBACK pin so it won’t when the fed back output goes into 3–state.

9 MOTOROLA

must be tied to the FEEDBACK input pin to prevent it from floating when the fedback output goes into high impedance. also be used for low frequency board testing. Figure 4. Representation of a Potential Multi–Processing Application Utilizing the MC88LV915T

BR1333 — Rev 6 OUTLINE DIMENSIONS FN SUFFIX PLASTIC PACKAGE CASE 776–02 ISSUE D NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). –N– –M––L– V W D D Y BRK 28 1 VIEW S SL–M S0.010 (0.250) N ST SL–M M0.007 (0.180) N ST 0.004 (0.100) G J C Z R E A SEATING PLANE SL–M M0.007 (0.180) N ST –T– B SL–M S0.010 (0.250) N ST SL–M M0.007 (0.180) N STU SL–M M0.007 (0.180) N ST Z G1X VIEW D–D SL–M M0.007 (0.180) N ST VIEW S H K F SL–M M0.007 (0.180) N ST DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.485 0.495 12.32 12.57 B 0.485 0.495 12.32 12.57 C 0.165 0.180 4.20 4.57 E 0.090 0.110 2.29 2.79 F 0.013 0.019 0.33 0.48 G 0.050 BSC 1.27 BSC H 0.026 0.032 0.66 0.81 R 0.450 0.456 11.43 11.58 U 0.450 0.456 11.43 11.58 V 0.042 0.048 1.07 1.21 W 0.042 0.048 1.07 1.21 X 0.042 0.056 1.07 1.42 Z 2 10 2 10 G1 0.410 0.430 10.42 10.92 /C0095/C0095 /C0095/C0095

BR1333 — Rev 6

11 MOTOROLA

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution;JAPAN : Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, P.O. Box 5405; Denver, Colorado 80217. 303–675–2140 or 1–800–441–24473–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 MC88LV915T/D◊