MC88916DW

MC88916 MOTOROLA | Alldatasheet

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/C0077/C0079/C0084/C0079/C0082/C0079/C0076/C0065 SEMICONDUCTOR TECHNICAL DATA  Motorola, Inc. 1995 1 REV 2 /C0076/C0111/C0119 /C0083/C0107/C0101/C0119 /C0067/C0077/C0079/C0083 /C0080/C0076/C0076 /C0067/C0108/C0111/C0099/C0107 /C0068/C0114/C0105/C0118/C0101/C0114 /C0087/C0105/C0116/C0104 /C0080/C0114/C0111/C0099/C0101/C0115/C0115/C0111/C0114 /C0082/C0101/C0115/C0101/C0116 The MC88916 Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for CISC microprocessor or single processor RISC systems. The RST _IN/RST_OUT (LOCK) pins provide a processor reset function designed specifically for the MC68/EC/LC030/040 microprocessor family. The 88916 comes in two speed grades: 70 and 80MHz. These frequencies correspond to the 2X_Q maximum output frequency. The two grades should be ordered as the MC88916DW70 and MC88916DW80, respectively.

• Provides Performance Required to Drive 68030 Microprocessor Family as well as the 33 and 40MHz 68040 Microprocessors
• Three Outputs (Q0–Q2) With Output–Output Skew <500ps and Six Outputs Total (Q0–Q2, Q3, 2X_Q,) With <1ns Skew Each Being Phase and Frequency Locked to the SYNC Input
• The Phase Variation From Part–to–Part Between SYNC and the ‘Q’ Outputs Is Less Than 600ps (Derived From the TPD Specification, Which Defines the Part–to–Part Skew)
• SYNC Input Frequency Range From 5MHZ to 2X_Q FMax /4
• Additional Outputs Available at 2X and ÷2 the System ‘Q’ Frequency. Also a Q (180° Phase Shift) Output Available.
• All Outputs Have ±36mA Drive (Equal High and Low) CMOS Levels. Can Drive Either CMOS or TTL Inputs. All Inputs Are TTL–Level Compatible
• Test Mode Pin (PLL_EN) Provided for Low Frequency Testing The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple locations on a board. The PLL also allows the MC88916 to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency. Three ‘Q’ outputs (Q0–Q2) are provided with less than 500ps skew between their rising edges. The Q3 output is inverted (180° phase shift) from the ‘Q’ outputs. A 2X_Q output runs at twice the ‘Q’ output frequency. The 2X_Q output does not meet the stringent duty cycle requirement of the 20 and 25Mhz 68040 microprocessor PCLK input. The 88920 has been designed specifically to provide the 68040 PCLK and BCLK inputs for the low frequency 68040 microprocessor. 68040 designers should refer to the 88920 data sheet for more details. For the 33 and 40MHz 68040, the 2X_Q output will meet the duty cycle requirements of the PCLK input. The Q/2 output runs at 1/2 the ‘Q’ frequency. This output is fed back internally, providing a fixed 2X multiplication from the ‘Q’ outputs to the SYNC input. Since the feedback is done internally (no external feedback pin is provided) the input/output frequency relationships are fixed. In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the 88916 in a static ‘test mode’. In this mode there is no frequency limitation on the input clock, which is necessary for a low frequency board test environment. The RST _OUT (LOCK) pin doubles as a phase–lock indicator. When the RST_IN pin is held high, the open drain RST_OUT pin will be pulled actively low until phase–lock is achieved. When phase–lock occurs, the RST_OUT (LOCK) is released and a pull–up resistor will pull the signal high. To give a processor reset signal, the RST_IN pin is toggled low, and the RST _OUT (LOCK) pin will stay low for 1024 cycles of the ‘Q’ output frequency after the RST_IN pin is brought back high. Description of the RST_IN/RST_OUT (LOCK) Functionality The RST_IN and RST_OUT (LOCK) pins provide a 68030/040 processor reset function, with the RST_OUT pin also acting as a lock indicator. If the RST_IN pin is held high during system power–up, the RST_OUT pin will be in the low state until steady state phase/frequency lock to the input reference is achieved. 1024 ‘Q’ output cycles after phase–lock is achieved the RST _OUT (LOCK) pin will go into a high impedance state, allowing it to be pulled high by an external pull–up resistor (see the AC/DC specs for the characteristics of the RST_OUT (LOCK) pin). If the RST_IN pin is held low during power–up, the RST _OUT (LOCK) pin will remain low. /C0077/C0067/C0056/C0056/C0057/C0049/C0054 LOW SKEW CMOS PLL CLOCK DRIVER WITH PROCESSOR RESET DW SUFFIX SOIC PACKAGE CASE 751D–04

BR1333 — REV 5 Pinout: 20–Lead Wide SOIC Package (Top View) GNDQ3 2X_QVCC Q/2MR VCCRST _IN Q2VCC (AN) GNDRC1 RST _OUT (LOCK)GND(AN) PLL_ENSYNC Q1GND VCCQ0 Description of the RST_IN/RST_OUT (LOCK) Functionality (continued) After the system start–up is complete and the 88916 is phase–locked to the SYNC input signal (RST_OUT high), the processor reset functionality can be utilized. When the RST _IN pin is toggled low (min. pulse width=10nS), RST _OUT (LOCK) will go to the low state and remain there for 1024 cycles of the ‘Q’ output frequency (512 SYNC cycles). During the time in which the RST _OUT (LOCK) is actively pulled low, all the 88916 clock outputs will continue operating correctly and in a locked condition to the SYNC input (clock signals to the 68030/040 family of processors must continue while the processor is in reset). A propagation delay after the 1024th cycle RST _OUT (LOCK) goes back to the high impedance state to be pulled high by the resistor. Power Supply Ramp Rate Restriction for Correct 68030 Processor Reset Operation During System Start–up Because the RST_OUT (LOCK) pin is an indicator of phase–lock to the reference source, some constraints must be placed on the power supply ramp rate to make sure the RST _OUT (LOCK) signal holds the processor in reset during system start–up (power–up). With the recommended loop filter values (see Figure 7) the lock time is approximately 10ms. The phase–lock loop will begin attempting to lock to a reference source (if it is present) when VCC reaches 2V. If the VCC ramp rate is significantly slower than 10ms, then the PLL could lock to the reference source, causing RST _OUT (LOCK) to go high before the 88916 and 68030 processor is fully powered up, violating the processor reset specification. Therefore, if it is necessary for the RST _IN pin to be held high during power–up, the VCC ramp rate must be less than 10mS for proper 68030/040 reset operation. This ramp rate restriction can be ignored if the RST _IN pin can be held low during system start–up (which holds RST _OUT low). The RST_OUT (LOCK) pin will then be pulled back high 1024 cycles after the RST_IN pin goes high. CAPACITANCE AND POWER SPECIFICATIONS Symbol Parameter Value Typ Unit Test Conditions C IN Input Capacitance 4.5 pF VCC = 5.0V C PD Power Dissipation Capacitance 40 pF VCC = 5.0V PD 1 Power Dissipation at 33MHz With 50Ω Thevenin Termination 15mW/Output 90mW/Device mW VCC = 5.0V T = 25°C PD 2 Power Dissipation at 33MHz With 50Ω Parallel Termination to GND 37.5mW/Output 225mW/Device mW VCC = 5.0V T = 25°C

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MAXIMUM RATINGS* Symbol Parameter Limits Unit VCC , AVCC DC Supply Voltage Referenced to GND –0.5 to 7.0 V Vin DC Input Voltage (Referenced to GND) –0.5 to VCC +0.5 V Vout DC Output Voltage (Referenced to GND) –0.5 to VCC +0.5 V Iin DC Input Current, Per Pin ±20 mA Iout DC Output Sink/Source Current, Per Pin ±50 mA ICC DC V CC or GND Current Per Output Pin ±50 mA Tstg Storage Temperature –65 to +150 °C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Limits Unit VCC Supply Voltage 5.0 ±10% V Vin DC Input Voltage 0 to VCC V Vout DC Output Voltage 0 to VCC V TA Ambient Operating Temperature –40 to 85 °C ESD Static Discharge Voltage > 1500 V DC CHARACTERISTICS (TA = –40°C to +85°C; VCC = 5.0V ± 5%) Symbol Parameter VCC Guaranteed Limits Unit Condition VIH Minimum High Level Input Voltage 4.75 5.25 2.0 2.0 V VOUT = 0.1V or VCC – 0.1V VIL Minimum Low Level Input Voltage 4.75 5.25 0.8 0.8 V VOUT = 0.1V or VCC – 0.1V VOH Minimum High Level Output Voltage 4.75 5.25 4.01 4.51 V VIN = VIH or VIL IOH –36mA –36mA VOL Minimum Low Level Output Voltage 4.75 5.25 0.44 0.44 V VIN = VIH or VIL IOH +36mA 1 +36mA IIN Maximum Input Leakage Current 5.25 ±1.0 µA VI = VCC , GND ICCT Maximum ICC /Input 5.25 2.02 mA VI = VCC – 2.1V IOLD Minimum Dynamic3 Output Current 5.25 88 mA VOLD = 1.0V Max IOHD 5.25 –88 mA VOHD = 3.85 Min ICC Maximum Quiescent Supply Current 5.25 750 µA VI = VCC , GND 1. IOL is +12mA for the RST_OUT output. 2. The PLL_EN input pin is not guaranteed to meet this specification. 3. Maximum test duration 2.0ms, one output loaded at a time.

Figure 1. MC88916 Logic Block Diagram

1. Maximum Operating Frequency is guaranteed with the 88916 in a phase–locked condition, and all outputs loaded at 50Ω terminated to VCC /2.

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AC CHARACTERISTICS (TA = –40°C to +85°C; VCC = 5.0V ± 5%) Symbol Parameter Mimimum Maximum Unit Condition tRISE/FALL1 All Outputs Rise/Fall Time, All Outputs into a 50Ω Load 0.3 1.6 ns tRISE – 0.8V to 2.0V tFALL – 2.0V to 0.8V tRISE/FALL1 2X_Q Output Rise/Fall Time into a 20pF Load, With Termination Specified in AppNote 3 0.5 1.6 ns tRISE – 0.8V to 2.0V tFALL – 2.0V to 0.8V tpulse width(a)1 (Q0, Q1, Q2, Q3) Output Pulse Width Q0, Q1, Q2, Q3 at VCC /2 0.5tcycle – 0.5 0.5tcycle + 0.5 ns 50Ω Load Terminated to VCC /2 (See App Note 3) tpulse width(b)1 (2X_Q Output) Output Pulse Width 40–49MHz 2X_Q at VCC /2 50–65MHz 66–80MHz 0.5tcycle – 1.55 0.5tcycle – 1.05 0.5tcycle – 0.5 0.5tcycle + 1.55 0.5tcycle + 1.05 0.5tcycle + 0.5 ns 50Ω Load Terminated to VCC /2 (See App Note 3) tPD 1,4 SYNC – Q/2 SYNC Input to Q/2 Output Delay (Measured at SYNC and Q/2 Pins) –0.75 –0.15 ns With 1MΩ From RC1 to An VCC (See Application Note 2) +1.257 +3.257 ns With 1MΩ From RC1 to An GND (See Application Note 2) tSKEWr 1,2 (Rising) Output–to–Output Skew Between Outputs Q0–Q2, Q/2 (Rising Edge Only) — 500 ps Into a 50Ω Load Terminated to VCC /2 (See Timing Diagram in Figure 6) tSKEWf 1,2 (Falling) Output–to–Output Skew Between Outputs Q0–Q2 (Falling Edge Only) — 1.0 ns Into a 50Ω Load Terminated to VCC /2 (See Timing Diagram in Figure 6) tSKEWall1,2 Output–to–Output Skew 2X_Q, Q/2, Q0–Q2 Rising Q3 Falling — 1.0 ns Into a 50Ω Load Terminated to VCC /2 (See Timing Diagram in Figure 6) tLOCK 3 Phase–Lock Acquisition Time, All Outputs to SYNC Input 1 10 ms tPHL MR – Q Propagation Delay, MR to Any Output (High–Low) 1.5 13.5 ns Into a 50Ω Load Terminated to VCC /2 (See Timing Diagram in Figure 6) tREC , MR to SYNC 6 Reset Recovery Time rising MR edge to falling SYNC edge 9 — ns tW , MR LOW 6 Minimum Pulse Width, MR input Low 5 — ns tW , RST_IN LOW Minimum Pulse Width, RST_IN Low 10 — ns When in Phase–Lock tPZL Output Enable Time RST _IN Low to RST_OUT Low 1.5 16.5 ns See Application Note 5 tPLZ Output Enable Time RST _IN High to RST_OUT High Z 1016 ‘Q’ Cycles (508 Q/2 Cycles) 1024 ‘Q’ Cycles (512 Q/2 Cycles) ns See Application Note 5 1. These specifications are not tested, they are guaranteed by statistical characterization. See Application Note 1 for a discussion of this methodology. 2. Under equally loaded conditions and at a fixed temperature and voltage. 3. With VCC fully powered–on: tCLOCK Max is with C1 = 0.1µF; tLOCK Min is with C1 = 0.01µF. 4. See Application Note 4 for the distribution in time of each output referenced to SYNC. 5. Limits do not meet requirements of the 68040 microprocessor. Refer to the 88920 for a low frequency 68040 clock driver. 6. Specification is valid only when the PLL_EN pin is low. 7. This is a typical specification only, worst case guarantees are not provided.

1. Several specifications can only be measured when the
2. A 1MΩ resistor tied to either Analog VCC or Analog GND,

this offset varies with process, temperature, and voltage.

1. The pulse width spec for the Q and 2Q_X outputs is

termination scheme pictured in Figure 3 must be used. input of the 68040 microprocessor with the 88916 outputs.

1. The tPD spec (SYNC to Q/2) guarantees how close the

spec is equivalent to a part–to–part specification. TABLE 1. Distribution of Each Output versus SYNC Figure 2. Depiction of the Fixed SYNC to Q0 Offset (tPD ) Which Is Present

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Figure 3. MC68040 PCLK Input Termination Scheme Figure 5. Logical Representation of the MC88916 With Figure 4. RST_OUT Test Circuit Figure 6. Output/Input Switching Waveforms and Timing Relationships

1. The MC88916 aligns rising edges of the outputs and the SYNC input, therefore the SYNC input does not require a 50%
2. All skew specs are measured between the VCC /2 crossing point of the appropriate output edges. All skews are specified as

‘windows’, not as a ± deviation around a center point.

specification limits, the tPD spec window will be reduced.

1. The RST_OUT pin is an open drain N–Channel output.

is used as a pull–up as shown in Figure 4.

1. Figure 7 shows a loop filter and analog isolation scheme

undesirable voltage transients at the RC1 pin. more than a 100ps phase deviation. high frequency, high speed digital system.

1. In addition to the bypass capacitors used in the analog

close to the 88916 package as possible. Figure 7. Recommended Loop Filter and Analog Isolation Scheme for the MC88916

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CASE 751D–04 ISSUE E MIN MIN MAX MAX MILLIMETERS INCHES DIM A B C D F G J K M P R 0.510 0.299 0.104 0.019 0.035 0.012 0.009 0.415 0.029 0.499 0.292 0.093 0.014 0.020 0.010 0.004 0.395 0.010 12.95 7.60 2.65 0.49 0.90 0.32 0.25 10.55 0.75 12.65 7.40 2.35 0.35 0.50 0.25 0.10 10.05 0.25 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. 1.27 BSC 0.050 BSC P 10 PL 11 0 1120 D 20 PL K C SEATING PLANE R X 45° M 0.010 (0.25) BM M 0.010 (0.25) T A BM S S G 18 PL F J How to reach us: USA/EUROPE : Motorola Literature Distribution; JAPAN : Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 INTERNET : http://Design–NET.com 51 Ting Kok R oad, Tai Po, N.T., Hong Kong. 852–26629298 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MC88916/D /C0042/C0077/C0067/C0056/C0056/C0057/C0049/C0054/C0047/C0068/C0042 ◊ CODELINE