MC8640DVU1250H

MPC8640DEC FREESCALE | Alldatasheet

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© Freescale Semiconductor, Inc., 2008. All rights reserved. Freescale Semiconductor Technical Data 1O v e r v i e w The MPC8640 processor family integrates either one or two Power Architecture™ e600 processor cores with system logic required for networking, storage, wireless infrastructure, and general-purpose embedded applications. The MPC8640 integrates one e600 core while the MPC8640D integrates two cores. This section provides a high-level overview of the MPC8640 and MPC8640D features. When referring to the MPC8640 throughout the document, the functionality described applies to both the MPC8640 and the MPC8640D. Any differences specific to the MPC8640D are noted. Figure 1 shows the major functional units within the MPC8640 and MPC8640D. The major difference between the MPC8640 and MPC8640D is that there are two cores on the MPC8640D.

Contents

1. Ethernet: Enhanced Three-Speed Ethernet (eTSEC), 9. Ethernet Management Interface Electrical 12. I MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications Document Number: MPC8640DEC Rev. 1, 11/2008

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Figure 1. MPC8640 and MPC8640D

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 3 Overview

1.1 Key Features

The following lists an overview of the MPC8640 key feature set:  Major features of the e600 core are as follows: — High-performance, 32-bit superscalar micr oprocessor that implements the PowerPC ISA — Eleven independent execution uni ts and three register files – Branch processing unit (BPU) – Four integer units (IUs) that share 32 GPRs for integer operands – 64-bit floating-point unit (FPU) – Four vector units and a 32-entry vector register file (VRs) – Three-stage load/store unit (LSU) — Three issue queues, FIQ, VIQ, and GIQ, can accept as many as one, two, and three instructions, respectively, in a cycle. — Rename buffers — Dispatch unit — Completion unit — Two separate 32-Kbyte instructi on and data level 1 (L1) caches — Integrated 1-Mbyte, eight-way set-associative uni fied instruction and data level 2 (L2) cache with ECC — 36-bit real addressing — Separate memory management units (MMUs) for instructions and data — Multiprocessing support features — Power and thermal management — Performance monitor — In-system testability and debugging features — Reliability and serviceability  MPX coherency module (MCM) — Ten local address windows plus two default windows — Optional low memory offset mode for core 1 to allow for address disambiguation  Address translation and mapping units (A TMUs) — Eight local access windows define mapping within local 36-bit address space — Inbound and outbound A TMUs map to larger external address spaces — Three inbound windows plus a configuration window on PCI Express — Four inbound windows plus a default window on serial RapidIO — Four outbound windows plus default translation for PCI Express — Eight outbound windows plus default translation for serial RapidIO with segmentation and sub-segmentation support

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

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 DDR memory controllers — Dual 64-bit memory controllers (72-bit with ECC) — Support of up to a 266 MHz clock rate and a 533 MHz DDR2 SDRAM — Support for DDR, DDR2 SDRAM — Up to 16 Gbytes per memory controller — Cache line and page interleaving between memory controllers.  Serial RapidIO interface unit — Supports RapidIO Interconnect Specification, Revision 1.2 — Both 1x and 4x LP-Serial link interfaces lane — RapidIO–compliant message unit — RapidIO atomic transactions to the memory controller  PCI Express interface — PCI Express 1.0a compatible — Supports x1, x2, x4, and x8 link widths — 2.5 Gbaud, 2.0 Gbps lane  Four enhanced three-speed Ethernet controllers (eTSECs) — Three-speed support (10/100/1000 Mbps) — Support of the following physical interfaces: MII, RMII, GMII, RGMII, TBI, and RTBI — Support a full-duplex FIFO mode for high-efficiency ASIC connectivity — TCP/IP off-load — Header parsing — Quality of service support — VLAN insertion and deletion — MAC address recognition — Buffer descriptors are backward compatible with PowerQUICC II and PowerQUICC III programming models — RMON statistics support — MII management interface for control and status  Programmable interrupt controller (PIC) — Programming model is compliant with the OpenPIC architecture — Supports 16 programmable interrupt a nd processor task priority levels — Supports 12 discrete external interrupts and 48 internal interrupts — Eight global high resolution timers/counters that can generate interrupts — Allows processors to interrupt each other with 32b messages

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 5

Electrical Characteristics

— Support for PCI-Express message-shared interrupts (MSIs)  Local bus controller (LBC) — Multiplexed 32-bit address and data operating at up to 125 MHz — Eight chip selects support eight external slaves  Integrated DMA controller — Four-channel controller — All channels accessible by both the local and the remote masters — Supports transfers to or from any local memory or I/O port — Ability to start and flow control each DMA channel from external 3-pin interface  Device performance monitor — Supports eight 32-bit counters that count the occurrence of selected events — Ability to count up to 512 counter-specific events — Supports 64 reference events that can be counted on any of the 8 counters — Supports duration and quantity threshold counting — Burstiness feature that permits counting of burst events with a programmable time between bursts — Triggering and chaining capability — Ability to generate an interrupt on overflow  Dual I 2C controllers — Two-wire interface — Multiple master support — Master or slave I 2C mode support — On-chip digital filtering rejects spikes on the bus  Boot sequencer — Optionally loads configuration data from serial ROM at reset via the I 2C interface — Can be used to initialize configuration registers and/or memory — Supports extended I 2C addressing mode — Data integrity checked with preamble signature and CRC  DUART — Two 4-wire interfaces (SIN, SOUT, RTS , CTS) — Programming model compatible with the original 16450 UART and the PC16550D  IEEE 1149.1-compliant, JTAG boundary scan  Available as 1023 pin Hi-CTE flip chip ceramic ball grid array (FC-CBGA)

2 Electrical Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8640. The MPC8640 is currently targeted to these specifications.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

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2.1 Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

2.1.1 Absolute Maximum Ratings

Table 1 provides the absolute maximum ratings. Table 1. Absolute Maximum Ratings 1

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 7

2.1.2 Recommended Operating Conditions

Table 2 provides the recommended operating conditions for the MPC8640. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. For details on order information and specific operating conditions for parts, see Section 21, “Ordering Information.” Storage temperature range T STG -55 to 150 °C Notes: 1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Core 1 characteristics apply only to MPC8640D. If two separate power supplies are used for VDD_Core0 and VDD_Core1, they must be kept within 100 mV of each other during normal run time. 4. The 3.63V maximum is only supported when the port is configured in GMII, MII, RMII, or TBI modes; otherwise the 2.75V maximum applies. See Section 8.2, “FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications” for details on the recommended operating conditions per protocol. 5. During run time (M,L,T ,O)VIN and Dn_MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2. Table 2. Recommended Operating Conditions

2.5 V ± 125 mV V 7

1.8 V ± 90 mV 7

2.5 V ± 125 mV V 8

Table 1. Absolute Maximum Ratings 1 (continued)

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

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eTSEC 3 and 4 I/O supply voltage TV DD 3.3 V ± 165 mV V 8 Local Bus, DUART, DMA, Multiprocessor Interrupts, System Control & Clocking, Debug, T est, Power management, I2C, JT AG and Miscellaneous I/O voltage OVDD 3.3 V ± 165 mV V 5 Input voltage DDR and DDR2 SDRAM signals D n_MVIN GND to Dn_GVDD V3 , 6 DDR and DDR2 SDRAM reference D n_MVREF Dn_GVDD/2 ± 1% V Three-speed Ethernet signals LV IN TVIN GND to LVDD GND to TVDD V4 , 6 DUART , Local Bus, DMA, Multiprocessor Interrupts, System Control & Clocking, Debug, T est, Power management, I 2C, JTAG and Miscellaneous I/O voltage OVIN GND to OVDD V5 , 6 Junction temperature range T J 0 to 105 °C -40 to 105 12 Notes: 1. Core 1 characteristics apply only to MPC8640D 2. If two separate power supplies are used for V DD_Core0 and VDD_Core1, they must be at the same nominal voltage and the individual power supplies must be tracked and kept within 100 mV of each other during normal run time. 3. Caution: Dn_MVIN must meet the overshoot/undershoot requirements for D n_GVDD as shown in Figure 2. 4. Caution: L/TVIN must meet the overshoot/undershoot requirements for L/TVDD as shown in Figure 2 during regular run time. 5. Caution: OVIN must meet the overshoot/undershoot requirements for OV DD as shown in Figure 2 during regular run time. 6. Timing limitations for M,L,T,O)VIN and Dn_MVREF during regular run time is provided in Figure 2 7. The 2.5 V ± 125 mV range is for DDR and 1.8 V ± 90 mV range is for DDR2. 8. See Section 8.2, “FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications ” for details on the recommended operating conditions per protocol. 9. The PCI Express interface of the device is expected to receive signals from 0.175 to 1.2 V . For more information refer to Section 14.4.3, “Differential Receiver (RX) Input Specifications." 10. Applies to Part Number MC8640wxx1067NC only. V DD_Coren = 0.95 V and VDD_PLA T = 1.05 V devices. Refer to Ta ble 7 3 Part Numbering Nomenclature to determine if the device has been marked for V DD_Coren = 0.95 V . 11. This voltage is the input to the filter discussed in Section 20.2, “Power Supply Design and Sequencing” and not necessarily the voltage at the AVDD_Coren pin, which may be reduced from V DD_Coren by the filter. 12. Applies to part number MC8640DTxxyyyyaC. Refer to Ta bl e 7 3 Part Numbering Nomenclature to determine if the device has been marked for extended operating temperature range. Table 2. Recommended Operating Conditions (continued)

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 9 Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8640. Figure 2. Overshoot/Undershoot Voltage for D n_M/O/L/TVIN to Dn_GVDD/2) as is appropriate for the (SSTL-18 and SSTL-25) electrical signaling standards.

2.1.3 Output Driver Characteristics

1. tCLK references clocks for various functional blocks as follows:

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

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Table 3. Output Drive Capability

1. See the DDR Control Driver registers in the MPC8641D reference manual for more information.
2. Only the following local bus signals have programmable drive strengths: LALE, LAD[0:31], LDP[0:3], LA[27:31], LCKE,

about local bus signals and their drive strength programmability.

1. See Section 17, “Signal Listings” for details on resistor requirements for the calibration of SD

SDn_IMP_CAL_RX transmit and receive signals.

1. Stub Series T erminated Logic (SSTL-25) type pins.
2. Stub Series T erminated Logic (SSTL-18) type pins.
3. Low Voltage Transistor-Transistor Logic (L VTTL) type pins.
4. Low Voltage Differential Signaling (L VDS) type pins.
5. The drive strength of the DDR interface in half strength mode is at T

j = 105C and at Dn_GVDD (min).

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 11

2.2 Power Up/Down Sequence

The MPC8640 requires its power rails to be applied in a specific sequence in order to ensure proper device operation. NOTE The recommended maximum ramp up time for power supplies is 20 milliseconds. The chronological order of power up is: 1. All power rails other than DDR I/O (Dn_GVDD, and Dn_MVREF). NOTE There is no required order sequence between the individual rails for this item (# 1). However, VDD_PLAT, A VDD_PLAT rails must reach 90% of their recommended value before the rail for Dn_GVDD, and Dn_MVREF (in next step) reaches 10% of their recommended value. A VDD type supplies must be delayed with respect to their source supplies by the RC time constant of the PLL filter circuit described in Section 20.2.1, “PLL Power Supply Filtering”. 2. Dn_GVDD, Dn_MVREF NOTE It is possible to leave the related power supply (Dn_GVDD, Dn_MVREF) turned off at reset for a DDR port that will not be used. Note that these power supplies can only be powered up again at reset for functionality to occur on the DDR port. 3. SYSCLK The recommended order of power down is as follows: 1. Dn_GV DD, Dn_MVREF 2. All power rails other than DDR I/O (Dn_GVDD, Dn_MVREF). NOTE SYSCLK may be powered down simultaneous to either of item # 1 or # 2 in the power down sequence. Beyond this, the power supplies may power down simultaneously if the preservation of DDRn memory is not a concern. See Figure 3 for more details on the Power and Reset Sequencing details

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

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Figure 3 illustrates the Power Up sequence as described above. Figure 3. MPC8640 Power-Up and Reset Sequence

1. Dotted waveforms correspond to optional supply values for a specified power supply. See Ta ble 2.
2. The recommended maximum ramp up time for power supplies is 20 milliseconds.
3. Refer to Section 5, “RESET Initialization” for additional information on PLL relock and reset signal

assertion timing requirements.

1. Refer to Table 10 for additional information on reset configuration pin setup timing requirements. In

and JT AG connection details including TRST.

1. e600 PLL relock time is 100 microseconds maximum plus 255 MPX_clk cycles.
2. Stable PLL configuration signals are required as stable SYSCLK is applied. All other POR configuration

information on setup and hold time of reset configuration signals.

1. VDD_PLA T, AVDD_PLA T must strictly reach 90% of their recommended voltage before the rail for

Dn_GVDD, and Dn_MVREF reaches 10% of their recommended voltage.

1. SYSCLK must be driven only AFTER the power for the various power supplies is stable.
2. In device sleep mode, the reset configuration signals for DRAM types (TSEC2_TXD[4],TSEC2_TX_ER)

3 Power Characteristics

The power dissipation for the dual core MPC8640D device is shown in Table 4. Table 4. MPC8640D Power Dissipation (Dual Core)

1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and

configurations. The values do not include power dissipation for I/O supplies.

1. Typical power is an average value measured at the nominal recommended core voltage (V DD_Coren) and 65°C

MIPs/MHz with one core at 100% efficiency and the second core at 65% efficiency.

1. Thermal power is the average power measured at nominal core voltage (V DD_Coren) and maximum operating

MIPs/MHz on both cores and a typical workload on platform interfaces.

1. Maximum power is the maximum power measured at nominal core voltage (V DD_Coren) and maximum operating

sequence of instructions which keep all the execution units maximally busy on both cores.

1. These power numbers are for Part Number MC8640Dwxx1067NC and MC8640wxx1067NC only. VDD_Coren = 0.95

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The power dissipation for the MPC8640 single core device is shown in Table 5.

4 Input Clocks

Table 6 provides the system clock (SYSCLK) DC specifications for the MPC8640. Table 6. SYSCLK DC Electrical Characteristics ( OVDD = 3.3 V ± 165 mV.) Table 5. MPC8640 Power Dissipation (Single Core)

1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and

configurations. The values do not include power dissipation for I/O supplies.

1. T ypical power is an average value measured at the nominal recommended core voltage (VDD_Coren) and 65°C junction

temperature (see Ta ble 2)while running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz.

1. Thermal power is the average power measured at nominal core voltage (V DD_Coren) and maximum operating junction

workload on platform interfaces.

1. Maximum power is the maximum power measured at nominal core voltage (V DD_Coren) and maximum operating junction

instructions which keep all the execution units maximally busy.

1. These power numbers are for Part Number MC8640Dwxx1067NC and MC8640wxx1067NC only. VDD_Coren = 0.95 V and
2. Note that the symbol V IN, in this case, represents the OVIN symbol referenced in Ta ble 1 and Ta ble 2.

4.1 System Clock Timing

Table 7 provides the system clock (SYSCLK) AC timing specifications for the MPC8640.

4.1.1 SYSCLK and Spread Spectrum Sources

the clock generator’s cycle-to-cycle output jitter should meet the MPC8640 input cycle-to-cycle jitter requirement. sources if the recommendations listed in Table 8 are observed. Table 7. SYSCLK AC Timing Specifications At recommended operating conditions (see Table 2) with OVDD = 3.3 V ± 165 mV.

1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the

Section 18.3, “e600 to MPX clock PLL Ratio”, for ratio settings.

1. Rise and fall times for SYSCLK are measured at 0.4 V and 2.7 V.
2. Timing is guaranteed by design and characterization.
3. This represents the short term jitter only and is guaranteed by design.
4. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to

what is supported based on design.

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use a source without significant unintended modulation.

4.2 Real Time Clock Timing

timing specifications for the MPC8640. Table 8. Spread Spectrum Clock Source Recommendations At recommended operating conditions. See Table 2.

1. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO

frequencies, must meet the minimum and maximum specifications given in Table 7. Table 9. ECn_GTX_CLK125 AC Timing Specifications

(ports 3 and 4) is no more than 100 ps.

4.4 Platform Frequency Requirements for PCI-Express and Serial

Express and Serial RapidIO interfaces as described below.

527 MHz x (PCI-Express link width)

cfg_plat_freq = 0 or greater than or equal to 527 MHz with cfg_plat_freq = 1.

4.5 Other Input Clocks

see the specific section of this document.

5 RESET Initialization

the MPC8640. Table 10 provides the RESET initialization AC timing specifications.

1. Timing is guaranteed by design and characterization.

n_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. for 10Base-T and 100Base-T reference clock.

1. ±100 ppm tolerance on EC n_GTX_CLK125 frequency

Table 9. ECn_GTX_CLK125 AC Timing Specifications (continued)

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Table 11 provides the PLL lock times.

6 DDR and DDR2 SDRAM

6.1 DDR SDRAM DC Electrical Characteristics

MPC8640 when Dn_GVDD(typ) = 1.8 V. Table 10. RESET Initialization Timing Specifications

1. SYSCLK is the primary clock input for the MPC8640.

2 This is related to HRESET

Table 11. PLL Lock Times

1. The PLL lock time for e600 PLLs require an additional 255 MPX_CLK cycles.

Table 13 provides the DDR2 capacitance when Dn_GVDD(typ) = 1.8 V . Table 12. DDR2 SDRAM DC Electrical Characteristics for D n_GVDD(typ) = 1.8 V

1. Dn_GVDD is expected to be within 50 mV of the DRAM D n_GVDD at all times.
2. Dn_MVREF is expected to be equal to 0.5 × Dn_GVDD, and to track Dn_GVDD DC variations as measured at the

receiver. Peak-to-peak noise on Dn_MVREF may not exceed ±2% of the DC value.

1. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to Dn_MVREF. This rail should track variations in the DC level of D n_MVREF.

1. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ Dn_GVDD.

Table 13. DDR2 SDRAM Capacitance for D n_GVDD(typ)=1.8 V

1. This parameter is sampled. D n_GVDD = 1.8 V ± 0.090 V , f = 1 MHz, TA = 25°C, VOUT = Dn_GVDD/2, VOUT

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Table 15 provides the DDR capacitance when Dn_GVDD (typ)=2.5 V . Table 16 provides the current draw characteristics for MVREF. Table 14. DDR SDRAM DC Electrical Characteristics for D n_GVDD (typ) = 2.5 V

1. Dn_GVDD is expected to be within 50 mV of the DRAM D n_GVDD at all times.
2. MVREF is expected to be equal to 0.5 × Dn_GVDD, and to track Dn_GVDD DC variations as measured at the receiver.

Peak-to-peak noise on Dn_MVREF may not exceed ±2% of the DC value.

1. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to Dn_MVREF. This rail should track variations in the DC level of D n_MVREF.

1. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ Dn_GVDD.

Table 15. DDR SDRAM Capacitance for D n_GVDD (typ) = 2.5 V

1. This parameter is sampled. D n_GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT = Dn_GVDD/2,

VOUT (peak-to-peak) = 0.2 V. Table 16. Current Draw Characteristics for MV REF

1. The voltage regulator for MVREF must be able to supply up to 500 μA current.

6.2 DDR SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR SDRAM interface.

6.2.1 DDR SDRAM Input AC Timing Specifications

Table 17 provides the input AC timing specifications for the DDR2 SDRAM when Dn_GVDD(typ)=1.8 V . Table 18 provides the input AC timing specifications for the DDR SDRAM when Dn_GVDD(typ)=2.5 V . Table 19 provides the input AC timing specifications for the DDR SDRAM interface. Figure 4 shows the DDR SDRAM input timing for the MDQS to MDQ skew measurement (tDISKEW). Table 17. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface Table 18. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface At recommended operating conditions. Table 19. DDR SDRAM Input AC Timing Specifications At recommended operating conditions.

533 MHz –300 300 3

400 MHz –365 365

1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding

bit that will be captured with MDQS[n]. This should be subtracted from the total timing budget.

1. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called

the clock period and abs(t CISKEW) is the absolute value of t CISKEW.

1. Maximum DDR1 frequency is 400 MHz.

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Figure 4. DDR Input Timing Diagram for tDISKEW

6.2.2 DDR SDRAM Output AC Timing Specifications

Table 20. DDR SDRAM Output AC Timing Specifications At recommended operating conditions.

533 MHz

400 MHz

533 MHz 590 — 7

400 MHz 700 —

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1. The symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)

invalid (X) or data output hold time.

1. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V .
2. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK , MCS, and MDQ/MECC/MDM/MDQS.
3. Note that tDDKHMH follows the symbol conventions described in note 1. For example, t DDKHMH describes the DDR
4. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ),
5. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t DDKHMP follows

the symbol conventions described in note 1.

1. Maximum DDR1 frequency is 400 MHz
2. Per the JEDEC spec the DDR2 duty cycle at 400 and 533 MHz is the low and high cycle time values.

Table 20. DDR SDRAM Output AC Timing Specifications (continued) At recommended operating conditions.

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Figure 7 provides the AC test load for the DDR bus. Figure 7. DDR AC Test Load This section describes the DC and AC electrical specifications for the DUART interface of the MPC8640.

7.1 DUART DC Electrical Characteristics

Table 21 provides the DC electrical characteristics for the DUART interface.

7.2 DUART AC Electrical Specifications

Table 22 provides the AC timing parameters for the DUART interface. Table 21. DUART DC Electrical Characteristics

1. Note that the symbol V IN, in this case, represents the OVIN symbol referenced in Ta bl e 1

8 Ethernet: Enhanced Three-Speed Ethernet (eTSEC),

8.1 Enhanced Three-Speed Ethernet Controller (eTSEC)

interfaces are defined for 2.5 V , while the GMII and TBI interfaces can be operated at 3.3 or 2.5 V . OH into a GMII receiver powered from a 2.5-V supply). Table 22. DUART AC Timing Specifications

1. MPX clock refers to the platform clock.
2. Actual attainable baud rate will be limited by the latency of interrupt processing.
3. The middle of a start bit is detected as the 8

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Table 23. GMII, MII, RMII, TBI and FIFO DC Electrical Characteristics 1 LVDD supports eTSECs 1 and 2. 2 TVDD supports eTSECs 3 and 4. 3 The symbol VIN, in this case, represents the LVIN and TVIN symbols referenced in Ta ble 1 and Ta ble 2. Table 24. GMII, RGMII, RTBI, TBI and FIFO DC Electrical Characteristics 1 LVDD supports eTSECs 1 and 2. 2 TVDD supports eTSECs 3 and 4.

8.2 FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing

8.2.1 FIFO AC Specifications

source clock in GMII fashion. (ports 3 and 4) is no more than 100 ps. A summary of the FIFO AC specifications appears in Table 25 and Table 26. 3 Note that the symbol VIN, in this case, represents the LVIN and TVIN symbols referenced in Ta ble 1 and Ta ble 2. Table 25. FIFO Mode Transmit AC Timing Specification At recommended operating conditions with L/TV DD of 3.3 V ± 5% and 2.5 V ± 5%.

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Timing diagrams for FIFO appear in Figure 8 and Figure 9. Figure 8. FIFO Transmit AC Timing Diagram Table 26. FIFO Mode Receive AC Timing Specification At recommended operating conditions with L/TV DD of 3.3 V ± 5% and 2.5 V ± 5%. Table 25. FIFO Mode Transmit AC Timing Specification (continued) At recommended operating conditions with L/TV DD of 3.3 V ± 5% and 2.5 V ± 5%.

Figure 9. FIFO Receive AC Timing Diagram

8.2.2 GMII AC Timing Specifications

This section describes the GMII transmit and receive AC timing specifications.

8.2.2.1 GMII Transmit AC Timing Specifications

Table 27 provides the GMII transmit AC timing specifications. Table 27. GMII Transmit AC Timing Specifications At recommended operating conditions with L/TV DD of 3.3 V ± 5% and 2.5 V ± 5%.

1. The symbols used for timing specifications herein follow the pattern t (first two letters of functional block)(signal)(state) (reference)(state)

times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

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Figure 10 shows the GMII transmit AC timing diagram. Figure 10. GMII Transmit AC Timing Diagram

8.2.2.2 GMII Receive AC Timing Specifications

Table 28 provides the GMII receive AC timing specifications. Figure 11 provides the AC test load for eTSEC. Figure 11. eTSEC AC Test Load Table 28. GMII Receive AC Timing Specifications At recommended operating conditions with L/TV DD of 3.3 V ± 5% and 2.5 V ± 5%.

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

the time data input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L) state or hold time. the latter convention is used with the appropriate letter: R (rise) or F (fall).

1. ±100 ppm tolerance on RX_CLK frequency

Figure 12 shows the GMII receive AC timing diagram. Figure 12. GMII Receive AC Timing Diagram

8.2.3 MII AC Timing Specifications

This section describes the MII transmit and receive AC timing specifications.

8.2.3.1 MII Transmit AC Timing Specifications

Table 29 provides the MII transmit AC timing specifications. Figure 13 shows the MII transmit AC timing diagram. Table 29. MII Transmit AC Timing Specifications At recommended operating conditions with L/TV DD of 3.3 V ± 5%.

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

convention is used with the appropriate letter: R (rise) or F (fall).

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Figure 13. MII Transmit AC Timing Diagram

8.2.3.2 MII Receive AC Timing Specifications

Table 30 provides the MII receive AC timing specifications. Figure 14 provides the AC test load for eTSEC. Figure 14. eTSEC AC Test Load Table 30. MII Receive AC Timing Specifications At recommended operating conditions with L/TV DD of 3.3 V ± 5%.

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. used with the appropriate letter: R (rise) or F (fall).

1. ±100 ppm tolerance on RX_CLK frequency

Figure 15 shows the MII receive AC timing diagram. Figure 15. MII Receive AC Timing Diagram

8.2.4 TBI AC Timing Specifications

This section describes the TBI transmit and receive AC timing specifications.

8.2.4.1 TBI Transmit AC Timing Specifications

Table 31 provides the TBI transmit AC timing specifications. Table 31. TBI Transmit AC Timing Specifications At recommended operating conditions with L/TV DD of 3.3 V ± 5% and 2.5 V ± 5%.

1. The symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state

(TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

36 Freescale Semiconductor

Figure 16 shows the TBI transmit AC timing diagram. Figure 16. TBI Transmit AC Timing Diagram

8.2.4.2 TBI Receive AC Timing Specifications

Table 32 provides the TBI receive AC timing specifications. Table 32. TBI Receive AC Timing Specifications At recommended operating conditions with L/TV DD of 3.3 V ± 5% and 2.5 V ± 5%.

1. The symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state)

receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX).

1. ±100 ppm tolerance on PMA_RX_CLK[0:1] frequency

Figure 17 shows the TBI receive AC timing diagram. Figure 17. TBI Receive AC Timing Diagram

8.2.5 TBI Single-Clock Mode AC Specifications

TSEC_GTX_CLK125 pin in all TBI modes. A summary of the single-clock TBI mode AC specifications for receive appears in Table 33. Table 33. TBI single-clock Mode Receive AC Timing Specification At recommended operating conditions with L/TV DD of 3.3 V ± 5% and 2.5 V ± 5%.

38 Freescale Semiconductor

A timing diagram for TBI receive appears in Figure 18. Figure 18. TBI Single-Clock Mode Receive AC Timing Diagram

8.2.6 RGMII and RTBI AC Timing Specifications

Table 34 presents the RGMII and RTBI AC timing specifications. Table 34. RGMII and RTBI AC Timing Specifications At recommended operating conditions with L/TV DD of 2.5 V ± 5%.

1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to

representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).

1. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than

1.5 ns will be added to the associated clock signal.

1. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
2. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains
3. Guaranteed by characterization
4. ±100 ppm tolerance on RX_CLK frequency

Figure 19 shows the RGMII and RTBI AC timing and multiplexing diagrams. Figure 19. RGMII and RTBI AC Timing and Multiplexing Diagrams

8.2.7 RMII AC Timing Specifications

This section describes the RMII transmit and receive AC timing specifications.

8.2.7.1 RMII Transmit AC Timing Specifications

The RMII transmit AC timing specifications are in Table 35. Table 35. RMII Transmit AC Timing Specifications At recommended operating conditions with L/TV DD of 3.3 V ± 5%.

40 Freescale Semiconductor

Figure 20 shows the RMII transmit AC timing diagram. Figure 20. RMII Transmit AC Timing Diagram

8.2.7.2 RMII Receive AC Timing Specifications

1. The symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state)

(TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). Table 36. RMII Receive AC Timing Specifications At recommended operating conditions with L/TV DD of 3.3 V ± 5%. Table 35. RMII Transmit AC Timing Specifications (continued) At recommended operating conditions with L/TV DD of 3.3 V ± 5%.

Figure 21 provides the AC test load for eTSEC. Figure 21. eTSEC AC Test Load Figure 22 shows the RMII receive AC timing diagram. Figure 22. RMII Receive AC Timing Diagram

9 Ethernet Management Interface Electrical

1. The symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state)

letter: R (rise) or F (fall). Table 36. RMII Receive AC Timing Specifications (continued) At recommended operating conditions with L/TV DD of 3.3 V ± 5%.

42 Freescale Semiconductor

9.1 MII Management DC Electrical Characteristics

for MDIO and MDC are provided in Table 37.

9.2 MII Management AC Electrical Specifications

Table 38 provides the MII management AC timing specifications. Table 37. MII Management DC Electrical Characteristics

1. Note that the symbol V IN, in this case, represents the OVIN symbol referenced in Ta bl e 1 and Ta bl e 2.

Table 38. MII Management AC Timing Specifications At recommended operating conditions with OVDD is 3.3 V ± 5%.

44 Freescale Semiconductor

10 Local Bus

This section describes the DC and AC electrical specifications for the local bus interface of the MPC8640.

10.1 Local Bus DC Electrical Characteristics

10.2 Local Bus AC Electrical Specifications

Table 40 describes the timing parameters of the local bus interface at OVDD = 3.3 V with PLL enabled. Table 39. Local Bus DC Electrical Characteristics (3.3 V DC)

1. Note that the symbol V IN, in this case, represents the OVIN symbol referenced in Ta ble 1 and Ta ble 2.

Table 40. Local Bus Timing Parameters (OVDD = 3.3 V)m - PLL Enabled

Figure 25 provides the AC test load for the local bus.

1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional
2. All timings are in reference to LSYNC_IN for PLL enabled and internal local bus clock for PLL
3. All signals are measured from OV DD/2 of the rising edge of LSYNC_IN for PLL enabled or
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when
6. tLBOTOT is a measurement of the minimum time between the negation of LALE and any

change in LAD. tLBOTOT is programmed with the LBCR[AHD] parameter.

1. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew

measured between complementary signals at BV DD/2. Table 40. Local Bus Timing Parameters (OVDD = 3.3 V)m - PLL Enabled (continued)

46 Freescale Semiconductor

Figure 25. Local Bus AC Test Load Figure 26 to Figure 31 show the local bus signals. Figure 26. Local Bus Signals (PLL Enabled)

Table 41. Local Bus Timing Parameters—PLL Bypassed

48 Freescale Semiconductor

1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state)

to the output (O) going invalid (X) or output hold time.

1. All timings are in reference to local bus clock for PLL bypass mode. Timings may be negative with respect to the local bus
2. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between

complementary signals at BV DD/2.

1. All signals are measured from BVDD/2 of the rising edge of local bus clock for PLL bypass mode to 0.4 x BVDD of the signal

in question for 3.3-V signaling levels.

1. Input timings are measured at the pin.
2. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

1. Guaranteed by characterization.

Table 41. Local Bus Timing Parameters—PLL Bypassed (continued)

Figure 27. Local Bus Signals (PLL Bypass Mode) rising edge of the internal clock.

50 Freescale Semiconductor

Figure 28. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (clock ratio of 4) (PLL Enabled)

Figure 29. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (clock ratio of 4)

52 Freescale Semiconductor

Figure 30. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 or 8 (clock ratio of 8 or 16)

Figure 31. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 or 8 (clock ratio of 8 or 16)

11 JTAG

11.1 JTAG DC Electrical Characteristics

Table 42 provides the DC electrical characteristics for the JTAG interface.

54 Freescale Semiconductor

11.2 JTAG AC Electrical Specifications

Table 43 provides the JTAG AC timing specifications as defined in Figure 33 through Figure 35. Table 42. JTAG DC Electrical Characteristics

1. Note that the symbol V IN, in this case, represents the OVIN symbol referenced in Ta bl e 1

Table 43. JTAG AC Timing Specifications (Independent of SYSCLK) 1 At recommended operating conditions (see Ta ble 3).

1. All outputs are measured from the midpoint voltage of the falling/rising edge of t TCLK to the midpoint of the signal

(see Figure 32). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

1. The symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state)

appropriate letter: R (rise) or F (fall). is an asynchronous level sensitive signal. The setup time is for test purposes only.

1. Non-JTAG signal input timing with respect to tTCLK.
2. Non-JTAG signal output timing with respect to tTCLK.

Table 43. JTAG AC Timing Specifications (Independent of SYSCLK) 1 (continued) At recommended operating conditions (see Ta ble 3).

56 Freescale Semiconductor

Figure 32 provides the AC test load for TDO and the boundary-scan outputs. Figure 32. AC Test Load for the JTAG Interface Figure 33 provides the JTAG clock input timing diagram. Figure 33. JTAG Clock Input Timing Diagram Figure 34 provides the TRST timing diagram. Figure 34. TRST Timing Diagram Figure 35 provides the boundary-scan timing diagram. Figure 35. Boundary-Scan Timing Diagram

12 I 2C

This section describes the DC and AC electrical characteristics for the I2C interfaces of the MPC8640.

12.1 I 2C DC Electrical Characteristics

Table 44 provides the DC electrical characteristics for the I2C interfaces.

12.2 I 2C AC Electrical Specifications

Table 45 provides the AC timing parameters for the I2C interfaces. Table 44. I2C DC Electrical Characteristics At recommended operating conditions with OVDD of 3.3 V ± 5%.

1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. Refer to the MPC8641 Integrated Host Processor Reference Manual for information on the digital filter used.
3. I/O pins will obstruct the SDA and SCL lines if OV DD is switched off.

Table 45. I2C AC Electrical Specifications All values refer to VIH (min) and VIL (max) levels (see Ta ble 44).

58 Freescale Semiconductor

Figure 32 provides the AC test load for the I2C. Figure 36. I2C AC Test Load Figure 37 shows the AC timing diagram for the I2C bus.

1. The symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state)

setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

1. As a transmitter, the MPC8640 provides a delay time of at least 300 ns for the SDA signal (referred to the Vihmin

Divider Ratio for SCL”. Note that the I2C Source Clock Frequency is half of the MPX clock frequency for MPC8640.

1. The maximum tI2DXKL has only to be met if the device does not stretch the LOW period (t I2CL) of the SCL signal.

B = capacitance of one bus line in pF . Table 45. I2C AC Electrical Specifications (continued) All values refer to VIH (min) and VIL (max) levels (see Ta ble 44).

Figure 37. I2C Bus AC Timing Diagram

13 High-Speed Serial Interfaces (HSSI)

can be used for PCI Express and/or Serial RapidIO data transfers.

13.1 Signal Terms Definition

used in the description and specification of differential signals. receiver input (SDn_RX and SDn_RX). Each signal swings between A V olts and B V olts where A > B.

1. Differential Output Voltage, VOD (or Differential Output Swing):
2. Differential Input Voltage, VID (or Differential Input Swing):

60 Freescale Semiconductor

1. Differential Peak Voltage, VDIFFp

is defined as Differential Peak V oltage, VDIFFp = |A - B| V olts.

1. Differential Peak-to-Peak, VDIFFp-p

calculated as VTX-DIFFp-p = 2*|VOD|. waveform is not referenced to ground. Refer to Figure 47 as an example for differential waveform.

1. Common Mode Voltage, V cm

Figure 38. Differential Voltage Definitions for Transmitter or Receiver

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 61 High-Speed Serial Interfaces (HSSI) To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing that goes between 2.5V and 2.0V . Using these values, the peak-to-peak voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since the differential signaling environment is fully symmetrical, the transmitter output’s differential swing OD) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500 mV and –500 mV , in other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV . The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.

13.2 SerDes Reference Clocks

The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding SerDes lanes. The SerDes reference clocks inputs are SDn_REF_CLK and SDn_REF_CLK for PCI Express and Serial RapidIO. The following sections describe the SerDes reference clock requirements and some application information.

13.2.1 SerDes Reference Clock Receiver Characteristics

Figure 39 shows a receiver reference diagram of the SerDes reference clocks.  The supply voltage requirements for XV DD_SRDSn are specified in Table 1 and Table 2.  SerDes Reference Clock Receiver Reference Circuit Structure —T h e S Dn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as shown in Figure 39. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a 50-Ω termination to SGND followed by on-chip AC-coupling. — The external reference clock driver must be able to drive this termination. — The SerDes reference clock input can be eith er differential or single-ended. Refer to the Differential Mode and Single-ended Mode description below for further detailed requirements.  The maximum average current requirement that also determines the common mode voltage range — When the SerDes reference clock differential i nputs are DC coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8mA. In this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 mA (refer to the following bullet for more detail), since the input is AC-coupled on-chip. — This current limitation sets the maximum common m ode input voltage to be less than 0.4V (0.4V/50 = 8mA) while the minimum common mode input level is 0.1V above SGND. For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0mA to 16mA (0-0.8V), such that each phase of the differential input has a single-ended swing from 0V to 800mV with the common mode voltage at 400mV . — If the device driving the SD n_REF_CLK and SD n_REF_CLK inputs cannot drive 50 ohms to SGND DC, or it exceeds the maximum input current limitations, then it must be AC-coupled off-chip.

62 Freescale Semiconductor

— This requirement is described in detail in the following sections. Figure 39. Receiver of SerDes Reference Clocks

13.2.2 DC Level Requirement for SerDes Reference Clocks

200mV . This requirement is the same for both external DC-coupled or AC-coupled connection. for DC-coupled connection scheme. requirement for AC-coupled connection scheme. n_REF_CLK either left unconnected or tied to ground. the SerDes reference clock input requirement for single-ended signaling mode.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

64 Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

13.2.3 Interfacing With Other Differential Signaling Levels

 With on-chip termination to SGND, the differentia l reference clocks inputs are HCSL (High-Speed Current Steering Logic) compatible DC-coupled.  Many other low voltage differen tial type outputs like LVDS (Low V oltage Differential Signaling) can be used but may need to be AC-coupled due to the limited common mode input range allowed (100 to 400 mV) for DC-coupled connection.  LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to AC-coupling. NOTE Figure 43 to Figure 46 below are for conceptual reference only. Due to the fact that clock driver chip's internal structure, output impedance and termination requirements are different between various clock driver chip manufacturers, it’s very possible that the clock circuit reference designs provided by clock driver chip vendor are different from what is shown below. They might also vary from one vendor to the other. Therefore, Freescale Semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. The system designer is recommended to contact the selected clock driver chip vendor for the optimal reference circuits with the MPC8640D SerDes reference clock receiver requirement provided in this document.

66 Freescale Semiconductor

Figure 45 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver. particular clock driver chip. Figure 45. AC-Coupled Differential Connection with L VPECL Clock Driver (Reference Only) Clock Driver 100 Ω differential PWB trace SerDes Refer.

Figure 46 shows the SerDes reference clock connection reference circuits for a single-ended clock driver. Figure 46. Single-Ended Connection (Reference Only)

13.2.4 AC Requirements for SerDes Reference Clocks

transmission line and reduce reflections which are a source of noise to the system. Table 46 describes some AC parameters common to PCI Express and Serial RapidIO protocols. Table 46. SerDes Reference Clock Common AC Parameters At recommended operating conditions with XV DD_SRDS1 or XVDD_SRDS2 = 1.1V ± 5% and 1.05V ± 5%. 100 Ω differential PWB trace SerDes Refer. output impedance is about 16 Ω.

68 Freescale Semiconductor

Figure 47. Differential Measurement Points for Rise and Fall Time Figure 48. Single-Ended Measurement Points for Rise and Fall Time Matching

1. Measurment taken from single ended waveform.
2. Measurment taken from differential waveform.
3. Measured from -200 mV to +200 mV on the differential waveform (derived from SD

on the differential zero crossing. See Figure 47.

1. Matching applies to rising edge rate for SD

exceed 20% of the slowest edge rate. See Figure 48. Table 46. SerDes Reference Clock Common AC Parameters (continued) At recommended operating conditions with XV DD_SRDS1 or XVDD_SRDS2 = 1.1V ± 5% and 1.05V ± 5%.

13.3 SerDes Transmitter and Receiver Reference Circuits

Figure 49 shows the reference circuits for SerDes data lane’s transmitter and receiver. Figure 49. SerDes Transmitter and Receiver Reference Circuits the capacitor value defined in specification of each protocol section.

14 PCI Express

This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8640.

14.1 DC Requirements for PCI Express SD n_REF_CLK and

14.2 AC Requirements for PCI Express SerDes Clocks

Table 47 lists AC requirements. Table 47. SDn_REF_CLK and SDn_REF_CLK AC Requirements

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

70 Freescale Semiconductor

14.3 Clocking Dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm) of each other at all times. This is specified to allow bit rate clock sources with a +/– 300 ppm tolerance.

14.4 Physical Layer Specifications

The following is a summary of the specifications for the physical layer of PCI Express on this device. For further details as well as the specifications of the Transport and Data Link layer please use the PCI EXPRESS Base Specification. REV . 1.0a document.

14.4.1 Differential Transmitter (TX) Output

specified at the component pins. Table 48. Differential Transmitter (TX) Output Specifications first bit after a transition. See Note 2.

0.70 UI The maximum T ransmitter jitter can be derived as

TTX-MAX-JITTER = 1 - TTX-EYE= 0.3 UI.

0.15 UI Jitter is defined as the measurement variation of the

0.125 UI See Notes 2 and 5

72 Freescale Semiconductor

Receiver is present. See Note 6.

50 UI Minimum time a T ransmitter must be in Electrical Idle

20 UI After sending an Electrical Idle ordered set, the

Idle after transitioning from LO.

20 UI Maximum time to meet all TX specifications when

the transmitting component itself. Table 48. Differential Transmitter (TX) Output Specifications (continued)

14.4.2 Transmitter Compliance Eye Diagrams

Figure 52) in place of any real PCI Express interconnect + RX component. of the de-emphasized bit will always be relative to the transition bit. The eye diagram must be valid for any 250 consecutive UIs. merit function (i.e., least squares and median deviation fits). one Downstream and one Upstream Port. See Note 7. 1.) No test load is necessarily associated with this value. TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. TX is optional for the return loss measurement. 5.) Measured between 20-80% at transmitter package pins into a test load as shown in Figure 52 for both VTX-D+ and VTX-D-.

74 Freescale Semiconductor

Figure 50. Minimum Transmitter Timing and Voltage Output Compliance Specifications

14.4.3 Differential Receiver (RX) Input Specifications

specified at the component pins. Table 49. Differential Receiver (RX) Input Specifications

0.4 UI The maximum interconnect media and

0.3 UI Jitter is defined as the measurement variation

the TX UI. See Notes 2, 3 and 7. (50 ± 20% tolerance). See Notes 2 and 5. signal an unexpected idle condition. Table 49. Differential Receiver (RX) Input Specifications (continued)

76 Freescale Semiconductor

14.5 Receiver Compliance Eye Diagrams

Figure 52) in place of any real PCI Express RX component. must be aligned in time using the jitter median to locate the center of the eye diagram. 1.) No test load is necessarily associated with this value. be used as a reference for the eye diagram. be used as the reference for the eye diagram. there is a 5 ms transition time before Receiver termination values must be met on all un-configured Lanes of a Port. measured at 300 mV above the RX ground.

The eye diagram must be valid for any 250 consecutive UIs. optional for the return loss measurement. Figure 51. Minimum Receiver Eye Timing and Voltage Compliance Specification

14.5.1 Compliance Test and Measurement Load

inches of the package pins, into a test/measurement load shown in Figure 52.

78 Freescale Semiconductor

Figure 52. Compliance Test/Measurement Load

15 Serial RapidIO

for the LP-Serial physical layer. The electrical specifications cover both single and multiple-lane links. from both the short run and long run transmitter specifications. power used by the transceivers. allow a distance of at least 50 cm at all baud rates. between any transmit and receive clock will be 200 ppm. coupling at the receiver input must be used.

15.1 DC Requirements for Serial RapidIO SD n_REF_CLK and

15.2 AC Requirements for Serial RapidIO SD n_REF_CLK and

Table 50 lists AC requirements.

15.3 Signal Definitions

1. The transmitter output signals and the receiver input signals TD, TD , RD and RD each have a
2. The differential output signal of the transmitter, V OD, is defined as VTD-VTD
3. The differential input signal of the receiver, VID, is defined as VRD-VRD
4. The differential output signal of the transmitter and the differential input signal of the receiver
5. The peak value of the differential transmitter output signal and the differential receiver input
6. The peak-to-peak value of the differential transmitter output signal and the differential receiver

Table 50. SDn_REF_CLK and SDn_REF_CLK AC Requirements

80 Freescale Semiconductor

Figure 53. Differential Peak-Peak Voltage of Transmitter or Receiver differential voltage is 500 mV . The peak-to-peak differential voltage is 1000 mV p-p.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 81 Serial RapidIO

15.4 Equalization

With the use of high speed serial links, the interconnect media will cause degradation of the signal at the receiver. Effects such as Inter-Symbol Interference (ISI) or data dependent jitter are produced. This loss can be large enough to degrade the eye opening at the receiver beyond what is allowed in the specification. To negate a portion of these effects, equalization can be used. The most common equalization techniques that can be used are:  A passive high pass filter network placed at the receiver. This is often referred to as passive equalization.  The use of active circuits in the receiver. This is often referred to as adaptive equalization.

15.5 Explanatory Note on Transmitter and Receiver Specifications

AC electrical specifications are given for transmitter and receiver. Long run and short run interfaces at three baud rates (a total of six cases) are described. The parameters for the AC electrical specifications are guided by the XAUI electrical interface specified in Clause 47 of IEEE 802.3ae-2002. XAUI has similar application goals to serial RapidIO, as described in Section 8.1. The goal of this standard is that electrical designs for serial RapidIO can reuse electrical designs for XAUI, suitably modified for applications at the baud intervals and reaches described herein.

15.6 Transmitter Specifications

LP-Serial transmitter electrical and timing specifications are stated in the text and tables of this section. The differential return loss, S11, of the transmitter in each case shall be better than  –10 dB for (Baud Frequency)/10 < Freq(f) < 625 MHz, and  –10 dB + 10log(f/625 MHz) dB for 625 MHz ≤ Freq(f) ≤ Baud Frequency The reference impedance for the differential return loss measurements is 100 Ohm resistive. Differential return loss includes contributions from on-chip circuitry, chip packaging and any off-chip components related to the driver. The output impedance requirement applies to all valid output levels. It is recommended that the 20%-80% rise/fall time of the transmitter, as measured at the transmitter output, in each case have a minimum value 60 ps. It is recommended that the timing skew at the output of an LP-Serial transmitter between the two signals that comprise a differential pair not exceed 25 ps at 1.25 GB, 20 ps at 2.50 GB and 15 ps at 3.125 GB.

82 Freescale Semiconductor

Table 51. Short Run Transmitter AC Timing Specifications—1.25 GBaud Table 52. Short Run Transmitter AC Timing Specifications—2.5 GBaud Table 53. Short Run Transmitter AC Timing Specifications—3.125 GBaud

Table 54. Long Run Transmitter AC Timing Specifications—1.25 GBaud Table 55. Long Run Transmitter AC Timing Specifications—2.5 GBaud Table 53. Short Run Transmitter AC Timing Specifications—3.125 GBaud (continued)

84 Freescale Semiconductor

Figure 54. Transmitter Output Compliance Mask Table 56. Long Run Transmitter AC Timing Specifications—3.125 GBaud

15.7 Receiver Specifications

LP-Serial receiver electrical and timing specifications are stated in the text and tables of this section. 100 Ohm resistive for differential return loss and 25 Ohm resistive for common mode. Table 57. Transmitter Differential Output Eye Diagram Parameters Table 58. Receiver AC Timing Specifications—1.25 GBaud

1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. Th e

is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.

86 Freescale Semiconductor

Table 59. Receiver AC Timing Specifications—2.5 GBaud

1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. Th e

is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects. Table 60. Receiver AC Timing Specifications—3.125 GBaud

1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. Th e

is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.

Figure 55. Single Frequency Sinusoidal Jitter Limits

15.8 Receiver Eye Diagrams

a 100 Ohm +/– 5% differential resistive load.

8.5 UI p-p

0.10 UI p-p

88 Freescale Semiconductor

Figure 56. Receiver Input Compliance Mask Table 61. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter

15.9 Measurement and Test Requirements

recommended as a reference for additional information on jitter test methods.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 89 Serial RapidIO

15.9.1 Eye Template Measurements

For the purpose of eye template measurements, the effects of a single-pole high pass filter with a 3 dB point at (Baud Frequency)/1667 is applied to the jitter. The data pattern for template measurements is the Continuous Jitter Test Pattern (CJPA T) defined in Annex 48A of IEEE802.3ae. All lanes of the LP-Serial link shall be active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A. Single lane implementations shall use the CJPA T sequence specified in Annex 48A for transmission on lane 0. The amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10-12. The eye pattern shall be measured with AC coupling and the compliance template centered at 0 V olts differential. The left and right edges of the template shall be aligned with the mean zero crossing points of the measured data eye. The load for this test shall be 100 Ohms resistive +/– 5% differential to 2.5 GHz.

15.9.2 Jitter Test Measurements

For the purpose of jitter measurement, the effects of a single-pole high pass filter with a 3 dB point at (Baud Frequency)/1667 is applied to the jitter. The data pattern for jitter measurements is the Continuous Jitter Test Pattern (CJPA T) pattern defined in Annex 48A of IEEE802.3ae. All lanes of the LP-Serial link shall be active in both the transmit and receive directions, and opposite ends of the links shall use asynchronous clocks. Four lane implementations shall use CJPA T as defined in Annex 48A. Single lane implementations shall use the CJPA T sequence specified in Annex 48A for transmission on lane 0. Jitter shall be measured with AC coupling and at 0 V olts differential. Jitter measurement for the transmitter (or for calibration of a jitter tolerance setup) shall be performed with a test procedure resulting in a BER curve such as that described in Annex 48B of IEEE802.3ae.

15.9.3 Transmit Jitter

Transmit jitter is measured at the driver output when terminated into a load of 100 Ohms resistive +/– 5% differential to 2.5 GHz.

15.9.4 Jitter Tolerance

Jitter tolerance is measured at the receiver using a jitter tolerance test signal. This signal is obtained by first producing the sum of deterministic and random jitter defined in Section 8.6 and then adjusting the signal amplitude until the data eye contacts the 6 points of the minimum eye opening of the receive template shown in Figure 8-4 and Table 8-11. Note that for this to occur, the test signal must have vertical waveform symmetry about the average value and have horizontal symmetry (including jitter) about the mean zero crossing. Eye template measurement requirements are as defined above. Random jitter is calibrated using a high pass filter with a low frequency corner at 20 MHz and a 20 dB/decade roll-off below this. The required sinusoidal jitter specified in Section 8.6 is then added to the signal and the test load is replaced by the receiver being tested.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

90 Freescale Semiconductor

This section details package parameters and dimensions.

16.1 Package Parameters for the MPC8640

The package parameters are as provided in the following list. The package type is 33 mm x 33 mm, 1023 pins. There are two package options: high-lead Flip Chip-Ceramic Ball Grid Array (FC-CBGA), and lead-free (FC-CBGA). For all package types: Die size 12.1 mm x 14.7 mm Package outline 33 mm x 33 mm Interconnects 1023 Pitch 1 mm Total Capacitor count 43 caps; 100 nF each For high-lead FC-CBGA (package option: HCTE

1 HX)

Maximum module height 2.97 mm Minimum module height 2.47 mm Solder Balls 89.5% Pb 10.5% Sn Ball diameter (typical 2) 0.60 mm For RoHS lead-free FC-CBGA (package option: HCTE1 VU) Maximum module height 2.77 mm Minimum module height 2.27 mm Solder Balls 95.5% Sn 4.0% Ag 0.5% Cu Ball diameter (typical 2) 0.60 mm

1 High-coefficient of thermal expansion

2 Typical ball diameter is before reflow

16.2 Mechanical Dimensions of the MPC8640 FC-CBGA

(package option: HCTE VU) are shown respectfully in Figure 57 and Figure 58. Figure 57. MPC8640D High-Head FC-CBGA Dimensions

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1

92 Freescale Semiconductor

1. All dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M-1994. 3. Maximum solder ball diameter measured parallel to datum A. 4. Datum A, the seating plane, is defined by the spherical crowns of the solder balls. 5. Capacitors may not be present on all devices. 6. Caution must be taken not to short capacitors or expose metal capacitor pads on package top. 7. All dimensions symmetrical about centerlines unless otherwise specified. 8. Note that for MPC8640 (single core) the solder balls for the following signals/pins are not populated in the package: VDD_Core1 (R16, R18, R20, T17, T19, T21, T23, U16, U18, U22, V17, V19, V21, V23, W16, W18, W20, W22, Y17, Y19, Y21, Y23, AA16, AA18, AA20, AA22, AB23, AC24) and SEN SEVDD_Core1 (U20).

Figure 58. MPC8640D Lead-Free FC-CBGA Dimensions

94 Freescale Semiconductor

1. All dimensions are in millimeters.
2. Dimensions and tolerances per ASME Y14.5M-1994.
3. Maximum solder ball diameter measured parallel to datum A.
4. Datum A, the seating plane, is defined by the spherical crowns of the solder balls.
5. Capacitors may not be present on all devices.
6. Caution must be taken not to short capacitors or expose metal capacitor pads on package top.
7. All dimensions symmetrical about centerlines unless otherwise specified.
8. Note that for MPC8640 (single core) the solder balls for the following signals/pins are not populated in the

17 Signal Listings

device (MPC8640) are italized and prefixed by “S”. Table 62. MPC8640 Signal Reference by Functional Block

Table 62. MPC8640 Signal Reference by Functional Block (continued)

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100 Freescale Semiconductor

102 Freescale Semiconductor

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1.8 DDR2

2.5 V - DDR

1.8 V - DDR2

106 Freescale Semiconductor

1. Multi-pin signals such as D1_MDQ[0:63] and D2_MDQ[0:63] have their physical package pin numbers listed in order

corresponding to the signal names.

1. Stub Series T erminated Logic (SSTL-18 and SSTL-25) type pins.
2. If a DDR port is not used, it is possible to leave the related power supply (Dn_GVDD, Dn_MVREF) turned off at reset. Note

that these power supplies can only be powered up again at reset for functionality to occur on the DDR port.

1. Low Voltage Differential Signaling (L VDS) type pins.
2. Low Voltage Transistor-Transistor Logic (L VTTL) type pins.
3. This pin is a reset configuration pin and appears again in the Reset Configuration Signals section of this table. See the Re set

Configuration Signals section of this table for config name and connection details.

1. Recommend a weak pull-up resistor (1–10 k Ω) be placed from this pin to its power supply.

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108 Freescale Semiconductor

1. Recommend a weak pull-down resistor (2–10 k Ω) be placed from this pin to ground. 9. This multiplexed pin has input status in one mode and output in another 10. This pin is a multiplexed signal for different functional blocks and appears more than once in this table. 11. This pin is open drain signal. 12. Functional only on the MPC8640D. 13. These pins should be left floating. 14. These pins should be connected to SV DD. 15. These pins should be pulled to ground with a strong resistor (270- Ω to 330-Ω). 16. These pins should be connected to OVDD. 17.This is a SerDes PLL/DLL digital test signal and is only for factory use. 18. This is a SerDes PLL/DLL analog test signal and is only for factory use. 19. This pin should be pulled to ground with a 100- Ω resistor. 20. The pins in this section are reset configuration pins. Each pin has a weak internal pull-up P-FET which is enabled only when the processor is in the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-k Ω pull-down resistor. However, if the signal is intended to be high after reset, and if there is any device on the net which might pull dow n the value of the net at reset, then a pullup or active driver is needed. 21. Should be pulled down at reset if platform frequency is at 400 MHz. 22. These pins require 4.7-kΩ pull-up or pull-down resistors and must be driven as they are used to determine PLL configuration ratios at reset. 23. This output is actively driven during reset rather than being tri-stated during reset. 24 These JT AG pins have weak internal pull-up P-FETs that are always enabled. 25. This pin should NOT be pulled down (or driven low) during reset. 26.These are test signals for factory use only and must be pulled up (100- Ω to 1- kΩ.) to OVDD for normal machine operation. 27. Dn_MDIC[0] should be connected to ground with an 18-Ω resistor +/- 1-Ω and Dn_MDIC[1] should be connected Dn_GVDD with an 18-Ω resistor +/- 1-Ω. These pins are used for automatic calibration of the DDR IOs. 28. Pin N18 is recommended as a reference point for determining the voltage of V DD_PLAT and is hence considered as the VDD_PLA T sensing voltage and is called SENSEVDD_PLAT . 29. Pin P18 is recommended as the ground reference point for SENSEVDD_PLA T and is called SENSEVSS_PLA T . 30.This pin should be pulled to ground with a 200- Ω resistor. 31.These pins are connected to the power/ground planes internally and may be used by the core power supply to improve tracking and regulation. 32. Must be tied low if unused 33. These pins may be used as defined functional reset configuration pins in the future. Please include a resistor pull up/down option to allow flexibility of future designs. 34. Used as serial data output for SRIO 1x/4x link. 35. Used as serial data input for SRIO 1x/4x link. 36.This pin requires an external 4.7-kΩ pull-down resistor to prevent PHY from seeing a valid T ransmit Enable before it is actively driven. 37.This pin is only an output in FIFO mode when used as Rx Flow Control. 38.This pin functions as cfg_dram_type[0 or 1] at reset and MUST BE VALID BEFORE HRESET ASSERTION in device sleep mode. 39. Should be pulled to ground if unused (such as in FIFO, MII and RMII modes). 40. See Section 18.4.2, “Platform to FIFO Restrictions” for clock speed limitations for this pin when used in FIFO mode. 41. The phase between the output clocks TSEC1_GTX_CLK and TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps. The phase between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK (ports 3 and 4) is no more than 100 ps. 42. For systems which boot from Local Bus (GPCM)-controlled flash, a pullup on LGPL4 is required. Special Notes for Single Core Device: S1. Solder ball for this signal will not be populated in the single core package. S2. The PLL filter from VDD_Core1 to AVDD_Core1 should be removed. AVDD_Core1 should be pulled to ground with a weak (2–10 kΩ) resistor. See Section 20.2.1, “PLL Power Supply Filtering” for more details.

S3. This pin should be pulled to GND for the single core device. S4. No special requirement for this pin on single core device. Pin should be tied to power supply as directed for dual core.

18 Clocking

18.1 Clock Ranges

provides the clocking for the Local bus. Table 63. Processor Core Clocking Specifications

1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such

and Section 18.3, “e600 to MPX clock PLL Ratio,” for ratio settings.

1. The minimum e600 core frequency is based on the minimum platform clock frequency of 400 MHz.

Table 64. Memory Bus Clocking Specifications

1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be
2. The memory bus clock speed is half the DDR/DDR2 data rate, hence, half the MPX clock

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18.2 MPX to SYSCLK PLL Ratio

frequency must equal the DDR data rate. Table 65. Platform/MPX bus Clocking Specifications

1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be
2. Platform/MPX frequencies between 400 and 500 MHz are not supported.

Table 66. Local Bus Clocking Specifications

1. The Local bus clock speed on LCLK[0:2] is determined by MPX clock divided by the Local Bus

Table 67. MPX:SYSCLK Ratio

0000 Reserved

0001 Reserved

18.4 Frequency Options

18.4.1 SYSCLK to Platform Frequency Options

0111 Reserved

1001 Reserved

Table 68. e600 Core to MPX Clock Ratio

11100 Reserved

10100 Reserved

01110 Reserved

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configuration pin that is related to platform frequency.

18.4.2 Platform to FIFO Restrictions

Please note the following FIFO maximum speed restrictions based on platform speed.

19 Thermal

This section describes the thermal specifications of the MPC8640.

19.1 Thermal Characteristics

Table 70 provides the package thermal characteristics for the MPC8640. Table 69. Frequency Options of SYSCLK with Respect to Platform/MPX Clock Speed frequency range is 400 MHz, 500-533 MHz.

19.2 Thermal Management Information

plastic backing structure. Screw and spring arrangements are also frequently used. Table 70. Package Thermal Characteristics 1

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
2. Per JEDEC JESD51-2 with the single-layer board (JESD51-3) horizontal.
3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

1. This is the thermal resistance between die and case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1) with the calculated case temperature. Actual thermal resistance is less than 0.1 °C/W.

114 Freescale Semiconductor

Figure 59. FC-CBGA Package Exploded Cross-Sectional View with Several Heat Sink Options

60 Alhambra Road, Suite 1

671 East Brokaw Road

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 115 Thermal Tyco Electronics 800-522-6752 Chip Coolers™ P.O. Box 3668 Harrisburg, PA 17105-3668 Internet: www.chipcoolers.com Wakefield Engineering 603-635-5102 33 Bridge St. Pelham, NH 03076 Internet: www.wakefield.com Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost.

19.2.1 Internal Package Conduction Resistance

For the exposed-die packaging technology described in Table 70, the intrinsic conduction thermal resistance paths are as follows:  The die junction-to-case thermal resistance (the case is actually the top of the exposed silicon die)  The die junction-to-board thermal resistance

116 Freescale Semiconductor

Figure 60. C4 Package with Heat Sink Mounted to a Printed-Circuit Board thermal resistances are the dominant terms.

19.2.2 Thermal Interface Materials

manufacturability, service temperature, dielectric properties, cost, and so on.

Figure 61. Thermal Performance of Select Thermal Interface Material

18930 West 78

118 Freescale Semiconductor

19.2.3 Heat Sink Selection Example

Table 2. The temperature of air cooling the component greatly depends on the ambient inlet air temperature below the maximum value of Table 2.

technology, system air temperature rise, altitude, and so on. well as system-level designs. collapsed thermal resistance with thermal conductivity of 9.6W/(m  K) and an effective height of 0.1 mm. Figure 62. Recommended Thermal Model of MPC8640

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19.2.4 Temperature Diode

The MPC8640 has a temperature diode on the microprocessor that can be used in conjunction with other system temperature monitoring devices (such as Analog Devices, ADT7461™). These devices use the negative temperature coefficient of a diode operated at a constant current to determine the temperature of the microprocessor and its environment. For proper operation, the monitoring device used should auto-calibrate the device by canceling out the V BE variation of each MPC8640’s internal diode. The following are the specifications of the MPC8640 on-board temperature diode: Vf > 0.40 V Vf < 0.90 V Operating range 2–300 μA Diode leakage < 10 nA @ 125°C Ideality factor over 5–150 μA at 60°C: n = 1.0275 ± 0.9% Ideality factor is defined as the deviation from the ideal diode equation: Another useful equation is: Where: Ifw = Forward current Is = Saturation current Vd = V oltage at diode Vf = V oltage forward biased VH = Diode voltage while IH is flowing VL = Diode voltage while IL is flowing IH = Larger diode bias current IL = Smaller diode bias current q = Charge of electron (1.6 x 10 –19 C) n = Ideality factor (normally 1.0) K = Boltzman’s constant (1.38 x 10–23 Joules/K) T = Temperature (Kelvins) Ifw = I s e – 1 qVf___ nKT VH – VL = n ln KT__ q IH__ IL

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 121 System Design Information The ratio of IH to IL is usually selected to be 10:1. The above simplifies to the following: Solving for T, the equation becomes:

20 System Design Information

This section provides electrical and thermal design recommendations for successful application of the MPC8640.

20.1 System Clocking

This device includes six PLLs, as follows: 1. The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in Section 18.2, “MPX to SYSCLK PLL Ratio.” 2. The dual e600 Core PLLs generate the e 600 clock from the externally supplied input. 3. The local bus PLL generates the clock for the local bus. 4. There are two internal PLLs for the SerDes block.

20.2 Power Supply Design and Sequencing

20.2.1 PLL Power Supply Filtering

Each of the PLLs listed above is provided with power through independent power supply pins. There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide independent filter circuits per PLL power supply as illustrated in Figure 64, one to each of the AVDD type pins. By providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the other is reduced. This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value capacitor. Each circuit should be placed as close as possible to the specific A VDD type pin being supplied to minimize noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the A VDD type pin, which is on the periphery of the footprint, without the inductance of vias. VH – VL = 1.986 × 10–4 × nT nT = 1.986 × 10–4

122 Freescale Semiconductor

Figure 63 and Figure 64 show the PLL power supply filter circuits for the platform and cores, respectively. Figure 63. MPC8640 PLL Power Supply Filter Circuit (for platform and Local Bus) Figure 64. MPC8640 PLL Power Supply Filter Circuit (for cores) frequency. All traces should be kept short, wide and direct. Figure 65. SerDes PLL Power Supply Filter A V DD_SRDSn should be a filtered version of SVDD.  Signals on the SerDes interface are fed from the SV DD power plan. (2-10 kΩ) pull-down resistor.

1. An 0805 sized capacitor is recommended for system initial bring-up.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 123 System Design Information

20.2.2 PLL Power Supply Sequencing

For details on power sequencing for the A VDD type and supplies refer to Section 2.2, “Power Up/Down Sequence.”

20.3 Decoupling Recommendations

Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC8640 system, and the device itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each OVDD, Dn_GVDD, LVDD, TVDD, VDD_Coren, and VDD_PLAT pin of the device. These decoupling capacitors should receive their power from separate OVDD, Dn_GVDD, LVDD, TVDD, VDD_Coren, and VDD_PLAT and GND power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly under the device using a standard escape pattern. Others may surround the part. These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the OVDD, Dn_GVDD, LVDD, TVDD, VDD_Coren, and VDD_PLAT planes, to enable quick recharging of the smaller chip capacitors. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (A VX TPS tantalum or Sanyo OSCON).

20.4 SerDes Block Power Supply Decoupling Recommendations

The SerDes block requires a clean, tightly regulated source of power (SVDD and XVDD_SRDSn) to ensure low jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below. Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections from all capacitors to power and ground should be done with multiple vias to further reduce inductance.  First, the board should have at least 10 x 10-nF SMT ceramic chip capacitors as close as possible to the supply balls of the device. Where the board has blind vias, these capacitors should be placed directly below the chip supply and ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the device as close to the supply and ground connections as possible.  Second, there should be a 1-µF ceramic chip capac itor on each side of the device. This should be done for all SerDes supplies.  Third, between the device and any SerDes voltage regulator there should be a 10-µF, low equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-µF, low ESR SMT tantalum chip capacitor. This should be done for all SerDes supplies.

124 Freescale Semiconductor

20.5 Connection Recommendations

should be connected to GND. All NC (no-connect) signals must remain unconnected. occur on the DDR port. Power supplies for other functional buses should remain powered. flash, a pullup on LGPL4 is required.

20.5.1 Guidelines for High-Speed Interface Termination

20.5.1.1 SerDes Interface

for a SerDes port. The termination recommendations must be followed for each port. Table 71. SerDes Port Enabled/Disabled Configurations

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 125 System Design Information If the high-speed SerDes port requires complete or partial termination, the unused pins should be terminated as described in this section. The following pins must be left unconnected (floating): S D n_TX[7:0] S D n_TX[7:0] The following pins must be connected to GND: S D n_RX[7:0] S D n_RX[7:0] S D n_REF_CLK  SDn_REF_CLK NOTE It is recommended to power down the unused lane through SRDS1CR1[0:7] register (offset = 0xE_0F08) and SRDS2CR1[0:7] register (offset = 0xE_0F44.) (This prevents the oscillations and holds the receiver output in a fixed state.) that maps to SERDES lane 0 to lane 7 accordingly. For other directions on reserved or no-connects pins see Section 17, “Signal Listings.”

20.6 Pull-Up and Pull-Down Resistor Requirements

The MPC8640 requires weak pull-up resistors (2–10 kΩ is recommended) on all open drain type pins. The following pins must NOT be pulled down during power-on reset: TSEC4_TXD[4], LGPL0/LSDA10, LGPL1/LSDWE, TRIG_OUT/READY , and D1_MSRCID[2]. The following are factory test pins and require strong pull up resistors (100Ω –1 kΩ) to OVDD LSSD_MODE, TEST_MODE[0:3].The following pins require weak pull up resistors (2–10 kΩ) to their specific power supplies: LCS[0:4], LCS[5]/DMA_DREQ2, LCS[6]/DMA_DACK[2], LCS[7]/DMA_DDONE[2], IRQ_OUT, IIC1_SDA, IIC1_SCL, IIC2_SDA, IIC2_SCL, and CKSTP_OUT. The following pins should be pulled to ground with a 100-Ω resistor: SD1_IMP_CAL_TX, SD2_IMP_CAL_TX. The following pins should be pulled to ground with a 200-Ω resistor: SD1_IMP_CAL_RX, SD2_IMP_CAL_RX. TSECn_TX_EN signals require an external 4.7-kΩ pull down resistor to prevent PHY from seeing a valid Transmit Enable before it is actively driven. When the platform frequency is 400 MHz, TSEC1_TXD[1] must be pulled down at reset.

1 Partial Termination when a SerDes port is enabled through both POR input and DEVDISR is determined by

the SerDes port mode. If the port is in x8 PCI Express mode, no termination is required because all pins are being used. If the port is in x1/x2/x4 PCI Express mode, termination is required on the unused pins. If the port is in x4 Serial RapidIO mode termination is required on the unused pins. 2 If a SerDes port is enabled through the POR input and then disabled through DEVDISR, no hardware changes are required. T ermination of the SerDes port should follow what is required when the port is enabled through both POR input and DEVDISR. See Note 1 for more information.

126 Freescale Semiconductor

V ALID BEFORE HRESET ASSERTION when coming out of device sleep mode.

20.6.1 Special instructions for Single Core device

SENSEVSS_Core1 and needs to be connected to ground with a weak (2-10 kΩ) pull down resistor. Likewise, AVDD_Core1 needs to be pulled to ground as shown in Figure 64.

20.7 Output Buffer DC Impedance

is a push-pull single-ended driver type (open drain for I2C). output impedance is the average of two components, the resistances of the pull-up and pull-down devices. other in value. Then, Z0 = (RP + RN)/2. Figure 66. Driver Impedance Measurement

20.8 Configuration Pin Muxing

pins). These pins are generally used as output only pins in normal operation. needed only when non-default settings are required by the user.

20.9 JTAG Configuration Signals

Table 72. Impedance Characteristics Note: Nominal supply voltages. See Ta ble 1, Tj = 105°C.

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if the TRST signal is asserted during power-on reset. Because the JTAG interface is also used for accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not practical. The COP function of these processors allows a remote computer system (typically a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP port connects primarily through the JTAG interface of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 67 allows the COP port to independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well. The COP interface has a standard header, shown in Figure 67, for connection to the target system, and is based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector key. The COP header adds many benefits such as breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features. An inexpensive option can be to leave the COP header unpopulated until needed. There is no standardized way to number the COP header shown in Figure 67; consequently, many different pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in Figure 67 is common to all known emulators. For a multi-processor non-daisy chain configuration, Figure 68, can be duplicated for each processor. The recommended daisy chain configuration is shown in Figure 69. Please consult with your tool vendor to determine which configuration is supported by their emulator.

20.9.1 Termination of Unused Signals

If the JTAG interface and COP header will not be used, Freescale recommends the following connections: T R S T should be tied to HRESET through a 0 kΩ isolation resistor so that it is asserted when the system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during the power-on reset flow. Freescale recommends that the COP header be designed into the system as shown in Figure 68. If this is not possible, the isolation resistor will allow future access to TRST in case a JTAG interface may need to be wired onto the system in future debug situations.  Tie TCK to OV DD through a 10 kΩ resistor. This will prevent TCK from changing state and reading incorrect data into the device.  No connection is required for TDI, TMS, or TDO.

Figure 67. COP Connector Physical Pinout

130 Freescale Semiconductor

Figure 68. JTAG/COP Interface Connection for one MPC8640 device

1. The KEY location (pin 14) is not physically present on the COP header.
2. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for
3. This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid

accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed or removed.

1. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.
2. The COP port and target board should be able to independently assert HRESET and TRST to the processor

in order to fully control the processor as shown here.

MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 131

Ordering Information

Figure 69. JTAG/COP Interface Connection for Multiple MPC8640 Devices in Daisy Chain Configuration

2 HRESET

1. Populate this with a 10Ω resistor for short circuit/current-limiting protection.
2. KEY location; pin 14 is not physically present on the COP header.
3. Use a AND gate with sufficient drive strength to drive two inputs.
4. The COP port and target board should be able to independently assert HRESET and TRST to the processor in order

to fully control the processor as shown above.

1. This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid

accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed or removed.

1. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for

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132 Freescale Semiconductor

21.1 Part Numbers Fully Addressed by This Document

Table 73 provides the Freescale part numbering nomenclature for the MPC8640. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify special application conditions. Each part number also contains a revision code which refers to the die mask revision number. Table 74 shows the parts that are available for ordering and their operating conditions. Table 73. Part Numbering Nomenclature

1. See Section 16, “Package,” for more information on available package types.
2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specifica tion
3. The P prefix in a Freescale part number designates a “Pilot Production Prototype” as defined by Freescale SOP 3-13. These parts

that product changes may still occur while shipping pilot production prototypes.

1. Part Number MC8640xxx1067NC is our low V

DD_Coren device. VDD_Coren = 0.95 V and VDD_PLAT = 1.05 V.

1. MC - Qualified production

Table 74. Part Offerings and Operating Conditions

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21.2 Part Marking

Parts are marked as the example shown in Figure 70. Figure 70. Part Marking for FC-CBGA Device package option. For more information see Table 73. YWWLAZ is the assembly traceability code. MMMMMM is the M00 (mask) number.

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22 Document Revision History

Table 76 provides a revision history for the MPC8640D hardware specification. Table 75. Document Revision History  Updated Section 6, “DDR and DDR2 SDRAM” to include 533 MHz. MPC8640D (dual core)” from Note 2 in Table 73 because MPC8640D is not offered at 1500 MHz core.  Added Note 8 to Figure 57 and Figure 58.

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