MC8610PX800GZ

MC8610TPX1066JB FREESCALE | Alldatasheet

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Technical content

Features

• High-performance, 32-bit e600 core, that implements the Power Architecture™ technology – Eleven execution units and three register files – Two separate 32-Kbyte instruction and data level 1 (L1) caches – Integrated 256-Kbyte, eight-way set-associative unified instruction and data level 2 (L2) cache with ECC – 36-bit real addressing – Multiprocessing support features – Power and thermal management  MPX coherency module (MCM)  Address translation and mapping units (A TMUs)  DDR/DDR2 memory controller – 64- or 32-bit data path (72-bit with ECC) – Up to 533-MHz DDR2 data rate and up to 400 MHz DDR data rate – Up to 16 Gbytes memory  Enhanced local bus controller (eLBC) – Operating at up to 133 MHz – Eight chip selects  Display interface unit – Maximum display resolution: 1280 ×1 0 2 4 – Maximum display refresh rate: 60 Hz – Display color depth: up to 24 bpp – Display interface: parallel TTL  OpenPIC-compliant programmable interrupt controller (PIC) – Supports 16 programmable interrupt and processor task priority levels – Supports 12 discrete external interrupts and 48 internal interrupts – Eight global high resolution timers/counters that can generate interrupts – Support for PCI Express message-shared interrupts (MSIs) D u a l I 2C controllers – Master or slave I 2C mode support – Boot sequencer – Optionally loads configuration data from serial ROM at reset via I2C interface – Can be used to initialize configuration registers and/or memory – Supports extended I 2C addressing mode  DUART  Fast InfraRed interface  Serial peripheral interface – Master or slave support  Dual integrated four-channel DMA controllers – All channels accessible by both local and remote masters – Supports transfers to or from any local memory or I/O port – Ability to start and flow control each DMA channel from external 3-pin interface  Watchdog timer  Dual global timer modules  32-bit PCI interface, 33 or 66 MHz bus frequency  Dual PCI Express® controllers – PCI Express 1.0a compatible – PCI Express controller 1 supports x1, x2, and x4 link widths; PCI Express controller 2 supports x1, x2, x4, and x8 link widths – 2.5 Gbaud, 2.0 Gbps lane  Device performance monitor – Supports eight 32-bit counters that count the occurrence of selected events – Ability to count up to 512 counter-specific events – Supports 64 reference events that can be counted on any of the 8 counters – Supports duration and quantity threshold counting – Burstiness feature that permits counting of burst events with a programmable time between bursts – Triggering and chaining capability – Ability to generate an interrupt on overflow  IEEE Std 1149.1™ compliant, JTAG boundary scan  Available as 783-pin, flip-chip, plastic ball grid array (FC-PBGA) MPC8610 Integrated Host Processor Hardware Specifications

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor2 Table of Contents 2.9 I

3.4 SerDes Block Power Supply Decoupling

4.1 Part Numbers Fully Addressed by This Document . . . 90 5.2 Mechanical Dimensions of the MPC8610 FC-PBGA. . 93

1 Pin Assignments and Reset States

Table 1 provides the pin assignments for the signals. Table 1. Signal Reference by Functional Block

Table 1. Signal Reference by Functional Block (continued)

1. Multi-pin signals such as LDP[0:3] have their physical package pin numbers listed in order corresponding to the signal names.
2. Stub series terminated logic type pins.
3. All SSI signals are multiplexed with eLBC signals.
4. Low voltage transistor-transistor logic (LVTTL) type pins.
5. The pins for the SSI interface on the device are multiplexed with certain eLBC signals, which have the ability to operate at a

correctly interface to other devices on the board at the proper voltage.

1. This pin should be pulled to ground with a 100- Ω resistor.
2. This pin should be pulled to ground with a 200- Ω resistor.
3. These pins should be left floating.

10.This is a SerDes PLL/DLL digital test signal and is only for factory use. 11.This is a SerDes PLL/DLL analog test signal and is only for factory use. 12.This pin should be pulled down if the platform frequency is 400 MHz or below. 13.This pin should be pulled down if the core frequency is 800 MHz or below. the value of the net at reset, then a pullup or active driver is needed. 16.These pins should be left floating. 17.Must be tied low if unused. 18.This output is actively driven during reset rather than being tri-stated during reset. resistor ± 1 Ω. These pins are used for automatic calibration of the DDR IOs. Configuration Signals section of this table for config name and connection details. 21.Recommend a weak pull-up resistor (1–10 k Ω) be placed from this pin to its power supply. 22.This multiplexed pin has input status in one mode and output in another. 23.This pin is a multiplexed signal for different functional blocks and appears more than once in this table. 24.For systems which boot from local bus (GPCM)-controlled flash, a pullup on LGPL4 is required. 25.This pin is open drain signal. DD for normal machine operation. 27.These JT AG pins have weak internal pull-up P-FETs that are always enabled.

Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 15

2 Electrical Characteristics

This section provides the AC and DC electrical specifications for the MPC8610. The MPC8610 is currently targeted to these specifications.

2.1 Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

2.1.1 Absolute Maximum Ratings

Table 2 provides the absolute maximum ratings. Table 2. Absolute Maximum Ratings 1

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

2.1.2 Recommended Operating Conditions

Table 3 provides the recommended operating conditions for the MPC8610. Note that the values in Table 3 are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. For details on order information and specific operating conditions for parts, see Section 4, “Ordering Information.” Storage temperature range T STG –55 to 150 °C Notes: 1 Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2 During run time (M, B, O)V IN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Ta ble 2. Table 3. Recommended Operating Conditions

1.8 V ± 90 mV

2.5 V ± 125 mV

Table 2. Absolute Maximum Ratings 1 (continued)

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 17 LCD, PCI, general timer, MPIC, IrDA, DUART , DMA, interrupts, system control and clocking, debug, test, JTAG, power management, I2C, SPI, and miscellaneous I/O voltage OVDD 3.3 V ± 165 mV V 6 Input voltage DDR and DDR2 SDRAM signals MV IN (GND – 0.3) to (GVDD +0 . 3 ) V 7, 5 DDR and DDR2 SDRAM reference MV REF (GND – 0.3) to (GVDD/2 + 0.3) V 7 Local Bus I/O voltage BV IN (GND – 0.3) to (BVDD +0 . 3 ) LCD, PCI, general purpose timer, MPIC, IrDA, DUART , DMA, interrupts, system control and clocking, debug, test, JT AG, power management, I 2C, SPI, and miscellaneous I/O voltage OVIN (GND – 0.3) to (OVDD +0 . 3 ) V 7, 6 Junction temperature range T J 0 to 105 °C –40 to 105 8 Notes: 1 Applies to devices marked with a core frequency of 1333 MHz. Refer to T able Part Numbering Nomenclature to determine if the device has been marked for a core frequency of 1333 MHz. 2 Applies to devices marked with a core frequency below 1333 MHz. Refer to T able Part Numbering Nomenclature to determine if the device has been marked for a core frequency below 1333 MHz. 3 AVDD measurements are made at the input of the R/C filter described in Section 3.2.1, “PLL Power Supply Filtering,” and not at the processor pin. Receiver (RX) Input Specifications,” for more information. 5 Caution: MVIN must meet the overshoot/undershoot requirements for GV DD as shown in Figure 2. 6 Caution: OVIN must meet the overshoot/undershoot requirements for OV DD as shown in Figure 2. 7 Timing limitations for (M, B, O) VIN and MVREF during regular run time is provided in Figure 2. 8 Applies to devices marked MC8610TxxyyyyMz for extended temperature range. Note that MC8610Txx1333Jz is not offered. Table 3. Recommended Operating Conditions (continued)

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8610. Figure 2. Overshoot/Undershoot Voltage for M/B/OV IN The MPC8610 core voltage must always be provided at nominal VDD_Core (see Table 3 for actual recommended core voltage). appropriate for the (SSTL-18 and SSTL-2) electrical signaling standards.

2.1.3 Output Driver Characteristics

Table 4 provides information on the characteristics of the output driver strengths. The values are preliminary estimates. Table 4. Output Drive Capability

1. tCLK references clocks for various functional blocks as follows:

For DDR, tCLK references MCK. For LBIU, tCLK references LCLK. For PCI, tCLK references PCI_CLK or SYSCLK. For I2C and JT AG, tCLK references SYSCLK.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 19

2.2 Power Sequencing

The MPC8610 requires its power rails to be applied in a specific sequence in order to ensure proper device operation. These requirements are as follows: The chronological order of power up is: 1. OV DD, BVDD 2. V DD_PLAT, A VDD_PLAT, VDD_Core, A VDD_Core, AVDD_PCI, SnVDD, XnVDD, SDnAVDD (this rail must reach 90% of its value before the rail for GV DD and MVREF reaches 10% of its value) 3. GV DD, MVREF 4. SYSCLK The order of power down is as follows: 1. SYSCLK 2. GV DD, MVREF 3. V DD_PLAT, A VDD_PLAT, VDD_Core, A VDD_Core, AVDD_PCI, SnVDD, XnVDD, SDnAVDD 4. O DD, BVDD NOTE AVDD type supplies should be delayed with respect to their source supplies by the RC time constant of the PLL filter circuit described in Section 3.2, “Power Supply Design and Sequencing.” Local bus 25 BVDD = 3.3 V BVDD = 2.5 V 45 (default) 45 (default) 125 BVDD = 3.3 V BVDD = 2.5 V BVDD = 1.8 V PCI, DUART , DMA, interrupts, system control and clocking, debug, test, JTAG, power management, and miscellaneous I/O voltage 45 OV DD = 3.3 V I2C 150 OV DD = 3.3 V PCI Express 100 XV DD = 1.0 V 3 Notes: 1. See the DDR control driver registers in the MPC8610 Integrated Host Processor Reference Manual, for more information. 2. See the POR impedance control register in the MPC8610 Integrated Host Processor Reference Manual, for more information about local bus signals and their drive strength programmability. 3. See Section 1, “Pin Assignments and Reset States,” for details on resistor requirements for the calibration of SDn_IMP_CAL_TX and SDn_IMP_CAL_RX transmit and receive signals. 4. Stub series terminated logic (SSTL-25) type pins. 5. Stub series terminated logic (SSTL-18) type pins. 6. The drive strength of the DDR interface in half strength mode is at T j = 105°C and at GVDD (min). Table 4. Output Drive Capability (continued)

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 21

2.3 Power Characteristics

The power dissipation for the MPC8610 device is shown in Table 5. The estimated maximum power dissipation for individual power supplies of the MPC8610 is shown in Table 6. Table 5. MPC8610 Power Dissipation

1. These values specify the power consumption at nominal voltage and apply to all valid processor bus frequencies and

configurations. The values do not include power dissipation for I/O supplies.

1. Typical power is an average value measured at the nominal recommended core voltage (V DD_Core) and 65°C junction

at 100% efficiency. This parameter is not 100% tested but periodically sampled.

1. Thermal power is the average power measured at nominal core voltage (V DD_Core) and maximum operating junction

and a typical workload on platform interfaces. This parameter is not 100% tested but periodically sampled.

1. Maximum power is the maximum power measured at nominal core voltage (V DD_Core) and maximum operating junction

instructions which keep all the execution units maximally busy on the core. Table 6. MPC8610 Individual Supply Maximum Power Dissipation 1

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

2.3.1 Frequency Derating

To reduce power consumption, these devices support frequency derating if the reduced maximum processor core frequency and reduced maximum platform frequency requirements are observed. The reduced maximum processor core frequency, resulting maximum platform frequency and power consumption are provided in Table 7. Only those parameters in Table 7 are affected; all other parameter specifications are unaffected.

2.4 Input Clocks

Table 8 provides the system clock (SYSCLK) DC specifications for the MPC8610. Platform PLL voltage supply AV DD_PLAT = 1.025 V @ 1333 MHz 0.0125 AVDD_PLA T = 1.00 V @ 1066 MHz 0.0125 Notes: 1. This is a maximum power supply number which is provided for power supply and board design information. The numbers are based on 100% utilization for each component. The components listed are not expected to have 100% usage simultaneously for all components. Actual numbers may vary based on activity. Note that the production parts should have a total maximum power value based on Table 5. The ‘Est.’ in the Est. Power column is to emphasize that these numbers are based on theoretical estimates. The device is tested to ensure that the sum of all four supplies does not exceed the power stated in Table 5. No specific supply should ever exceed its individual amount estimated in Ta ble 6. Table 7. Core Frequency, Platform Frequency and Power Consumption Derating Table 8. SYSCLK DC Electrical Characteristics (OV DD = 3.3 V ± 165 mV) 1 Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 2 and Table 3. Table 6. MPC8610 Individual Supply Maximum Power Dissipation 1 (continued)

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 23

2.4.1 System Clock Timing

Table 9 provides the system clock (SYSCLK) AC timing specifications for the MPC8610.

2.4.1.1 SYSCLK and Spread Spectrum Sources

Spread spectrum clock sources are a popular way to control electromagnetic interference emissions (EMI) by spreading the emitted noise over a wider spectrum and reducing the peak noise magnitude. These clock sources intentionally add long-term jitter in order to diffuse the EMI spectral content. The jitter specification given in Table 9 considers short-term (cycle-to-cycle) jitter only and the clock generator’s cycle-to-cycle output jitter should meet the MPC8610 input cycle-to-cycle jitter requirement. Frequency modulation and spread are separate concerns, and the MPC8610 is compatible with spread spectrum sources if the recommendations listed in Table 10 are observed. It is imperative to note that the processor’s minimum and maximum SYSCLK, core, and VCO frequencies must not be exceeded regardless of the type of clock source. Therefore, systems in which the processor is operated at its maximum rated e600 core frequency should avoid violating the stated limits by using down-spreading only. Table 9. SYSCLK AC Timing Specifications

1. Caution: The platform to SYSCLK clock ratio and e600 core to platform clock ratio settings must be chosen such that the

Clock PLL Ratio,” for ratio settings.

1. Rise and fall times for SYSCLK are measured at 0.4 and 2.7 V .
2. Timing is guaranteed by design and characterization.
3. This represents the short term jitter only and is guaranteed by design.
4. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to allow

Table 10. Spread Spectrum Clock Source Recommendations

1. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO frequencies, must meet the

minimum and maximum specifications given in Ta bl e 1 0.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 SDn_REF_CLK and SDn_REF_CLK was designed to work with a spread spectrum clock (+0 to 0.5% spreading at 30–33 kHz rate is allowed), assuming both ends have same reference clock. For better results use a source without significant unintended modulation.

2.4.2 Real Time Clock Timing

The RTC input is sampled by the platform clock. The output of the sampling latch is then used as an input to the counters of the PIC. There is no jitter specification. The minimum pulse width of the RTC signal should be greater than 2 × the period of the platform clock. That is, minimum clock high time is 2 × tMPX, and minimum clock low time is 2 × tMPX. There is no minimum RTC frequency; RTC may be grounded if not needed.

2.4.3 PCI/PCI-X Reference Clock Timing

When the PCI/PCI-X controller is configured for asynchronous operation, the reference clock for the PCI/PCI-X controller is not the SYSCLK input, but instead the PCI n_CLK. Table 11provides the PCI/PCI-X reference clock AC timing specifications for the MPC8610.

2.4.4 Platform Frequency Requirements for PCI-Express

The MPX platform clock frequency must be considered for proper operation of the high-speed PCI Express interface as described below. For proper PCI Express operation, the MPX clock frequency must be greater than or equal to:

527 MHz x (PCI-Express link width)

16 / (1 + cfg_net2_div) Note that at MPX = 333 - 400 MHz, cfg_net2_div = 0 and at MPX > 400 MHz, cfg_net2_div = 1. Therefore, when operating PCI Express in x8 link width, the MPX platform frequency must be 333-400 MHz with cfg_net2_div = 0 or greater than or equal to 527 MHz with cfg_net2_div = 1. Table 11. PCI

1. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V .
2. Timing is guaranteed by design and characterization.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 25

2.4.5 Other Input Clocks

For information on the input clocks of other functional blocks of the platform such as SerDes see the specific section of this document.

2.5 RESET Initialization

Table 12 describes the AC electrical specifications for the RESET initialization timing requirements of the MPC8610. Table 13 provides the PLL lock times.

2.6 DDR and DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8610. Note that DDR SDRAM is GVDD = 2.5 V and DDR2 SDRAM is GV DD = 1.8 V . Table 12. RESET Initialization Timing Specifications

1. SYSCLK is he primary clock input for the device.
2. This is related to HRESET

Table 13. PLL Lock Times

1. The PLL lock time for the e600 core PLL requires an additional 255 platform clock cycles.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

2.6.1 DDR SDRAM DC Electrical Characteristics

Table 14 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the MPC8610 when GVDD(typ) = 1.8 V . Table 15 provides the DDR capacitance when GV DD(typ) = 1.8 V . Table 16 provides the recommended operating conditions for the DDR SDRAM component(s) when GV DD(typ) = 2.5 V . Table 14. DDR2 SDRAM DC Electrical Characteristics for GV DD(typ) = 1.8 V

1. GVDD is expected to be within 50 mV of the DRAM GV DD at all times.
2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak

noise on MVREF may not exceed ±2% of the DC value.

1. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF. This rail should track variations in the DC level of MV REF.

1. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.

Table 15. DDR2 SDRAM Capacitance for GV DD(typ)=1.8 V Table 16. DDR SDRAM DC Electrical Characteristics for GV DD (typ) = 2.5 V

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 27 Table 17 provides the DDR capacitance when GV DD (typ)=2.5 V . Table 18 provides the current draw characteristics for MV REF.

2.6.2 DDR SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR/DDR2 SDRAM interface.

2.6.2.1 DDR SDRAM Input AC Timing Specifications

Table 19 provides the input AC timing specifications for the DDR2 SDRAM when GV DD(typ)=1.8 V . Output high current (VOUT = 1.95 V) I OH –16.2 — mA Output low current (VOUT = 0.35 V) I OL 16.2 — mA Notes: 1. GVDD is expected to be within 50 mV of the DRAM GV DD at all times. 2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MVREF may not exceed ±2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREF. This rail should track variations in the DC level of MV REF. 4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD. Table 17. DDR SDRAM Capacitance for GV DD (typ) = 2.5 V Table 18. Current Draw Characteristics for MV REF

1. The voltage regulator for MVREF must be able to supply up to 500 μA current.

Table 19. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface At recommended operating conditions. Table 16. DDR SDRAM DC Electrical Characteristics for GV DD (typ) = 2.5 V (continued)

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Table 20 provides the input AC timing specifications for the DDR SDRAM when GV DD(typ)=2.5 V . Table 21 provides the input AC timing specifications for the DDR SDRAM interface. Figure 4 shows the DDR SDRAM input timing for the MDQS to MDQ skew measurement (t DISKEW). Figure 4. DDR Input Timing Diagram for tDISKEW Table 20. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface At recommended operating conditions. Table 21. DDR SDRAM Input AC Timing Specifications At recommended operating conditions.

533 MHz

400 MHz

333 MHz

1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[ n] and any corresponding bit that

will be captured with MDQS[ n]. This should be subtracted from the total timing budget.

1. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t DISKEW.This can be
2. Maximum DDR1 frequency is 400 MHz.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 29

2.6.2.2 DDR SDRAM Output AC Timing Specifications

Table 22. DDR SDRAM Output AC Timing Specifications At recommended operating conditions.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 31 Figure 6 shows the DDR SDRAM output timing diagram. Figure 6. DDR SDRAM Output Timing Diagram Figure 7 provides the AC test load for the DDR bus. Figure 7. DDR AC Test Load

2.7 Local Bus

This section describes the DC and AC electrical specifications for the local bus interface of the MPC8610.

2.7.1 Local Bus DC Electrical Characteristics

Table 23 provides the DC electrical characteristics for the local bus interface operating at BV DD =3 . 3V . Table 23. Local Bus DC Electrical Characteristics (BV DD = 3.3 V)

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Table 24 provides the DC electrical characteristics for the local bus interface operating at BV DD =2 . 5VD C . Table 25 provides the DC electrical characteristics for the local bus interface operating at BV DD =1 . 8V .

2.7.2 Local Bus AC Electrical Specifications

Table 26 describes the general timing parameters of the local bus interface at BV DD = 3.3 V , 2.5 V and 1.8 V . For information about the frequency range of local bus see Section 3.1.1, “Clock Ranges.” Low-level output voltage (BVDD = min, IOL = 2 mA) V OL —0 . 2 V Note: 1. The symbol VIN, in this case, represents the BV IN symbol referenced in Table 2 and Table 3. Table 24. Local Bus DC Electrical Characteristics (BV DD = 2.5 V)

1. The symbol VIN, in this case, represents the BV IN symbol referenced in Table 2 and Ta bl e 3.

Table 25. Local Bus DC Electrical Characteristics (BV DD = 1.8 V)

1. The symbol VIN, in this case, represents the BV IN symbol referenced in Table 2 and Ta bl e 3.

Table 26. Local Bus Timing Parameters (BV DD = 3.3 V, 2.5 V and 1.8 V) Table 23. Local Bus DC Electrical Characteristics (BV DD = 3.3 V) (continued)

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Output signals are latched at the falling edge of LCLK and input signals are captured at the rising edge of LCLK, with the exception of the LGTA/LUPWAIT signal, which is captured at the falling edge of LCLK. Figure 9. Local Bus Signals

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 35 Figure 10. Local Bus Signals, GPCM/UPM/FCM Signals for LCRR[CLKDIV] = 2 (Clock Ratio of 4)

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Figure 11. Local Bus Signals, GPCM/UPM/FCM Signals for LCRR[CLKDIV] = 4 or 8 (Clock Ratio of 8 or 16)

2.8 Display Interface Unit

This section describes the DIU DC and AC electrical specifications.

2.8.1 DIU DC Electrical Characteristics

Table 27 provides the DIU DC electrical characteristics. Table 27. DIU DC Electrical Characteristics

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 37

2.8.2 DIU AC Timing Specifications

Figure 12 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and the data. All parameters shown in the diagram are programmable. This timing diagram corresponds to positive polarity of the DIU_CLK_OUT signal and active-high polarity of the DIU_ HSYNC, DIU_VSYNC, and DIU_DE signals. By default, all control signals and the display data are generated at the rising edge of the internal pixel clock, and the DIU_CLK_OUT output to drive the panel has the same polarity with the internal pixel clock. User can select the polarity of the DIU_HSYNC and DIU_VSYNC signal (via the SYN_POL register), whether active-high or active-low, the default is active-high. The DIU_DE signal is always active-high. Figure 12. TFT DIU/LCD Interface Timing Diagram—Horizontal Sync Pulse

1. The symbol VIN, in this case, represents the OVIN symbol referenced in Ta ble 2 and Ta ble 3.

Table 27. DIU DC Electrical Characteristics (continued)

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 39 The DELTA_X and DELTA_Y parameters are programmed via the DISP_SIZE register. The PW_H, BP_H, and FP_H parameters are programmed via the HSYN_PARA register; and the PW_V , BP_V , and FP_V parameters are programmed via the VSYN_PARA register. Figure 14 depicts the synchronous display interface timing for access level, and Table 29 lists the timing parameters. Figure 14. LCD Interface Timing Diagram—Access Level

2.9 I 2C

This section describes the DC and AC electrical characteristics for the I 2C interfaces of the MPC8610.

2.9.1 I 2C DC Electrical Characteristics

Table 30 provides the DC electrical characteristics for the I 2C interfaces. Table 29. LCD Interface Timing Parameters—Access Level Table 30. I2C DC Electrical Characteristics At recommended operating conditions with OVDD of 3.3 V ± 5%.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

2.9.2 I 2C AC Electrical Specifications

Table 31 provides the AC timing parameters for the I 2C interfaces. Input current each I/O pin (input voltage is between 0.1 × OVDD and 0.9 × OVDD(max) II –10 10 μA3 Capacitance for each I/O pin C I —1 0 p F Notes: 1. Output voltage (open drain or open collector) condition = 3 mA sink current. 2. Refer to the MPC8610 Integrated Host Processor Reference Manual , for information on the digital filter used. 3. I/O pins will obstruct the SDA and SCL lines if OV DD is switched off. Table 31. I2C AC Electrical Specifications All values refer to VIH (min) and VIL (max) levels (see Ta ble 30). Table 30. I2C DC Electrical Characteristics (continued) At recommended operating conditions with OVDD of 3.3 V ± 5%.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

2.10 DUART

This section describes the DC and AC electrical specifications for the DUART interface of the MPC8610.

2.10.1 DUART DC Electrical Characteristics

Table 32 provides the DC electrical characteristics for the DUART interface.

2.10.2 DUART AC Electrical Specifications

Table 33 provides the AC timing parameters for the DUART interface.

2.11 Fast/Serial Infrared Interfaces (FIRI/SIRI)

The fast/serial infrared interfaces (FIRI/SIRI) implements asynchronous infrared protocols (FIR, MIR, SIR) that are defined by IrDA (Infrared Data Association). Refer to http://www.IrDA.org for details on FIR and SIR protocols.

2.12 Synchronous Serial Interface (SSI)

This section describes the DC and AC electrical specifications for the SSI interface of the MPC8610.

2.12.1 SSI DC Electrical Characteristics

Table 34 provides SSI DC electrical characteristics. Table 32. DUART DC Electrical Characteristics

1. The symbol VIN, in this case, represents the OVIN symbol referenced in Ta ble 2 and Ta ble 3.

Table 33. DUART AC Timing Specifications

1. Actual attainable baud rate will be limited by the latency of interrupt processing.
2. The middle of a start bit is detected as the 8

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 43

2.12.2 SSI AC Timing Specifications

All timings for the SSI are given for a noninverted serial clock polarity (TSCKP/RSCKP = 0) and a noninverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the following tables and figures. For internal frame sync operation using external clock, the FS timing will be same as that of Tx Data.

2.12.2.1 SSI Transmitter Timing with Internal Clock

Table 35 provides the transmitter timing parameters with internal clock. Table 34. SSI DC Electrical Characteristics (3.3 V DC)

1. The symbol BVIN, in this case, represents the BV IN symbol referenced in Table 2 and Table 3.

Table 35. SSI Transmitter with Internal Clock Timing Parameters

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 45

2.12.2.2 SSI Receiver Timing with Internal Clock

Table 36 provides the receiver timing parameters with internal clock. Figure 18 provides the SSI receiver timing with internal clock. Figure 18. SSI Receiver with Internal Clock Timing Diagram

2.12.2.3 SSI Transmitter Timing with External Clock

Table 37 provides the transmitter timing parameters with external clock. Table 36. SSI Receiver with Internal Clock Timing Parameters Table 37. SSI Transmitter with External Clock Timing Parameters

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 47

2.12.2.4 SSI Receiver Timing with External Clock

Table 38 provides the receiver timing parameters with external clock. Figure 20 provides the SSI receiver timing with external clock. Figure 20. SSI Receiver with External Clock Timing Diagram Table 38. SSI Receiver with External Clock Timing Parameters

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

2.13 Global Timer Module

This section describes the DC and AC electrical specifications for the global timer module (GTM) of the MPC8610.

2.13.1 GTM DC Electrical Characteristics

Table 39 provides the DC electrical characteristics for the MPC8610 global timer module pins, including GTM n_TINn, GTMn_TOUTn, GTMn_TGA TEn, and RTC.

2.13.2 GTM AC Timing Specifications

Table 40 provides the GTM input and output AC timing specifications. Figure 21 provides the AC test load for the GTM. Figure 21. GTM AC Test Load Table 39. GTM DC Electrical Characteristics

1. The symbol VIN, in this case, represents the OVIN symbol referenced in Ta ble 2 and Ta ble 3.

Table 40. GTM Input and Output AC Timing Specification 1

1. Input specifications are measured from the 50 percent level of the signal to the 50 percent level of the rising edge of CLKIN.

Timings are measured at the pin.

1. Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by external

synchronous logic. Timer inputs are required to be valid for at least t GTIWID ns to ensure proper operation.

1. The minimum pulse width is a function of the MPX/platform clock. The minimum pulse width must be greater than or equal

to 4 times the MPX/platform clock period.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 49

2.14 GPIO

This section describes the DC and AC electrical specifications for the GPIO of the MPC8610.

2.14.1 GPIO DC Electrical Characteristics

Table 41 provides the DC electrical characteristics for the GPIO.

2.14.2 GPIO AC Timing Specifications

Table 42 provides the GPIO input and output AC timing specifications. Figure 22 provides the AC test load for the GPIO. Figure 22. GPIO AC Test Load Table 41. GPIO DC Electrical Characteristics

1. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 2 and Table 3.

Table 42. GPIO Input and Output AC Timing Specifications 1

1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are
2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any

external synchronous logic. GPIO inputs are required to be valid for at least t PIWID ns to ensure proper operation.

1. The minimum pulse width is a function of the MPX/platform clock. The minimum pulse width must be greater than or equal

to 4 times the MPX/platform clock period.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

2.15 Serial Peripheral Interface (SPI)

This section describes the DC and AC electrical specifications for the SPI interface of the MPC8610.

2.15.1 SPI DC Electrical Characteristics

Table 43 provides the SPI DC electrical characteristics.

2.15.2 SPI AC Timing Specifications

Table 44 provides the SPI input and output AC timing specifications. Table 43. SPI DC Electrical Characteristics

1. The symbol VIN, in this case, represents the OVIN symbol referenced in Ta ble 2 and Ta ble 3.

Table 44. SPI AC Timing Specifications 1

1. Output specifications are measured from the 50 percent level of the rising edge of CLKIN to the 50 percent level of the signal.

Timings are measured at the pin.

1. The symbols for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for inputs

(NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

2.16 PCI Interface

This section describes the DC and AC electrical specifications for the PCI bus interface.

2.16.1 PCI DC Electrical Characteristics

Table 45 provides the DC electrical characteristics for the PCI interface.

2.16.2 PCI AC Electrical Specifications

This section describes the general AC timing parameters of the PCI bus. Note that the SYSCLK signal is used as the PCI input clock. Table 46 provides the PCI AC timing specifications at 66 MHz. Table 45. PCI DC Electrical Characteristics 1

1. Ranges listed do not meet the full range of the DC specifications of the PCI 2.2 Local Bus Specifications .
2. The symbol VIN, in this case, represents the OVIN symbol referenced in Ta ble 2 and Ta ble 3.

Table 46. PCI AC Timing Specifications at 66 MHz

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Figure 28 shows the PCI output AC timing conditions. Figure 28. PCI Output AC Timing Measurement Condition

2.17 High-Speed Serial Interfaces (HSSI)

for PCI Express (x1/x2/x4/x8) data transfers. reference clocks. The SerDes data lane’s transmitter and receiver reference circuits are also shown.

2.17.1 Signal Terms Definition

and specification of differential signals. signal swings between A volts and B volts where A > B. transmitter and receiver operate in a fully symmetrical differential signaling environment. peak-to-peak swing of A – B volts. This is also referred as each signal wire’s single-ended swing.

1. Differential output voltage, VOD (or differential output swing):

output voltages: VSDn_TX – VSDn_TX. The VOD value can be either positive or negative.

1. Differential input voltage, V ID (or differential input swing):

input voltages: VSDn_RX –V SDn_RX. The VID value can be either positive or negative.

1. Differential peak voltage, V DIFFp

differential peak voltage, V DIFFp = |A – B| volts.

1. Differential peak-to-peak, V DIFFp-p

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 55 of differential swing in amplitude, or twice of the differential peak. For example, the output differential peak-peak voltage can also be calculated as V TX-DIFFp-p = 2 * |VOD|. 6. Differential waveform The differential waveform is constructed by subtracting the inverting signal (SD n_TX, for example) from the noninverting signal (SD n_TX, for example) within a differential pair. There is only one signal trace curve in a differential waveform. The voltage represented in the differential waveform is not referenced to ground. Refer to Figure 38 as an example for differential waveform. 7. Common mode voltage, V cm The common mode voltage is equal to one half of the sum of the voltages between each conductor of a balanced interchange circuit and ground. In this example, for SerDes output, V cm_out = (VSDn_TX + VSDn_TX)/2 = (A + B)/2, which is the arithmetic mean of the two complimentary output voltages within a differential pair. In a system, the common mode voltage may often differ from one component’s output to the other’s input. Sometimes, it may be even different between the receiver input and driver output circuits within the same component. It’s also referred as the DC offset in some occasion. Figure 29. Differential Voltage Definitions for Transmitter or Receiver (VDIFFp) is 500 mV . The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.

2.17.2 SerDes Reference Clocks

The following sections describe the SerDes reference clock requirements and some application information.

2.17.2.1 SerDes Reference Clock Receiver Characteristics

Figure 30 shows a receiver reference diagram of the SerDes reference clocks.  The supply voltage requirements for X nVDD are specified in Table 2 and Table 3.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2  SerDes reference clock receiver reference circuit structure —T h e S D n_REF_CLK and SD n_REF_CLK are internally AC-coupled differential inputs as shown in Figure 30. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a 50-Ω termination to SGND followed by on-chip AC-coupling. — The external reference clock driver must be able to drive this termination. — The SerDes reference clock input can be either differential or single-ended. Refer to the differential mode and single-ended mode description below for further detailed requirements.  The maximum average current requirement that also determines the common mode voltage range — When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 mA (refer to the following bullet for more detail), since the input is AC-coupled on-chip. — This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V/50 = 8 mA) while the minimum common mode input level is 0.1 V above SGND. For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0 to 16 mA (0–0.8 V), such that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode voltage at 400 mV . — If the device driving the SD n_REF_CLK and SD n_REF_CLK inputs cannot drive 50 Ω to SGND DC, or it exceeds the maximum input current limitations, then it must be AC-coupled off-chip.  The input amplitude requirement — This requirement is described in detail in the following sections. Figure 30. Receiver of SerDes Reference Clocks

2.17.2.2 DC Level Requirement for SerDes Reference Clocks

to connect the clock driver chip and SerDes reference clock inputs as described below. DC-coupled connection scheme.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

2.17.2.3 Interfacing With Other Differential Signaling Levels

 With on-chip termination to SGND, the differential reference clocks inputs are HCSL (high-speed current steering logic) compatible DC-coupled.  Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can be used but may need to be AC-coupled due to the limited common mode input range allowed (100 to 400 mV) for DC-coupled connection.  LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to AC-coupling. NOTE Figure 34 to Figure 37 are for conceptual reference only. Due to the fact that clock driver chip's internal structure, output impedance and termination requirements are different between various clock driver chip manufacturers, it is very possible that the clock circuit reference designs provided by clock driver chip vendor are different from what is shown below. They might also vary from one vendor to the other. Therefore, Freescale Semiconductor can neither provide the optimal clock driver reference circuits nor guarantee the correctness of the following clock driver connection reference circuits. The system designer is recommended to contact the selected clock driver chip vendor for the optimal reference circuits with the MPC8610 SerDes reference clock receiver requirement provided in this document. Figure 34 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It assumes that the DC levels of the clock driver chip is compatible with MPC8610 SerDes reference clock input’s DC requirement. Figure 34. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only) output impedance is about 16 Ω.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Figure 37 shows the SerDes reference clock connection reference circuits for a single-ended clock driver. It assumes the DC levels of the clock driver are compatible with MPC8610 SerDes reference clock input’s DC requirement. Figure 37. Single-Ended Connection (Reference Only)

2.17.2.4 AC Requirements for SerDes Reference Clocks

driver should be 50 Ω to match the transmission line and reduce reflections which are a source of noise to the system. Table 47 describes some AC parameters common to PCI Express protocols. Table 47. SerDes Reference Clock Common AC Parameters At recommended operating conditions with X1V DD or X2VDD = 1.0 V ± 5% and 1.025 V ± 5%. output impedance is about 16 Ω.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

2.17.3 SerDes Transmitter and Receiver Reference Circuits

Figure 40 shows the reference circuits for SerDes data lane’s transmitter and receiver. Figure 40. SerDes Transmitter and Receiver Reference Circuits in specification of each protocol section.

2.18 PCI Express

This section describes the DC and AC electrical specifications for the PCI Express bus of the MPC8610.

2.18.1 DC Requirements for PCI Express SD n_REF_CLK and

2.18.2 AC Requirements for PCI Express SerDes Clocks

Table 48 lists AC requirements.

2.18.3 Clocking Dependencies

times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance. Table 48. SDn_REF_CLK and SDn_REF_CLK AC Requirements

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 63

2.18.4 Physical Layer Specifications

The following is a summary of the specifications for the physical layer of PCI Express on this device. For further details as well as the specifications of the transport and data link layer, use the PCI Express Base Specification, Rev. 1.0a.

2.18.4.1 Differential Transmitter (TX) Output

Table 49 defines the specifications for the differential output at all transmitters (TXs). The parameters are specified at the component pins. Table 49. Differential Transmitter (TX) Output Specifications

0.70 UI The maximum transmitter jitter can be derived as

TTX-MAX-JITTER = 1 – TTX-EYE= 0.3 UI.

0.15 UI Jitter is defined as the measurement variation of the

0.125 UI See Notes 2 and 5

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 VTX-IDLE-DIFFp Electrical idle differential peak output voltage 02 0 m V V TX-IDLE-DIFFp = |VTX-IDLE-D+ –V TX-IDLE-D-| <= 20 mV See Note 2 VTX-RCV-DETECT The amount of voltage change allowed during receiver detection 600 mV The total amount of voltage change that a transmitter can apply to sense whether a low impedance receiver is present. See Note 6 V TX-DC-CM The TX DC common mode voltage 0 3.6 V The allowed DC common mode voltage under any conditions. See Note 6 ITX-SHORT TX short circuit current limit 90 mA The total current the transmitter can provide when shorted to its ground TTX-IDLE-MIN Minimum time spent in electrical idle

50 UI Minimum time a transmitter must be in electrical idle

utilized by the receiver to start looking for an electrical idle exit after successfully receiving an electrical idle ordered set T TX-IDLE-SET -TO-IDLE Maximum time to transition to a valid electrical idle after sending an electrical idle ordered set

20 UI After sending an electrical idle ordered set, the

transmitter must meet all electrical idle specifications within this time. This is considered a debounce time for the transmitter to meet electrical idle after transitioning from LO. T TX-IDLE-TO-DIFF-DA TA Maximum time to transition to valid TX specifications after leaving an electrical idle condition

20 UI Maximum time to meet all TX specifications when

transitioning from electrical idle to sending differential data. This is considered a debounce time for the TX to meet all TX specifications after leaving electrical idle RL TX-DIFF Differential return loss 12 dB Measured over 50 MHz to 1.25 GHz. See Note 4 RLTX-CM Common mode return loss 6 dB Measured over 50 MHz to 1.25 GHz. See Note 4 ZTX-DIFF-DC DC differential TX impedance 80 100 120 Ω TX DC differential mode low impedance ZTX-DC T ransmitter DC impedance 40 Ω Required TX D+ as well as D- DC Impedance during all states LTX-SKEW Lane-to-lane output skew 500 + 2 UI ps Static skew between any two transmitter lanes within a single link CTX AC coupling capacitor 75 200 nF All transmitters shall be AC-coupled. The AC coupling is required either within the media or within the transmitting component itself. Table 49. Differential Transmitter (TX) Output Specifications (continued)

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 65

2.18.4.2 Transmitter Compliance Eye Diagrams

The TX eye diagram in Figure 41 is specified using the passive compliance/test measurement load (see Figure 43) in place of any real PCI Express interconnect + RX component. There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in time using the jitter median to locate the center of the eye diagram. The different eye diagrams will differ in voltage depending whether it is a transition bit or a de-emphasized bit. The exact reduced voltage level of the de-emphasized bit will always be relative to the transition bit. The eye diagram must be valid for any 250 consecutive UIs. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI. NOTE It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function (i.e., least squares and median deviation fits). Tcrosslink Crosslink random timeout 0 1 ms This random timeout helps resolve conflicts in crosslink configuration by eventually resulting in only one downstream and one upstream port. See Note 7 Notes: 1.) No test load is necessarily associated with this value. 2.) Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 43 and measured over any 250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 41.) 3.) A T TX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of T TX-JITTER-MAX = 0.30 UI for the transmitter collected over any 250 consecutive TX UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. 4.) The transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss measurements is 50 Ω to ground for both the D+ and D– line (that is, as measured by a vector network analyzer with 50-Ω probes—see Figure 43). Note that the series capacitors C TX is optional for the return loss measurement. 5.) Measured between 20–80% at transmitter package pins into a test load as shown in Figure 43 for both VTX-D+ and VTX-D–.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Figure 41. Minimum Transmitter Timing and Voltage Output Compliance Specifications

2.18.4.3 Differential Receiver (RX) Input Specifications

Table 50. Differential Receiver (RX) Input Specifications Spread Spectrum Clock dictated variations.

0.4 UI The maximum interconnect media and transmitter

RX-MAX-JITTER = 1 – TRX-EYE= 0.6 UI.

0.3 UI Jitter is defined as the measurement variation of the

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 67 VRX-CM-ACp AC peak common mode input voltage 150 mV V RX-CM-ACp = |VRXD+ – VRXD-|/2 – VRX-CM-DC VRX-CM-DC = DC(avg) of |VRX-D+ – VRX-D-|/2 See Note 2 RLRX-DIFF Differential return loss 15 dB Measured over 50 MHz to 1.25 GHz with the D+ and D– lines biased at +300 and –300 mV, respectively. See Note 4 RL RX-CM Common mode return loss 6 dB Measured over 50 MHz to 1.25 GHz with the D+ and D– lines biased at 0 V . See Note 4 ZRX-DIFF-DC DC differential input impedance 80 100 120 Ω RX DC differential mode impedance. See Note 5 ZRX-DC DC input impedance 40 50 60 Ω Required RX D+ as well as D– DC impedance (50 ± 20% tolerance). See Notes 2 and 5 ZRX-HIGH-IMP-DC Powered down DC input impedance 200 k Ω Required RX D+ as well as D– DC Impedance when the receiver terminations do not have power. See Note 6 V RX-IDLE-DET-DIFFp-p Electrical idle detect threshold 65 175 mV V RX-IDLE-DET-DIFFp-p = 2*|VRX-D+ – VRX-D–| Measured at the package pins of the receiver TRX-IDLE-DET -DIFF- ENTERTIME Unexpected electrical idle enter detect threshold integration time 10 ms An unexpected Electrical Idle (V RX-DIFFp-p < VRX-IDLE-DET-DIFFp-p) must be recognized no longer than TRX-IDLE-DET-DIFF-ENTERING to signal an unexpected idle condition. Table 50. Differential Receiver (RX) Input Specifications (continued)

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

2.18.5 Receiver Compliance Eye Diagrams

The RX eye diagram in Figure 42 is specified using the passive compliance/test measurement load (see Figure 43) in place of any real PCI Express RX component. Note: In general, the minimum receiver eye diagram measured with the compliance/test measurement load (see Figure 43) will be larger than the minimum receiver eye diagram measured over a range of systems at the input receiver of any real PCI Express component. The degraded eye diagram at the input receiver is due to traces internal to the package as well as silicon parasitic characteristics which cause the real PCI Express component to vary in impedance from the compliance/test measurement load. The input receiver eye diagram is implementation specific and is not specified. RX component designer should provide additional margin to adequately compensate for the degraded minimum receiver eye diagram (shown in Figure 42) expected at the input receiver based on some adequate combination of system simulations and the return loss measured looking into the RX package and silicon. The RX eye diagram must be aligned in time using the jitter median to locate the center of the eye diagram. The eye diagram must be valid for any 250 consecutive UIs. A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX UI. LTX-SKEW T otal skew 20 ns Skew across all lanes on a link. This includes variation in the length of SKP ordered set (e.g., COM and one to five symbols) at the RX as well as any delay differences arising from the interconnect itself. Notes: 1.)No test load is necessarily associated with this value. 2.)Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 43 should be used as the RX device when taking measurements (also refer to the receiver compliance eye diagram shown in Figure 42). If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram. 3.)A T RX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram. 4.)The receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line bias ed to 300 mV and the D– line biased to –300 mV and a common mode return loss greater than or equal to 6 dB (no bias required) over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The reference impedance for return loss measurements for is 50 Ω to ground for both the D+ and D– line (that is, as measured by a Vector Network Analyzer with 50-Ω probes—see Figure 43). Note that the series capacitors CTX is optional for the return loss measurement. 5.)Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM) there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port. 6.)The RX DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps ensure that the receiver detect circuit will not falsely assume a receiver is powered on when it is not. This term must be measured at 300 mV above the RX ground. 7.)It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated data.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 69 NOTE The reference impedance for return loss measurements is 50 Ω to ground for both the D+ and D– line (i.e., as measured by a vector network analyzer with 50- Ω probes—see Figure 43). Note that the series capacitors, CTX, are optional for the return loss measurement. Figure 42. Minimum Receiver Eye Timing and Voltage Compliance Specification

2.18.5.1 Compliance Test and Measurement Load

pins, into a test/measurement load shown in Figure 43. exactly matched in length at the package pin boundary. Figure 43. Compliance Test/Measurement Load

2.19 JTAG

This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the MPC8610.

2.19.1 JTAG DC Electrical Characteristics

Table 51 provides the JTAG DC electrical characteristics for the JTAG interface.

0.4 UI = TRX-EYE-MIN

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

2.19.2 JTAG AC Electrical Specifications

Table 52 provides the JTAG AC timing specifications as defined in Figure 45 through Figure 47. Table 51. JTAG DC Electrical Characteristics

1. The symbol VIN, in this case, represents the OVIN symbol referenced in Ta ble 2 and Ta ble 3.

Table 52. JTAG AC Timing Specifications (Independent of SYSCLK) 1 At recommended operating conditions (see Ta ble 3).

Figure 47 provides the boundary-scan timing diagram. Figure 47. Boundary-Scan Timing Diagram

3 Hardware Design Considerations

This section provides electrical and thermal design recommendations for successful application of the MPC8610.

3.1 System Clocking

1. The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio
2. The e600 core PLL generates the core clock from the platform clock. The frequency ratio between the e600 core
3. The PCI PLL generates the clocking for the PCI bus
4. Each of the two SerDes blocks has a PLL.

3.1.1 Clock Ranges

Table 53 provides the clocking specifications for the processor core. Table 54 provides the clocking specifications for the memory bus. Table 55 provides the clocking specifications for the local bus. Table 53. Processor Core Clocking Specifications

1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting

MPX/Platform Clock PLL Ratio,” for ratio settings.

1. The minimum e600 core frequency is based on the minimum platform clock frequency of 333 MHz.
2. The reset config pin cfg_core_speed must be pulled low if the core frequency is 800 MHz or below.

Table 54. Memory Bus Clocking Specifications

1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting
2. The memory bus clock speed is half the DDR/DDR2 data rate, hence, half the MPX clock frequency.

Table 55. Local Bus Clocking Specifications

1. The local bus clock speed on LCLK[0:2] is determined by the MPX clock divided by the local bus ratio programmed in

LCRR[CLKDIV]. Refer to the MPC8610 Integrated Host Processor Reference Manual, for more information.

Table 56 provides the clocking specifications for the Platform/MPX bus. Table 56. Platform/MPX Bus Clocking Specifications

3.1.2 Platform/MPX to SYSCLK PLL Ratio

platform frequency, since the platform frequency must equal the DDR data rate. For specifications on the PCI_CLK, refer to the PCI 2.2 Specification.

1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting
2. For MPX clock frequencies at 400 MHz and below, cfg_net2_div must be pulled low.

Table 57. Platform/SYSCLK Clock Ratios

LGPL2/LOE/LFRE, DIU_LD4 (cfg_core_pll[0:3]–reset config) signals at power up. Table 58 describes the supported ratios. Note that cfg_core_speed must be pulled low if the core frequency is 800 MHz or below.

3.1.4 Frequency Options

3.1.4.1 SYSCLK and Platform Frequency Options

Table 59 shows the expected frequency options for SYSCLK and platform frequencies. Table 58. e600 Core/Platform Clock Ratios Table 59. SYSCLK and Platform Frequency Options

1 Platform/MPX Frequency values are shown rounded down to the nearest

3.2 Power Supply Design and Sequencing

3.2.1 PLL Power Supply Filtering

will be derived directly from V DD through a low frequency filter scheme such as the following. opportunity to cause noise injection from one PLL to the other is reduced. capacitors of equal value are recommended over a single large value capacitor. 783 FC-PBGA the footprint, without the inductance of vias. Figure 48 shows the filter circuit for the platform PLL power supplies (A VDD_PLAT). Figure 48. MPC8610 PLL Power Supply Filter Circuit (for Platform) Figure 49 shows the filter circuit for the core PLL power supply (A VDD_Core). Figure 49. MPC8610 PLL Power Supply Filter Circuit (for Core) Figure 50. SerDes PLL Power Supply Filter

1. An 0805 sized capacitor is recommended for system initial bring-up.

Hardware Design Considerations MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 77 Note the following: S D nAVDD should be a filtered version of SV DD.  Signals on the SerDes interface are fed from the SV DD power plane.

3.3 Decoupling Recommendations

Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC8610 system, and the device itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each V DD, BVDD, OVDD, GVDD, VDD_Core, and VDD_PLA T pin of the device. These decoupling capacitors should receive their power from separate V DD, BVDD, OVDD, GVDD, VDD_Core, VDD_PLA T, and GND power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly under the device using a standard escape pattern. Others may surround the part. These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, BVDD, OVDD, GVDD, VDD_Core, and VDD_PLA T planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (A VX TPS tantalum or Sanyo OSCON).

3.4 SerDes Block Power Supply Decoupling Recommendations

The SerDes block requires a clean, tightly regulated source of power (S nVDD and XnVDD) to ensure low jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is outlined below. Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections from all capacitors to power and ground should be done with multiple vias to further reduce inductance.  First, the board should have at least 10 x 10-nF SMT ceramic chip capacitors as close as possible to the supply balls of the device. Where the board has blind vias, these capacitors should be placed directly below the chip supply and ground connections. Where the board does not have blind vias, these capacitors should be placed in a ring around the device as close to the supply and ground connections as possible.  Second, there should be a 1-µF ceramic chip capacitor on each side of the device. This should be done for all SerDes supplies.  Third, between the device and any SerDes voltage regulator there should be a 10-µF, low equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-µF, low ESR SMT tantalum chip capacitor. This should be done for all SerDes supplies.

3.5 Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. All unused active low inputs should be tied to VDD, BVDD, OVDD, GVDD, VDD_Core, VDD_PLAT, XnVDD, and SnVDD as required. All unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external V DD, BVDD, OVDD, GVDD, VDD_Core, VDD_PLAT, XnVDD, SnVDD, and GND pins of the device. Special cases:  Local Bus—If parity is not used, tie LDP[0:3] to ground via a 4.7-k Ω resistor, tie LPBSE to OVDD via a 4.7-kΩ resistor (pull-up resistor). For systems which boot from local bus (GPCM)-controlled Flash, a pull up on LGPL4 is required.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Hardware Design Considerations Freescale Semiconductor78  SerDes—Receiver lanes configured for PCI Express are allowed to be disconnected (as would occur when a PCI Express slot is connected but not populated). Directions for terminating the SerDes signals is discussed in Section 3.10, “Guidelines for High-Speed Interface Termination.”

3.6 Pull-Up and Pull-Down Resistor Requirements

The MPC8610 requires weak pull-up resistors (2–10 k Ω is recommended) on open drain type pins including I 2C pins and PIC interrupt pins. Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 53. Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavior and spurious assertion will give unpredictable results. Refer to the PCI 2.2 specification for all pull-ups required for PCI. The following pins must not be pulled down during power-on reset: DIU_LD[5:6], MSRCID[1:2], HRESET_REQ , and TRIG_OUT/READY . The following are factory test pins and require strong pull up resistors (100 Ω – 1 kΩ) to OVDD: LSSD_MODE, TEST_MODE[0:3]. The following pins require weak pull-up resistors (2–10 kΩ) to their specific power supplies: LCS[0:4], LCS[5]/DMA_DREQ2, LCS[6]/DMA_DACK[2], LCS[7]/DMA_DDONE [2], IRQ_OUT, IIC1_SDA, IIC1_SCL, IIC2_SDA, IIC2_SCL, and CKSTP_OUT. The following pins should be pulled to ground with a 100-Ω resistor: SD1_IMP_CAL_TX, SD2_IMP_CAL_TX. The following pins should be pulled to ground with a 200- Ω resistor: SD1_IMP_CAL_RX, SD2_IMP_CAL_RX. When the platform frequency is 400 MHz, cfg_platform_freq must be pulled down at reset. Also, cfg_dram_type[0 or 1] must be valid at power-up even before HRESET assertion. For other pin pull-up or pull-down recommendations of signals, see Section 1, “Pin Assignments and Reset States.”

3.7 Output Buffer DC Impedance

The MPC8610 drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I 2C). To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OV DD or GND. Then, the value of each resistor is varied until the pad voltage is OV DD/2 (see Figure 51). The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and

are designed to be close to each other in value. Then, Z 0 = (RP + RN)/2. Figure 51. Driver Impedance Measurement

3.8 Configuration Pin Muxing

output only pins in normal operation. resistor should minimize the disruption of signal quality or speed for output pins thus configured. The platform PLL ratio and e600 core PLL ratio configuration pins are not equipped with these default pull-up devices. Table 60. Impedance Characteristics Note: Nominal supply voltages. See Ta ble 3, Tj = 105°C.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Hardware Design Considerations Freescale Semiconductor80

3.9 JTAG Configuration Signals

Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 53. Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most have asynchronous behavior and spurious assertion will give unpredictable results. Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1 specification, but is provided on all processors that implement the Power Architecture technology. The device requires TRST to be asserted during reset conditions to ensure the JTAG boundary logic does not interfere with normal chip operation. While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset. Because the JTAG interface is also used for accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not practical. The COP function of these processors allows a remote computer system (typically a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP port connects primarily through the JTAG interface of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 52 allows the COP port to independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well. The COP interface has a standard header, shown in Figure 52, for connection to the target system, and is based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector key. The COP header adds many benefits such as breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features. An inexpensive option can be to leave the COP header unpopulated until needed. There is no standardized way to number the COP header shown in Figure 53; consequently, many different pin numbers have been observed from emulator vendors. Some are numbered top-to-b ottom then left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in Figure 53 is common to all known emulators.

3.9.1 Termination of Unused Signals

If the JTAG interface and COP header will not be used, Freescale recommends the following connections: T R S T should be tied to HRESET through a 0-kΩ isolation resistor so that it is asserted when the system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during the power-on reset flow. Freescale recommends that the COP header be designed into the system as shown in Figure 53. If this is not possible, the isolation resistor will allow future access to TRST in case a JTAG interface may need to be wired onto the system in future debug situations. T i e T C K t o O VDD through a 10-kΩ resistor. This will prevent TCK from changing state and reading incorrect data into the device.  No connection is required for TDI, TMS, or TDO.

Figure 52. COP Connector Physical Pinout

Figure 53. JTAG Interface Connection

1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented.

Connect pin 5 of the COP header to OV DD with a 10-kΩ pull-up resistor.

1. Key location; pin 14 is not physically present on the COP header.

3.10 Guidelines for High-Speed Interface Termination

3.10.1 SerDes Interface

scenarios for a SerDes port. The termination recommendations must be followed for each port. Table 61. SerDes Port Enabled/Disabled Configurations mode, termination is required on the unused pins. both POR input and DEVDISR. See Note 1 for more information.

3.11 Guidelines for PCI Interface Termination

PCI termination if PCI is not used at all. PCI_AD[31:0], PCI_C/BE [3:0], and PCI_PAR signals. — All PCI control pins can be grouped together and tied to OV DD through a single 10-k Ω resistor. — It is optional to disable PCI block through DEVDISR register after POR reset. — It is optional to disable PCI block through DEVDISR register after POR reset.

3.12 Thermal

This section describes the thermal specifications of the MPC8610.

3.12.1 Thermal Characteristics

Table 62 provides the package thermal characteristics for the MPC8610.

3.12.2 Thermal Management Information

detect excessive temperature conditions and alert the system; see Section 3.12.2.5, “Temperature Diode,” for more information. Table 62. Package Thermal Characteristics

1. Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets JEDEC

specification for this package.

1. Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for
2. Junction-to-case resistance is less than 0.1°C/W because the silicon die is the top of the packaging case..

to soldered hooks or to a plastic backing structure. Screw and spring arrangements are also frequently used. Figure 54. FC-PBGA Package Exploded Cross-Sectional View with Several Heat Sink Options

60 Alhambra Road, Suite 1

671 East Brokaw Road

velocity, spatial volume, mass, attachment method, assembly, and cost.

3.12.2.1 Internal Package Conduction Resistance

Figure 55 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. Figure 55. C4 Package with Heat Sink Mounted to a Printed-Circuit Board

3.12.2.2 Thermal Interface Materials

A thermal interface material is recommended at the package-to-heat sink interface to minimize the thermal contact resistance.

Often, heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see Figure 54). Therefore, synthetic grease offers the best thermal performance, considering the low interface pressure, and is recommended. manufacturability, service temperature, dielectric properties, cost, and so on. Figure 56. Thermal Performance of Select Thermal Interface Material

18930 West 78

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Hardware Design Considerations Freescale Semiconductor88 Thermagon Inc. 888-246-9050 4707 Detroit Ave. Cleveland, OH 44102 Internet: www.thermagon.com

3.12.2.3 Heat Sink Selection Example

This section provides a heat sink selection example using one of the commercially available heat sinks. For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: Tj = Ti + Tr + (RθJC + Rθint + Rθsa) × Pd where: Tj is the die-junction temperature Ti is the inlet cabinet ambient temperature Tr is the air temperature rise within the computer cabinet RθJC is the junction-to-case thermal resistance Rθint is the adhesive or interface material thermal resistance Rθsa is the heat sink base-to-ambient thermal resistance Pd is the power dissipated by the device During operation, the die-junction temperatures (T j) should be maintained less than the value specified in Table 3. The temperature of air cooling the component greatly depends on the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (T i) may range from 30° to 40°C. The air temperature rise within a cabinet (Tr) may be in the range of 5 ° to 10°C. The thermal resistance of the thermal interface material (R θint) is typically about 0.2°C/W. For example, assuming a Ti of 30°C, a Tr of 5°C, a package RθJC = 0.1, and a typical power consumption (Pd) of 10 W, the following expression for T j is obtained: Die-junction temperature: T j = 30°C + 5°C + (0.1°C/W + 0.2°C/W + θsa) × 10 W For this example, a Rθsavalue of 6.7°C/W or less is required to maintain the die junction temperature below the maximum value of Table 3. Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The final die-junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. In addition to the component's power consumption, a number of factors affect the final operating die-junction temperature—airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, and so on. Due to the complexity and variety of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board as well as system-level designs.

3.12.2.4 Recommended Thermal Model

For system thermal modeling, the MPC8610 thermal model is shown in Figure 57. Four cuboids are used to represent this dissipation details. The substrate is modeled as a single block 29 × 29 × 1.18 mm with orthotropic conductivity of 23.3 W/(m  K) in the xy-plane and 0.95 W/(m  K) in the z-direction. The die is centered on the substrate. The bump/underfill layer is modeled as a collapsed thermal resistance between the die and substrate with a conductivity of 8.1 W/(m  K) in the thickness dimension of 0.07 mm. The C5 solder layer is modeled as a cuboid with dimensions 29 × 29 × 0.4 mm with orthotropic thermal conductivity of 0.034 W/(m  K) in the xy-plane and 12.1 W/(m  K) in the z-direction. An LGA solder layer would be

thermal model uses median dimensions to reduce grid. Please refer to the case outline for actual dimensions. The thermal model uses approximate dimensions to reduce grid. The approximations used do not impact thermal performance. Please refer to the case outline for exact dimensions. Figure 57. MPC8610 Thermal Model

3.12.2.5 Temperature Diode

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Ordering Information

An approximate value of the ideality may be obtained by calibrating the device near the expected operating temperature. Ideality factor is defined as the deviation from the ideal diode equation: Another useful equation is: Where: Ifw = Forward current Is = Saturation current Vd = V oltage at diode Vf = V oltage forward biased VH = Diode voltage while I H is flowing VL = Diode voltage while I L is flowing IH = Larger diode bias current IL = Smaller diode bias current q = Charge of electron (1.6 × 10 –19 C) n = Ideality factor (normally 1.0) K = Boltzman’s constant (1.38 × 10 –23 Joules/K) T = Temperature (Kelvins) The ratio of IH to IL is usually selected to be 10:1. The above simplifies to the following: Solving for T, the equation becomes:

4 Ordering Information

Ordering information for the parts fully covered by this specification document is provided in Section 4.1, “Part Numbers Fully Addressed by This Document .”

4.1 Part Numbers Fully Addressed by This Document

Table 63 provides the Freescale part numbering nomenclature for the MPC8610. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify special application conditions. Each part number also contains a revision code which refers to the die mask revision number. Ifw = I s e – 1 qVf___ nKT VH – VL = n ln KT__ q IH__ IL VH – VL = 1.986 × 10–4 × nT nT = 1.986 × 10–4

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 91 Table 64 shows the parts that are available for ordering and their operating conditions. Table 63. Part Numbering Nomenclature

1. See Section 5, “Package Information,” for more information on available package types.
2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
3. Extended temperature range devices are offered only with core frequencies of 1066 and 800 MHz.

Table 64. Part Offerings and Operating Conditions

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2

Package Information

4.2 Part Marking

Parts are marked as the example shown in Figure 58. Figure 58. Part Marking for FC-PBGA Device

5 Package Information

This section details package parameters and dimensions.

5.1 Package Parameters for the MPC8610

package options: leaded flip chip-plastic ball grid array (FC-PBGA) and RoHS lead-free (FC-PBGA). YWWLAZ is the assembly traceability code. MMMM is the M00 (mask) number.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 93

5.2 Mechanical Dimensions of the MPC8610 FC-PBGA

Figure 59 shows the mechanical dimensions and bottom surface nomenclature of the MPC8610 lead-free FC-PBGA. Notes: 1 All dimensions are in millimeters. 2 Dimensions and tolerances per ASME Y14.5M-1994. 3 Maximum solder ball diameter measured parallel to datum A. 4 Datum A, the seating plane, is defined by the spherical crowns of the solder balls. 5 Capacitors may not be present on all devices. 6 Caution must be taken not to short capacitors or expose metal capacitor pads on package top. 7 All dimensions symmetrical about centerlines unless otherwise specified. Figure 59. MPC8610 FC-PBGA Dimensions

6 Product Documentation

The following documents are required for a complete description of the device and are needed to design properly with the part.

7 Revision History

Table 65 summarizes revisions to this document. Table 65. Revision History  Removed subheading Section 1.1. pin assignments. Information.” Renumbered subsequent sections and subsections accordingly. because SRIO is not available on MPC8610. i2cr and ti2CF. Added row for Cb.  Replaced 1067 with 1066 in Ta ble 63.

MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2 Freescale Semiconductor 95 THIS PAGE INTENTIONALL Y BLANK

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