MC80C0432L

MC80F0424 ETC1 | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1.1 Description
• 1.2 Features
• 1.3 Development Tools
• 1.4 Ordering Information
• 5.1 MC80F0424/0432/0448 Pin Description
• 7.1 Absolute Maximum Ratings
• 7.2 Recommended Operating Conditions
• 7.3 A/D Converter Characteristics
• 7.4 DC Electrical Characteristics
• 7.5 AC Characteristics
• 7.6 Serial Interface Timing Characteristics
• 7.7 Typical Characteristic Curves
• 8.1 Registers
• 8.2 Program Memory
• 8.3 Data Memory
• 8.4 Addressing Mode
• 14.6 PWM Mode

MAGNACHIP SEMICONDUCTOR LTD. 8-BIT SINGLE-CHIP MICROCONTROLLERS MC80F0424/0432/0448 MC80C0424/0432/0448 User’s Manual (Ver. 0.2)

Version 0.2 Published by 2005 MagnaChip Semiconductor Ltd. All right reserved. Additional information of this manual may be served by MagnaChip semiconductor offices in Korea or Distributors and Representatives. MagnaChip semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, MagnaChip semiconductor is in no way re- sponsible for any violations of patents or other rights of the third party generated by the use of this manual. Version History Ver 0.2 (MAR, 2005) this book FLASH memory feature is included. Ver 0.1 (MAR, 2005) First release version.

MAR. 2005 Ver 0.2

MAR. 2005 Ver 0.2 MC80F0424/0432/0448 MC80C0424/0432/0448 CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH 10-BIT A/D CONVERTER AND UART 1. OVERVIEW

1.1 Description

The MC80F0424/0432/0448 is advanced CMOS 8-bit microcontroller with 48K/32K/24K bytes of ROM(FLASH). This is a powerful mi- crocontroller which provides a highly flexible and cost effective solution to many embedded control applications. This provides the fol- lowing standard features : 24K/32K/48K bytes of ROM(FLASH), 1.5K bytes of RAM, 8/16-bit timer/counter, watchdog timer, watch timer, 10-bit A/D converter, 8-bit Serial Input/Output, UART, 6-bit buzzer driving port, 10-bit PWM output and on-chip oscillator and clock circuitry. It also has 8 high current I/O pins with typical 20mA. In addition, the MC80F0424/0432/0448 supports power saving modes to reduce power consumption.

1.2 Features

• 24/32K/48K Bytes On-chip ROM
• FLASH memory - Endurance : 100 cycles - Data retention time : 10 years
• 1.5K Bytes of On-chip Data RAM (Included stack memory)
• Minimum Instruction Execution Time - 333ns at 12MHz (NOP instruction)
• 57 I/O Ports at 64 pin
• One 8-bit Basic Interval Timer
• Four 8-bit and one 16-bit Timer/Event counter (or three 16-bit Timer/Event counter)
• One Watchdog timer
• One Watch timer
• Two 10-bit PWM
• Three 8-bit Serial Communication Interface - One SIO and two UART
• One Buzzer Driving port - 488Hz ~ 250kHz@4MHz
• 16 channel 10-bit A/D converter
• Four External Interrupt input ports
• Fifteen Interrupt sources - Basic Interval Timer(1), External input(4) - Timer/Event counter(5), ADC(1) - Serial Interface(3), WDT and Watch Timer(1)
• Built in Noise Immunity Circuit - Noise filter - 3-level Power fail detector [3.0V, 2.7V, 2.4V]
• Power Down Mode - Stop, Sleep, Sub active, Sub sleep mode
• Wide Operating Voltage Range - 2.7V to 5.5V @ (0.4~4MHz) - 4.5V to 5.5V @ (0.4~12MHz)
• 0.4 ~ 12MHz Wide Operating Frequency Range
• 64SDIP, 64MQFP, 64LQFP type
• Operating Temperature : -40°C ~ 85°C
• Oscillator Type - Crystal, Ceramic resonator, External clock
• Sub-clock : 32.768kHz crystal oscillator FLASH MCU MASK MCU ROM RAM ADC PWM I/O PORT Package MC80F0424 MC80C0424 24KB 1.5KB 16 channel 2 channel 57 port 64SDIP, 64MQFP 64LQFP MC80F0432 MC80C0432 32KB 1.5KB MC80F0448 MC80C0448 48KB 1.5KB

MAR. 2005 Ver 0.2

1.3 Development Tools

The MC80F0424/0432/0448 is supported by a full-featured mac- ro assembler, an in-circuit emulator CHOICE-Dr.TM and OTP programmers. There are two different type of programmers such as single type and gang type. For mode detail, Refer to “25. FLASH PROGRAMMING” on page 113. Macro assembler op- erates under the MS-Windows 95 and upversioned Windows OS. Please contact sales part of MagnaChip semiconductor. Figure 1-1 Choice-Dr (Emulator) Figure 1-2 PGM-Plus (Single writer) Figure 1-3 Standalone GANG4 (Gang writer) Software - MS-Windows based assembler - MS-Windows based Debugger - HMS800 C compiler Hardware (Emulator) - CHOICE-Dr. - CHOICE-Dr. EVA 80C0x B/D FLASH Writer - CHOICE - SIGMA I/II(Single writer) - PGM Plus I/II/III(Single writer) - Standalone GANG4 I/II(Gang writer)

MAR. 2005 Ver 0.2

1.4 Ordering Information

Table 1-1 Ordering Information of MC80F0424/0432/0448 Device name ROM Size RAM size Package Mask version MC80C0424K MC80C0424Q MC80C0424L 24K bytes 1.5K bytes K : 64SDIP Q : 64QFP L : 64LQFP MC80C0432K MC80C0432Q MC80C0432L 32K bytes MC80C0448K MC80C0448Q MC80C0448L 48K bytes FLASH version MC80F0424K MC80F0424Q MC80F0424L 24K bytes MC80F0432K MC80F0432Q MC80F0432L 32K bytes MC80F0448K MC80F0448Q MC80F0448L 48K bytes

MAR. 2005 Ver 0.2 2. BLOCK DIAGRAM ALU Interrupt Controller Data 10-bit ADC 8-bit Counter Timer/ Program Memory Data Table PC Watch/ Timer Instruction PSW System controller Timing Generator System Clock Controller Clock Generator RESET XIN XOUT R10 / INT0 R11 / INT1 R40 R20~R23 Power Supply 8-bit serial R41 R42 / SCK R43 / SI R44 / SO R45 / ACLK0 R46 / RxD0 R47 / TxD0 Interface Buzzer Driver R60 / AN0 R61 / AN1 R62 / AN2 R63 / AN3 R64 / AN4 R65 / AN5 R66 / AN6 R67 / AN7 (1.5K bytes) 10-bit AVDD AVSS ADC Power Supply SP R00~R07 R70 / AN8 R71 / AN9 R72 / AN10 R12 / INT2 R13 / BUZO R73 / AN11 Sub System Clock Controller R21 / SXIN R22 / SXOUT PWM A X Y SIO/UART0 R74 / AN12 R75 / AN13 R76 / AN14 R77 / AN15 R14 / T0O R15 / EC0 R16 R17 R50 / INT3 R51 / EC1 R52 / T2O R53 / PWM1O / T1O R54 / PWM3O / T3O Watchdog 8-bit Basic Timer Interval VDD VSS Decoder R30 R31 / ACLK1 R32 / RxD1 R33 / TxD1 R34 R35 R36 R37 Memory UART1

MAR. 2005 Ver 0.2 3. PIN ASSIGNMENT AN8 / R70 AN9 / R71 AN10 / R72 AN11 / R73 AN12 / R74 AN13 / R75 AN14 / R76 AN15 / R77 R00 R01 R02 R03 R04 R05 R06 R07 INT0 / R10 INT1 / R11 INT2 / R12 BUZO / R13 T0O /R14 EC0 / R15 R16 R17 R20 SXIN / R21 SXOUT / R22 R23 RESET XIN XOUT VSS VDD R67 / AN7 R66 / AN6 R65 / AN5 R64 / AN4 R63 / AN3 R62 / AN2 R61 / AN1 R60 / AN0 AVDD AVSS R54 / PWM3O / T3O R53 / PWM1O / T1O R52 / T2O R51 / EC1 R50 / INT3 R47 / TxD0 R46 / RxD0 R45 / ACLK0 R44 / SO R43 / SI R42 / SCK R41 R40 R37 R36 R35 R34 R33 / TxD1 R32 / RxD1 R31 / ACLK1 R30 AN13 / R75 AN2 / R62 AN3 / R63 AN4 / R64 AN5 / R65 AN6 / R66 AN7 / R67 VDD AN8 / R70 AN9 / R71 AN10 / R72 AN11 / R73 AN12 / R74 R21 / SXIN R35 R34 R33 / TxD1 R32 / RxD1 R31 / ACLK1 R30 VSS XOUT XIN RESET R23 R22 / SXOUT R61 / AN1 AVDD AVSS R54 / PWM3O / T3O R53 / PWM1O / T1O R52 / T2O R51 / EC1 R50 / INT3 R47 / Tx0D R46 / RxD0 R45 / ACLK0 R44 / SO R43 / SI R42 / SCK R41 R40 R60 / AN0 R37 R36 AN14 / R76 R00 R01 R02 R03 R04 R05 R06 R07 INT0 / R10 INT1 / R11 INT2 / R12 BUZO / R13 T0O / R14 EC0 / R15 R16 AN15 / R77 R17 R20 64MQFP 64SDIP MC80F0424/0432/0448K MC80F0424/0432/0448Q (Top View) (Top View)

MAR. 2005 Ver 0.2 64LQFP (Top View) R37 R36 R35 R34 R33 / TxD1 R32 / RxD1 R31 / ACLK1 R30 VSS XOUT XIN RESET R23 R22 / SXOUT R21/ SXIN R20 R60 / AN0 AVDD AVSS R54 / PWM3O / T3O R53 / PWM1O / T1O R52 / T2O R51 / EC0 R50 / INT3 R47 / TxD0 R46 / RxD0 R45 / ACLK0 R44 / SO R43 / SI R42 / SCK R41 R40 R00 R01 R02 R03 R04 R05 R06 R07 NT0 / R10 INT1 / R11 INT2 / R12 BUZO / R13 T0O / R14 EC0 / R15 R16 R17 AN1 / R61 AN2 / R62 AN3 / R63 AN4 / R64 AN5 / R65 AN7 / R67 AN7 / R67 AN8 / R70 AN9 / R71 AN10 / R72 AN11 / R73 AN12 / R74 AN13 / R75 AN14 / R76 AN15 / R77 VDD MC80F0424/0432/0448L

MAR. 2005 Ver 0.2 4. PACKAGE DIAGRAM UNIT: INCH 2.280 2.260 0.022 0.016 0.050 0.030

0.070 BSC

0.140 0.120 min. 0.015 0.680 0.660 0.750 Typ. 0-15° 64SDIP 0.012 0.008 0.205 max. 20.10 19.90 24.15 23.65 18.15 17.65 14.10 13.90 3.18 max. 0.50 0.35

1.00 BSC

SEE DETAIL “A” 1.03 0.73 0-7° 0.36 0.10 0.23 0.13 1.95 REF DETAIL “A” UNIT: MM 64MQFP

MAR. 2005 Ver 0.2 1.60 max. SEE DETAIL "A" 0.75 0.45 0-7° 0.15 0.05 1.00 REF DETAIL "A" UNIT: MM

10.00 BSC

12.00 BSC

0.38 0.22

0.50 BSC

1.45 1.35 64LQFP

MAR. 2005 Ver 0.2 5. PIN FUNCTION VDD: Supply voltage. VSS: Circuit ground. AVDD: Supply voltage to the ladder resistor of ADC circuit. AVSS: ADC circuit ground. RESET: Reset the MCU. XIN: Input to the inverting oscillator amplifier and input to the in- ternal main clock operating circuit. XOUT: Output from the inverting oscillator amplifier. R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0 pins with 1 or 0 written to the R0 Port Direction Register R0IO can be used as outputs or inputs. The internal pull-up resistor can be con- nected by using the pull-up selection register 0 (PU0). R10~R17: R1 is an 8-bit CMOS bidirectional I/O port. R1 pins with 1 or 0 written to the R1 Port Direction Register R1IO can be used as outputs or inputs. The internal pull-up resistor can be con- nected by using the pull-up selection register 1 (PU1). In addition, R1 serves the functions of the various following spe- cial features such as INT0 (External interrupt 0), INT1 (External interrupt 1), INT2 (External interrupt 2), BUZO (Buzzer driver output), T0O (Timer 0 output), EC0 (Event counter input 0). R20~R23: R2 is an 4-bit CMOS bidirectional I/O port. R2 pins with 1 or 0 written to the R2 Port Direction Register R2IO can be used as outputs or inputs. In addition, R2 serves the functions of the various following spe- cial features such as SXIN (Sub clock input), SXOUT (Sub clock output). R30~R37: R3 is an 8-bit CMOS bidirectional I/O port. R3 pins with 1 or 0 written to the R3 Port Direction Register R3IO can be used as outputs or inputs. R3 operates as the high current output port with typical 20mA at low level output. In addition, R3 serves the functions of the various following spe- cial features such as ACLK1 (UART1 Asynchronous serial clock input), RxD1 (UART1 data input), TxD1 (UART1 data output) R40~R47: R4 is an 8-bit CMOS bidirectional I/O port. R4 pins with 1 or 0 written to the R4 Port Direction Register R4IO can be used as outputs or inputs. The internal pull-up resistor can be con- nected by using the pull-up selection register 4 (PU4). In addition, R4 serves the functions of the various following spe- cial features such as SCK (Serial clock), SI (Serial data input), SO (Serial data output), ACLK0 (UART0 Asynchronous serial clock input), RxD0 (UART0 data input), TxD0 (UART0 data output). R50~R54: R5 is an 5-bit CMOS bidirectional I/O port. R5 pins with 1 or 0 written to the R5 Port Direction Register R5IO can be used as outputs or inputs. In addition, R5 serves the functions of the various following spe- cial features such as INT3 (External interrupt 3), EC1 (Event counter input 1), T2O (Timer 2 output), PWM1O (PWM 1 out- put) / T1O (Timer 1 compare output), PWM3O (PWM 3 output) / T3O (Timer 3 compare output). R60~R67: R6 is an 8-bit CMOS bidirectional I/O port. R6 pins with 1 or 0 written to the R6 Port Direction Register R6IO can be used as outputs or inputs. In addition, R6 serves the functions of the ADC analog input port AN[7:0]. R70~R77: R7 is an 8-bit CMOS bidirectional I/O port. R7 pins with 1 or 0 written to the R7 Port Direction Register R7IO can be used as outputs or inputs. The internal pull-up resistor can be con- nected by using the pull-up selection register 7 (PU7). In addition, R7 serves the functions of the ADC analog input port AN[15:8].

MAR. 2005 Ver 0.2

5.1 MC80F0424/0432/0448 Pin Description

5.1.1 MC80F0424/0432/0448 Pin Description

R00~R07 I/O Port 0. 8-bit I/O port. Can be set as input or output mode in 1-bit units. Internal pull-up resistor PU0 can be used via software. Input R10 I/O Port 1. 8-bit I/O port. Can be set as input or output mode in 1-bit units. Internal pull-up resistor PU1 can be used via software. Input INT0 R11 INT1 R12 INT2 R13 BUZO R14 T0O R15 EC0 R16 R17 R20 I/O Port 2. 4-bit I/O port. Can be set in input or output mode in 1-bit units. Crystal(32.768KHz) connecting pins(R21,R22) Input R21 SXIN R22 SXOUT R23 P30 I/O Port 3. 8-bit I/O port. Can be set in input or output mode in 1-bit units. Operates as high current output port with typical 20mA at low level output. Input P31 ACLK1 P32 RxD1 P33 TxD1 P34 P35 P36 P37 R40 I/O Port 4. 8-bit I/O port. Can be set in input or output mode in 1-bit units. Internal pull-up resistor PU4 can be used via software. Input R41 R42 SCK R43 SI R44 SO R45 ACLK0 R46 RxD0 R47 TxD0 R50 I/O Port 5. 5-bit I/O port. Can be set in input or output mode in 1-bit units. Input INT3 R51 EC1 R52 T2O R53 PWM1O/T1O R54 PWM3O/T3O Table 5-1 MC80F0424/0432/0448 Pin Description

MAR. 2005 Ver 0.2 R60~R67 I/O Port 6. 8-bit I/O port. Can be set in input or output mode in 1-bit units. Input AN0~AN7 R70~R77 I/O Port 7. 8-bit I/O port. Can be set in input or output mode in 1-bit units. Internal pull-up resistor PU7 can be used via software. Input AN8~AN15 RESET I System reset input. Input XIN I Crystal connection for main system clock oscillation. Input XOUT O Output AVDD Analog power/reference voltage input to A/D converter. Set the same potential as VDD. AVSS Ground potential for A/D converter. Set the same potential as VSS. VDD Positive power supply. VSS Ground potential. PIN NAME In/Out Function Initial state Alternate Function Table 5-1 MC80F0424/0432/0448 Pin Description

MAR. 2005 Ver 0.2

5.1.2 MC80F0424/0432/0448 Alternate Function Pin Description

I Valid edges(rising, falling, or both rising and falling) can be spec- ified. External Interrupt request Input. Input R10 INT1 R11 INT2 R12 INT3 R50 BUZO O Buzzer Output Input R13 T0O O Timer0 Output Input R14 T2O O Timer2 Output Input R52 EC0 I Timer0 Event Counter Input Input R15 EC1 I Timer2 Event Counter Input Input R51 SXIN I Resonator connecting pins (32.768KHz) Input R21 SXOUT O Input R22 ACLK1 I UART1 Asynchronous serial interface serial clock input. Input R31 RxD1 I UART1 Asynchronous serial interface serial data input. Input R32 TxD1 O UART1 Asynchronous serial interface serial data output. Input R33 SCK I/O Serial clock input/output of serial interface. Input R42 SI I Serial data input of serial interface. Input R43 SO O Serial data output of serial interface. Input R44 ACLK0 I UART0 Asynchronous serial interface serial clock input. Input R45 RxD0 I UART0 Asynchronous serial interface serial data input. Input R46 TxD0 O UART0 Asynchronous serial interface serial data output. Input R47 PWM1O/T1O O Timer1 PWM Output / Timer 1 Compare Output Input R53 PWM3O/T3O O Timer3 PWM Output / Timer 1 Compare Output Input R54 AN0~AN7 I Analog input Channel 0 ~ 7 for A/D converter. Input R60~R67 AN8~AN15 I Analog input Channel 8 ~ 15 for A/D converter. Input R70~R77 Table 5-2 MC80F0424/0432/0448 Alternate Function Pin Description

MAR. 2005 Ver 0.2 6. PORT STRUCTURES R00~R07, R16, R17, R40, R41 R10(INT0), R11(INT1), R12(INT2), R15(EC0), R43(SI),R45(ACLK0),R46(RxD0) R50(INT3),R51(EC1) R33(TxD1) VDD VSS Pin Data Reg. Direction Reg. Pull-up Tr. Pull-up Reg. VDD RD Data Bus VDD VSS MUX VDD VSS Pin Data Reg. Direction Reg. RD INT,EC,SI, INT_EN,SI_EN,ACLK0_EN, Pull-up Tr. Pull-up Reg. VDD Noise Filter Data Bus VDD VSS MUX ACLK0,RxD0 EC_EN,RxD_EN VDD VSS Pin Data Reg. Direction Reg. RD Data Bus VDD INT3,EC1 INT3_EN,EC1_EN Noise Filter MUX VDD VSS Pin Data Reg. Direction Reg. TxD1_EN Data Bus TxD1 VDD VSS MUX MUX RD

MAR. 2005 Ver 0.2 R31(ACLK1), R32(RxD1) R13(BUZO), R14(T0O), R47(TxD0) R52(T2O), R53(PWM1O), R54(PWM3O) R20, R23, R30~R37 VDD VSS Pin Data Reg. Direction Reg. RD Data Bus VDD ACLK1,RxD1 ACLK1_EN, RxD1_EN Noise Filter MUX VDD VSS Pin Data Reg. Direction Reg. Pull-up Tr. Pull-up Reg. VDD BUZO_EN, T0O_EN Data Bus BUZO,T0O,TxD0 VDD VSS MUX MUX RD TxD0_EN VDD VSS Pin Data Reg. Direction Reg. RD PWM1_EN,T2O_EN Data Bus T2O,PWM1O,PWM3O VDD VSS MUX MUX PWM3_EN VDD VSS Pin Data Reg. Direction Reg. Data Bus VDD VSS MUX RD

MAR. 2005 Ver 0.2 R42(SCK) R44(SO, IOSWIN(SI)) R60~R67(AN0~AN7) R70~R77(AN8~AN15) VDD VSS Pin Data Reg. Direction Reg. RD SCK SCKI_EN Pull-up Tr. Pull-up Reg. VDD Noise Filter Data Bus SCK SCKO_EN VDD VSS MUX MUX VDD VSS Pin Data Reg. Direction Reg. RD SI Pull-up Tr. Pull-up Reg. VDD Noise Filter Data Bus SO SO_EN IOSWIN_EN IOSWIN_EN(SI) VDD VSS MUX MUX VDD VSS Pin Data Reg. Direction Reg. RD AN[7:0] ADC_EN & CH_SEL Data Bus VDD VSS MUX VDD VSS Pin Data Reg. Direction Reg. RD AN[15:0] ADC_EN & CH_SEL Pull-up Tr. Pull-up Reg. VDD Data Bus VDD VSS MUX

MAR. 2005 Ver 0.2 RESET R21(SXIN), R22(SXOUT) XIN, XOUT Pin VDD VSS Internal Reset Mask only VDD VSS SXIN Data Reg. Direction Reg. RD Data Bus VDD VSS VDD VSS SXOUT Data Reg. Direction Reg. RD Data Bus VDD VSS XT_EN MUX MUX XOUT VDD VSS XIN VDD VSS VSS STOP MAIN CLOCK

MAR. 2005 Ver 0.2 7. ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

Voltage on any pin with respect to Ground (VSS) Maximum output current sourced by (IOH per I/O Pin) Note: Stresses above those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the de- vice. This is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for ex- tended periods may affect device reliability.

7.2 Recommended Operating Conditions

7.3 A/D Converter Characteristics

(Ta=-40~85°C, VSS=0V, VDD=2.7~5.5V @Conversion Clock of 1MHz) Parameter Symbol Condition Specifications Unit Min. Max. Supply Voltage VDD fXIN=0.4~12MHz fXIN=0.4~4MHz 4.5 2.7 5.5 5.5 V Operating Frequency fXIN VDD=4.5~5.5V VDD=2.7~5.5V 0.4 0.4 MHz Operating Temperature TOPR -40 Parameter Symbol Conditions Min. Typ. Max. Unit Resolution ±10 BIT Overall Accuracy NACC LSB Non Linearity Error NNLE LSB Differential Non Linearity Error NDNLE LSB Full Scale Error NFSE LSB Zero Offset Error NZOE LSB Gain Error NNLE LSB Conversion Time TCONV fXIN µS Analog Input Voltage VAIN AVSS AVDD V Analog Power Supply AVDD VDD V Analog Ground AVSS VSS VSS+0.3 V Analog Block Current IAVDD AVDD=VDD=5.12V 2.5 mA

MAR. 2005 Ver 0.2

7.4 DC Electrical Characteristics

(TA=-40~85°C, VDD=5.0V±10%, VSS=0V, fXIN=8MHz) Parameter Symbol Pin/Condition Min. Typ. Max. Unit Input High Voltage VIH1 INT0, INT1, INT2, INT3, EC0, EC1, SI, SCK, ACLK0, RxD0, ACLK1, RxD1, RESET 0.8VDD VDD+0.3 V VIH2 R0, R1, R2, R3, R4, R5, R6, R7 0.7VDD VDD+0.3 V VIH3 XIN, SXIN 0.8VDD VDD+0.3 V Input Low Voltage VIL1 INT0, INT1, INT2, INT3, EC0, EC1, SI, SCK, ACLK0, RxD0, ACLK1, RxD1, RESET -0.3 0.2VDD V VIL2 R0, R1, R2, R3, R4, R5, R6, R7 -0.3 0.3VDD V VIL3 XIN, SXIN -0.3 0.2VDD V Output High Voltage VOH1 R0, R1, R2, R3, R4, R5, R6, R7 (IOH=-0.7mA) VDD-0.4 V VOH2 XOUT (IOH=-50µA) VDD-0.5 V VOH3 SXOUT (IOH=-5µA) VDD-0.5 V Output Low Voltage VOL1 R0, R1, R2, R3, R4, R5, R6, R7 (IOL=1.6mA) 0.4 V VOL2 XOUT (IOL=50µA) 0.5 V VOL3 SXOUT (IOL=5µA) 0.5 V High Current IOL R3 (VOL=1V) mA Input High Leakage Current IIH R0, R1, R2, R3, R4, R5, R6, R7 µA Input Low Leakage Current IIL R0, R1, R2, R3, R4, R5, R6, R7 µA Pull-up Resistor RPU R0, R1, R4, R7 100 kΩ OSC Feedback Resistor RX XIN, XOUT 0.45 4.5 MΩ RSX SXIN, SXOUT MΩ Internal RC WDT Period (RCWDT) IIL VDD=4.5V 100 µS Hysteresis VT INT0, INT1, INT2, INT3, EC0, EC1, SI, SCK, ACLK, RxD 0.3 0.8 V Power Fail Detect Voltage VPFD 2.2 2.7 3.2 V 2.5 3.0 3.5 V 1.9 2.4 2.9 V Power Supply Current IDD1 Active Mode, XIN=8MHz mA IDD2 Sub_Active Mode, SXIN=0.32MHz 160 µA ISLEEP1 Sleep Mode, XIN=8MHz mA ISLEEP2 Sub_Sleep Mode, SXIN=0.32MHz µA ISTOP Stop Mode, Oscillator Stop, XIN=4MHz µA

MAR. 2005 Ver 0.2

7.5 AC Characteristics

(TA=-40~85°C, VDD=5V±10%, VSS=0V) Figure 7-1 Timing Chart Parameter Symbol Pins Specifications Unit Min. Typ. Max. Operating Frequency fXIN XIN 0.4 MHz System Clock Cycle Time tSYS 166 5000 nS Oscillation Stabilizing Time (4MHz) tST XIN, XOUT mS External Clock Pulse Width tCPW XIN nS External Clock Transi- tion Time tRCP,tFCP XIN nS Interrupt Pulse Width tIW INT0, INT1, INT2, INT3 tSYS RESET Input Width tRST RESET tSYS Event Counter Input Pulse Width tECW EC0, EC1 tSYS Event Counter Transi- tion Time tREC,tFEC EC0, EC1 nS tRCP tFCP XIN INT0~INT3 0.1VDD 0.9VDD 0.2VDD 0.8VDD 0.2VDD RESET tREC tFEC 0.2VDD 0.8VDD EC0, EC1 tIW tIW tRST tECW tECW tSYS = 1/fXIN tCPW tCPW

MAR. 2005 Ver 0.2

7.6 Serial Interface Timing Characteristics

(TA=-40~+85°C, VDD=5V±10%, VSS=0V, fXIN=8MHz) Figure 7-2 Serial I/O Timing Chart Parameter Symbol Pins Specifications Unit Min. Typ. Max. Serial Input Clock Pulse tSCYC SCK 2tSYS+200 nS Serial Input Clock Pulse Width tSCKW SCK tSYS+70 nS Serial Input Clock Pulse Transition Time tFSCK tRSCK SCK nS Serial Input Pulse Transition Time tFSIN tRSIN SI nS Serial Input Setup Time (External SCK) tSUS SI 100 nS Serial Input Setup Time (Internal SCK) tSUS SI 200 nS Serial Input Hold Time tHS SI tSYS+70 nS Serial Output Clock Cycle Time tSCYC SCK 4tSYS 16tSYS nS Serial Output Clock Pulse Width tSCKW SCK tSYS-30 nS Serial Output Clock Pulse Transition Time tFSCK tRSCK SCK nS Serial Output Delay Time sOUT SO 100 nS SCLK SI 0.2VDD SO 0.2VDD 0.8VDD tSCYC tSCKW tSCKW tRSCK tFSCK 0.8VDD tSUS tHS tDS 0.2VDD 0.8VDD tRSIN tFSIN

MAR. 2005 Ver 0.2

7.7 Typical Characteristic Curves

This graphs and tables provided in this section are for design guidance only and are not tested or guaranteed. In some graphs or tables the data presented are out- side specified operating range (e.g. outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. “Typ- ical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean − 3σ) respectively where σ is standard deviation IOH−VOH -12 0.5 1.0 1.5 2.0 (V) TA=25°C VDD=5.0V R0~R7 pins (mA) IOH VDD-VOH IOL−VOL1 (mA) IOL 0.5 1.0 1.5 2.0 2.5 VOL(V) TA=25°C VDD=5.0V R0~R2, R4~R7 pins IOH−VOH -12 0.5 1.0 1.5 2.0 (V) TA=25°C VDD=3.0V R0~R7 pins (mA) IOH VDD-VOH IOL−VOL1 (mA) IOL 0.5 1.0 1.5 2.0 VOL(V) TA=25°C VDD=3.0V R0~R2, R4~R7 pins IOL−VOL2 (mA) IOL 0.5 1.0 1.5 2.0 2.5 VOL (V) TA=25°C VDD=5.0V R3 pin IOL−VOL2 (mA) IOL 0.5 1.0 1.5 2.0 VOL (V) TA=25°C VDD=3.0V R3 pin 2.5

MAR. 2005 Ver 0.2 TA=25°C IDD−VDD 7.5 2.5 (mA) IDD VDD (V) Main Active Mode ISLEEP−VDD (mA) IDD VDD (V) Main Active Mode 4MHz fXIN = 12MHz ISTOP−VDD (µA) IDD VDD (V) Main Active Mode 4MHz fXIN = 12MHz 8MHz 8MHz TA=25°C IDD−VDD 500 175 250 125 (µA) IDD VDD (V) Sub Active Mode2 fXIN = 12MHz, 8MHz, 4MHz ISLEEP−VDD (µA) IDD VDD (V) Sub Active Mode2 fXIN = 12MHz, 8MHz, 4MHz TA=25°C IDD−VDD (mA) IDD VDD (V) Sub Active Mode1 ISLEEP−VDD 1.5 0.5 (mA) IDD VDD (V) Sub Active Mode1 fXIN = 12MHz, 8MHz, 4MHz fXIN = 12MHz, 8MHz, 4MHz * Main Active mode : System clock(Main) * Sub Active mode1 : System clock(Sub) (at main clock ON, sub clock ON) * Sub Active mode2 : System clock(Sub) (at main clock OFF, sub clock ON) TA=25°C TA=25°C TA=25°C TA=25°C TA=25°C

MAR. 2005 Ver 0.2 Actual Operating Area (MHz) fXIN VDD (V) Operating Area TA= -40~85°C Spec Operating Area

MAR. 2005 Ver 0.2 8. MEMORY ORGANIZATION The MC80F0424/0432/0448 has separate address spaces for Pro- gram memory and Data Memory. Program memory can only be read, not written to. It can be up to 48K bytes of Program memo- ry. Data memory can be read and written to up to 1024 bytes in- cluding the stack area.

8.1 Registers

This device has six registers that are the Program Counter (PC), a Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register. Figure 8-1 Configuration of Registers Accumulator: The Accumulator is the 8-bit general purpose reg- ister, used for data operation such as transfer, temporary saving, and conditional judgement, etc. The Accumulator can be used as a 16-bit register with Y Register as shown below. Figure 8-2 Configuration of YA 16-bit Register X, Y Registers: In the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. These modes are extremely ef- fective for referencing subroutine tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumula- tors. Stack Pointer: The Stack Pointer is an 8-bit register used for oc- currence interrupts and calling out subroutines. Stack Pointer identifies the location in the stack to be accessed (save or restore). Generally, SP is automatically updated when a subroutine call is executed or an interrupt is accepted. However, if it is used in ex- cess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. The stack can be located at any position within 100H to 1FFH of the internal data memory. The SP is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of “FFH” is used. Note: The Stack Pointer must be initialized by software be- cause its value is undefined after Reset. Example: To initialize the SP LDX #0FFH TXSP ; SP ← FFH Program Counter: The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indi- cates the address of the next instruction to be executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH). Program Status Word: The Program Status Word (PSW) con- tains several bits that reflect the current state of the CPU. The PSW is described in Figure 8-3. It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD opera- tion), the Interrupt enable flag, the Zero flag, and the Carry flag. [Carry flag C] This flag stores any carry or borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruc- tion or Rotate Instruction. [Zero flag Z] This flag is set when the result of an arithmetic operation or data transfer is “0” and is cleared by any other result. ACCUMULATOR X REGISTER Y REGISTER STACK POINTER PROGRAM COUNTER PROGRAM STATUS WORD X A SP Y PCL PSW PCH Two 8-bit Registers can be used as a “YA” 16-bit Register Y A Y A SP 01H Stack Address (100H ~ 1FFH) Bit 15 Bit 0 8 7 Hardware fixed 00H~FFH

MAR. 2005 Ver 0.2 Figure 8-3 PSW (Program Status Word) Register [Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All interrupts are disabled when cleared to “0”. This flag immediately becomes “0” when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction. [Half carry flag H] After operation, this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V). [Break flag B] This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector address. [Direct page flag G] This flag assigns RAM page for direct addressing mode. In the di- rect addressing mode, addressing area is from zero page 00H to 0FFH when this flag is "0". If it is set to "1", addressing area is assigned 100H to 1FFH. It is set by SETG instruction and cleared by CLRG. [Overflow flag V] This flag is set to “1” when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127(7FH) or - 128(80H). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is exe- cuted, bit 7 of memory is copied to this flag. N NEGATIVE FLAG V G B H I Z C MSB LSB RESET VALUE: 00H PSW OVERFLOW FLAG BRK FLAG CARRY FLAG RECEIVES ZERO FLAG INTERRUPT ENABLE FLAG CARRY OUT HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS SELECT DIRECT PAGE when G=1, page is selected to “page 1”

MAR. 2005 Ver 0.2 Figure 8-4 Stack Operation

8.2 Program Memory

A 16-bit program counter is capable of addressing up to 64K bytes, but this device has 24/32/48K bytes program memory space only physically implemented. Accessing a location above FFFFH will cause a wrap-around to 0000H. Figure 8-5, shows a map of Program Memory. After reset, the CPU begins execution from reset vector which is stored in ad- dress FFFEH and FFFFH as shown in Figure 8-6. As shown in Figure 8-5, each area is assigned a fixed location in Program Memory. Program Memory area contains the user pro- gram At execution of a CALL/TCALL/PCALL PCL PCH 01FC SP after execution SP before execution 01FD 01FD 01FE 01FF 01FF Push down At acceptance of interrupt PCL PCH 01FC 01FC 01FD 01FE 01FF 01FF Push down PSW At execution of RET instruction PCL PCH 01FC 01FF 01FD 01FE 01FF 01FD Pop up At execution of RET instruction PCL PCH 01FC 01FF 01FD 01FE 01FF 01FC Pop up PSW 0100H 01FFH Stack depth At execution of PUSH instruction A 01FC 01FE 01FD 01FE 01FF 01FF Push down SP after execution SP before execution PUSH A (X,Y,PSW) At execution of POP instruction A 01FC 01FF 01FD 01FE 01FF 01FE Pop up POP A (X,Y,PSW)

MAR. 2005 Ver 0.2 Figure 8-7 PCALL and TCALL Memory Area PCALL→ rel 4F35 PCALL 35H TCALL→ n TCALL 4 0FFC0H Address Program Memory 0FF00H Address PCALL Area Memory 0FFFFH PCALL Area (256 Bytes) * means that the BRK software interrupt is using same address with TCALL0. NOTE: TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK * CA CB CC CD CE CF DA DB DC DD DE DF NEXT 0FF35H 0FF00H 0FFFFH 11111111 11010110 01001010 PC: FH FH DH 6H 0FFD6H 0FF00H 0FFFFH NEXT 0FFD7H 0D125H Reverse

MAR. 2005 Ver 0.2 Example: The usage software example of Vector address for MC80F0448. ;Interrupt Vector Table ORG 0FFE0H DW BIT_TIMER ; BIT DW WATCH_WDT ; WDT & WT DW ADC ; AD Converter DW TIMER4 ; Timer-4 DW TIMER3 ; Timer-3 DW TIMER2 ; Timer-2 DW TIMER1 ; Timer-1 DW TIMER0 ; Timer-0 DW SIO ; Serial Interface DW UART1 ; UART1 Rx/Tx DW UART0 ; UART0 Rx/Tx DW INT3 ; Ext Int.3 DW INT2 ; Ext Int.2 DW INT1 ; Ext Int.1 DW INT0 ; Ext Int.0 DW RESET ; Reset ORG 04000H ; 48K bytes ROM Start address MAIN PROGRAM RESET: DI ;Disable All Interrupt RAMCLEAR: LDX #00H ;USER RAM START ADDRESS LOAD ! LDY RAMCLR1: LDA #00H ;Page0 Ram Clear(0000h ~ 00BFh) STA {X}+ CMPX #0C0H BNE RAMCLR1 INC Y STY !RPR ;Page1 Ram Select SETG ;G-FLAG SET ! LDX #00H RAMCLR2: LDA #00H STA {X}+ CMPX #00H BNE RAMCLR2 INC Y CMPY BCS RAMCLR3 ;Page1 ~ Page5 Clear(0100h ~ 04FFh) STY !RPR SETG BRA RAMCLR2 RAMCLR3: STY !RPR ;Page6 Clear(0600h ~ 063Fh) SETG LDA #00H ;A <-- #0 STA {X}+ CMPX #40H BNE RAMCLR3 CLRG ;G-FLAG CLEAR ! LDX #0FFH TXSP ;Initial Stack Point (01FFh)

MAR. 2005 Ver 0.2

8.3 Data Memory

Figure 8-8 shows the internal Data Memory space available. Data Memory is divided into three groups, a user RAM, control regis- ters, and Stack memory. Figure 8-8 Data Memory Map User Memory The MC80F0424/0432/0448 has 1.5kbytes for the user memory (RAM). RAM pages are selected by RPR (See Figure 8-9). Note: After setting RPR(RAM Page Select Register), be sure to execute SETG instruction. When executing CLRG instruction, be selected PAGE0 regardless of RPR. Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. There- fore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and I/O ports. The control registers are in address range of 0C0H to 0FFH. Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return ran- dom data, and write accesses will have an indeterminate effect. More detailed informations of each register are explained in each peripheral section. Note: Write only registers can not be accessed by bit ma- nipulation instruction. Do not use read-modify-write instruc- tion. Use byte manipulation instruction, for example “LDM”. Example; To write at CKCTLR LDM CLCTLR,#0AH ;Divide ratio(÷32) Stack Area The stack provides the area where the return address is saved be- fore a jump is performed during the processing routine at the ex- ecution of a subroutine call instruction or the acceptance of an interrupt. When returning from the processing routine, executing the sub- routine return instruction [RET] restores the contents of the pro- gram counter from the stack; executing the interrupt return instruction [RETI] restores the contents of the program counter and flags. The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save. Refer to Figure 8-4 on page 26. Figure 8-9 RPR(RAM Page Select Register) User Memory Control Registers (64Bytes) 0000H 00BFH 00C0H PAGE0 PAGE1 (When “G-flag=0”, this page0 is selected) or Stack Area User Memory User Memory 00FFH 0100H 01FFH 0200H 03FFH 0400H 05FFH 0600H 04FFH 0500H 063FH 0640H (192Bytes) (256Bytes) (64Bytes) Not Used PAGE2 User Memory PAGE3 PAGE4 (256Bytes) User Memory PAGE5 (256Bytes) User Memory Extended SFR (64Bytes) (256Bytes) (256Bytes) User Memory (256Bytes) User Memory PAGE6 02FFH 0300H 0EBFH 0EC0H 0EFFH RAM page select 000 : PAGE0 001 : PAGE1 INITIAL VALUE: -----000B ADDRESS: 0E1H RPR 010 : PAGE2 011 : PAGE3 R/W R/W R/W RPR2 RPR1 RPR0 100 : PAGE4 101 : PAGE5 110 : PAGE6

MAR. 2005 Ver 0.2 Address Register Name Symbol R/W Initial Value Addressing mode 00C0 R0 port data register R/W 0 0 0 0 0 0 0 0 byte, bit1 00C1 R0 port I/O direction register R0IO W 0 0 0 0 0 0 0 0 byte2 00C2 R1 port data register R/W 0 0 0 0 0 0 0 0 byte, bit 00C3 R1 port I/O direction register R1IO W 0 0 0 0 0 0 0 0 byte 00C4 R2 port data register R/W 0 0 0 0 byte, bit 00C5 R2 port I/O direction register R2IO W 0 0 0 0 byte 00C6 R3 port data register R/W 0 0 0 0 0 0 0 0 byte, bit 00C7 R3 port I/O direction register R3IO W 0 0 0 0 0 0 0 0 byte 00C8 R4 port data register R/W 0 0 0 0 0 0 0 0 byte, bit 00C9 R4 port I/O direction register R4IO W 0 0 0 0 0 0 0 0 byte 00CA R5 port data register R/W 0 0 0 0 0 byte, bit 00CB R5 port I/O direction register R5IO W 0 0 0 0 0 byte 00CC R6 port data register R/W 0 0 0 0 0 0 0 0 byte, bit 00CD R6 port I/O direction register R6IO W 0 0 0 0 0 0 0 0 byte 00CE R7 port data register R/W 0 0 0 0 0 0 0 0 byte, bit 00CF R7 port I/O direction register R7IO W 0 0 0 0 0 0 0 0 byte 00D0 Timer 0 mode control register TM0 R/W 0 0 0 0 0 0 byte, bit 00D1 Timer 0 register R 0 0 0 0 0 0 0 0 byte Timer 0 data register TDR0 W 1 1 1 1 1 1 1 1 Timer 0 capture data register CDR0 R 0 0 0 0 0 0 0 0 00D2 Timer 1 mode control register TM1 R/W 0 0 0 0 0 0 0 0 byte, bit 00D3 Timer 1 data register TDR1 W 1 1 1 1 1 1 1 1 byte Timer 1 PWM period register T1PPR W 1 1 1 1 1 1 1 1 00D4 Timer 1 register R 0 0 0 0 0 0 0 0 byte Timer 1 PWM duty register T1PDR R/W 0 0 0 0 0 0 0 0 Timer 1 capture data register CDR1 R 0 0 0 0 0 0 0 0 00D5 Timer 1 PWM high register T1PWHR W 0 0 0 0 byte 00D6 Timer 2 mode control register TM2 R/W 0 0 0 0 0 0 byte, bit 00D7 Timer 2 register R 0 0 0 0 0 0 0 0 byte Timer 2 data register TDR2 W 1 1 1 1 1 1 1 1 Timer 2 capture data register CDR2 R 0 0 0 0 0 0 0 0 00D8 Timer 3 mode control register TM3 R/W 0 0 0 0 0 0 0 0 byte, bit Table 8-1 Control Registers

MAR. 2005 Ver 0.2 00D9 Timer 3 data register TDR3 W 1 1 1 1 1 1 1 1 byte Timer 3 PWM period register T3PPR W 1 1 1 1 1 1 1 1 00DA Timer 3 register R 0 0 0 0 0 0 0 0 byte Timer 3 PWM duty register T3PDR R/W 0 0 0 0 0 0 0 0 Timer 3 capture data register CDR3 R 0 0 0 0 0 0 0 0 00DB Timer 3 PWM high register T3PWHR W 0 0 0 0 byte 00DC Timer 4 mode control register TM4 R/W 0 0 0 0 0 0 byte, bit 00DD Timer 4 low register T4L R 0 0 0 0 0 0 0 0 byte Timer 4 low data register TDR4L W 1 1 1 1 1 1 1 1 Timer 4 capture low data register CDR4L R 0 0 0 0 0 0 0 0 00DE Timer 4 high register T4H R 0 0 0 0 0 0 0 0 byte Timer 4 high data register TDR4H W 1 1 1 1 1 1 1 1 Timer 4 capture high data register CDR4H R 0 0 0 0 0 0 0 0 00DF Interrupt flag register IFR R/W 0 0 0 0 0 0 byte, bit 00E0 Buzzer driver register BUZR W 1 1 1 1 1 1 1 1 byte 00E1 RAM page selection register RPR R/W 0 0 0 byte, bit 00E2 SIO mode control register SIOM R/W 0 0 0 0 0 0 0 1 byte, bit 00E3 SIO data shift register SIOR R/W Undefined byte, bit 00E4 Reserved 00E5 Reserved 00E6 UART0 mode register ASIMR R/W 0 0 0 0 0 0 byte, bit 00E7 UART0 status register ASISR R 0 0 0 byte 00E8 UART0 Baud rate generator control register BRGCR R/W 0 0 1 0 0 0 0 byte, bit 00E9 UART0 Receive buffer register RXR R 0 0 0 0 0 0 0 0 byte UART0 Transmit shift register TXR W 1 1 1 1 1 1 1 1 00EA Interrupt enable register high IENH R/W 0 0 0 0 0 0 0 0 byte, bit 00EB Interrupt enable register low IENL R/W 0 0 0 0 0 0 0 0 byte, bit 00EC Interrupt request register high IRQH R/W 0 0 0 0 0 0 0 0 byte, bit 00ED Interrupt request register low IRQL R/W 0 0 0 0 0 0 0 0 byte, bit 00EE Interrupt edge selection register IEDS R/W 0 0 0 0 0 0 0 0 byte, bit 00EF A/D converter mode control register ADCM R/W 0 0 0 0 0 0 0 1 byte, bit 00F0 A/D converter result high register ADCRH R 0 1 1 Undefined byte 00F1 A/D converter result low register ADCRL R Undefined byte Address Register Name Symbol R/W Initial Value Addressing mode Table 8-1 Control Registers

MAR. 2005 Ver 0.2 00F2 Basic interval timer register BITR R Undefined byte Clock control register CKCTLR W 0 1 0 1 1 1 00F3 System clock mode register SCMR R/W 0 0 0 byte, bit 00F4 Watch dog timer register WDTR W 0 1 1 1 1 1 1 1 byte Watch dog timer data register WDTDR R Undefined 00F5 Stop & sleep mode control register SSCR W 0 0 0 0 0 0 0 0 byte 00F6 Watch timer mode register WTMR R/W 0 0 0 0 0 byte, bit 00F7 PFD control register PFDR R/W 0 0 0 byte, bit 00F8 Port selection register 0 PSR0 W 0 0 0 0 0 0 0 0 byte 00F9 Port selection register 1 PSR1 W 0 0 0 0 byte 00FA Reserved 00FB Reserved 00FC Pull-up selection register 0 PU0 W 0 0 0 0 0 0 0 0 byte 00FD Pull-up selection register 1 PU1 W 0 0 0 0 0 0 0 0 byte 00FE Pull-up selection register 4 PU4 W 0 0 0 0 0 0 0 0 byte 00FF Pull-up selection register 7 PU7 W 0 0 0 0 0 0 0 0 byte 0EE6 UART1 mode register ASIMR1 R/W 0 0 0 0 0 0 byte, bit 0EE7 UART1 status register ASISR1 R 0 0 0 byte 0EE8 UART1 Baud rate generator control register BRGCR1 R/W 0 0 1 0 0 0 0 byte, bit 0EE9 UART1 Receive buffer register RXR1 R 0 0 0 0 0 0 0 0 byte UART1 Transmit shift register TXR1 W 1 1 1 1 1 1 1 1 Address Register Name Symbol R/W Initial Value Addressing mode Table 8-1 Control Registers The ‘byte’ means registers are controlled by only byte manipulation instruction. Do not use bit manipulation The ‘byte, bit’ means registers are controlled by both bit and byte manipulation instruction. instruction such as SET1, CLR1 etc. If bit manipulation instruction is used on these registers, content of other seven bits are may varied to unwanted value. *The mark of ‘-’ means this bit location is reserved. Caution) The R/W register except T1PDR and T3PDR are both can be byte and bit manipulated.

MAR. 2005 Ver 0.2 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C0H R0 Port Data Register C1H R0IO R0 Port Direction Register C2H R1 Port Data Register C3H R1IO R1 Port Direction Register C4H R2 Port Data Register C5H R2IO R2 Port Direction Register C6H R3 Port Data Register C7H R3IO R3 Port Direction Register C8H R4 Port Data Register C9H R4IO R4 Port Direction Register CAH R5 Port Data Register CBH R5IO R5 Port Direction Register CCH R6 Port Data Register CDH R6IO R6 Port Direction Register CEH R7 Port Data Register CFH R7IO R7 Port Direction Register D0H TM0 CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST D1H T0/TDR0/ CDR0 Timer0 Register / Timer0 Data Register / Timer0 Capture Data Register D2H TM1 POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST D3H TDR1/ T1PPR Timer1 Data Register / Timer1 PWM Period Register D4H T1/CDR1/ T1PDR Timer1 Register / Timer1 Capture Data Register / Timer1 PWM Duty Register D5H PWM1HR Timer1 PWM High Register D6H TM2 CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST D7H T2/TDR2/ CDR2 Timer2 Register / Timer2 Data Register / Timer2 Capture Data Register D8H TM3 POL 16BIT PWM3E CAP3 T3CK1 T3CK0 T3CN T3ST D9H TDR3/ T3PPR Timer3 Data Register / Timer3 PWM Period Register DAH T3/CDR3/ T3PDR Timer3 Register / Timer3 Capture Data Register / Timer3 PWM Duty Register DBH PWM3HR Timer3 PWM High Register DCH TM4 CAP4 T4CK2 T4CK1 T4CK0 T4CN T4ST DDH T4L/ TDR4L/ CDR4L Timer4 Register Low / Timer4 Data Register Low / Timer4 Capture Data Register Low Table 8-2 Control Register Function Description

MAR. 2005 Ver 0.2 DEH T4H/ TDR4H/ CDR4H Timer4 Register High / Timer4 Data Register High / Timer4 Capture Data Register High DFH IFR IFRX0 IFTX0 IFRX1 IFTX1 IFWT IFWDT E0H BUZR BUCK1 BUCK0 BUR5 BUR4 BUR3 BUR2 BUR1 BUR0 E1H RPR RPR2 RPR1 RPR0 E2H SIOM POL IOSW SM1 SM0 SCK1 SCK0 SIOST SIOSF E3H SIOR SIO Data Shift Register E4H Reserved E5H Reserved E6H ASIMR TXE RXE PS1 PS0 SL ISRM E7H ASISR PE FE OVE E8H BRGCR TPS2 TPS1 TPS0 MLD3 MLD2 MLD1 MLD0 E9H RXR UART0 Receive Buffer Register TXR UART0 Transmit Shift Register EAH IENH INT0E INT1E INT2E INT3E UART0E UART1E SIOE T0E EBH IENL T1E T2E T3E T4E ADCE WDTE WTE BITE ECH IRQH INT0IF INT1IF INT2IF INT3IF UART0IF UART1IF SIOIF T0IF EDH IRQL T1IF T2IF T3IF T4IF ADCIF WDTIF WTIF BITIF EEH IEDS IED3H IED3L IED2H IED2L IED1H IED1L IED0H IED0L EFH ADCM ADEN ADCK ADS3 ADS2 ADS1 ADS0 ADST ADSF F0H ADCRH PSSEL1 PSSEL0 ADC8 ADC Result Reg. High F1H ADCRL ADC Result Register Low F2H BITR1 Basic Interval Timer Data Register CKCTLR1 ADRST RCWDT WDTON BTCL BTS2 BTS1 BTS0 F3H SCMR MCC CS1 CS0 F4H WDTR WDTCL 7-bit Watchdog Timer Register WDTDR Watchdog Timer Data Register (Counter Register) F5H SSCR Stop & Sleep Mode Control Register F6H WTMR WTEN WTIN2 WTIN1 WTIN0 WTCK1 WTCK0 F7H PFDR PFDEN PFDM PFDS F8H PSR0 PWM3O PWM1O EC1E EC0E INT3E INT2E INT1E INT0E F9H PSR1 XTEN BUZO T2O T0O FAH Reserved FBH Reserved FCH PU0 R0 Pull-up Selection Register FDH PU1 R1 Pull-up Selection Register FEH PU4 R4 Pull-up Selection Register Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Table 8-2 Control Register Function Description

MAR. 2005 Ver 0.2

8.4 Addressing Mode

The MC800 series MCU uses six addressing modes;

• Register addressing
• Immediate addressing
• Direct page addressing
• Absolute addressing
• Indexed addressing
• Register-indirect addressing

8.4.1 Register Addressing

Register addressing accesses the A, X, Y, C and PSW.

8.4.2 Immediate Addressing → #imm

In this mode, second byte (operand) is accessed as a data imme- diately. Example: 0435 ADC #35H When G-flag is 1, then RAM address is defined by 16-bit address which is composed of 8-bit RAM paging register (RPR) and 8-bit immediate data. Example: G=1 E45535 LDM 35H,#55H

8.4.3 Direct Page Addressing → dp

In this mode, a address is specified within direct page. Example; G=0 FEH PU4 R4 Pull-up Selection Register EE6H ASIMR1 TXE RXE PS1 PS0 SL ISRM EE7H ASISR1 PE FE OVE EE8H BRGCR1 TPS2 TPS1 TPS0 MLD3 MLD2 MLD1 MLD0 EE9H RXR1 UART1 Receive Buffer Register TXR1 UART1 Transmit Shift Register 1. The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR. Caution) The registers of dark-shaded area can not be accessed by bit manipulation instruction such as "SET1, CLR1", but should be accessed by register operation instruction such as "LDM dp,#imm". Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Table 8-2 Control Register Function Description A+35H+C → A MEMORY 0F100H data ← 55H data 0135H 0F102H 0F101H

MAR. 2005 Ver 0.2 C535 LDA 35H ;A ←RAM[35H] 8.4.4 Absolute Addressing → !abs Absolute addressing sets corresponding memory data to Data, i.e. second byte (Operand I) of command becomes lower level ad- dress and third byte (Operand II) becomes upper level address. With 3 bytes command, it is possible to access to whole memory area. ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR, SBC, STA, STX, STY Example; 0735F0 ADC !0F035H ;A ←ROM[0F035H] The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135H regardless of G-flag. 983501 INC !0135H ;A ←ROM[135H]

8.4.5 Indexed Addressing

X indexed direct page (no offset) → {X} In this mode, a address is specified by the X register. ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Example; X=15H, G=1 LDA {X} ;ACC←RAM[X]. X indexed direct page, auto increment→ {X}+ In this mode, a address is specified within direct page by the X register and the content of X is increased by 1. LDA, STA Example; G=0, X=35H DB LDA {X}+ data 35H 0E551H data → A 0E550H 0F100H data 0F035H 0F102H 0F101H A+data+C → A address: 0F035 0F100H data 135H 0F102H 0F101H data+1 → data address: 0135 data 115H 0E550H data → A

MAR. 2005 Ver 0.2 X indexed direct page (8 bit offset) → dp+X This address value is the second byte (Operand) of command plus the data of X-register. And it assigns the memory in Direct page. ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY, XMA, ASL, DEC, INC, LSR, ROL, ROR Example; G=0, X=0F5H C645 LDA 45H+X Y indexed direct page (8 bit offset) → dp+Y This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead of X. Y indexed absolute → !abs+Y Sets the value of 16-bit absolute address plus Y-register data as Memory.This addressing mode can specify memory in whole ar- ea. Example; Y=55H D500FA LDA !0FA00H+Y

8.4.6 Indirect Addressing

Direct page indirect → [dp] Assigns data address to use for accomplishing command which sets memory data (or pair memory) by Operand. Also index can be used with Index register X,Y. JMP, CALL Example; G=0 3F35 JMP [35H] X indexed indirect → [dp+X] Processes memory data as Data, assigned by 16-bit pair memory which is determined by pair data [dp+X+1][dp+X] Operand plus X-register data in Direct page. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, X=10H data DB 35H data → A 36H → X data 3AH 0E551H data → A 0E550H 45H+0F5H=13AH 0F100H data → A data 0FA55H 0FA00H+55H=0FA55H FA 0F102H 0F101H 35H jump to 0FA00H 36H 0E30AH NEXT address 0E30AH

MAR. 2005 Ver 0.2 1625 ADC [25H+X] Y indexed indirect → [dp]+Y Processes memory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Direct page plus Y- register data. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, Y=10H 1725 ADC [25H]+Y Absolute indirect → [!abs] The program jumps to address specified by 16-bit absolute ad- dress. JMP Example; G=0 1F25E0 JMP [!0C025H] 35H 0E005H 0FA00H 36H 0E005H data ➌ A + data + C → A 25 + X(10) = 35H 25H 0E005H + Y(10) 0FA00H 26H 0E015H data = 0E015H A + data + C → A 0E025H jump to 0FA00H 0E026H 0E725H NEXT PROGRAM MEMORY þ address 0E30AH

MAR. 2005 Ver 0.2 9. I/O PORTS The MC80F0424/0432/0448 has eight ports (R0, R1, R2, R3, R4, R5, R6 and R7). These ports pins may be multiplexed with an al- ternate function for the peripheral features on the device. R3 port can drive maximum 20mA of high current in output low state, so it can directly drive LED device. All pins have data direction registers which can define these ports as output or input. A “1” in the port direction register configure the corresponding port pin as output. Conversely, write “0” to the corresponding bit to specify it as input pin. For example, to use the even numbered bit of R0 as output ports and the odd num- bered bits as input ports, write “55H” to address 0C1H (R0 port direction register) during initial setting as shown in Figure 9-1. All the port direction registers in the MC80F0424/0432/0448 have 0 written to them by reset function. On the other hand, its in- itial status is input. Figure 9-1 Example of port I/O assignment R0 and R0IO register: R0 is an 8-bit CMOS bidirectional I/O port (address 0C0H). Each I/O pin can independently used as an input or an output through the R0IO register (address 0C1H). The on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up selection register 0 (PU0). R1 and R1IO register: R1 is an 8-bit CMOS bidirectional I/O port (address 0C2H). Each I/O pin can independently used as an input or an output through the R1IO register (address 0C3H). The on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up selection register 1 (PU1). In addition, Port R1 is multiplexed with various special features. The control register PSR0 (address 0F8H) and PSR1 (address 0F9H) controls the selection of alternate function. After reset, this value is “0”, port may be used as normal I/O port. To use alternate function such as external interrupt, event counter input or timer clock output, write “1” in the corresponding bit of PSR0 or PSR1. Regardless of the direction register R1IO, PSR0 or PSR1 is selected to use as alternate functions, port pin can be used as a corresponding alternate features. I: INPUT PORT WRITE “55H” TO PORT R0 DIRECTION REGISTER 0 1 0 1 0 1 0 1 I O I O I O I O R0 data R1 data R0 direction R1 direction 0C0H 0C1H 0C2H 0C3H 7 6 5 4 3 2 1 0 BIT 7 6 5 4 3 2 1 0 PORT O: OUTPUT PORT Port Pin Alternate Function R10 R11 R12 R13 R14 R15 R16 R17 INT0 (External Interrupt 0) INT1 (External Interrupt 1) INT2 (External Interrupt 2) BUZO (Square-wave output for buzzer) T0O (Timer 0 Clock-out) EC0 (Event counter input to Counter 0) R0 Data Register ADDRESS: 0C0H RESET VALUE: 00H R07 R06 R05 R04 R03 R02 R01 R00 Port Direction R0 Direction Register R0IO ADDRESS: 0C1H RESET VALUE: 00H 0: Input 1: Output Input / Output data R0 Pull-up PU0 ADDRESS: 0FCH RESET VALUE: 00H Selection Register 0: Disable 1: Enable Pull-up Resister Selection

MAR. 2005 Ver 0.2 R2 and R2IO register: R2 is an 4-bit CMOS bidirectional I/O port (address 0C4H). Each I/O pin can independently used as an input or an output through the R2IO register (address 0C5H). In addition, Port R2 is multiplexed with various special features. The control register PSR1 (address 0F9H) controls the selection of alternate function. After reset, this value is “0”, port may be used as normal I/O port. To use alternate function such as sub clock input and sub clock output, write “1” in the corresponding bit of PSR1. R3 and R3IO register: R3 is an 8-bit CMOS bidirectional I/O port (address 0C6H). Each I/O pin can independently used as an input or an output through the R3IO register (address 0C7H). In addition, Port R3 is multiplexed with various special features. After reset, this value is "0", port may be used as normal I/O port. To use alternate function, write “1” in the corresponding bit of ASIMR1 and BRGCR1 register. R1 Data Register ADDRESS: 0C2H RESET VALUE: 00H R17 R16 R15 R14 R13 R12 R11 R10 Port Direction R1 Direction Register R1IO ADDRESS: 0C3H RESET VALUE: 00H 0: Input 1: Output Input / Output data R1 Pull-up PU1 ADDRESS: 0FDH RESET VALUE: 00H Selection Register 0: Disable 1: Enable Pull-up Resister Selection PWM1 XTEN T2O T0O Timer2/0 Output 0 : R52/R514 Port 1 : Timer2/0 Output Sub Clock Selection 0: R21,R22 Port 1: SXin, SXout Port Port / INT Selection 0: R10, R11,R12, R50 1: INT0, INT1,INT2, INT3 Port / EC Selection 0: R15, R51 1: EC0, EC1 PSR0 INT2E INT0E INT1E INT3E EC0E EC1E PWM3 Port / PWM3(1) Selection 0: R54 (P53) 1: PWM3O/T3O port (PWM1O/T1O port) PSR1 ADDRESS: 0F9H RESET VALUE: ---- 0000B BUZO R13/BUZO Selection 0: R13 port (Turn off buzzer) 1: BUZO port (Turn on buzzer) ADDRESS: 0F8H RESET VALUE: 0000 0000B Port Pin Alternate Function R20 R21 R22 R23 SXIN (sub clock input) SXOUT (sub clock output) Port Pin Alternate Function R30 R31 R32 R33 R33 R33 R33 R37 ACLK1 (UART1 clock input) RxD1 (UART1 data input) TxD1(UART1 data output)- R2 Data Register ADDRESS: 0C4H RESET VALUE: ----0000B R23 R22 R21 R20 Port Direction R2 Direction Register R2IO ADDRESS: 0C5H RESET VALUE: ----0000B 0: Input 1: Output Input / Output data

MAR. 2005 Ver 0.2 R4 and R4IO register: R4 is an 8-bit CMOS bidirectional I/O port (address 0C8H). Each I/O pin can independently used as an input or an output through the R4IO register (address 0C9H). The on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up selection register 4 (PU4). In addition, Port R4 is multiplexed with various special features. After reset, this value is “0”, port may be used as normal I/O port. To use alternate function, write “1” in the corresponding bit of ASIMR and BRGCR register. R5 and R5IO register: R5 is an 5-bit CMOS bidirectional I/O port (address 0CAH). Each I/O pin can independently used as an input or an output through the R5IO register (address 0CBH). In addition, Port R5 is multiplexed with various special features. The control register PSR0 (address 0F8H) and PSR1 (address 0F9H) controls the selection of alternate function. After reset, this value is “0”, port may be used as normal I/O port. To use alternate function such as external interrupt, event counter input, timer clock output or PWM output, write “1” in the corre- sponding bit of PSR0 or PSR1. Regardless of the direction regis- ter R5IO, PSR0 or PSR1 is selected to use as alternate functions, port pin can be used as a corresponding alternate features. Port Pin Alternate Function R40 R41 R42 R43 R44 R45 R46 R47 SCK (SIO clock input/output) SI (SIO data input) SO (Serial1 data output) ACLK (Asynchronous serial clock input) RxD (Asynchronous serialdata input) TxD (Asynchronous serial data output) R3 Data Register ADDRESS: 0C6H RESET VALUE: 00H R37 R36 R35 R34 R33 R32 R31 R30 Port Direction R3 Direction Register R3IO ADDRESS: 0C7H RESET VALUE: 00H 0: Input 1: Output Input / Output data Port Pin Alternate Function R50 R51 R52 R53 R54 INT3 (External Interrupt 3) EC1 (Event counter input to Counter 2) T2O (Timer 2 Clock-out) PWM1O (PWM1 output) / T1O PWM3O (PWM3 output) / T3O R4 Data Register ADDRESS: 0C8H RESET VALUE: 00H R47 R46 R45 R44 R43 R42 R41 R40 Port Direction R4 Direction Register R4IO ADDRESS: 0C9H RESET VALUE: 00H 0: Input 1: Output Input / Output data R4 Pull-up PU4 ADDRESS: 0FEH RESET VALUE: 00H Selection Register 0: Disable 1: Enable Pull-up Resister Selection R5 Data Register ADDRESS: 0CAH RESET VALUE: ---00000B R54 R53 R52 R51 R50 Port Direction R5 Direction Register R5IO ADDRESS: 0CBH RESET VALUE: ---00000B 0: Input 1: Output Input / Output data

MAR. 2005 Ver 0.2 R6 and R6IO register: R6 is an 8-bit CMOS bidirectional I/O port (address 0CCH). Each I/O pin can independently used as an input or an output through the R6IO register (address 0CDH). In addition, Port R6 is multiplexed with AD converter analog in- put AN0~AN7. R6IO (address CDH) controls the direction of the R6 pins, except when they are being used as analog input channels. The user don’t have to keep the pins configured as inputs when using them as an- alog input channels, because the analog input mode is activated by the setting of ADC enable bit of ADCM register and ADC channel selection. R7 and R7IO register: R7 is an 8-bit CMOS bidirectional I/O port (address 0CEH). Each I/O pin can independently used as an input or an output through the R7IO register (address 0CFH). The on-chip pull-up resistor can be connected to them in 1-bit units with a R7 pull-up selection register (PU7). In addition, Port R7 is multiplexed with AD converter analog in- put channel AN8~AN15. R7IO (address CFH) controls the direction of the R7 pins, except when they are being used as analog input channels. The user don’t have to keep the pins configured as inputs when using them as an- alog input channels, because the analog input mode is activated by the setting of ADC enable bit of ADCM register and ADC channel selection. Port Pin Alternate Function R60 R61 R62 R63 R64 R65 R66 R67 AN0 (ADC input channel 0) AN1 (ADC input channel 1) AN2 (ADC input channel 2) AN3 (ADC input channel 3) AN4 (ADC input channel 4) AN5 (ADC input channel 5) AN6 (ADC input channel 6) AN7 (ADC input channel 7) R6 Data Register ADDRESS: 0CCH RESET VALUE: 00H R67 R66 R65 R64 R63 R62 R61 R60 Input / Output data Port Direction R6 Direction Register R6IO ADDRESS: 0CDH RESET VALUE: 00H 0: Input 1: Output Port Pin Alternate Function R70 R71 R72 R73 R74 R75 R76 R77 AN8 (ADC input channel 8) AN9 (ADC input channel 9) AN10 (ADC input channel 10) AN11 (ADC input channel 11) AN12 (ADC input channel 12) AN13 (ADC input channel 13) AN14 (ADC input channel 14) AN15 (ADC input channel 15) R7 Data Register ADDRESS: 0CEH RESET VALUE: 00H R77 R76 R75 R74 R73 R72 R71 R70 Input / Output data Port Direction R7 Direction Register R7IO ADDRESS: 0CFH RESET VALUE: 00H 0: Input 1: Output R7 Pull-up PU7 ADDRESS: 0FFH RESET VALUE: 00H Selection Register 0: Disable 1: Enable Pull-up Resister Selection

MAR. 2005 Ver 0.2 11. BASIC INTERVAL TIMER The MC80F0424/0432/0448 has one 8-bit Basic Interval Timer that is free-run and can not stop. Block diagram is shown in Fig- ure 11-1. In addition, the Basic Interval Timer generates the time base for watchdog timer counting. It also provides a Basic inter- val timer interrupt (BITIF). The 8-bit Basic interval timer register (BITR) is increased every internal count pulse which is divided by prescaler. Since prescal- er has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 of the oscillator frequency. As the count overflow from FFH to 00H, this overflow causes the interrupt to be generated. The Basic Interval Timer is controlled by the clock control register (CKCTLR) shown in Figure 10-2. When write "1" to bit BTCL of CKCTLR, BITR register is cleared to "0" and restart to count-up. The bit BTCL becomes "0" after one machine cycle by hardware. If the STOP instruction executed after writing "1" to bit RCWDT of CKCTLR, it goes into the internal RC oscillated watchdog tim- er mode. In this mode, all of the block is halted except the internal RC oscillator, Basic Interval Timer and RC Watchdog Timer. More detail informations are explained in Power Saving Func- tion. The bit WDTON decides Watchdog Timer or the normal 7- bit timer. Source clock can be selected by lower 3 bits of CKCTLR. BITR and CKCTLR are located at same address, and address 0F2H is read as a BITR, and written to CKCTLR. Figure 11-1 Block Diagram of Basic Interval Timer Table 11-1 Basic Interval Timer Interrupt Period MUX Basic Interval BITR Select Input clock Basic Interval Timer source clock 8-bit up-counter BTS[2:0] BTCL ÷1024 ÷512 ÷256 ÷128 ÷64 ÷32 ÷16 CKCTLR clear overflow Internal bus line clock control register [0F2H] [0F2H] BITIF Read XIN PIN Prescaler Timer Interrupt Internal RC OSC RCWDT RCWDT RCWDT Watchdog timer (WDTCK) CKCTLR [2:0] Source clock Interrupt (overflow) Period (ms) @ fXIN = 8MHz 000 001 010 011 100 101 110 111 fXIN÷8 fXIN÷16 fXIN÷32 fXIN÷64 fXIN÷128 fXIN÷256 fXIN÷512 fXIN÷1024 0.256 0.512 1.024 2.048 4.096 8.192 16.384 32.768

MAR. 2005 Ver 0.2 Figure 11-2 BITR: Basic Interval Timer Mode Register Example 1: Interrupt request flag is generated every 8.192ms at 4MHz. LDM CKCTLR,#1BH SET1 BITE EI Example 2: Interrupt request flag is generated every 8.192ms at 8MHz. LDM CKCTLR,#1CH SET1 BITE EI BTCL RCWDT ADRST BTS1 Basic Interval Timer source clock select 000: fXIN ÷ 8 001: fXIN ÷ 16 010: fXIN ÷ 32 011: fXIN ÷ 64 100: fXIN ÷ 128 101: fXIN ÷ 256 110: fXIN ÷ 512 111: fXIN ÷ 1024 Clear bit 0: Normal operation (free-run) 1: Clear 8-bit counter (BITR) to “0”. This bit becomes 0 automatically INITIAL VALUE: 0-010111B ADDRESS: 0F2H after one machine cycle, and starts counting. CKCTLR INITIAL VALUE: Undefined ADDRESS: 0F2H BITR Both register are in same address, when write, to be a CKCTLR, when read, to be a BITR. Caution: 8-BIT FREE-RUN BINARY COUNTER WDTON BTS0 BTS2 BTCL BTCL Watchdog timer Enable bit 0: Operate as 7-bit Timer See the section “Watchdog Timer”. Address Fail Reset Selection 0: Enable Address Fail Reset 1: Disable Address Fail Reset 1: Enable Watchdog Timer operation 0: Disable Internal RC Watchdog Timer 1: Enable Internal RC Watchdog Timer RC Watchdog Selection bit

MAR. 2005 Ver 0.2 12. WATCHDOG TIMER The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and resumes the CPU to the normal state. The watchdog timer signal for detecting mal- function can be selected either a reset CPU or a interrupt request. When the watchdog timer is not being used for malfunction de- tection, it can be used as a timer to generate an interrupt at fixed intervals. The watchdog timer has two types of clock source. The first type is an on-chip RC oscillator which does not require any external components. This RC oscillator is separated from the external os- cillator of the XIN pin. It means that the watchdog timer will run, even if the clock on the XIN pin of the device has been stopped, for example, by entering the STOP mode. The other type is a prescaler system clock. The watchdog timer consists of 7-bit binary counter and the watchdog timer data register. When the value of 7-bit binary counter is equal to the lower 7 bits of WDTR, the interrupt re- quest flag is generated. This can be used as Watchdog timer inter- rupt or reset the CPU in accordance with the bit WDTON. Note: Because the watchdog timer counter is enabled af- ter clearing Basic Interval Timer, after the bit WDTON set to "1", maximum error of timer is depend on prescaler ratio of Basic Interval Timer. The 7-bit binary counter is cleared by setting WDTCL(bit7 of WDTR) and the WDTCL is cleared automatically after 1 machine cycle. The RC oscillated watchdog timer is activated by setting the bit RCWDT as shown below. LDM CKCTLR,#3FH; enable the RC-OSC WDT LDM WDTR,#0FFH ; set the WDT period LDM SSCR, #5AH ;ready for STOP mode STOP ; enter the STOP mode NOP NOP ; RC-OSC WDT running The RC-WDT oscillation period is vary with temperature, VDD and process variations from part to part (approximately, 33~100uS). The following equation shows the RCWDT oscillat- ed watchdog timer time-out. TRCWDT=CLKRCWDT×28×WDTR + (CLKRCWDT×28)/2 where, CLKRCWDT = 33~100uS In addition, this watchdog timer can be used as a simple 7-bit tim- er by interrupt WDTIF. The interval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is as below. TWDT = (WDTR+1) × Interval of BIT Figure 12-1 Block Diagram of Watchdog Timer to reset CPU BASIC INTERVAL TIMER Count enable Watchdog 7-bit compare data comparator Watchdog Timer interrupt clear clear WDTIF Counter (7-bit) WDTCL “0” “1” WDTON in CKCTLR [0F2H] OVERFLOW Watchdog Timer Register WDTR Internal bus line [0F4H] source

MAR. 2005 Ver 0.2 14. TIMER/EVENT COUNTER The MC80F0424/0432/0448 has five Timer/Counter registers. Each module can generate an interrupt to indicate that an event has occurred (i.e. timer match). Timer 0 and Timer 1 are can be used either two 8-bit Timer/ Counter or one 16-bit Timer/Counter with combine them. Also Timer 2 and Timer 3 are same. Timer 4 is 16-bit Timer/Counter. In the “timer” function, the register is increased every internal clock input. Thus, one can think of it as counting internal clock input. Since a least clock consists of 2 and most clock consists of 2048 oscillator periods, the count rate is 1/2 to 1/2048 of the os- cillator frequency. In the “counter” function, the register is increased in response to a 0-to-1 (rising edge) transition at its corresponding external input pin, EC0(Timer 0) or EC1(Timer 2). In addition the “capture” function, the register is increased in re- sponse external or internal clock sources same with timer or counter function. When external interrupt edge input, the count register is captured into capture data register CDRx. It has seven operating modes: "8-bit timer/counter", "16-bit tim- er/counter", "8-bit capture", "16-bit capture", "8-bit compare out- put", "16-bit compare output" and "10-bit PWM" which are selected by bit in Timer mode register TMx as shown in Table 14- 1, Table 14-2, Table 14-3, Figure 14-10, Figure 14-2 and Figure 14-3. In 8/16 Timer mode, pin R14/T0O and R52/T2O can output Timer0 or Timer2 output by setting "1" respectively to bit T0O and T2O in PSR0 register. In operation of Timer 2 and Timer 3, their operations are same as Timer 0 and Timer 1, respectively as shown in Table 14-2. 16BIT CAP0 CAP1 PWM1E T0CK [2:0] T1CK [1:0] PWM1O TIMER 0 TIMER 1 XXX XX 8-bit Timer 8-bit Timer 111 XX 8-bit Event counter 8-bit Capture XXX XX 8-bit Capture 8-bit Compare Output XXX XX 8-bit Timer/Counter 10-bit PWM XXX 16-bit Timer 111 16-bit Event counter XXX 16-bit Capture XXX 16-bit Compare Output Table 14-1 Operating Modes of Timer 0, 1 1. X: The value “0” or “1” corresponding to user operation. 16BIT CAP2 CAP3 PWM3E T2CK [2:0] T3CK [1:0] PWM3O TIMER 2 TIMER 3 XXX XX 8-bit Timer 8-bit Timer 111 XX 8-bit Event counter 8-bit Capture XXX XX 8-bit Capture 8-bit Compare Output XXX XX 8-bit Timer/Counter 10-bit PWM XXX 16-bit Timer 111 16-bit Event counter XXX 16-bit Capture XXX 16-bit Compare Output Table 14-2 Operating Modes of Timer 2, 3 1. X: The value “0” or “1” corresponding to user operation.

MAR. 2005 Ver 0.2 CAP4 T4CK[2:0] TIMER 4 XXX1 16-bit Timer XXX 16-bit Capture Table 14-3 Operating Modes of Timer 4 1. X: The value “0” or “1” corresponding to user operation.

MAR. 2005 Ver 0.2 Figure 14-1 TM0, TM1 Registers BTCL 16BIT POL T1CN INITIAL VALUE: 00H ADDRESS: 0D2H TM1 T1ST T1CK0 T1CK1 PWM1E CAP1 Bit Name Bit Position

Description

TM1.7 0: PWM Duty Active Low 1: PWM Duty Active High 16BIT TM1.6 0: 8-bit Mode 1: 16-bit Mode PWMIE TM1.5 0: Disable PWM 1: Enable PWM CAP1 TM1.4 0: Timer/Counter mode 1: Capture mode selection flag T1CK1 T1CK0 TM1.3 TM1.2 00: 8-bit Timer, Clock source is fXIN 01: 8-bit Timer, Clock source is fXIN ÷ 2 10: 8-bit Timer, Clock source is fXIN ÷ 8 11: 8-bit Timer, Clock source is Using the Timer 0 Clock T1CN TM1.1 0: Timer count pause 1: Timer count start T1ST TM1.0 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again. BTCL T0CN INITIAL VALUE: --000000B ADDRESS: 0D0H TM0 T0ST T0CK0 T0CK1 CAP0 T0CK2 Bit Name Bit Position TM0.5 0: Timer/Counter mode 1: Capture mode selection flag T0CK2 T0CK1 T0CK0 TM0.4 TM0.3 TM0.2 000: 8-bit Timer, Clock source is fXIN ÷ 2 001: 8-bit Timer, Clock source is fXIN ÷ 4 010: 8-bit Timer, Clock source is fXIN ÷ 8 011: 8-bit Timer, Clock source is fXIN ÷ 32 100: 8-bit Timer, Clock source is fXIN ÷ 128 101: 8-bit Timer, Clock source is fXIN ÷ 512 110: 8-bit Timer, Clock source is fXIN ÷ 2048 111: EC0 (External clock) T0CN TM0.1 0: Timer count pause 1: Timer count start T0ST TM0.0 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again. INITIAL VALUE: 0FFH ADDRESS: 0D1H TDR0 Read: Count value read Write: Compare data write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W INITIAL VALUE: 0FFH ADDRESS: 0D3H TDR1 R/W R/W R/W R/W R/W R/W R/W R/W

MAR. 2005 Ver 0.2 Figure 14-2 TM2, TM3 Registers BTCL 16BIT POL T3CN INITIAL VALUE: 00H ADDRESS: 0D8H TM3 T3ST T3CK0 T3CK1 PWM3E CAP3 Bit Name Bit Position TM3.7 0: PWM Duty Active Low 1: PWM Duty Active High 16BIT TM3.6 0: 8-bit Mode 1: 16-bit Mode PWM3E TM3.5 0: Disable PWM 1: Enable PWM CAP3 TM3.4 0: Timer/Counter mode 1: Capture mode selection flag T3CK1 T3CK0 TM3.3 TM3.2 00: 8-bit Timer, Clock source is fXIN 01: 8-bit Timer, Clock source is fXIN ÷ 4 10: 8-bit Timer, Clock source is fXIN ÷ 16 11: 8-bit Timer, Clock source is Using the Timer 2 Clock T3CN TM3.1 0: Timer count pause 1: Timer count start T3ST TM3.0 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again. BTCL T2CN INITIAL VALUE: --000000B ADDRESS: 0D6H TM2 T2ST T2CK0 T2CK1 CAP2 T2CK2 Bit Name Bit Position TM2.5 0: Timer/Counter mode 1: Capture mode selection flag T2CK2 T2CK1 T2CK0 TM2.4 TM2.3 TM2.2 000: 8-bit Timer, Clock source is fXIN ÷ 2 001: 8-bit Timer, Clock source is fXIN ÷ 4 010: 8-bit Timer, Clock source is fXIN ÷ 8 011: 8-bit Timer, Clock source is fXIN ÷ 16 100: 8-bit Timer, Clock source is fXIN ÷ 64 101: 8-bit Timer, Clock source is fXIN ÷ 256 110: 8-bit Timer, Clock source is fXIN ÷ 1024 111: EC1 (External clock) T2CN TM2.1 0: Timer count pause 1: Timer count start T2ST TM2.0 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again. INITIAL VALUE: 0FFH ADDRESS: 0D7H TDR2 Read: Count value read Write: Compare data write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W INITIAL VALUE: 0FFH ADDRESS: 0D9H TDR3 R/W R/W R/W R/W R/W R/W R/W R/W

MAR. 2005 Ver 0.2 Figure 14-3 TM4 Registers 14.1 8-bit Timer / Counter Mode The MC80F0424/0432/0448 has four 8-bit Timer/Counters, Tim- er 0, Timer 1, Timer 2, Timer 3. The Timer 0, Timer 1 are shown in Figure 14-4 and Timer 2, Timer 3 are shown in Figure 14-5. The “timer” or “counter” function is selected by control registers TM0, TM1, TM2, TM3 as shown in Figure 14-1. To use as an 8- bit timer/counter mode, bit CAP0, CAP1, CAP2, or CAP3 of TMx should be cleared to “0” and 16BIT of TM1 or TM3 should be cleared to "0"(Figure 14-4). These timers have each 8-bit count register and data register. The count register is increased by every internal or external clock input. The internal clock has a prescaler divide ratio option of 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048 or external clock (selected by control bits TxCK0, TxCK1, TxCK2 of register TMx). BTCL T4CN INITIAL VALUE: --000000B ADDRESS: 0DCH TM4 T4ST T4CK0 T4CK1 CAP4 T4CK2 Bit Name Bit Position TM4.5 0: Timer/Counter mode 1: Capture mode selection flag T4CK2 T4CK1 T4CK0 TM4.4 TM4.3 TM4.2 000: 8-bit Timer, Clock source is fXIN ÷ 2 001: 8-bit Timer, Clock source is fXIN ÷ 4 010: 8-bit Timer, Clock source is fXIN ÷ 8 011: 8-bit Timer, Clock source is fXIN ÷ 16 100: 8-bit Timer, Clock source is fXIN ÷ 64 101: 8-bit Timer, Clock source is fXIN ÷ 256 110: 8-bit Timer, Clock source is fXIN ÷ 1024 111: 8-bit Timer, Clock source is fXIN ÷ 2048 T4CN TM4.1 0: Timer count pause 1: Timer count start T4ST TM4.0 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again. INITIAL VALUE: 0FFH ADDRESS: 0DDH TDR4H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W INITIAL VALUE: 0FFH ADDRESS: 0DEH TDR4L R/W R/W R/W R/W R/W R/W R/W R/W

MAR. 2005 Ver 0.2 Figure 14-4 8-bit Timer/Counter 0, 1 EC0 PIN ÷ 2 ÷ 4 ÷ 8 XIN PIN MUX Prescaler clear 0: Stop 1: Clear and start T0ST T0CK[2:0] 111 000 001 010 T0CN MUX T1IF clear 0: Stop 1: Clear and start T1ST T1CK[1:0] TIMER 1 INTERRUPT ÷ 1 ÷ 2 ÷ 8 TDR0 (8-bit) TDR1 (8-bit) T1 (8-bit) T0 (8-bit) Comparator Comparator TIMER 0 TIMER 1 BTCL T0CN INITIAL VALUE: --000000B ADDRESS: 0D0H TM0 T0ST T0CK0 T0CK1 CAP0 T0CK2 X X X X X means the value of "0" or "1" corresponding to user operation ÷ 32 ÷ 128 ÷ 512 ÷ 2048 011 100 101 110 T0IF TIMER 0 INTERRUPT T1CN INITIAL VALUE: 00H ADDRESS: 0D2H TM1 X BTCL 16BIT POL T1CN T1ST T1CK0 T1CK1 PWM1E CAP1 X X X X X RISING EDGE DETECTOR F/F R14/T0O F/F R53/PWM1O/T1O

MAR. 2005 Ver 0.2 Figure 14-5 8-bit Timer/Counter 2, 3 EC1 PIN ÷ 2 ÷ 4 ÷ 8 XIN PIN MUX Prescaler clear 0: Stop 1: Clear and start T2ST T2CK[2:0] 111 000 001 010 T2CN MUX T3IF clear 0: Stop 1: Clear and start T3ST T3CK[1:0] TIMER 3 INTERRUPT ÷ 1 ÷ 4 ÷ 16 TDR2 (8-bit) TDR3 (8-bit) T3 (8-bit) T2 (8-bit) Comparator Comparator TIMER 2 TIMER 3 BTCL T2CN INITIAL VALUE: --000000B ADDRESS: 0D6H TM2 T2ST T2CK0 T2CK1 CAP2 T2CK2 X X X X X means the value of "0" or "1" corresponding to user operation ÷ 16 ÷ 64 ÷ 256 ÷ 1024 011 100 101 110 T2IF TIMER 2 INTERRUPT T3CN INITIAL VALUE: 00H ADDRESS: 0D8H TM3 X BTCL 16BIT POL T3CN T3ST T3CK0 T3CK1 PWM3E CAP3 X X X X X RISING EDGE DETECTOR F/F R52/T2O F/F R54/PWM3O/T3O

MAR. 2005 Ver 0.2 Example 1: Timer0 = 2ms 8-bit timer mode at 4MHz Timer1 = 0.5ms 8-bit timer mode at 4MHz Timer2 = 1ms 8-bit timer mode at 4MHz Timer3 = 1ms 8-bit timer mode at 4MHz LDM TDR0,#249 LDM TDR1,#249 LDM TDR2,#249 LDM TDR3,#249 LDM TM0,#0000_1111B LDM TM1,#0000_1011B LDM TM2,#0000_1111B LDM TM3,#0000_1011B SET1 T0E SET1 T1E SET1 T2E SET1 T3E EI Example 2: Timer0 = 8-bit event counter mode Timer1 = 0.5ms 8-bit timer mode at 4MHz Timer2 = 8-bit event counter mode Timer3 = 1ms 8-bit timer mode at 4MHz LDM TDR0,#249 LDM TDR1,#249 LDM TDR2,#249 LDM TDR3,#249 LDM TM0,#0001_1111B LDM TM1,#0000_1011B LDM TM2,#0001_1111B LDM TM3,#0000_1011B SET1 T0E SET1 T1E SET1 T2E SET1 T3E EI These timers have each 8-bit count register and data register. The count register is increased by every internal or external clock in- put. The internal clock has a prescaler divide ratio option of 2, 4, 8, 32, 128, 512, 2048 selected by control bits T0CK[2:0] of reg- ister TM0 or 1, 2, 8 selected by control bits T1CK[1:0] of register TM1, or 2, 4, 8, 16, 64, 256, 1024 selected by control bits T2CK[2:0] of register TM2, or 1, 4, 16 selected by control bits T3CK[1:0] of register TM3. In the Timer 0, timer register T0 in- creases from 00H until it matches TDR0 and then reset to 00H. The match output of Timer 0 generates Timer 0 interrupt (latched in T0IF bit). In counter function, the counter is increased every 0-to-1(1-to-0) (rising & falling edge) transition of EC0 pin. In order to use counter function, the bit EC0 of the Port Selection Regis- ter(PSR0.4) is set to "1". The Timer 0 can be used as a counter by pin EC0 input, but Timer 1 can not. Likewise, In order to use Timer2 as counter function, the bit EC1 of the Port Selection Register(PSR0.5) is set to "1". The Timer 2 can be used as a counter by pin EC1 input, but Timer 3 can not. 14.1.1 8-bit Timer Mode In the timer mode, the internal clock is used for counting up. Thus, you can think of it as counting internal clock input. The contents of TDRn are compared with the contents of up-counter, Tn. If match is found, a timer n interrupt (TnIF) is generated and the up-counter is cleared to 0. Counting up is resumed after the up-counter is cleared. As the value of TDRn is changeable by software, time interval is set as you want. Figure 14-6 Timer Mode Timing Chart n-2 n n-1 n Source clock Up-counter TDR1 T1IF interrupt Start count Match Detect Counter Clear

MAR. 2005 Ver 0.2 Figure 14-9 Count Operation of Timer / Event counter Timer 1 (T1IF) Interrupt TDR1 TIME Occur interrupt Occur interrupt stop clear & start disable enable Start & Stop T1ST T1CN Control count up-count T1ST = 0 T1ST = 1 T1CN = 0 T1CN = 1

MAR. 2005 Ver 0.2 14.2 16-bit Timer / Counter Mode The Timer register is being run with all 16 bits. A 16-bit timer/ counter register T0, T1 are incremented from 0000H until it matches TDR0, TDR1 and then resets to 0000H. The match out- put generates Timer 0 interrupt. The clock source of the Timer 0 is selected either internal or ex- ternal clock by bit T0CK[2:0]. In 16-bit mode, the bits T1CK[1:0] and 16BIT of TM1 should be set to "1" respectively as shown in Figure 14-10. Likewise, A 16-bit timer/counter register T2, T3 are incremented from 0000H until it matches TDR2, TDR3 and then resets to 0000H. The match output generates Timer 2 interrupt. The clock source of the Timer 2 is selected either internal or ex- ternal clock by bit T2CK[2:0]. In 16-bit mode, the bits T3CK[1:0] and 16BIT of TM3 should be set to "1" respectively as shown in Figure 14-11. Even if the Timer 0 (including Timer 1) is used as a 16-bit timer, the Timer 2 and Timer 3 can still be used as either two 8-bit timer or one 16-bit timer by setting the TM2. Reversely, even if the Timer 2 (including Timer 3) is used as a 16-bit timer, the Timer 0 and Timer 1 can still be used as 8-bit timer independently. A 16-bit timer/counter 4 register T4H, T4L are increased from 0000H until it matches TDR4H, TDR4L and then resets to 0000H. The match output generates Timer 4 interrupt. Timer/Counter 4 is 16 bit mode as shown in Figure 14-12. Figure 14-10 16-bit Timer/Counter for Timer 0, 1 clear 0: Stop 1: Clear and start T0ST T0CN TDR1 + TDR0 Comparator TIMER 0 + TIMER 1 → TIMER 0 (16-bit) Higher byte Lower byte (16-bit) COMPARE DATA T1 + T0 (16-bit) (Not Timer 1 interrupt) RISING EDGE BTCL T0CN INITIAL VALUE: --000000B ADDRESS: 0D0H TM0 T0ST T0CK0 T0CK1 CAP0 T0CK2 X X X X X means the value of "0" or "1" corresponding to user operation INITIAL VALUE: 00H ADDRESS: 0D2H TM1 X BTCL 16BIT POL T1CN T1ST T1CK0 T1CK1 PWM1E CAP1 X X X EC0 PIN ÷ 2 ÷ 4 ÷ 8 XIN PIN MUX Prescaler T0CK[2:0] 111 000 001 010 ÷ 32 ÷ 128 ÷ 512 ÷ 2048 011 100 101 110 DETECTOR T0IF TIMER 0 INTERRUPT R14/T0O F/F

MAR. 2005 Ver 0.2 Figure 14-11 16-bit Timer/Counter for Timer 2, 3 14.3 8-bit Compare Output (16-bit) The MC80F0424/0432/0448 has a function of Timer Compare Output. To pulse out, the timer match can goes to port pin(T0O, PWM1O, T2O, PWM3O) as shown in Figure 14-4, Figure 14-5 and Figure 14-12. In this mode, the bit PWM1O and PWM3O of PSR0 register should be set to “1”, and the bit PWM1E/PWM3E of timer1/timer3 mode register (TM1/TM3) should be set to “0”. These Compare output pins output the signal having a 50:50 duty square wave, and output frequency is same as below equation. clear 0: Stop 1: Clear and start T2ST T2CN TDR3 + TDR2 Comparator TIMER 2 + TIMER 3 → TIMER 2 (16-bit) Higher byte Lower byte (16-bit) COMPARE DATA T3 + T2 (16-bit) (Not Timer 3 interrupt) RISING EDGE BTCL T2CN INITIAL VALUE: --000000B ADDRESS: 0D6H TM2 T2ST T2CK0 T2CK1 CAP2 T2CK2 X X X X X means the value of "0" or "1" corresponding to user operation INITIAL VALUE: 00H ADDRESS: 0D8H TM3 X BTCL 16BIT POL T3CN T3ST T3CK0 T3CK1 PWM3E CAP3 X X X EC1 PIN ÷ 2 ÷ 4 ÷ 8 XIN PIN MUX Prescaler T2CK[2:0] 111 000 001 010 ÷ 16 ÷ 64 ÷ 256 ÷ 1024 011 100 101 110 DETECTOR T2IF TIMER 2 INTERRUPT R52/T2O F/F fCOMP Oscillation Frequency Prescaler Value TDR 1 )

MAR. 2005 Ver 0.2 In addition, 16-bit Compare output mode is available, also. Figure 14-12 Timer 4 for only 16 bit mode 14.4 8-bit Capture Mode The Timer 0 capture mode is set by bit CAP0 of timer mode reg- ister TM0 (bit CAP1 of timer mode register TM1 for Timer 1) as shown in Figure 14-13. Likewise, the Timer 2 capture mode is set by bit CAP2 of timer mode register TM2 (bit CAP3 of timer mode register TM3 for Timer 3) as shown in Figure 14-14. The Timer/Counter register is increased in response internal or external input. This counting function is same with normal timer mode, and Timer interrupt is generated when timer register T0 (T1, T2, T3) increases and matches TDR0 (TDR1, TDR2, TDR3). This timer interrupt in capture mode is very useful when the pulse width of captured signal is more wider than the maximum period of Timer. For example, in Figure 14-16, the pulse width of captured signal is wider than the timer data value (FFH) over 2 times. When ex- ternal interrupt is occurred, the captured value (13H) is more little than wanted value. It can be obtained correct value by counting the number of timer overflow occurrence. Timer/Counter still does the above, but with the added feature that a edge transition at external input INTx pin causes the current value in the Timer x register (T0,T1,T2,T3), to be captured into registers CDRx (CDR0, CDR1, CDR2, CDR3), respectively. Af- ter captured, Timer x register is cleared and restarts by hardware. It has three transition modes: "falling edge", "rising edge", "both edge" which are selected by interrupt edge selection register IEDS. Refer to “19.5 External Interrupt” on page 96. In addition, the transition at INTn pin generate an interrupt. Note: The CDRn and TDRn are in same address.In the capture mode, reading operation is read the CDRn, not TDRn because path is opened to the CDRn. clear 0: Stop 1: Clear and start T4ST T4CN TDR4H + TDR4L Comparator Higher byte Lower byte (16-bit) COMPARE DATA T4H + T4L (16-bit) INITIAL VALUE: 00H ADDRESS: 0DCH TM4 X means the value of "0" or "1" corresponding to user operation BTCL T4CN T4ST T4CK0 T4CK1 CAP4 T4CK2 X X X X X X X ÷ 2 ÷ 4 ÷ 8 XIN PIN MUX Prescaler T4CK[2:0] 111 000 001 010 ÷ 16 ÷ 64 ÷ 256 ÷ 1024 011 100 101 110 T4IF TIMER 4 INTERRUPT ÷ 2048

MAR. 2005 Ver 0.2 Figure 14-13 8-bit Capture Mode for Timer 0, 1 INT0IF 0: Stop 1: Clear and start T0ST INT0 INTERRUPT T0CN CDR0 (8-bit) T0 (8-bit) “01” “10” “11” Capture IEDS[1:0] EC0 PIN ÷ 2 ÷ 4 ÷ 8 XIN PIN MUX Prescaler T0CK[2:0] 111 000 001 010 MUX T1CK[1:0] ÷ 1 ÷ 2 ÷ 8 ÷ 32 ÷ 128 ÷ 512 ÷ 2048 011 100 101 110 INT0 PIN INT1IF 0: Stop 1: Clear and start T1ST INT1 INTERRUPT T1CN CDR1 (8-bit) T1 (8-bit) “01” “10” “11” Capture IEDS[3:2] INT1 PIN BTCL T0CN INITIAL VALUE: --000000B ADDRESS: 0D0H TM0 T0ST T0CK0 T0CK1 CAP0 T0CK2 X X X X X means the value of "0" or "1" corresponding to user operation INITIAL VALUE: 00H ADDRESS: 0D2H TM1 X BTCL 16BIT POL T1CN T1ST T1CK0 T1CK1 PWM1E CAP1 X X X X X Rising Edge Detector clear clear

MAR. 2005 Ver 0.2 Figure 14-14 8-bit Capture Mode for Timer 2, 3 INT2IF 0: Stop 1: Clear and start T2ST INT2 INTERRUPT T2CN CDR2 (8-bit) T2 (8-bit) “01” “10” “11” Capture IEDS[5:4] EC1 PIN ÷ 2 ÷ 4 ÷ 8 XIN PIN MUX Prescaler T2CK[2:0] 111 000 001 010 MUX T3CK[1:0] ÷ 1 ÷ 4 ÷ 16 ÷ 16 ÷ 64 ÷ 256 ÷ 1024 011 100 101 110 INT2 PIN INT3IF 0: Stop 1: Clear and start T3ST INT3 INTERRUPT T3CN CDR3 (8-bit) T3 (8-bit) “01” “10” “11” Capture IEDS[7:6] INT3 PIN BTCL T2CN INITIAL VALUE: --000000B ADDRESS: 0D6H TM2 T2ST T2CK0 T2CK1 CAP2 T2CK2 X X X X X means the value of "0" or "1" corresponding to user operation INITIAL VALUE: 00H ADDRESS: 0D8H TM3 X BTCL 16BIT POL T3CN T3ST T3CK0 T3CK1 PWM3E CAP3 X X X X X Rising Edge Detector clear clear

MAR. 2005 Ver 0.2 14.5 16-bit Capture Mode 16-bit capture mode is the same as 8-bit capture, except that the Timer register is being run will 16 bits. The clock source of the Timer 0 is selected either internal or external clock by bit T0CK[2:0]. In 16-bit mode, the bits T1CK1, T1CK0, CAP1 and 16BIT of TM1 should be set to "1" respectively as shown in Fig- ure 14-17. The clock source of the Timer 2 is selected either internal or ex- ternal clock by bit T2CK[2:0]. In 16-bit mode, the bits T3CK1,T3CK0, CAP3 and 16BIT of TM3 should be set to "1" re- spectively as shown in Figure 14-18. The clock source of the Timer 4 is selected either internal or ex- ternal clock by bit T4CK[2:0] as shown in Figure 14-18. Figure 14-17 16-bit Capture Mode of Timer 0, 1 0: Stop 1: Clear and start T0ST T0CN Capture CDR1 + CDR0 Higher byte Lower byte (16-bit) CAPTURE DATA TDR1 + TDR0 (16-bit) INT0IF INT0 INTERRUPT “01” “10” “11” IEDS[1:0] EC0 PIN ÷ 2 ÷ 4 ÷ 8 XIN PIN MUX Prescaler T0CK[2:0] 111 000 001 010 ÷ 32 ÷ 128 ÷ 512 ÷ 2048 011 100 101 110 INT0 PIN BTCL T0CN INITIAL VALUE: --000000B ADDRESS: 0D0H TM0 T0ST T0CK0 T0CK1 CAP0 T0CK2 X X X X X means the value of "0" or "1" corresponding to user operation INITIAL VALUE: 00H ADDRESS: 0D2H TM1 X BTCL 16BIT POL T1CN T1ST T1CK0 T1CK1 PWM1E CAP1 X X X Rising Edge Detector clear

MAR. 2005 Ver 0.2 Figure 14-18 16-bit Capture Mode of Timer 2, 3 0: Stop 1: Clear and start T2ST T2CN Capture CDR3 + CDR2 Higher byte Lower byte (16-bit) CAPTURE DATA TDR3 + TDR2 (16-bit) INT2IF INT2 INTERRUPT “01” “10” “11” IEDS[5:4] EC1 PIN ÷ 2 ÷ 4 ÷ 8 XIN PIN MUX Prescaler T2CK[2:0] 111 000 001 010 ÷ 16 ÷ 64 ÷ 256 ÷ 1024 011 100 101 110 INT2 PIN BTCL T2CN INITIAL VALUE: --000000B ADDRESS: 0D6H TM2 T2ST T2CK0 T2CK1 CAP2 T2CK2 X X X X X means the value of "0" or "1" corresponding to user operation INITIAL VALUE: 00H ADDRESS: 0D8H TM3 X BTCL 16BIT POL T3CN T3ST T3CK0 T3CK1 PWM3E CAP3 X X X X Rising Edge Detector clear

MAR. 2005 Ver 0.2 Figure 14-19 16-bit Capture Mode of Timer 4 Example 1: Timer0 = 16-bit timer mode, 0.5s at 4MHz LDM TM0,#0000_1111B;8uS LDM TM1,#0100_1100B;16bit Mode LDM TDR0,#<62499 ;8uS X 62500 LDM SET1 T0E EI Example 2: Timer0 = 16-bit event counter mode LDM PSR0,#0001_0000B;EC0 Set LDM TM0,#0001_1111B;CounterMode LDM TM1,#0100_1100B;16bit Mode LDM TDR0,#<0FFFFH ; LDM TDR1,#>0FFFFH ; SET1 T0E EI Example 3: Timer0 = 16-bit capture mode LDM PSR0,#0000_0001B;INT0 set LDM TM0,#0010_1111B;CaptureMode LDM TM1,#0100_1100B;16bit Mode LDM TDR0,#<0FFFFH ; LDM TDR1,#>0FFFFH ; LDM IEDS,#01H ;Falling Edge SET1 T0E SET1 INT0E EI 0: Stop 1: Clear and start T4ST T4CN Capture CDR4H + CDR4L Higher byte Lower byte (16-bit) CAPTURE DATA TDR4H + TDR4L (16-bit) INT3IF INT3 INTERRUPT “01” “10” “11” IEDS[1:0] INT3 PIN clear INITIAL VALUE: 00H ADDRESS: 0DCH TM4 X means the value of "0" or "1" corresponding to user operation BTCL T4CN T4ST T4CK0 T4CK1 CAP4 T4CK2 X X X X X X X ÷ 2 ÷ 4 ÷ 8 XIN PIN MUX Prescaler T4CK[2:0] 111 000 001 010 ÷ 16 ÷ 64 ÷ 256 ÷ 1024 011 100 101 110 ÷ 2048

MAR. 2005 Ver 0.2

14.6 PWM Mode

The MC80F0424/0432/0448 has a high speed PWM (Pulse Width Modulation) functions which shared with Timer1 and Timer3. In PWM mode, pin R53/PWM1O and R54/PWM3O outputs up to a 10-bit resolution PWM output. This pin should be configured as a PWM output by setting "1" to bit PWM1O and PWM3O in PSR0 register. The period of the PWM1 output is determined by the T1PPR (T1 PWM Period Register) and T1PWHR[3:2] (bit3,2 of T1 PWM High Register) and the duty of the PWM1 output is determined by the T1PDR (T1 PWM Duty Register) and T1PWHR[1:0] (bit1,0 of T1 PWM High Register). The user writes the lower 8-bit period value to the T1PPR and the higher 2-bit period value to the T1PWHR[3:2]. And writes duty value to the T1PDR and the T1PWHR[1:0] same way. The T1PDR is configured as a double buffering for glitch less PWM output. In Figure 14-1, the duty data is transferred from the master to the slave when the period data matched to the counted value. (i.e. at the beginning of next duty cycle) PWM1 Period = [PWM1HR[3:2]T1PPR] X Source Clock PWM1 Duty = [PWM1HR[1:0]T1PDR] X Source Clock Likewise, the period of the PWM3 output is determined by the T3PPR (T3 PWM Period Register) and T3PWHR[3:2] (bit3,2 of T3 PWM High Register) and the duty of the PWM output is de- termined by the T3PDR (T3 PWM Duty Register) and T3PWHR[1:0] (bit1,0 of T3 PWM High Register). The user writes the lower 8-bit period value to the T3PPR and the higher 2-bit period value to the T3PWHR[3:2]. And writes duty value to the T3PDR and the T3PWHR[1:0] same way. The T3PDR is configured as a double buffering for glitch less PWM output. In Figure 14-21, the duty data is transferred from the master to the slave when the period data matched to the count- ed value. (i.e. at the beginning of next duty cycle) PWM3 Period = [PWM3HR[3:2]T3PPR] X Source Clock PWM3 Duty = [PWM3HR[1:0]T3PDR] X Source Clock The relation of frequency and resolution is in inverse proportion. Table 14-4 shows the relation of PWM frequency vs. resolution. If it needed more higher frequency of PWM, it should be reduced resolution. The bit POL of TM1 decides the polarity of duty cycle. If the duty value is set same to the period value, the PWM output is determined by the bit POL (1: High, 0: Low). And if the duty value is set to "00H", the PWM output is determined by the bit POL (1: Low, 0: High). It can be changed duty value when the PWM output. However the changed duty value is output after the current period is over. And it can be maintained the duty value at present output when changed only period value shown as Figure 14-23. As it were, the absolute duty time is not changed in varying frequency. But the changed period value must greater than the duty value. Note: If changing the Timer1 to PWM function, it should be stopped with the timer clock uncounted firstly, and then set period and duty register value. If user writes register values while timer is in operation, these register could be set with certain values. Ex) Sample Program @4MHz 2uS LDM TM1,#1010_1000b ; Set Clock & PWM1E LDM T1PPR,#199 ; Period :400uS=2uSX(199+1) LDM T1PDR,#99 ; Duty:200uS=2uSX(99+1) LDM PWM1HR,00H LDM TM1,#1010_1011b ; Start timer1 Resolution Frequency T1CK[1:0] = 00(250nS) T1CK[1:0] = 01(500nS) T1CK[1:0] = 10(2uS) 10-bit 3.9kHz 0.98kHz 0.49kHz 9-bit 7.8kHz 1.95kHz 0.97kHz 8-bit 15.6kHz 3.90kHz 1.95kHz 7-bit 31.2kHz 7.81kHz 3.90kHz Table 14-4 PWM Frequency vs. Resolution at 4MHz

MAR. 2005 Ver 0.2 Figure 14-20 PWM1 Mode ÷ 1 ÷ 2 ÷ 8 T1PWHR ADDRESS : D5H RESET VALUE : ----0000B T1PWHR3 T1PWHR2 T1PWHR1 T1PWHR0 X X X X MUX T1CN T1CK[1:0] T1 ( 8-bit ) T1ST 0 : Stop 1 : Clear and Start CLEAR COMPARATOR COMPARATOR T1PDR(8-bit) T1PWHR[1:0] T1PPR(8-bit) T1PWHR[3:2] T1PDR(8-bit) S Q R POL PWM1O R53/PWM1O T0 clock source XIN TM1 ADDRESS : D2H RESET VALUE : 00000000 POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST X X X X X [PSR0.6] Period High Duty High Slave Master Bit Manipulation Not Available X : The value "0" or "1" corresponding to user operation. [T0CK] (2-bit) R/W R/W R/W R/W R/W R/W R/W R/W W W W W T1PPR ADDRESS : D3H RESET VALUE : 0FFH W W W W W W W W T1PDR ADDRESS : D4H RESET VALUE : 00H R/W R/W R/W R/W R/W R/W R/W R/W

MAR. 2005 Ver 0.2 Figure 14-21 PWM3 Mode ÷ 1 ÷ 4 ÷ 16 T3PWHR ADDRESS : DBH RESET VALUE : ----0000 T3PWHR3 T3PWHR2 T3PWHR1 T3PWHR0 X X X X MUX T3CN T3CK[1:0] T3 ( 8-bit ) T3ST 0 : Stop 1 : Clear and Start CLEAR COMPARATOR COMPARATOR T3PDR(8-bit) T1PWHR[1:0] T3PPR(8-bit) T3PWHR[3:2] T3PDR(8-bit) S Q R POL PWM3O R54/PWM3O T2 clock source XIN TM3 ADDRESS : D8H RESET VALUE : 00000000 POL 16BIT PWM3E CAP3 T3CK1 T3CK0 T3CN T3ST X X X X X [PSR0.7] Period High Duty High Slave Master Bit Manipulation Not Available X : The value "0" or "1" corresponding to user operation. [T2CK] (2-bit) T3PPR ADDRESS : D9H RESET VALUE : 0FFH W W W W W W W W T3PDR ADDRESS : DAH RESET VALUE : 00H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W W W W

MAR. 2005 Ver 0.2 (4) AVDD pin input impedance A series resistor string of approximately 5KΩ is connected be- tween the AVDD pin and the AVSS pin. Therefore, if the output impedance of the analog power source is high, this will result in parallel connection to the series resistor string between the AVDD pin and the AVSS pin, and there will be a large analog supply volt- age error. Figure 15-3 A/D Block Diagram R60/AN0 Sample & Hold R61/AN1 R76/AN14 R77/AN15 Successive Approximation ADCIF ADC INTERRUPT MUX Resistor Ladder Circuit AVDD AVSS ADS[5:2] Circuit ADEN 8-bit ADC ADC Result Register ADC Result Register ADC8 8 ... ADCRL (8-bit) 10-bit ADCR ADCRH 0 0 ADCRL (8-bit) ADCRH ADCR (10-bit) 9 8 ... 10-bit ADCR 10-bit Mode 8-bit Mode ... 1 0 ... 3 2

MAR. 2005 Ver 0.2 Figure 15-4 A/D Converter Control & Result Register BTCL ADEN ADST A/D status bit Analog input channel select INITIAL VALUE: 00-0 0001B ADDRESS: 0EFH ADCM ADSF A/D converter Clock Source Divide Ratio Selection bit 0: Clock Source fPS ÷ 4 1: Clock Source fPS ÷ 8 R/W R/W R/W R/W R 0000: Channel 0 (AN0) 0001: Channel 1 (AN1) 0010: Channel 2 (AN2) 0011: Channel 3 (AN3) 0100: Channel 4 (AN4) 0101: Channel 5 (AN5) 0110: Channel 6 (AN6) 0: A/D conversion is in progress 1: A/D conversion is completed A/D start bit Setting this bit starts an A/D conversion. After one cycle, bit is cleared to “0” by hardware. ADS1 ADS0 ADS2 ADS2 ADCK 0111: Channel 7 (AN7) A/D converter Enable bit 0: A/D converter module turn off and current is not flow. 1: Enable A/D converter INITIAL VALUE: Undefined ADDRESS: 0F1H ADCRL A/D Conversion Low Data R/W R/W BTCL PSSEL1 ADCRH ADC8 - PSSEL0 INITIAL VALUE: 010- ----B ADDRESS: 0F0H A/D Conversion High Data (for 10-bit mode) A/D Conversion Clock (fPS) Source Selection 00: fXIN 01: fXIN ÷ 2 10: fXIN ÷ 4 11: fXIN ÷ 8 BTCL R R W W R R R R R R R R ADC 8-bit Mode select bit 0: 10-bit Mode 1: 8-bit Mode W 1000: Channel 8 (AN8) 1001: Channel 9 (AN9) 1010: Channel 10 (AN10) 1011: Channel 11 (AN11) 1100: Channel 12 (AN12) 1101: Channel 13 (AN13) 1110: Channel 14 (AN14) 1111: Channel 15 (AN15)

MAR. 2005 Ver 0.2 16. SERIAL INPUT/OUTPUT (SIO) The serial Input/Output is used to transmit/receive 8-bit data se- rially. The Serial Input/Output(SIO) module is a serial interface useful for communicating with other peripheral of microcontrol- ler devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. This SIO is 8- bit clock synchronous type and consists of serial I/O data register, serial I/O mode register, clock selection circuit, octal counter and control circuit as illustrated in Figure 16-1. The SO pin is de- signed to input and output. So the Serial I/O(SIO) can be operated with minimum two pin. Pin R42/SCK, R43/SI, and R44/SO pins are controlled by the Serial Mode Register. The contents of the Serial I/O data register can be written into or read out by software. The data in the Serial Data Register can be shifted synchronously with the transfer clock signal. Figure 16-1 SIO Block Diagram ÷ 4 ÷ 16 XIN PIN Prescaler MUX SCK[1:0] SCK PIN SIO Shift Input shift register SIOR Clock Clock Octal Serial communication Interrupt SIOIF Internal Bus SIOSF Counter SCK[1:0] “11” overflow not “11” Complete Timer0 Overflow SI PIN IOSW SO PIN SOUT IOSW CONTROL CIRCUIT “0” “1” POL Start SIOST clear SM0 (3-bit)

MAR. 2005 Ver 0.2 Serial I/O Mode Register(SIOM) controls serial I/O function. Ac- cording to SCK1 and SCK0, the internal clock or external clock can be selected. Serial I/O Data Register(SIOR) is an 8-bit shift register. First LSB is send or is received. Figure 16-2 SIO Control Register

16.1 Transmission/Receiving Timing

The serial transmission is started by setting SIOST(bit1 of SIOM) to “1”. After one cycle of SCK, SIOST is cleared automatically to “0”. At the default state of POL bit clear, the serial output data from 8-bit shift register is output at falling edge of SCLK, and in- put data is latched at rising edge of SCLK pin (Refer to Figure 16- 3). When transmission clock is counted 8 times, serial I/O counter is cleared as ‘0”. Transmission clock is halted in “H” state and se- rial I/O interrupt(SIOIF) occurred. BTCL IOSW POL SIOST Serial transmission status bit Serial transmission Clock selection INITIAL VALUE: 0000 0001B ADDRESS: 0E2H SIOM SIOSF Serial Input Pin Selection bit 0: SI Pin Selection 1: SO Pin Selection R/W R/W R/W R/W R/W R 00: fXIN ÷ 4 01: fXIN ÷ 16 10: TMR0OV(Timer0 Overflow) 11: External Clock 0: Serial transmission is in progress 1: Serial transmission is completed Serial transmission start bit Setting this bit starts an Serial transmission. After one cycle, bit is cleared to “0” by hardware. SCK1 SCK0 SM1 SM0 R/W Serial transmission Operation Mode 00: Normal Port(R42,R43,R44) 01: Sending Mode(SCK,R43,SO) 10: Receiving Mode(SCK,SI,R44) 11: Sending & Receiving Mode(SCK,SI,SO) INITIAL VALUE: Undefined ADDRESS: 0E3H SIOR BTCL R/W R/W R/W R/W R/W R/W R/W R/W Sending Data at Sending Mode Receiving Data at Receiving Mode Serial Clock Polarity Selection bit 0: Data Transmission at Falling Edge Received Data Latch at Rising Edge 1: Data Transmission at Rising Edge Received Data Latch at Falling Edge R/W

MAR. 2005 Ver 0.2

16.2 The method of Serial I/O

1. Select transmission/receiving mode. 2. In case of sending mode, write data to be send to SIOR. 3. Set SIOST to “1” to start serial transmission. 4. The SIO interrupt is generated at the completion of SIO and SIOIF is set to “1”. In SIO interrupt service routine, correct transmission should be tested. 5. In case of receiving mode, the received data is acquired by reading the SIOR. Note: When external clock is used, the frequency should be less than 1MHz and recommended duty is 50%. If both transmission mode is selected and transmission is per- formed simultaneously, error will be made.

16.3 The Method to Test Correct Transmission

Figure 16-5 Serial IO Method to Test Transmission LDM SIOR,#0AAh ;set tx data LDM SIOM,#0011_1100b ;set SIO mode NOP LDM SIOM,#0011_1110b ;SIO Start Serial I/O Interrupt Service Routine SIOE = 0 Write SIOM Normal Operation Overrun Error Abnormal SIOSF - SIOE: Interrupt Enable Register High IENH(Bit3) - SIOIF: Interrupt Request Flag Register High IRQH(Bit3) SIOIF

MAR. 2005 Ver 0.2 17. UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART)

17.1 UART Serial Interface Functions

The Universal Asynchronous Receiver/Transmitter(UART) en- ables full-duplex operation wherein one byte of data after the start bit is transmitted and received. The on-chip baud rate generator dedicated to UART enables communications using a wide range of selectable baud rates. In addition, a baud rate can also be de- fined by dividing clocks input to the ACLK pin. The UART driver consists of RXR, TXR, ASIMR, ASISR and BRGCR register. Clock asynchronous serial I/O mode (UART) can be selected by ASIMR register. Figure 17-1 shows a block di- agram of the UART driver. In operation of UART0 and UART1, their operations are same as UART0 and UART1 Note: The UART1 control register ASIMR1,ASISR1, BRGCR1, RXR1 and TXR1 are located at EE6H ~ EE9H address. These address must be controlled (read and writ- ten) by absolute addressing manipulation instruction. Figure 17-1 UART Block Diagram (ASISR / Transmit Shift Register Internal Data Bus TxD0 PIN / RxD0 PIN / TXE RXE ACLK0 PIN / fXIN/2 ~ fXIN/128 (TXR / TXR1) Transmit Controller (Parity Addition) Receive Buffer Register (RXR / RXR1) Receive Shift Register (RXSR) Receive Controller (Parity Check) Baud Rate Generator PE FE OVE UART0IF / IFTX0 / IFTX1 (UART0/1 interrupt) IFRX0 / IFRX1 ACLK1 PIN RxD1 PIN TxD1 PIN ASISR1) UART1IF

MAR. 2005 Ver 0.2 Figure 17-2 Baud Rate Generator Block Diagram

17.2 Serial Interface Configuration

The UART interface consists of the following hardware. Transmit shift register (TXR) This is the register for setting transmit data. Data written to TXR is transmitted as serial data. When the data length is set as 7 bit, bit 0 to 6 of the data written to TX are transferred as transmit data. Writing data to TXR starts the transmit operation. TXR can be written by an 8 bit memory manipulation instruction. It cannot be read. The RESET input sets TXR to 0FFH. Note: Do not write to TXR during a transmit operation. The same address is assigned to TXR and the receive buffer register (RXR). A read operation reads values from RXR. Receive buffer register (RXR) This register is used to hold receive data. When one byte of data is received, one byte of new receive data is transferred from the receive shift register (RXSR). When the data length is set as 7 bits, receive data is sent to bits 0 to 6 of RXR. In this case, the MSB of RXR always becomes 0. RXR can be read by an 8 bit memory manipulation instruction. It cannot be written. The RESET input sets RXR to 00H. Note: The same address is assigned to RXR and the transmit shift register (TXR). During a write operation, val- ues are written to TXR. Receive shift register This register converts serial data input via the RxD pin to paral- leled data. When one byte of data is received at this register can- not be manipulated directly by a program. MUX RECEIVE RXE Tx_Clock Rx_Clock TXE SEND 5-bit counter Decoder 5-bit counter match match (BRGCR / BRGCR1) TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 ACLK0 PIN / fXIN/2 ~ fXIN/128 Internal Data Bus (Divider) (Divider) ACLK1 PIN Item Configuration Register Transmit shift register (TXR) Receive buffer register (RXR) Receive shift register Control register Serial interface mode register (ASIMR) Serial interface status register (ASISR) Baudrate generator control register (BRGCR) Table 17-1 Serial Interface Configuration

MAR. 2005 Ver 0.2 Asynchronous serial interface mode register (ASIMR) This is an 8 bit register that controls UART serial transfer opera- tion. ASIMR is set by a 1 bit or 8 bit memory manipulation in- truction. The RESET input sets ASIMR to 0000_-00-B. Table 17- 2 shows the format of ASIMR. Table 17-2 Asynchronous Serial Interface Mode register (ASIMR) format Note: Do not switch the operation mode until the current serial transmit/receive operation has stopped. Asynchronous serial interface status register (ASISR) When a receive error occurs during UART mode, this register in- dicates the type of error. ASISR can be read by an 8 bit memory manipulation instruction. The RESET input sets ASISR to ----- 000B. Table 17-3 shows the format of ASISR. Table 17-3 Asynchronous Serial Interface Status Register (ASISR) Format Baud rate generator control register (BRGCR) This register sets the serial clock for serial interface. BRGCR is set by an 8 bit memory manipulation instruction. The RESET in- put sets BRGCR to -001_0000B. Table 17-4 shows the format of BRGCR. Address : 0E6H / EE6H Reset value : 0000-00-B ASIMR / TXE RXE Operation Mode Operation stop UART mode UART mode UART mode RxD Pin Func. Port function(R46) Serial function Port function Serial function TxD Pin Func. Port (Receive only) (Transmit only) ( RX & TX ) (RxD0) (R46) (RxD0) Serial function (TxD0) PS1 PS0 Parity Bit Specification No parity Zero parity always added during transmission. No parity detection during reception (parity errors do not Odd parity Even parity SL 1 bit 2 bit Stop Bit Length for Specification for Transmit Data ISRM Receive interrupt request is issued when an error occurs Receive completion interrupt request is not issued when an error Receive Completion Interrupt Control When Error Occurs function(R47) occur) occurs TXE RXE PS1 PS0 SL ISRM ASIMR1 Address : 0E7H / EE7H Reset value : -----000B ASISR / PE No parity error Parity error (Transmit data parity not matched) Parity Error Flag FE No Frame error Framing errorNote1 (stop bit not detected) Frame Error Flag OVE No overrun error Overrun errorNote2 Overrun Error Flag (Next receive operation was completed before data was read from receive buffer register (RXR) Note 1. Even if a stop bit length is set to 2 bits by setting bit2(SL) in ASIMR, stop bit detection during a recive operation only applies to a stop bit length of 1bit. 2. Be sure to read the contents of the receive buffer register(RXR) when an overrun error has occurred. Until the contents of RXR are read, futher overrun errors will occur when receiving data. PE FE OVE ASISR1

MAR. 2005 Ver 0.2 Table 17-4 Baud Rate Generator Control Register (BRGCR / BRGCR1) Format

17.3 Communication operation

Figure 17-3 UART data format and interrupt timing diagram The transmit operation is enabled when bit 7 (TXE) of the asyn- chronous serial interface mode register (ASIMR/ASIMR1) is set to 1. The transmit operation is started when transmit data is writ- ten to the transmit shift register (TXR). The timing of the transmit completion interrupt request is shown in Figure 17-3. The receive operation is enabled when bit 6 (RXE) of the asyn- chronous serial interface mode register (ASIMR/ASIMR1) is set to 1, and input via the RxD0 pin is sampled. The serial clock spec- ified by ASIMR/ASIMR1 is used to sample the RxD0/RxD1 pin. Once reception of one data frame is completed, a receive comple- tion interrupt request (UART0IF/UART1IF) occurs. Even if an error has occurred, the receive data in which the error occurred is Address : 0E8H / EE8H Reset value : -0010000B BRGCR / 1. fSCK : Source clock for 5 bit counter MDL3 MDL2 MDL1 MDL0 Input Clock Selection k fSCK / 16 fSCK / 17 fSCK / 18 fSCK / 19 fSCK / 20 fSCK / 21 fSCK / 22 fSCK / 23 fSCK / 24 fSCK / 25 fSCK / 26 fSCK / 27 fSCK / 28 fSCK / 29 fSCK / 30 Setting prohibited n TPS2 TPS1 TPS0 Source Clock Selection for 5 Bit count ACLK0 / ACLK1 fXIN / 2 fXIN / 4 fXIN / 8 fXIN / 16 fXIN / 32 fXIN / 64 fXIN / 128 2. n : Value set via TPS0 to TPS2 ( 0 ≤ n ≤ 7 ) 3. k : Source clock for 5 bit counter ( 0 ≤ k ≤ 14 ) Remarks Writing to BRGCR/BRGXR1 during a communication operation may cause abnormal output from the baud rate generator and disable further communication operations. Therefore, do not write to BRGCR/BRGCR1 during a communication operation. Caution TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 BRGCR1 TxD TX RxD Parity INTERRUPT Stop 1 data frame character bits 1 data frame consists of following bits. - Start bit : 1 bit - Character bits : 8 bits - Parity bit : Even parity, Odd parity, Zero parity, No parity - Stop bit(s) : 1 bit or 2 bits (In case of 1 stop bit) RX INTERRUPT (In case of 1 stop bit) Start

MAR. 2005 Ver 0.2 still transferred to RXR. When bit 1 (ISRM) of ASIMR(ASIMR1) is cleared to 0 upon occurrence of an error, in- terrupt by Rx occurs. When ISRM bit is set to 1, interrupt by Rx does not occur in case of error occurrence. Figure 17-3 shows the timing of the asynchronous serial interface receive completion in- terrupt request.

17.4 Relationship between main clock and baud rate

The transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock or ACLK0/ACLK1 pin clock. The baud rate generated from the main system clock or ACLK0/ACLK1 pin clock is determined according to the follow- ing formula. If the high 4 bits of BRGCR/BRGCR1 is 0, ACLK0/ ACLK1 pin clock is used for source clock of baud rate generator. Baud Rate = fXIN / ( 2n+1(k+16) ) - fXIN : Main system clock oscillation frequency - n : Value set via TPS0 to TPS2 (0 ≤ n ≤ 7) - k : Value set via MDL0 to MDL3 (0 ≤ k ≤ 14) When ACLK0/ACLK1 is selected as the source clock of the 5-bit counter, substitute the input clock frequency to ACLK0/ACLK1 pin clock for in the above expression. Baud Rate (bps) fXIN=12M fXIN=11.0592M fXIN=10.0M fXIN=8.0M fXIN=6.0M fXIN=5.0M fXIN=4.0M BRGCR ERR (%) BRGCR ERR (%) BRGCR ERR (%) BRGCR ERR (%) BRGCR ERR (%) BRGCR ERR (%) BRGCR ERR (%) 600 7AH 0.16 1200 7AH 0.16 74H 2.34 70H 1.73 6AH 0.16 2400 74H 2.34 72H 0.00 70H 1.73 6AH 0.16 64H 2.34 60H 1.73 5AH 0.16 4800 64H 2.34 62H 0.00 60H 1.73 5AH 0.16 54H 2.34 50H 1.73 4AH 0.16 9600 54H 2.34 52H 0.00 50H 1.73 4AH 0.16 44H 2.34 40H 1.73 3AH 0.16 19200 44H 2.34 42H 0.00 40H 1.73 3AH 0.16 34H 2.34 30H 1.73 2AH 0.16 31250 38H 0.00 36H 0.53 34H 0.00 30H 0.00 28H 0.00 24H 0.00 20H 0.00 38400 34H 2.34 32H 0.00 30H 1.73 2AH 0.16 24H 2.34 20H 1.73 1AH 0.16 57600 2AH 0.16 28H 0.00 26H 1.35 21H 2.11 1AH 0.16 16H 1.36 11H 2.12 76800 24H 2.34 22H 0.00 20H 1.73 1AH 0.16 14H 2.34 10H 1.73 115200 1AH 0.16 18H 0.00 16H 1.36 11H 2.12 Table 17-5 Relationship between main clock and Baud Rate

MAR. 2005 Ver 0.2

17.5 Communication operation

The transmit operation is enabled when bit 7 (TXE) of the asyn- chronous serial interface mode register (ASIMR/ASIMR1) is set to 1. The transmit operation is started when transmit data is writ- ten to the transmit shift register (TXR/TXR1). The timing of the transmit completion interrupt request is shown in Figure 17-3. The receive operation is enabled when bit 6 (RXE) of the asyn- chronous serial interface mode register (ASIMR/ASIMR1) is set to 1, and input via the RxD0/RxD1 pin is sampled. The serial clock specified by ASIMR/ASIMR1 is used to sample the RxD0/ RxD1 pin. Once reception of one data frame is completed, a re- ceive completion interrupt request (UART0IF/UART1IF) oc- curs. Even if an error has occurred, the receive data in which the error occurred is still transferred to RXR/RXR1. When ASIMR bit 1 (ISRM) is cleared to 0 upon occurrence of an error, UART0/ UART1 interrupt occurs. When ISRM bit is set to 1, UART0/ UART1 interrupt does not occur in case of error occurrence. Fig- ure 17-3 shows the timing of the asynchronous serial interface re- ceive completion interrupt request. In case of using interrupts of UART0 Tx and UART0 Rx togeth- er, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the UART0 Tx and UART0 Rx is shared with interrupt vector address. In case of using interrupts of UART1 Tx and UART1 Rx togeth- er, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the UART1 Tx and UART1 Rx is shared with interrupt vector address. These flag bits must be cleared by software after reading this reg- ister. These flag bits must be cleared by software after reading this register. Each processing step is determined by IFR as shown in Figure 17-1. Figure 17-1 Shared Interrupt Vector of UART IFTX0(IFTX1) TX0(TX1) Interrupt UART0(UART1) Interrupt Request Routine Clear IFTX0(IFTX1) IFRX0(IFRX1) RX0(RX1) Interrupt RETI Routine Clear IFRX0(IFRX1)

MAR. 2005 Ver 0.2 The 6-bit counter is cleared and starts the counting by writing sig- nal at BUZR register. It is incremental from 00H until it matches 6-bit BUR value. When main-frequency is 4MHz, buzzer frequency is shown as below Table 18-1. BUR [5:0] BUR[7:6] BUR [5:0] BUR[7:6] 250.000 125.000 83.333 62.500 50.000 41.667 35.714 31.250 125.000 62.500 41.667 31.250 25.000 20.833 17.857 15.625 62.500 31.250 20.833 15.625 12.500 10.417 8.929 7.813 31.250 15.625 10.417 7.813 6.250 5.208 4.464 3.906 7.576 7.353 7.143 6.944 6.757 6.579 6.410 6.250 3.788 3.676 3.571 3.472 3.378 3.289 3.205 3.125 1.894 1.838 1.786 1.736 1.689 1.645 1.603 1.563 0.947 0.919 0.893 0.868 0.845 0.822 0.801 0.781 27.778 25.000 22.727 20.833 19.231 17.857 16.667 15.625 13.889 12.500 11.364 10.417 9.615 8.929 8.333 7.813 6.944 6.250 5.682 5.208 4.808 4.464 4.167 3.906 3.472 3.125 2.841 2.604 2.404 2.232 2.083 1.953 6.098 5.952 5.814 5.682 5.556 5.435 5.319 5.208 3.049 2.976 2.907 2.841 2.778 2.717 2.660 2.604 1.524 1.488 1.453 1.420 1.389 1.359 1.330 1.302 0.762 0.744 0.727 0.710 0.694 0.679 0.665 0.651 14.706 13.889 13.158 12.500 11.905 11.364 10.870 10.417 7.353 6.944 6.579 6.250 5.952 5.682 5.435 5.208 3.676 3.472 3.289 3.125 2.976 2.841 2.717 2.604 1.838 1.736 1.645 1.563 1.488 1.420 1.359 1.302 5.102 5.000 4.902 4.808 4.717 4.630 4.545 4.464 2.551 2.500 2.451 2.404 2.358 2.315 2.273 2.232 1.276 1.250 1.225 1.202 1.179 1.157 1.136 1.116 0.638 0.625 0.613 0.601 0.590 0.579 0.568 0.558 10.000 9.615 9.259 8.929 8.621 8.333 8.065 7.813 5.000 4.808 4.630 4.464 4.310 4.167 4.032 3.906 2.500 2.404 2.315 2.232 2.155 2.083 2.016 1.953 1.250 1.202 1.157 1.116 1.078 1.042 1.008 0.977 4.386 4.310 4.237 4.167 4.098 4.032 3.968 3.907 2.193 2.155 2.119 2.083 2.049 2.016 1.984 1.953 1.096 1.078 1.059 1.042 1.025 1.008 0.992 0.977 0.548 0.539 0.530 0.521 0.512 0.504 0.496 0.488 Table 18-1 buzzer frequency (kHz unit)

MAR. 2005 Ver 0.2 19. INTERRUPTS The MC80F0424/0432/0448 interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, Priority circuit, and Master enable flag (“I” flag of PSW). Fifteen interrupt sources are provided. The configuration of inter- rupt circuit is shown in Figure 19-1 and interrupt priority is shown in Table 19-1. The External Interrupts INT0 ~ INT3 each can be transition-acti- vated (1-to-0 or 0-to-1 transition) by selection IEDS register. The flags that actually generate these interrupts are bit INT0IF, INT1IF, INT2IF and INT3IF in register IRQH. When an external interrupt is generated, the generated flag is cleared by the hard- ware when the service routine is vectored to only if the interrupt was transition-activated. The Timer 0 ~ Timer 4 Interrupts are generated by T0IF, T1IF, T2IF, T3IF and T4IF which is set by a match in their respective timer/counter register. The Basic Interval Timer Interrupt is generated by BITIF which is set by an overflow in the timer register. The AD converter Interrupt is generated by ADCIF which is set by finishing the analog to digital conversion. The Watchdog timer and Watch Timer Interrupt is generated by WDTIF and WTIF which is set by a match in Watchdog timer register or Watch timer register. The IFR(Interrupt Flag Register) is used for discrimination of the interrupt source among these two Watchdog timer and Watch Timer Interrupt. The Basic Interval Timer Interrupt is generated by BITIF which is set by a overflow in the timer counter register. Figure 19-1 Block Diagram of Interrupt UART0 Tx/Rx INT2 INT1 INT0 INT0IF IENH Interrupt Enable Interrupt Enable IRQH IRQL Internal bus line Register (Lower byte) Internal bus line Register (Higher byte) Release STOP/SLEEP To CPU Interrupt Master Enable Flag I-flag IENL Priority Control I-flag is in PSW, it is cleared by “DI”, set by “EI” instruction. When it goes interrupt service, I-flag is cleared by hardware, thus any other interrupt are inhibited. When interrupt service is completed by “RETI” instruction, I-flag is set to “1” by hardware. [0EAH] [0ECH] [0EDH] INT1IF INT2IF INT3IF UART0IF T0IF SIOIF INT3 UART1 Tx/Rxt Timer 0 Serial UART1IF Timer 1 T1IF T4IF T3IF Timer 2 Timer 3 Timer 3 T2IF A/D Converter ADCIF BITIF WTIF Watchdog Timer BIT Watch Timer WDTIF [0EBH] Communication Interrupt Vector Address Generator

MAR. 2005 Ver 0.2 The UART receive/transmit interrupt is generated by UART0IF and UART1IF which are set by completion of UART data recep- tion or transmission. The SIO interrupt is generated by SIOIF which is set by comple- tion of SIO data reception or transmission. The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW on Figure 8-3), the interrupt enable register (IENH, IENL), and the interrupt request flags (in IRQH and IRQL) except Power-on reset and software BRK interrupt. The Table 19-1 shows the Interrupt priority. Vector addresses are shown in Figure 8-6. Interrupt enable regis- ters are shown in Figure 19-2. These registers are composed of in- terrupt enable flags of each interrupt source and these flags determines whether an interrupt will be accepted or not. When enable flag is “0”, a corresponding interrupt source is prohibited. Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once. Figure 19-2 Interrupt Enable Flag Register Reset/Interrupt Symbol Priority Hardware Reset External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 UART0 Rx/Tx Interrupt UART1 Rx/Tx Interrupt Serial Input/Output Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 Timer/Counter 3 Timer/Counter 4 ADC Interrupt Watchdog/Watch Timer Basic Interval Timer RESET INT0 INT1 INT2 INT3 UART0 UART1 SIO Timer 0 Timer 1 Timer 2 Timer 3 Timer 4 ADC WDT_WT BIT Table 19-1 Interrupt Priority INT3E R/W INT0E Timer/Counter 0 interrupt enable flag INITIAL VALUE: 0000 0000B ADDRESS: 0EAH IENH INT1E MSB LSB SIOE T0E UART0E UART1E INT2E R/W R/W Serial Communication interrupt enable flag UART1 Tx/Rx interrupt enable flag External interrupt 0 enable flag UART0 Tx/Rx interrupt enable flag R/W R/W R/W R/W R/W External interrupt 1 enable flag External interrupt 2 enable flag External interrupt 3 enable flag R/W T1E INITIAL VALUE: 0000 0000B ADDRESS: 0EBH IENL T2E MSB R/W Timer/Counter 4 interrupt enable flag Timer/Counter 3 interrupt enable flag R/W R/W Timer/Counter 2 interrupt enable flag Timer/Counter 1 interrupt enable flag LSB R/W ADCE WDTE R/W R/W R/W T3E T4E WTE BITE Basic Interval Timer interrupt enable flag Watch timer interrupt enable flag Watchdog timer interrupt enable flag A/D Converter interrupt enable flag

MAR. 2005 Ver 0.2 Figure 19-3 Interrupt Request Flag Register

19.1 Interrupt Sequence

An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to “0” by a reset or an instruction. Inter- rupt acceptance sequence requires 8 cycles of fXIN (2µs at fX- IN=4MHz) after the completion of the current instruction execution. The interrupt service task is terminated upon execu- tion of an interrupt return instruction [RETI]. INT3IF R/W INT0IF Timer/Counter 0 interrupt request flag INITIAL VALUE: 0000 0000B ADDRESS: 0ECH IRQH INT1IF MSB LSB SIOIF T0IF UART0IF UART1IF INT2IF R/W R/W Serial Communication interrupt request flag UART1Tx/Rx interrupt request flag External interrupt 3 request flag UART0 Tx/Rx interrupt request flag R/W R/W R/W R/W R/W External interrupt 2 request flag External interrupt 1 request flag External interrupt 0 request flag R/W T1IF INITIAL VALUE: 0000 0000B ADDRESS: 0EDH IRQL T2IF MSB R/W Timer/Counter 4 interrupt request flag Timer/Counter 3 interrupt request flag R/W R/W Timer/Counter 2 interrupt request flag Timer/Counter 1 interrupt request flag LSB R/W ADCIF WDTIF R/W R/W R/W T3IF T4IF WTIF BITIF Basic Interval Timer interrupt request flag Watch timer interrupt request flag Watchdog timer interrupt request flag A/D Converter interrupt request flag NOTE1 : In case of using interrupts of Watchdog Timer and Watch Timer together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the Watchdog timer and Watch timer is shared with interrupt vector address. These flag bits must be cleared by software after read- ing this register. R/W INITIAL VALUE: --00 0000B ADDRESS: 0DFH IFR MSB R/W UART0 Tx interrupt occurred flagNOTE3 UART0 Rx interrupt occurred flagNOTE3 LSB R/W R/W R/W R/W IFRX0 IFTX0 IFWT WDT interrupt occurred flagNOTE1 WT interrupt occurred flagNOTE1 UART1 Tx interrupt occurred flagNOTE2 UART1 Rx interrupt occurred flagNOTE2 IFRX1 IFTX1 IFWDT NOTE2 : In case of using interrupts of UART1 Tx and UART1 Rx together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the UART1 Tx and UART1 Rx is shared with interrupt vector address. These flag bits must be cleared by software after reading this register. NOTE3 : In case of using interrupts of UART0 Tx and UART0 Rx together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the UART0 Tx and UART0 Rx is shared with interrupt vector address. These flag bits must be cleared by software after reading this register.

MAR. 2005 Ver 0.2

19.1.1 Interrupt acceptance

1. The interrupt master enable flag (I-flag) is cleared to “0” to temporarily disable the acceptance of any follow- ing maskable interrupts. When a non-maskable inter- rupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. Interrupt request flag for the interrupt source accepted is cleared to “0”. 3. The contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. The stack pointer decreases 3 times. 4. The entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. The instruction stored at the entry address of the inter- rupt service program is executed. Figure 19-4 Timing chart of Interrupt Acceptance and Interrupt Return Instruction A interrupt request is not accepted until the I-flag is set to “1” even if a requested interrupt has higher priority than that of the current interrupt being serviced. When nested interrupt service is required, the I-flag should be set to “1” by “EI” instruction in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.

19.1.2 Saving/Restoring General-purpose Regis-

During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. These regis- ters are saved by the software if necessary. Also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory area for saving registers. The following method is used to save/restore the general-purpose registers. Example: Register save using push and pop instructions V.L. System clock Address Bus PC SP SP-1 SP-2 V.H. New PC V.L. Data Bus Not used PCH PCL PSW ADL OP code ADH Instruction Fetch Internal Read Internal Write Interrupt Processing Step Interrupt Service Task ADL and ADH are start addresses of interrupt service routine as vector contents. Basic Interval Timer 012H 0E3H 0FFE0H 0FFE1H 0EH 2EH 0E312H 0E313H Entry Address Correspondence between vector table address for BIT interrupt and the entry address of the interrupt service program. Vector Table Address INTxx: PUSH A PUSH X PUSH Y ;SAVE ACC. ;SAVE X REG. ;SAVE Y REG. interrupt processing

MAR. 2005 Ver 0.2 General-purpose register save/restore using push and pop instruc- tions;

19.2 BRK Interrupt

Software interrupt can be invoked by BRK instruction, which has the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK inter- rupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0. Each processing step is determined by B-flag as shown in Figure 19-5. Figure 19-5 Execution of BRK/TCALL0

19.3 Shared Interrupt Vector

In case of using interrupts of Watchdog Timer and Watch Timer together, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the Watchdog timer and Watch timer is shared with interrupt vector address. These flag bits must be cleared by software after reading this reg- ister. In case of using interrupts of UART0 Tx and UART0 Rx togeth- er, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the UART0 Tx and UART0 Rx is shared with interrupt vector address. These flag bits must be cleared by software after reading this register. In case of using interrupts of UART1 Tx and UART1 Rx togeth- er, it is necessary to check IFR in interrupt service routine to find out which interrupt is occurred, because the UART1 Tx and UART1 Rx is shared with interrupt vector address. These flag bits must be cleared by software after reading this register. Each processing step is determined by IFR as shown in Figure 19-6. POP Y POP X POP A RETI ;RESTORE Y REG. ;RESTORE X REG. ;RESTORE ACC. ;RETURN main task interrupt service task saving registers restoring registers acceptance of interrupt interrupt return B-FLAG BRK INTERRUPT ROUTINE RETI TCALL0 ROUTINE RET BRK or TCALL0

MAR. 2005 Ver 0.2 Figure 19-6 Software Flowchart of Shared Interrupt Vector

19.4 Multi Interrupt

If two interrupt requests of different priority level are received si- multaneously, the request of higher priority level is serviced. If interrupt requests of of equal priority level are received at the same time simultaneously, an internal polling sequence deter- mines by hardware which request is serviced. However, multiple processing through software for special fea- tures is possible. Generally when an interrupt is accepted, the I- flag is cleared to disable any further interrupt. But as user sets I- flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress. Refer to Figure 19-7. Example: During Timer1 interrupt is in progress, INT0 interrupt serviced without any suspend. TIMER1: PUSH A PUSH X PUSH Y LDM IENH,#80H ;Enable INT0 only LDM IENL,#0 ;Disable other int. EI ;Enable Interrupt LDM IENH,#0FFH ;Enable all interrupts LDM IENL,#0FFH POP Y POP X POP A RETI IFTX0(IFTX1) TX0(TX1) Interrupt UART0(UART1) Interrupt Request Routine Clear IFTX0(IFTX1) IFRX0(IFRX1) RX0(RX1) Interrupt Routine Clear IFRX0(IFRX1) RETI IFWDT WDT Interrupt WDT or WT Interrupt Request Routine Clear IFWDT IFWT WT Interrupt RETI Routine Clear IFWT

MAR. 2005 Ver 0.2 Figure 19-7 Execution of Multi Interrupt

19.5 External Interrupt

The external interrupt on INT0, INT1, INT2 and INT3 pins are edge triggered depending on the edge selection register IEDS (ad- dress 0EEH) as shown in Figure 19-8. The edge detection of external interrupt has three transition acti- vated mode: rising edge, falling edge, and both edge. INT0 ~ INT3 are multiplexed with general I/O ports (R10, R11, R12, R50). To use as an external interrupt pin, the bit of port se- lection register PSR0 should be set to “1” correspondingly. Example: To use as an INT0 and INT2 ;** Set external interrupt port as pull-up state. LDM PU1,#0000_0101B ; Set port as an external interrupt port LDM PSR0,#0000_0101B ;** Set Falling-edge Detection LDM IEDS,#0001_0001B Figure 19-8 External Interrupt Block Diagram enable INT0 TIMER 1 service INT0 service Main Program service Occur TIMER1 interrupt Occur INT0 EI disable other enable INT0 enable other In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting the interrupt enable registers IENH,IENL and master enable “EI” in the TIMER1 routine. INT0IF INT0 pin INT0 INTERRUPT INT1IF INT1 pin INT1 INTERRUPT INT2IF INT2 pin INT2 INTERRUPT IEDS [0EEH] INT3IF INT3 pin INT3 INTERRUPT Edge selection Register

MAR. 2005 Ver 0.2 20. OPERATION MODE The system clock controller starts or stops the main-frequency clock oscillator and switches between the main and sub frequency clock. The operating mode is generally divided into the main ac- tive mode, the sub active mode 1 and sub active mode 2, which are controlled by System clock control register (SCMR). Figure 20-1 shows the operating mode transition diagram. System clock control is performed by the system clock mode reg- ister, SCMR. During reset, this register is initialized to “0” so that the main-clock operating mode is selected. Main Active mode This mode is fast-frequency operating mode. The CPU and the peripheral hardware are operated on the high-frequency clock. At reset release, this mode is invoked. Sub Active mode This mode is low-frequency operating mode. In this mode, the CPU and the peripheral hardware clock are provided by low-fre- quency clock oscillation, so power consumption can be reduced. SLEEP mode In this mode, the CPU clock stops while peripherals and the os- cillation source continues to operate normally. STOP mode In this mode, the system operations are all stopped, holding the internal states valid immediately before the stop at the low power consumption level. The main oscillation source stops, but the sub clock oscillation and watch timer by sub clock and RC-oscillated watchdog timer don’t stop. Figure 20-1 Operating Mode Main Active Mode Main : Oscillation Sub : Oscillation or stop Sub Active Mode 1 Sub Active Mode 2 Stop / Sleep Mode * Note1 / * Note2 System Clock : Main Main : Oscillation Sub : Oscillation System Clock : Sub LDM SCMR, #02H LDM SCMR, #01H * Note3 * Note1 / Note2 LDM SCMR,#06H CLR1 SCMR.2 SET1 SCMR.2 Sleep : System Clock Oscillation run Main : Stop Sub : Oscillation System Clock : Sub * Note1 : Stop released by Reset, Watch Timer, Watchdog Timer SIO (External clock), UART External interrupt * Note2 : Sleep released by Reset, or All interrupts * Note3 : List of instruction is CLR1 SCMR.2 ;Main OSC ON NOP ;for Oscillation stabilization time NOP ;for Oscillation stabilization time - Sub clock cannot be stopped by STOP instruction. LDM SCMR, #01H * Note1 / Note2 * Note4 * Note4 * Note4 * Note4 : 1) Stop mode Admission 2) Sleep mode Admission LDM SSCR, #5AH STOP LDM SSCR, #0FH NOP NOP Timer(event counter), Stop : System Clock Oscillation stop (CPU stops, Peripherals operate)

MAR. 2005 Ver 0.2

20.1 Operation Mode Switching

In the Main active mode, only the high-frequency clock oscillator is used. In the Sub active mode, the low-frequency clock oscilla- tion is used, so the low power voltage operation or the low power consumption operation can be enabled. Instruction execution does not stop during the change of operation mode. In this case, some peripheral hardware capabilities may be affected. For de- tails, refer to the description of the relevant operation. The following describes the switching between the Main active mode and the Sub active mode. During reset, the system clock mode register is initialized at the Main active mode. It must be set to the Sub active mode for reducing the power consumption. Switching from Main active to Sub active 1 First, write “02H” into SCMR to switch the main system clock to the sub-frequency clock of Sub Active mode 1. Example: LDM SCMR,#02H ;Switch to sub active1 Switching from Main active to Sub active 2 First, write “06H” into SCMR to switch the main system clock to the sub-frequency clock of Sub Active mode 2. Example: LDM SCMR,#06H ;Switch to sub active2 Returning from Sub active 1 to Main active First, write “01H” into SCMR to turn on the main-frequency os- cillation. Sub active mode can also be released by setting the RE- SET pin to low, which immediately performs the reset operation. After reset, the MC80F0424/0432/0448 is placed in Main active mode. Example: LDM SCMR,#01H ;Switch to main-clock Switching from Sub active 1 to Sub active 2 First, set SCMR.2 to switch the main system clock to the sub-fre- quency clock of Sub Active mode 2. Example: SET1 SCMR.2 ;Switch to sub active2 Returning from Sub active 2 to Main active First, set the SCMR.2 bit clear, and wait for a while for oscillation stabilization time. Secondly, write “01H” into the SCMR to turn on the main-frequency oscillation. This time, the stabilization (warm-up) time needs to be taken by the software delay routine with the length of two or more NOP instruction. Sub active mode can also be released by setting the RESET pin to low, which im- mediately performs the reset operation. After reset, the MC80F0424/0432/0448 is placed in Main active mode. Example: CLR1 SCMR.2 ;Turn on main-clock NOP ;for OSC stabilization time NOP ;for OSC stabilization time LDM SCMR,#01h ;Move to main active Returning from Sub active 2 to Sub active 1 First, clear SCMR.2 to switch the main system clock to the sub- frequency clock of Sub Active mode 2. Example: CLR1 SCMR.2 ;Switch to sub active1 Shifting from the Normal operation to the SLEEP mode If the SLEEP mode is invoked, the external clock oscillation does not stops but the CPU clock stops while other peripherals are op- erate normally. The ways of release from this mode are by setting the RESET pin to low and all available interrupts. For more detail, See "21. POWER SAVING OPERATION" on page 101. Shifting from the Normal operation to the STOP mode If the STOP mode is invoked, the main-frequency clock oscilla- tion stops and the CPU clock stops and other peripherals are stop too. But sub-frequency clock oscillation operate continuously if enabled previously. After the STOP operation is released by re- set, the operation mode is changed to Main active mode. The methods of release from this mode are Reset, Watch Timer, RC watchdog timer, Event counter, SIO(External clock), UART, and External Interrupt. For more details, see "21. POWER SAVING OPERATION" on page 101. Note: In the STOP and SLEEP operating modes, the pow- er consumption by the oscillator and the internal hardware is reduced. However, the power for the pin interface (de- pending on external circuitry and program) is not directly associated with the low-power consumption operation. This must be considered in system design as well as interface circuit design.

MAR. 2005 Ver 0.2 Figure 20-2 System Clock Switching Timing Operation clock Sub-clock operation Main-clock operation Sub freq. clock Main freq. clock (XIN pin) (SXIN pin) Changed to the Sub-clock SCMR ← XXXX X010B Operation clock Main-clock operation Stabilizing Time > 20ms Sub freq. clock Main freq. clock (XIN pin) (SXIN pin) Changed to the Transition Changed to the Main-clock SCMR.2 bit LOW SCMR ← XXXX X000B Sub-clock operation (a) Main active mode → Sub active mode 1 → Sub active mode 2 (b) Sub active mode 2 → Sub active mode 1 → Main active mode or XXXX X001B Turn off main clock SCMR.2 bit HIGH

MAR. 2005 Ver 0.2 101 21. POWER SAVING OPERATION The MC80F0424/0432/0448 has two power-down modes. In power-down mode, power consumption is reduced considerably. For applications where power consumption is a critical factor, de- vice provides two kinds of power saving functions, STOP mode and SLEEP mode. Table 21-1 shows the status of each Power Saving Mode. SLEEP mode is entered by the SSCR register to “0Fh”., and STOP mode is entered by STOP instruction after the SSCR register to “5Ah”.

21.1 Sleep Mode

In this mode, the internal oscillation circuits remain active and oscillation continues and peripherals are operate normally, but CPU stops. Movement of all peripherals is shown in Table 21-1. SLEEP mode is entered by setting the SSCR register to “0Fh”. It is released by Reset or interrupt. To be released by interrupt, in- terrupt should be enabled before SLEEP mode. Figure 21-1 STOP and SLEEP Control Register Release the SLEEP mode The exit from SLEEP mode is hardware reset or all interrupts. Reset re-defines all the Control registers but does not change the on-chip RAM. Interrupts allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. If I-flag = 0, the chip will resume execution starting with the instruction fol- lowing the SLEEP instruction. It will not vector to interrupt serv- ice routine. (refer to Figure 21-4) When exit from SLEEP mode by reset, enough oscillation stabi- lization time is required to normal operation. Figure 21-3 shows the timing diagram. his guarantees that oscillator has started and stabilized. By interrupts, exit from SLEEP mode is shown in Fig- ure 21-2. By reset, exit from SLEEP mode is shown in Figure 21- INITIAL VALUE: 0000 0000B ADDRESS: 0F5H SSCR W Power Down Control 5AH: STOP mode 0FH: SLEEP mode W W W W W W W 1. To get into STOP mode, SSCR must be set to 5AH just before STOP instruction execution. At STOP mode, Stop & Sleep Control Register (SSCR) value is cleared automatically when released. 2. To get into SLEEP mode, SSCR must be set to 0FH.

MAR. 2005 Ver 0.2 Figure 21-2 SLEEP Mode Release Timing by External Interrupt Figure 21-3 Timing of SLEEP Mode Release by Reset

21.2 Stop Mode

In the Stop mode, the main oscillator, system clock and peripher- al clock is stopped, but the sub clock oscillation and Watch Timer by sub clock and RC-oscillated watchdog timer continue to oper- ate. With the clock frozen, all functions are stopped, but the on- chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. Oscillator stops and the systems internal operations are all held up.

• The states of the RAM, registers, and latches valid immediately before the system is put in the STOP state are all held.
• The program counter stop the address of the instruction to be executed after the instruction "STOP" which starts the STOP operating mode. Note: The Stop mode is activated by execution of STOP instruction after setting the SSCR to “5AH”. (This register should be written by byte operation. If this register is set by bit manipulation instruction, for example "set1" or "clr1" in- struction, it may be undesired operation) In the Stop mode of operation, VDD can be reduced to minimize power consumption. Care must be taken, however, to ensure that VDD is not reduced before the Stop mode is invoked, and that VDD is restored to its normal operating level, before the Stop mode is terminated. Oscillator (XIN pin) Normal Operation SLEEP Operation External Interrupt CPU SLEEP Instruction Executed Normal Operation Clock SLEEP Instruction Stabilization Time tST = 65.5mS @4MHz Internal RESET RESET Oscillator (XIN pin) CPU Clock Execution Normal Operation SLEEP Operation Normal Operation

MAR. 2005 Ver 0.2 103 The reset should not be activated before VDD is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize. Note: After STOP instruction, at least two or more NOP in- struction should be written. Ex) LDM CKCTLR,#0FH ;more than 20ms LDM SSCR,#5AH STOP NOP ;for stabilization time NOP ;for stabilization time In the STOP operation, the dissipation of the power associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the pin interface (depend- ing on the external circuitry and program) is not directly deter- mined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level (VDD/VSS); however, when the input level gets higher than the power voltage level (by approximately 0.3 to 0.5V), a current begins to flow. Therefore, if cutting off the out- put transistor at an I/O port puts the pin signal into the high-im- pedance state, a current flow across the ports input transistor, requiring to fix the level by pull-up or other means. Release the STOP mode The source for exit from STOP mode is hardware reset, external interrupt, Timer(Event Counter), Watchdog Timer(RCWDT), Watch Timer(by subclock), SIO(by external clock) or UART. Reset re-defines all the Control registers but does not change the on-chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. If I-flag = 0, the chip will resume execution starting with the instruction fol- lowing the STOP instruction. It will not vector to interrupt service routine. (refer to Figure 21-4) When exit from Stop mode by external interrupt, enough oscilla- tion stabilization time is required to normal operation. Figure 21- 5 shows the timing diagram. When released from the Stop mode, the Basic interval timer is activated on wake-up. It is increased from 00H until FFH. The count overflow is set to start normal op- eration. Therefore, before STOP instruction, user must set its rel- evant prescaler divide ratio to have long enough time (more than Peripheral STOP Mode SLEEP Mode CPU Stop Stop RAM Retain Retain Basic Interval Timer Halted (Only operates in RC-WDT mode) Operates Continuously Watchdog Timer Stop (Only operates in RC-WDT mode) Stop Watch Timer Stop (Only operates in Subclock mode) Stop Timer/Counter Halted(Only when the event counter mode is enabled, timer operates normally) Operates Continuously Buzzer, ADC Stop Stop SIO Only operate with external clock Only operate with external clock UART Only operate with external clock Only operate with external clock Oscillator Stop(XIN=L, XOUT=H) Oscillation Sub Oscillator Oscillation Oscillation I/O Ports Retain Retain Control Registers Retain Retain Internal Circuit Stop mode Sleep mode Prescaler Retain Active Address Data Bus Retain Retain Release Source Reset, Timer(EC0, EC1), RC WDT Timer, Watch Timer(Subclock), SIO(ext. clock), UART, External Interrupt Reset, All Interrupts Table 21-1 Peripheral Operation During Power Saving Mode

MAR. 2005 Ver 0.2 105 Figure 21-6 Timing of STOP Mode Release by Reset

21.3 Stop Mode at Internal RC-Oscillated Watchdog Timer Mode

In the Internal RC-Oscillated Watchdog Timer mode, the on-chip oscillator is stopped. But internal RC oscillation circuit is oscil- lated in this mode. The on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. The Internal RC-Oscillated Watchdog Timer mode is activated by execution of STOP instruction after setting the bit RCWDT of CKCTLR to "1". (This register should be written by byte opera- tion. If this register is set by bit manipulation instruction, for ex- ample "set1" or "clr1" instruction, it may be undesired operation) Note: Caution: After STOP instruction, at least two or more NOP instruction should be written Ex) LDM WDTR,#1111_1111B LDM CKCTLR,#0010_1110B LDM SSCR,#0101_1010B STOP NOP ;for stabilization time NOP ;for stabilization time The exit from Internal RC-Oscillated Watchdog Timer mode is hardware reset or external interrupt including RC watchdog tim- er. Reset re-defines all the Control registers but does not change the on-chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. In this case, if the bit WDTON of CKCTLR is set to "0" and the bit WDTE of IENH is set to "1", the device will execute the watch- dog timer interrupt service routine(Figure 8-6). However, if the bit WDTON of CKCTLR is set to "1", the device will generate the internal Reset signal and execute the reset processing(Figure 21-8). If I-flag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine.(refer to Figure 21-4) When exit from Stop mode at Internal RC-Oscillated Watchdog Timer mode by external interrupt, the oscillation stabilization time is required to normal operation. Figure 21-7 shows the tim- ing diagram. When release the Internal RC-Oscillated Watchdog Timer mode, the basic interval timer is activated on wake-up. It is increased from 00H until FFH. The count overflow is set to start normal operation. Therefore, before STOP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized. By reset, exit from internal RC-Oscillated Watch- dog Timer mode is shown in Figure 21-8. STOP Mode Time can not be control by software Oscillator (XI pin) STOP Instruction Execution Stabilization Time tST = 65.5mS @4MHz Internal Clock Internal RESET RESET

MAR. 2005 Ver 0.2 107

21.4 Minimizing Current Consumption

The Stop mode is designed to reduce power consumption. To minimize current drawn during Stop mode, the user should turn- off output drivers that are sourcing or sinking current, if it is prac- tical. Figure 21-9 Application Example of Unused Input Port Figure 21-10 Application Example of Unused Output Port Note: In the STOP operation, the power dissipation asso- ciated with the oscillator and the internal hardware is low- ered; however, the power dissipation associated with the pin interface (depending on the external circuitry and pro- gram) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level (VDD/VSS); however, when the input level becomes higher than the power voltage level (by approximately 0.3V), a cur- rent begins to flow. Therefore, if cutting off the output tran- sistor at an I/O port puts the pin signal into the high- impedance state, a current flow across the ports input tran- sistor, requiring it to fix the level by pull-up or other means. It should be set properly in order that current flow through port doesn't exist. First consider the port setting to input mode. Be sure that there is INPUT PIN VDD GND i VDD X Weak pull-up current flows VDD internal pull-up INPUT PIN i VDD X Very weak current flows VDD O O OPEN OPEN i=0 O i=0 O GND When port is configured as an input, input level should be closed to 0V or 5V to avoid power consumption. OUTPUT PIN GND i In the left case, much current flows from port to GND. X ON OFF OUTPUT PIN GND i In the left case, Tr. base current flows from port to GND. i=0 X OFF ON VDD L ON OFF OPEN GND VDD L ON OFF To avoid power consumption, there should be low output ON OFF O O VDD O to the port .

MAR. 2005 Ver 0.2 no current flow after considering its relationship with external circuit. In input mode, the pin impedance viewing from external MCU is very high that the current doesn’t flow. But input voltage level should be VSS or VDD. Be careful that if unspecified voltage, i.e. if uncertain voltage level (not VSS or VDD) is applied to input pin, there can be little current (max. 1mA at around 2V) flow. If it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. The port setting to High or Low is decided by considering its relationship with exter- nal circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to High, and if there is external pull- down register, it is set to low.

MAR. 2005 Ver 0.2 111 24. POWER FAIL PROCESSOR The MC80F0424/0432/0448 has an on-chip power fail detection circuitry to immunize against power noise. A configuration reg- ister, PFDR, can enable or disable the power fail detect circuitry. Whenever VDD falls close to or below power fail voltage for 100ns, the power fail situation may reset or freeze MCU accord- ing to PFDM bit of PFDR. Refer to “Figure 24-1 Power Fail Volt- age Detector Register” on page 111. In the in-circuit emulator, power fail function is not implemented and user can not experiment with it. Therefore, after final devel- opment of user program, this function may be experimented or evaluated. Note: User can select power fail voltage level according to CONFIG register(20FFH) at the FLASH MCU(MC80F0424/ 0432/0448) but must select the power fail voltage level to define PFD option of "Mask Order & Verification Sheet" at the mask chip(MC80C0424/0432/0448), because the pow- er fail voltage level of mask chip is determined according to mask option. Note: If power fail voltage is selected to 2.4V or 2.7V on below 3V operation, MCU is freezed at all the times. Table 24-1 Power fail processor Figure 24-1 Power Fail Voltage Detector Register Power Fail Function OTP MASK Enable/Disable PFDEN flag PFDEN flag Level Selection PFS0 bit PFS1 bit Mask option PFDM PFDS INITIAL VALUE: -----000B ADDRESS: 0F7H PFDR R/W R/W R/W PFDEN PFD Operation Mode 0 : MCU will be freezed by power fail detection 1 : MCU will be reset by power fail detection PFD Enable Bit 0: Power fail detection disable 1: Power fail detection enable Power Fail Status 0: Normal operate 1: Set to “1” if power fail is detected * Cautions : Be sure to set bits 3 through 7 to “0”.

MAR. 2005 Ver 0.2 113 25. FLASH PROGRAMMING The Device Configuration Area can be programmed or left un- programmed to select device configuration such as security bit. This area is not accessible during normal execution but is reada- ble and writable during FLASH program / verify mode. The De- vice Configuration Area register is located at the address 20FFH. Figure 25-1 Device Configuration Area Register

25.1 Lock bit

The lock bit exists in Device Configuration Area register. If lock bit is programmed and user tries to read FLASH memory cell, the output data from the data port is 5AH that means the normal pro- tection operation of user program data. Once the lock bit is pro- grammed, the user can’t modify and read the data of user program area.

25.2 Power Fail Detection level

The power fail detection provides 3 level of detection, 2.4V, 2.7V and 3.0V. The default level of detection is 2.7V and this level is applied if user does not select the specific level in FLASH pro- gramming S/W tools. For more information, refer to "24. POW- ER FAIL PROCESSOR" on page 111 INITIAL VALUE: 00H ADDRESS: 20FFH CONFIG Code Protect (Available FLASH version) 0 : Lock Disable 1 : Lock Enable (main cell read protection) PFD Level Selection 00: PFD = 2.7V 01: PFD = 2.7V PFS1 10: PFD = 3.0V 11: PFD = 2.4V PFS0 LOCK

MAR. 2005 Ver 0.2 26. Emulator EVA. Board Setting þ“ à ÃÕŒœ–— VCC AVDD GND R66 R64 R62 R60 GND R56 R54 R52 R50 GND R46 R44 R42 R40 GND R36 R34 R32 R30 GND U_XOUT GND VDD AVDD GND R67 R65 R63 R61 GND R57 R55 R53 R51 GND R47 R45 R43 R41 GND R37 R35 R33 R31 GND U_Reset GND VDD R71 R73 R75 R77 GND R81 R83 R85 R87 GND R01 R03 R05 R07 GND R11 R13 R15 R17 GND R21 R23 R25 R27 VDD R70 R72 R74 R76 GND R80 R82 R84 R86 GND R00 R02 R04 R06 GND R10 R12 R14 R16 GND R20 R22 R24 R26 J_USERB J_USERA

MAR. 2005 Ver 0.2 115 DIP Switch and VR Setting Before executing the user program, set up the EVA board according to the below configuration. DIP S/W This connector is only used for a device over 32 PIN. Used for the MC80F0424/0432/0448. This connector is only used for a device under 32 PIN. Not used for the MC80F0424/0432/0448. SW2 Eva. select switch Must be ON position. ON : MC80F0424/0432/0448 selection OFF : other MCU selection AVDD pin select switch These switches select the AVDD source. ON & OFF : Use Eva. VDD OFF & ON : Use User AVDD This switch select the /Reset source. Normally OFF. EVA. chip can be reset by external user tar- get board. ON : Reset is available by either user target system board or Emulator RESET switch. OFF : Reset the MCU by Emulator RESET switch. Does not work from user target board. This switch select the XOUT signal on/off. Normally OFF. MCU XOUT pin is disconnected internally in the Emulator. Some circumstance user may connect this circuit. ON : Output XOUT signal OFF : Disconnect circuit SW3 This switch select Eva. B/D Power supply source. Normally MDS. This switch select Eva. B/D Power supply source. SW4 This switch select the R22 or SXOUT. This switch select the R21 or SXIN. These switchs select the Normal I/O port(off) or Sub-Clock (on). ON : SXOUT, SXIN selection OFF : R22, R21 selection ON ON OFF OFF ON Use Eva. VDD Use User’s AVDD Use MDS Power MDS USER MDS USER Use User’s Power

MAR. 2005 Ver 0.2 SW5 These switches select the R33 or XIN This switch select the Normal I/O port(on&off) or special function select(off&on). It is not used for the MC80F0424/0432/ 0448. These switches select the R34 or XOUT These switches select the R35 or /Reset This is External oscillation socket(CAN Type. OSC) This is for External Clock(CAN Type. OSC). DIP S/W

MAR. 2005 Ver 0.2 117 27. IN-SYSTEM PROGRAMMING (ISP)

27.1 Getting Started / Installation

The following section details the procedure for accomplishing the installation procedure. 1. Connect the serial(RS-232C) cable between a target board and the COM port of your PC. 2. Configure the COM port of your PC as following. 3. Turn your target B/D power switch ON. Your target B/ D must be configured to enter the ISP mode. 4. Run the MagnaChip ISP software. 5. Press the Reset Button in the ISP S/W. If the status win- dows shows a message as "Connected", all the condi- tions for ISP are provided.

27.2 Basic ISP S/W Information

115,200 Data bit Parity No Stop bit Flow control No

MAR. 2005 Ver 0.2 Function Load the data from the selected file storage into the memory buffer. Save HEX File Save the current data in your memory buffer to a disk storage by using the Intel Motorolla HEX format. Erase Erase the data in your target MCU before programming it. Blank Check Verify whether or not a device is in an erased or unprogrammed state. Program This button enables you to place new data from the memory buffer into the target device. Read Read the data in the target MCU into the buffer for examination. The checksum will be displayed on the checksum box. Verify Assures that data in the device matches data in the memory buffer. If your device is secured, a verification error is detected. Option Write Progam the configuration data of target MCU. The security locking is performed with this button. Option Set the configuration data of target MCU. The security locking is set with this button. AUTO Erase & Program & Verify. Auto Option Write If selected with check mark, the option write is performed after erasure and write. Edit Buffer Modify the data in the selected address in your buffer memory Fill Buffer Fill the selected area with a data. Goto Display the selected page. Enter your target system’s oscillator value with discarding below point. Starting address End address Checksum Display the checksum(Hexdecimal) after reading the target device. Com Port Select serial port. Baud Rate Select UART baud rate. Select Device Select target device. Page Up Key Display the previous page of your memory buffer. Page Down Key Display the higher page than the current location. Table 27-1 ISP Function Description

MAR. 2005 Ver 0.2 119

27.3 Hardware Conditions to Enter the ISP Mode

The In-System Programming (ISP) is performed without remov- ing the microcontroller from the target system. The In-System Programming(ISP) facility consists of a series of internal hard- ware resources coupled with internal firmware through the serial port. The In-System Programming (ISP) facility has made in-cir- cuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area. The boot loader can be executed by holding ALEB high, RST/VPP as +9V, and ACLK0 with the OSC. 1.8432MHz. The ISP function uses five pins: TxD0, RxD0, ALEB, ACLK0 and RST/VPP. Note: Considerations to implement ISP function in a user target board

• The ACLK0 must be connected to the specifed oscillator.
• Connect the +9V to RESET/Vpp pin directly.
• The ALEB pin must be pulled high.
• The main clk must be higher than 2MHz. Figure 27-1 ISP Configuration VDD RESET XIN XOUT VSS R47 / TxD0 R46 / RxD0 R45 / ACLK0 R30 MC80F0424/0432/0448 Tx Data Rx Data 1.8432MHz VDD VDD(+5V) +9V ALE RST/VPP X-TAL 2MHz~12MHz

MAR. 2005 Ver 0.2

27.4 Reference ISP Circuit Diagram and MagnaChip Supplied ISP Board

The ISP software and hardware circuit diagram are provided at www.magnachipmcu.com . To get a ISP B/D, contact to sales de- partment. The following circuit diagram is for reference use.. Figure 27-2 Reference ISP Circuit Diagram Figure 27-3 MagnaChip supplied ISP Board T1IN T2IN R1OUT R2OUT C1+ C1- C2+ C2- T1OUT T2OUT R1IN R2IN VCC GND CON1 Female DB9 VSS External VDD RESET/VPP MCU_TxD MCU_RxD VDD VSS 10uF/16V 0.1uF MAX232 ACLK_CLK Vcc Out Gnd OSC 1.8432MHz 22Ω 0.1uF 22Ω The ragne of VDD must be from 4.5 to 5.5V and ISP function is not supported under 2MHz system clock. If the user supplied VDD is out of range, the external power is needed instead of the target system VDD. VDD(+5V) VSS VDD(+5V) VSS VSS VDD(+5V) 1uF 1uF 1uF 1uF * VPP : VDD + 4V From PC To MCU GND TxD RxD For the ISP operation, power consumption required is minimum 30mA. VDD VSS DTR VSS VSS 10uF/35V 100Ω 1kΩ 8.2kΩ 10kΩ 2N2907 VSS VSS VDD(+5V) 22Ω 22Ω VSS VSS 100pF 100pF

MAR. 2005 Ver 0.2 APPENDIX

MAR. 2005 Ver 0.2 i A. INSTRUCTION MAP LOW HIGH 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 000 SET1 dp.bit BBS A.bit,rel BBS dp.bit,rel ADC #imm ADC dp ADC dp+X ADC !abs ASL A ASL dp TCALL SETA1 .bit BIT dp POP A PUSH A BRK 001 CLRC SBC #imm SBC dp SBC dp+X SBC !abs ROL A ROL dp TCALL CLRA1 .bit COM dp POP X PUSH X BRA rel 010 CLRG CMP #imm CMP dp CMP dp+X CMP !abs LSR A LSR dp TCALL NOT1 M.bit TST dp POP Y PUSH Y PCALL Upage 011 DI OR #imm OR dp OR dp+X OR !abs ROR A ROR dp TCALL OR1 OR1B CMPX dp POP PSW PUSH PSW RET 100 CLRV AND #imm AND dp AND dp+X AND !abs INC A INC dp TCALL AND1 AND1B CMPY dp CBNE dp+X TXSP INC X 101 SETC EOR #imm EOR dp EOR dp+X EOR !abs DEC A DEC dp TCALL EOR1 EOR1B DBNE dp XMA dp+X TSPX DEC X 110 SETG LDA #imm LDA dp LDA dp+X LDA !abs TXA LDY dp TCALL LDC LDCB LDX dp LDX dp+Y XCN DAS 111 EI LDM dp,#imm STA dp STA dp+X STA !abs TAX STY dp TCALL STC M.bit STX dp STX dp+Y XAX STOP LOW HIGH 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 000 BPL rel CLR1 dp.bit BBC A.bit,rel BBC dp.bit,rel ADC {X} ADC !abs+Y ADC [dp+X] ADC [dp]+Y ASL !abs ASL dp+X TCALL JMP !abs BIT !abs ADDW dp LDX #imm JMP [!abs] 001 BVC rel SBC {X} SBC !abs+Y SBC [dp+X] SBC [dp]+Y ROL !abs ROL dp+X TCALL CALL !abs TEST !abs SUBW dp LDY #imm JMP [dp] 010 BCC rel CMP {X} CMP !abs+Y CMP [dp+X] CMP [dp]+Y LSR !abs LSR dp+X TCALL MUL TCLR1 !abs CMPW dp CMPX #imm CALL [dp] 011 BNE rel OR {X} OR !abs+Y OR [dp+X] OR [dp]+Y ROR !abs ROR dp+X TCALL DBNE Y CMPX !abs LDYA dp CMPY #imm RETI 100 BMI rel AND {X} AND !abs+Y AND [dp+X] AND [dp]+Y INC !abs INC dp+X TCALL DIV CMPY !abs INCW dp INC Y TAY 101 BVS rel EOR {X} EOR !abs+Y EOR [dp+X] EOR [dp]+Y DEC !abs DEC dp+X TCALL XMA {X} XMA dp DECW dp DEC Y TYA 110 BCS rel LDA {X} LDA !abs+Y LDA [dp+X] LDA [dp]+Y LDY !abs LDY dp+X TCALL LDA {X}+ LDX !abs STYA dp XAY DAA 111 BEQ rel STA {X} STA !abs+Y STA [dp+X] STA [dp]+Y STY !abs STY dp+X TCALL STA {X}+ STX !abs CBNE dp XYX NOP

MAR. 2005 Ver 0.2 B. INSTRUCTION SET 1. ARITHMETIC/ LOGIC OPERATION NO. MNEMONIC OP CODE BYTE NO CYCLE NO OPERATION FLAG NVGBHIZC ADC #imm Add with carry. ADC dp ADC dp + X ADC !abs NV--H-ZC ADC !abs + Y ADC [ dp + X ] ADC [ dp ] + Y ADC { X } AND #imm Logical AND AND dp A ← ( A ) ∧ ( M ) AND dp + X AND !abs N-----Z- AND !abs + Y AND [ dp + X ] AND [ dp ] + Y AND { X } ASL A Arithmetic shift left ASL dp N-----ZC ASL dp + X ASL !abs CMP #imm Compare accumulator contents with memory contents CMP dp ( A ) - ( M ) CMP dp + X CMP !abs N-----ZC CMP !abs + Y CMP [ dp + X ] CMP [ dp ] + Y CMP { X } CMPX #imm Compare X contents with memory contents CMPX dp ( X ) - ( M ) N-----ZC CMPX !abs CMPY #imm Compare Y contents with memory contents CMPY dp ( Y ) - ( M ) N-----ZC CMPY !abs COM dp 1’S Complement : ( dp ) ← ~( dp ) N-----Z- DAA DF Decimal adjust for addition N-----ZC DAS CF Decimal adjust for subtraction N-----ZC DEC A Decrement N-----Z- DEC dp M ← ( M ) - 1 DEC dp + X N-----Z- DEC !abs DEC X AF DEC Y BE DIV Divide : YA / X Q: A, R: Y NV--H-Z- “0” C

MAR. 2005 Ver 0.2 iii NO. MNEMONIC OP CODE BYTE NO CYCLE NO OPERATION FLAG NVGBHIZC EOR #imm Exclusive OR EOR dp A ← ( A ) ⊕ ( M ) EOR dp + X EOR !abs N-----Z- EOR !abs + Y EOR [ dp + X ] EOR [ dp ] + Y EOR { X } INC A Increment N-----ZC INC dp M ← ( M ) + 1 INC dp + X N-----Z- INC !abs INC X INC Y LSR A Logical shift right LSR dp N-----ZC LSR dp + X LSR !abs MUL Multiply : YA ← Y × A N-----Z- OR #imm Logical OR OR dp A ← ( A ) ∨ ( M ) OR dp + X OR !abs N-----Z- OR !abs + Y OR [ dp + X ] OR [ dp ] + Y OR { X } ROL A Rotate left through carry ROL dp N-----ZC ROL dp + X ROL !abs ROR A Rotate right through carry ROR dp N-----ZC ROR dp + X ROR !abs SBC #imm Subtract with carry SBC dp SBC dp + X SBC !abs NV--HZC SBC !abs + Y SBC [ dp + X ] SBC [ dp ] + Y SBC { X } TST dp Test memory contents for negative or zero ( dp ) - 00H N-----Z- XCN CE Exchange nibbles within the accumulator A7~A4 ↔ A3~A0 N-----Z- “0” C C C

MAR. 2005 Ver 0.2 2. REGISTER / MEMORY OPERATION NO. MNEMONIC OP CODE BYTE NO CYCLE NO OPERATION FLAG NVGBHIZC LDA #imm Load accumulator LDA dp A ← ( M ) LDA dp + X LDA !abs LDA !abs + Y N-----Z- LDA [ dp + X ] LDA [ dp ] + Y LDA { X } LDA { X }+ DB X- register auto-increment : A ← ( M ) , X ← X + 1 LDM dp,#imm Load memory with immediate data : ( M ) ← imm LDX #imm Load X-register LDX dp CC X ← ( M ) N-----Z- LDX dp + Y CD LDX !abs DC LDY #imm Load Y-register LDY dp Y ← ( M ) N-----Z- LDY dp + X LDY !abs STA dp Store accumulator contents in memory STA dp + X ( M ) ← A STA !abs STA !abs + Y STA [ dp + X ] STA [ dp ] + Y STA { X } STA { X }+ FB X- register auto-increment : ( M ) ← A, X ← X + 1 STX dp EC Store X-register contents in memory STX dp + Y ED ( M ) ← X STX !abs FC STY dp Store Y-register contents in memory STY dp + X ( M ) ← Y STY !abs TAX Transfer accumulator contents to X-register : X ← A N-----Z- TAY Transfer accumulator contents to Y-register : Y ← A N-----Z- TSPX AE Transfer stack-pointer contents to X-register : X ← sp N-----Z- TXA Transfer X-register contents to accumulator: A ← X N-----Z- TXSP Transfer X-register contents to stack-pointer: sp ← X N-----Z- TYA BF Transfer Y-register contents to accumulator: A ← Y N-----Z- XAX EE Exchange X-register contents with accumulator :X ↔ A XAY DE Exchange Y-register contents with accumulator :Y ↔ A XMA dp BC Exchange memory contents with accumulator XMA dp+X AD ( M ) ↔ A N-----Z- XMA {X} BB XYX FE Exchange X-register contents with Y-register : X ↔ Y

MAR. 2005 Ver 0.2 v 3. 16-BIT OPERATION 4. BIT MANIPULATION NO. MNEMONIC OP CODE BYTE NO CYCLE NO OPERATION FLAG NVGBHIZC ADDW dp 16-Bits add without carry YA ← ( YA ) + ( dp +1 ) ( dp ) NV--H-ZC CMPW dp Compare YA contents with memory pair contents : (YA) − (dp+1)(dp) N-----ZC DECW dp BD Decrement memory pair ( dp+1)( dp) ← ( dp+1) ( dp) - 1 N-----Z- INCW dp Increment memory pair N-----Z- LDYA dp Load YA YA ← ( dp +1 ) ( dp ) N-----Z- STYA dp DD Store YA ( dp +1 ) ( dp ) ← YA SUBW dp 16-Bits substact without carry YA ← ( YA ) - ( dp +1) ( dp) NV--H-ZC NO. MNEMONIC OP CODE BYTE NO CYCLE NO OPERATION FLAG NVGBHIZC AND1 M.bit Bit AND C-flag : C ← ( C ) ∧ ( M .bit ) AND1B M.bit Bit AND C-flag and NOT : C ← ( C ) ∧ ~( M .bit ) BIT dp Bit test A with memory : MM----Z- BIT !abs CLR1 dp.bit Clear bit : ( M.bit ) ← “0” CLRA1 A.bit Clear A bit : ( A.bit )← “0” CLRC Clear C-flag : C ← “0” CLRG Clear G-flag : G ← “0” --0----- CLRV Clear V-flag : V ← “0” -0--0--- EOR1 M.bit AB Bit exclusive-OR C-flag : C ← ( C ) ⊕ ( M .bit ) EOR1B M.bit AB Bit exclusive-OR C-flag and NOT : C ← ( C ) ⊕ ~(M .bit) LDC M.bit CB Load C-flag : C ← ( M .bit ) LDCB M.bit CB Load C-flag with NOT : C ← ~( M .bit ) NOT1 M.bit Bit complement : ( M .bit ) ← ~( M .bit ) OR1 M.bit Bit OR C-flag : C ← ( C ) ∨ ( M .bit ) OR1B M.bit Bit OR C-flag and NOT : C ← ( C ) ∨ ~( M .bit ) SET1 dp.bit Set bit : ( M.bit ) ← “1” SETA1 A.bit Set A bit : ( A.bit ) ← “1” SETC Set C-flag : C ← “1” SETG Set G-flag : G ← “1” --1----- STC M.bit EB Store C-flag : ( M .bit ) ← C TCLR1 !abs Test and clear bits with A : N-----Z- TSET1 !abs Test and set bits with A : N-----Z-

MAR. 2005 Ver 0.2 5. BRANCH / JUMP OPERATION NO. MNEMONIC OP CODE BYTE NO CYCLE NO OPERATION FLAG NVGBHIZC BBC A.bit,rel Branch if bit clear : BBC dp.bit,rel if ( bit ) = 0 , then pc ← ( pc ) + rel BBS A.bit,rel Branch if bit set : BBS dp.bit,rel if ( bit ) = 1 , then pc ← ( pc ) + rel BCC rel Branch if carry bit clear if ( C ) = 0 , then pc ← ( pc ) + rel BCS rel Branch if carry bit set if ( C ) = 1 , then pc ← ( pc ) + rel BEQ rel Branch if equal if ( Z ) = 1 , then pc ← ( pc ) + rel BMI rel Branch if minus if ( N ) = 1 , then pc ← ( pc ) + rel BNE rel Branch if not equal if ( Z ) = 0 , then pc ← ( pc ) + rel BPL rel Branch if minus if ( N ) = 0 , then pc ← ( pc ) + rel BRA rel Branch always pc ← ( pc ) + rel BVC rel Branch if overflow bit clear if (V) = 0 , then pc ← ( pc) + rel BVS rel Branch if overflow bit set if (V) = 1 , then pc ← ( pc ) + rel CALL !abs Subroutine call CALL [dp] M( sp)←( pcH ), sp←sp - 1, M(sp)← (pcL), sp ←sp - 1, if !abs, pc← abs ; if [dp], pcL← ( dp ), pcH← ( dp+1 ) . CBNE dp,rel FD Compare and branch if not equal : CBNE dp+X,rel if ( A ) ≠ ( M ) , then pc ← ( pc ) + rel. DBNE dp,rel AC Decrement and branch if not equal : DBNE Y,rel if ( M ) ≠ 0 , then pc ← ( pc ) + rel. JMP !abs Unconditional jump JMP [!abs] pc ← jump address JMP [dp] PCALL upage U-page call M(sp) ←( pcH ), sp ←sp - 1, M(sp) ← ( pcL ), sp ← sp - 1, pcL ← ( upage ), pcH ← ”0FFH” . TCALL n nA Table call : (sp) ←( pcH ), sp ← sp - 1, M(sp) ← ( pcL ),sp ← sp - 1, pcL ← (Table vector L), pcH ← (Table vector H)

MAR. 2005 Ver 0.2 vii 6. CONTROL OPERATION & etc. NO. MNEMONIC OP CODE BYTE NO CYCLE NO OPERATION FLAG NVGBHIZC BRK Software interrupt : B ← ”1”, M(sp) ← (pcH), sp ←sp-1, M(s) ← (pcL), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1, pcL ← ( 0FFDEH ) , pcH ← ( 0FFDFH) . ---1-0-- DI Disable interrupts : I ← “0” -----0-- EI Enable interrupts : I ← “1” -----1-- NOP FF No operation POP A sp ← sp + 1, A ← M( sp ) POP X sp ← sp + 1, X ← M( sp ) POP Y sp ← sp + 1, Y ← M( sp ) POP PSW sp ← sp + 1, PSW ← M( sp ) restored PUSH A M( sp ) ← A , sp ← sp - 1 PUSH X M( sp ) ← X , sp ← sp - 1 PUSH Y M( sp ) ← Y , sp ← sp - 1 PUSH PSW M( sp ) ← PSW , sp ← sp - 1 RET Return from subroutine sp ← sp +1, pcL ← M( sp ), sp ← sp +1, pcH ← M( sp ) RETI Return from interrupt sp ← sp +1, PSW ← M( sp ), sp ← sp + 1, pcL ← M( sp ), sp ← sp + 1, pcH ← M( sp ) restored STOP EF Stop mode ( halt CPU, stop oscillator )

MAR. 2005 Ver 0.2 C. MASK ORDER SHEET Refer to next page.

Mask Order & Verification Sheet MC80C04 - MD 1. Customer Information Company Name Application Order Date YYYY Tel: Fax: Name & Signature: .OTP file File Name (Please check mark√ into ) Customer should write inside thick line box. 64MQFP 64LQFP ( ) .OTP Customer’s logo Package 32K 48K ROM Size (bytes) Mask Data Check Sum ( ) 2. Device Information MM DD 4000 H (48K) 8000 H (32K) FFFFH 3. Marking Specification Customer logo is not required. YYWW KOREA MC80C04XXX-MD Customer’s part number If the customer logo must be used in the special mark, please submit a clean original of the logo. 4. Delivery Schedule Date Quantity MagnaChip Confirmation YYYY MM DD YYYY MM DD Customer sample Risk order pcs pcs E-mail address: 5. ROM Code Verification YYYY MM DD Verification date: Please confirm out verification data. Check sum: Tel: Fax: Name & Signature: E-mail address: YYYY MM DD Approval date: I agree with your verification data and confirm you to make mask set. Tel: Fax: Name & Signature: E-mail address: 24 or 32 or 48 Set “00H” in blanked area YYWW KOREA MC80C04XXX-MD 64SDIP 2.7V 2.7V 2.4V 3.0V * PFD Option 24K C000 H (24K) K : 64SDIP Q : 64MQFP L : 64LQFP 48 : 48K 32 : 32K 24 : 24K