MC80C0104

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MAGNACHIP SEMICONDUCTOR LTD. 8-BIT SINGLE-CHIP MICROCONTROLLERS MC80F0104/0204 MC80C0104/0204 Preliminary User’s Manual (Ver. 0.2)

Version 0.2 Published by 2005 MagnaChip semiconductor Ltd. All right reserved. Additional information of this manual may be served by MagnaChip semiconductor offices in Korea or Distributors and Representatives. MagnaChip semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and ot her data in this manual are corre ct and reliable; however, Magna Chip semiconductor is in no way re- sponsible for any violations of patents or other rights of the third party generated by the use of this manual.

REVISION HISTORY

VERSION 0.2 (MAR. 2005) This book Fix some errata. VERSION 0.1 (MAR. 2005) This book First Edition

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2

MC80F0104/0204 Preliminary Mar. 2005 Ver 0.2

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 1 MC80F0104/0204 MC80C0104/0204 CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH 10-BIT A/D CONVERTER AND UART 1. OVERVIEW

1.1 Description

The MC80F0104/0204 is advanced CMOS 8-bit microcontroller with 4K bytes of FLASH. This is a powerful microcontrol- ler which provides a highly flexible and cost effective soluti on to many embedded control applications. This provides the following features : 4K bytes of FLASH, 256 bytes of RAM, 8/16-bit timer/counter, watchdog timer, 10-bit A/D converter, 8-bit Serial Input/Output, UART, buzzer driving port, 10-bit PWM output and on-chip oscillator and clock circuitry. It also has ONP, noise filter, PFD for improving noise immunity. In addition, the MC80F0104/0204 supports power saving modes to reduce power consumption. The MC80C0104/0204 is the MASK ROM version of the MC80F0104/0204. It is fully compatible to the MC80F0104/0204 in function. This document explains the base MC80F0204, the other’s eliminated functions are same as below table.1.2 Features

• 4K Bytes On-chip FLASH - Endurance : 100 times - Retention time : 10 years
• 256 Bytes On-chip Data RAM (Included stack memory)
• Minimum Instruction Execution Time: - 333ns at 12MHz (NOP instruction)
• Programmable I/O pins (LED direct driving can be a source and sink) - MC80F0204 : 18(17) - MC80F0104 : 14(13)
• One 8-bit Basic Interval Timer
• Four 8-bit Timer/counters (or two 16-bit Timer/counter)
• One Watchdog timer
• Two 10-bit High Speed PWM Outputs
• 10-bit A/D converter - MC80F0204 : 10 channels - MC80F0104 : 8 channels
• Two 8-bit Serial Communication Interface - One Serial I/O and one UART
• One Buzzer Driving port - 488Hz ~ 250kHz@4MHz
• Four External Interrupt input ports
• On-chip POR (Power on Reset)
• Fourteen Interrupt sources - External input : 4 - Timer : 6 - A/D Conversion : 1 - Serial Interface : 1 - UART : 2
• Built in Noise Immunity Circuit - Noise Canceller - PFD (Power fail detector) - ONP (Oscillation Noise Protector)
• Operating Voltage & Frequency (MC80F0104/ 0204) Device Name FLASH (ROM) Size RAM ADC I/O PORT Package FLASH MASK ROM MC80F0204 MC80C0204 4KB 256B 10 channel 18 port 20 PDIP, 20SOP MC80F0104 MC80C0104 8 channel 14 port 16 PDIP, 16 SOP

MC80F0104/0204 Preliminary 2 Mar. 2005 Ver 0.2

• Operating Voltage & Frequency(MC80C0104/ 0204)
• Operating Temperature : -40°C ~ 85°C
• Power Saving Modes - STOP mode - SLEEP mode - RC-WDT mode
• Oscillator Type - Crystal - Ceramic resonator - External RC Oscillator (C can be omitted) - Internal Oscillator (4MHz/2MHz)

1.3 Development Tools

The MC80F0104/0204 is supported by a full-featured macro as- sembler, an in-circu it emulator CHOICE-Dr. TM and OTP pro- grammers. There are two different type of programmers such as single type and gang type. For mode detail, Macro assembler op- erates under the MS-Windows 95 and upversioned Windows OS. Please contact sales part of MagnaChip semiconductor. Software - MS-Windows based assembler - MS-Windows based Debugger - HMS800 C compiler Hardware (Emulator) - CHOICE-Dr. - CHOICE-Dr. EVA80C0x B/D FLASH Writer - CHOICE - SIGMA I/II(Single writer) - PGM Plus I/II/III(Single writer) - Standalone GANG4 I/II(Gang writer) Choice-Dr. (Emulator) PGMplus III ( Single Writer ) Standalone Gang4 II ( Gang Writer )

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 3

1.4 Ordering Information

Device name ROM Size RAM size Package Mask version MC80C0204B MC80C0204D MC80C0104B MC80C0104D 4K bytes 4K bytes 4K bytes 4K bytes 256 bytes 20PDIP 20SOP 16PDIP 16SOP FLASH version MC80F0204B MC80F0204D MC80F0104B MC80F0104D 4K bytes FLASH 4K bytes FLASH 4K bytes FLASH 4K bytes FLASH 256 bytes 20PDIP 20SOP 16PDIP 16SOP

MC80F0104/0204 Preliminary 4 Mar. 2005 Ver 0.2 2. BLOCK DIAGRAM ALU Accumulator Stack Pointer Interrupt Controller Data Memory 10-bit Converter A/D 8-bit Counter Timer/ Program Memory Data Table PC 8-bit Basic Timer Interval Watch-dog Timer Instruction R0 R1 Buzzer Driver PSW System controller Timing generator System Clock Controller Clock Generator RESET R00 / INT3 / SCK R01 / AN1 / SI R02 / AN2 / SOUT R03 / AN3 / INT2 R04 / AN4 / EC0 / RXD R05 / AN5 / T0O / TXD R06 / AN6 / T2O / ACLK R07 / AN7 / EC1 R10 / AN0 / AV REF / PWM1O R11 / INT0 / PWM3O R12 / INT1 / BUZO R13 R14 V DD VSS Power Supply Decoder High PWM Speed XOUT / R34 SIO/UART R31 / AN14 R32 / AN15 XIN / R33

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 5 3. PIN ASSIGNMENT R02 / AN2 / SOUT R01 / AN1 / SI R00 / INT3 / SCK VSS RESET / R35 XOUT / R34 XIN / R33 R32 / AN15 R31 / AN14 R05 / AN5 / T0O / TXD R06 / AN6 / T2O / ACLK R07 / AN7 / EC1 VDD R10 / AN0 / AVREF / PWM1O R11 / INT0 / PWM3O

20 PDIP

16 PDIP

R03 / AN3 / INT2R04 / AN4 / EC0 / RXD 20

16 SOP

R03 / AN3 / INT2R04 / AN4 / EC0 / RXD 20 MC80F0104B/0104D

20 SOP

MC80F0104/0204 Preliminary 6 Mar. 2005 Ver 0.2 4. PACKAGE DRAWING 1.043 0.050 TYP 0.100 TYP 0.300 0.270 0.014 0 ~ 15° MAX 0.180 MIN 0.0150.120

20 PDIP unit: inch

1.010 0.021 0.140 0.065 0.008 0.245 0.015 0.291 0.398 0.5118 0.104 0.013 TYP 0.050 0.004 0.0091 0 ~ 8° 0.016 0.419 0.299 0.4961 0.093 0.020 0.042 0.0125 0.0118

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 7 0.765 0.050 TYP 0.100 TYP 0.300 0.260 0.014 0 ~ 15° MAX 0.180 MIN 0.0150.1200.292 0.398 0.412 0.104 0.014 TYP 0.050 0.004 0.0091 0 ~ 8° 0.016 unit: inch MAX MIN 0.745 0.022 0.140 0.065 0.008 0.240 0.416 0.299 0.402 0.094 0.019 0.040 0.0125 0.0118 0.015

MC80F0104/0204 Preliminary 8 Mar. 2005 Ver 0.2 5. PIN FUNCTION VDD: Supply voltage. VSS: Circuit ground. RESET: Reset the MCU. XIN: Input to the inverting oscillator amplifier and input to the internal main clock operating circuit. XOUT: Output from the inverting oscillator amplifier. R00~R07: R0 is an 8-bit, CMOS, bidirectional I/O port. RA pins can be used as outputs or inputs according to “1” or “0” written the their Port Direction Register(R0IO). In addition, R0 serves the functions of the various special features in Table 5-1 . R10~R14: R1 is a 5-bit, CMOS, bidirectional I/O port. R1 pins can be used as outputs or inputs according to “1” or “0” written the their Port Direction Register (R1IO). R1 serves the functions of the various following special features in Table 5-2 R31~R34: R3 is an 4-bit, CMOS, bidirectional I/O port. R3 pins can be used as outpu ts or inputs according to “1” or “0” written the their Port Direction Register (R3IO). R3 serves the functions of the serial interface following special features in Table 5-3 . Port pin Alternate function R00 R01 R02 R03 R04 R05 R06 R07 INT3 ( External Interrupt Input Port3 ) SCK ( SPI CLK ) AN1 ( Analog Input Port 1 ) SI ( SPI Serial Data Input ) AN2 ( Analog Input Port 2 ) SOUT ( SPI Serial Data Output ) AN3 ( Analog Input Port 3 ) INT2 ( External Interrupt Input Port2 ) AN4 ( Analog Input Port 4 ) EC0 ( Event Counter Input Source 0 ) RXD ( UART Data Input ) AN5 ( Analog Input Port 5 ) T0O (Timer0 Clock Output ) TXD ( UART Data Output ) AN6 ( Analog Input Port 6 ) T2O (Timer2 Clock Output ) ACLK ( UART Clock Input ) AN7 ( Analog Input Port 7 ) EC1 ( Event Counter Input Source 1 ) Table 5-1 R0 Port Port pin Alternate function R10 R11 R12 R13 R14 AN0 ( Analog Input Port 0 ) AVref ( External Analog Reference Pin ) PWM1O ( PWM1 Output ) INT0 ( External Interrupt Input Port 0 ) PWM3O ( PWM3 Output ) INT1 ( External Interrupt Input Port 1 ) BUZ ( Buzzer Driving Output Port ) Table 5-2 R1 Port Port pin Alternate function R31 R32 R33 R34 R35 AN14 ( Analog Input Port 14 ) AN15 ( Analog Input Port 15 ) X IN ( Oscillation Input ) XOUT ( Oscillation Output ) RESET ( Reset input port ) Table 5-3 R3 Port

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 9 PIN NAME Pin No. (20PDIP) In/Out Function VDD 5 - Supply voltage VSS 16 - Circuit ground RESET (R35) 15 I ( I ) Reset signal input Input only port XIN (R33) 13 I (I/O) Oscillation Input Normal I/O Port XOUT (R34) 14 O (I/O) Oscillation Output Normal I/O Port R00 (INT3 / SCK) 17 I/O (Input / I/O) Normal I/O Ports External Interrupt Input3 / SPI clock Input/Output R01 (AN1 / SI) 18 I/O (Input/Input) Analog Input Port 1 / SPI Data Input R02 (AN2 / SOUT) 19 I/O (Input/Output) Analog Input Port 2 / SPI Data Output R03 (AN3 / INT2) 20 I/O (Input/Input) Analog Input Port 3 / External Interrupt Input2 R04 (AN4 / EC0 / RXD) 1 I/O (Input/Input/Input) Analog Input Port 4 / Event Counter Input 0 / UART Data Input R05 (AN5 / T0O / TXD) 2 I/O (Input/Output/Output) Analog Input Port 5 / Timer0 Output / UART Data Output R06 (AN6 / T2O / ACLK) 3 I/O (Input/Output/Input) Analog Input Port 6 / Timer2 Output / UART Clock Input R07 (AN7 / EC1) 4 I/O (Input/Input) Analog Input Port 7 / Event Counter Input 1 R10 (AN0 / AVREF / PWM1O) 6 I/O (Input/Input/Output) Analog Input Port 0 / Analog Reference / PWM 1 output R11 (INT0 / PWM3O) 7 I/O (Input/Output) External Interrupt Input 0 R12 (INT1 / BUZO) 8 I/O (Input/Output) External Interrupt Input 1 / Buzzer Driving Output R13 9 I/O - R14 10 I/O - R31 (AN14) 11 I/O (Input) Analog Input Port 14 R32 (AN15) 12 I/O (Input) Analog Input Port 15 Table 5-4 Pin Description

MC80F0104/0204 Preliminary 10 Mar. 2005 Ver 0.2 6. PORT STRUCTURES R13~R14 R31 (AN14), R32 (AN15) R01 (AN1 / SI) R03 (AN3 / INT2), R07 (AN7 / EC1) VDD VSS Pin Data Reg. Direction Reg. Pull-up Tr. Pull-up Reg. MUX VDD Data Bus VDD VSS Open Drain Reg. RD RD AN[15:14] ADEN & ADS[3:0] (ADCM) VDD VSS Pin Data Reg. Direction Reg. Pull-up Tr. Pull-up Reg. MUX VDD Data Bus VDD VSS Open Drain Reg. SI SI_EN (SIOM) Noise Filter RD AN[1] ADEN & ADS[3:0] VDD VSS Pin Data Reg. Direction Reg. Pull-up Tr.Pull-up Reg. MUX VDD Data Bus VDD VSS Open Drain Reg. (ADCM) INT2, EC1 INT2E (PSR0.2), EC1E (PSR0.5) Noise Filter RD AN[3, 7] ADEN & ADS[3:0] VDD VSS Pin Data Reg. Direction Reg. Pull-up Tr. Pull-up Reg. MUX VDD Data Bus VDD VSS Open Drain Reg. (ADCM)

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 11 R04 (AN4 / EC0 / RXD) R11 (INT0 / PWM3O), R12 (INT1 / BUZO) R02 (AN2 / SOUT) R00 (INT3 / SCK) EC0 EC0E (PSR0) Noise Filter RD AN[1] ADEN & ADS[3:0] VDD VSS Pin Data Reg. Direction Reg. Pull-up Tr. Pull-up Reg. MUX VDD Data Bus VDD VSS Open Drain Reg. (ADCM) RXD RXE (ASIMR) Noise Filter INT0,INT1 INT0E(PSR0.0) Noise Filter RD VDD VSS Pin Data Reg. Direction Reg. Pull-up Tr. Pull-up Reg. MUX VDD Data Bus VDD VSS Open Drain Reg. INT1E(PSR0.1) MUX PWM3OE(PSR0.7) BUZOE(PSR1.2) PWM3O, BUZO SOUT(SI) SO_OUT_EN (SIOM) Noise Filter RD VDD VSS Pin Data Reg. Direction Reg. Pull-up Tr. Pull-up Reg. MUX VDD Data Bus VDD VSS Open Drain Reg. MUX SO_EN(SIOM) SOUT AN[2] ADEN & ADS[3:0] (ADCM) SCK SCK_EN(SIOM) Noise Filter RD VDD VSS Pin Data Reg. Direction Reg. Pull-up Tr. Pull-up Reg. MUX VDD Data Bus VDD VSS Open Drain Reg. MUX SCKO_EN(SIOM) SCK INT3 INT3E(PSR0.3) Noise Filter

MC80F0104/0204 Preliminary 12 Mar. 2005 Ver 0.2 R06 (AN6 / T2O / ACLK) R10 (AN0 / AVREF / PWM1O) R05 (AN5 / T0O / TXD) RESET AN[6] ADEN & ADS[3:0] RD VDD VSS Pin Data Reg. Direction Reg. Pull-up Tr.Pull-up Reg. MUX VDD Data Bus VDD VSS Open Drain Reg. MUX T2OE(PSR1.1) T2O ACLK TPS[2:0](BRGCR[6:4]) Noise Filter (ADCM) AN[0] ADEN & ADS[3:0] RD VDD VSS Pin Data Reg. Direction Reg. Pull-up Tr. Pull-up Reg. MUX VDD Data Bus VDD VSS Open Drain Reg. MUX PWM1OE(PSR0.6) PWM1O ADC Reference AVREFS(PSR1.3) (ADCM) MUX VDD Voltage Input AN[5] ADEN & ADS[3:0] RD VDD VSS Pin Data Reg. Direction Reg. Pull-up Tr. Pull-up Reg. MUX VDD Data Bus VDD VSS Open Drain Reg. MUX T0OE(PSR1.0) TXD (ADCM) MUX T0O TXE(ASIMR.7) Pin VDD VSS Data Bus Mask only Pull-up Tr.Pull-up Reg. VDD RD Internal Reset Reset Disable (Configuration option bit)

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 13 XIN, XOUT (Crystal or Ceramic Resonator) XIN, XOUT (External RC or R oscillation) R33 (XIN), R34 (XOUT) VDD VSS VDD VSS VDD VDD STOP MAIN CLOCK XIN XOUT XIN VDD VSS XOUT VDD VSS VDD STOP MAIN CLOCK fXIN ÷ 4 RD VDD VSS Data Reg. Direction Reg. Pull-up Tr. Pull-up Reg. MUX VDD Data Bus VDD VSS Open Drain Reg. RD VDD VSS XOUT Data Reg. Direction Reg. Pull-up Tr. Pull-up Reg. MUX VDD Data Bus VDD VSS Open Drain Reg. System Clock ÷ 4 IN4MCLKXO IN2MCLKCO EXRCXO CLOCK option (Configuration option bit) IN4MCLKXO IN2MCLKXO CLOCK option (Configuration option bit) / R34 XIN / R33 Main Clock (to ONP Block) IN4MCLK IN2MCLK IN4MCLK IN2MCLK EXRC

MC80F0104/0204 Preliminary 14 Mar. 2005 Ver 0.2 7. ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

Voltage on any pin with respect to Ground (VSS) Maximum output current sourced by (IOH per I/O Pin) Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any oth- er conditions above thos e indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

7.2 Recommended Operating Conditions

7.3 A/D Converter Characteristics

(Ta=-40~85°C, VSS=0V, VDD=2.7~5.5V @fXIN=8MHz) Parameter Symbol Con dition Min. Max. Unit Supply Voltage VDD fXIN=0.4~12MHz fXIN=0.4~8MHz 4.5 2.5 5.5 5.5 V Operating Frequency fXIN VDD=4.5~5.5V VDD=2.7~5.5V(MC80F0X04) VDD=2.0~5.5V(MC80C0X04) 0.4 0.4 0.4 4.2 MHz Operating Temperature T OPR VDD=2.7~5.5V(MC80F0X04) VDD=2.0~5.5V(MC80C0X04) -40 85 °C Parameter Symbol Conditions Min. Typ. Max. Unit Resolution - - 10 - BIT Overall Accuracy - -- - ±3L S B Integral Linearity Error ILE VDD = AVREF = 5V CPU Clock = 10MHz VSS = 0V - −± 3L S B Differential Linearity Error DLE - −± 3L S B Offset Error of Top EOT - ±1 ±3L S B Offset Error of Bottom EOB - ±0.5 ±3L S B Conversion Time TCONV -1 3 - - µS Analog Input Voltage VAIN - VSS - VDD (AVREF) V Analog Reference Voltage AVREF -T B D - VDD V Analog Input Current IAIN VDD = AVREF = 5V -- 1 0 µA Analog Block Current IAVDD VDD = AVREF = 5V VDD = AVREF = 3V 0.5 1.5 mA VDD = AVREF = 5V power down mode - 100 500 nA

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 15

7.4 DC Electrical Characteristics

(TA=-40~85°C, VDD=5.0V, VSS=0V), Parameter Symbol Pin Condition Specifications Unit Min. Typ. Max. Input High Voltage VIH1 XIN, RESET 0.8 VDD - VDD VVIH2 Hysteresis Input1 0.8 VDD - VDD VIH3 Normal Input 0.7 VDD - VDD Input Low Voltage VIL1 XIN, RESET 0- 0.2 VDD VVIL2 Hysteresis Input1 0- 0.2 VDD VIL3 Normal Input 0 - 0.3 VDD Output High Voltage VOH All Output Port VDD=5V, IOH=-5mA V DD -1 -- V Output Low Voltage VOL All Output Port VDD=5V, IOL=10mA - -1 V Input Pull-up Current IP Normal Input VDD=5V -70 - -130 µA Input High Leakage Current IIH1 All Pins (except XIN)V DD=5V --5 µA IIH2 XIN VDD=5V -- 1 5 µA Input Low Leakage Current IIL1 All Pins (except XIN)V DD=5V -5 - - µA IIL2 XIN VDD=5V -15 - - µA Hysteresis | VT | Hysteresis Input1 VDD=5V 0.5 - - V PFD Voltage VPFD VDD 2.0 - 3.0 V POR Voltage VPOR VDD 2.4 V POR Start Voltage2 VSTART VDD 0T B D V POR Rising Time2 TRISE VDD TBD V/ms Internal RC WDT Period TRCWDT XOUT VDD=5.5V 36 - 90 µS Operating Current IDD VDD VDD=5.5V, fXIN=12MHz -69 m A Wake-up Timer Mode Current IWKUP VDD VDD=5.5V, fXIN=12MHz -12 m A RCWDT Mode Current at STOP Mode IRCWDT VDD VDD=5.5V -2 0 5 0 µA Stop Mode Current ISTOP VDD VDD=5.5V, fXIN=12MHz -0 . 7 1 . 6 µA Internal Oscillation Frequency fIN_CLK XOUT VDD=5V 345 M H z RESET Input Noise Cancel Time TRST_NC RESET VDD=5V 1.5 1.8 µs External RC Oscillator Frequency fRC-OSC fXOUT = fRC-OSC ÷ 4 VDD=5.5V R=30kΩ, C=10pF TBD MHz fR-OSC fXOUT = fR-OSC ÷ 4V DD=5.5V, R=30kΩ TBD MHz 1. Hysteresis Input: INT0 ~INT3(R11,R12,R03,R00),SIO(R00,R01,R02),UART(R04,R06),EC0,EC1 2. V START and TRiSE parameter is presented for design guidance only and not tested or guaranteed.

MC80F0104/0204 Preliminary 16 Mar. 2005 Ver 0.2

7.5 AC Characteristics

(TA=-40~+85°C, VDD=5V±10%, VSS=0V) Figure 7-1 Timing Chart Parameter Symbol Pins Specifications Unit Min. Typ. Max. Operating Frequency fCP XIN 1-8 M H z External Clock Pulse Width tCPW XIN 50 - - nS External Clock Transition Time tRCP,tFCP XIN -- 2 0 n S Oscillation Stabilizing Time tST XIN, XOUT -- 2 0 m S External Input Pulse Width tEPW INT0, INT1, INT2, INT3 EC0, EC1 2-- tSYS RESET Input Width tRST RESET 8-- tSYS tRCP tFCP XIN INT0, INT1 INT2, 0.5V VDD-0.5V 0.2VDD RESET 0.2VDD 0.8VDD EC0, tRST tEPWtEPW 1/fCP tCPW tCPW tSYS INT3 EC1

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 17

7.6 Typical Characteristics

These graphs and tables provided in this section are for de- sign guidance only and are not tested or guaranteed. In some graphs or tables the data presented are out- side specified operating range (e.g. outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean − 3σ) respectively where σ is standard deviation TBD

MC80F0104/0204 Preliminary 18 Mar. 2005 Ver 0.2 8. MEMORY ORGANIZATION The MC80F0104/0204 has separate address spaces for Program memory and Data Memory. 4K bytes program memory can only be read, not written to. Data memory can be read and written to up to 256 bytes in- cluding the stack area.

8.1 Registers

This device has six registers that are the Program Counter (PC), a Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register. Figure 8-1 Configuration of Registers Accumulator: The Accumulator is the 8-bit general pur- pose register, used for data operation such as transfer, tem- porary saving, and conditional judgement, etc. The Accumulator can be used as a 16-bit register with Y Register as shown below. Figure 8-2 Configuration of YA 16-bit Register X, Y Registers: In the addressing mode which uses these index registers, the register contents are added to the spec- ified address, which becomes the actual address. These modes are extremely effectiv e for referencing subroutine tables and memory tables. The index registers also have in- crement, decrement, comparison and data transfer func- tions, and they can be used as simple accumulators. Stack Pointer: The Stack Pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. Stack Pointer identifies the location in the stack to be accessed (save or restore). Generally, SP is automatically updated when a subroutine call is executed or an interrupt is accepted. However, if it is used in excess of the stack area permitted by the data memory allocating configurat ion, the user-processed data may be lost. The stack can be located at any position within 1C0 H to 1FFH of the internal data memory. The SP is not initialized by hardware, requiring to write the initial value (the loca- tion with which the use of the stack starts) by using the ini- tialization routine. Normally, the initial value of “FF H” is used. Note: The Stack Pointer must be initialized by software because its value is undefined after Reset. Example: To initialize the SP LDX #0FFH TXSP ; SP ← FFH Program Counter: The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset rou- tine address (PC H:0FFH, PCL:0FEH). Program Status Word: The Program Status Word (PSW) contains several bits that re flect the current state of the CPU. The PSW is described in Figure 8-3 . It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD operation), the Interrupt enable flag, the Zero flag, and the Carry flag. [Carry flag C] This flag stores any carry or borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction. [Zero flag Z] This flag is set when the result of an arithmetic operation or data transfer is “0” and is cleared by any other result. ACCUMULATOR X REGISTER Y REGISTER STACK POINTER PROGRAM COUNTER PROGRAM STATUS WORD X A SP Y PCL PSW PCH Two 8-bit Registers can be used as a “YA” 16-bit Register Y A Y A SP01H Stack Address (1C0H ~ 1FFH) Bit 15 Bit 0 87 Hardware fixed C0H~FFH

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 19 Figure 8-3 PSW (Program Status Word) Register [Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All inter- rupts are disabled when cleared to “0”. This flag immedi- ately becomes “0” when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction. [Half carry flag H] After operation, this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V). [Break flag B] This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector ad- dress. [Direct page flag G] This flag assigns RAM page for direct addressing mode. In the direct addressing mode, addressing area is from zero page 00 H to 0FFH when this flag is "0". If it is set to "1", addressing area is assigned 100 H to 1FF H. It is set by SETG instruction and cleared by CLRG. [Overflow flag V] This flag is set to “1” when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction ex- ceeds +127(7F H) or -128(80 H). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the re- sult of a data or arithmetic operation. When the BIT in- struction is executed, bit 7 of memory is copied to this flag. N NEGATIVE FLAG V G B H I Z C MSB LSB RESET VALUE: 00HPSW OVERFLOW FLAG BRK FLAG CARRY FLAG RECEIVES ZERO FLAG INTERRUPT ENABLE FLAG CARRY OUT HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS SELECT DIRECT PAGE when G=1, page is selected to “page 1”

MC80F0104/0204 Preliminary 20 Mar. 2005 Ver 0.2 Figure 8-4 Stack Operation At execution of a CALL/TCALL/PCALL PCL PCH 01FC SP after execution SP before execution 01FD 01FD 01FE 01FF 01FF Push down At acceptance of interrupt PCL PCH 01FC 01FC 01FD 01FE 01FF 01FF Push down PSW At execution of RET instruction PCL PCH 01FC 01FF 01FD 01FE 01FF 01FD Pop up At execution of RET instruction PCL PCH 01FC 01FF 01FD 01FE 01FF 01FC Pop up PSW 01C0H 01FFH Stack depth At execution of PUSH instruction A 01FC 01FE 01FD 01FE 01FF 01FF Push down SP after execution SP before execution PUSH A (X,Y,PSW) At execution of POP instruction A 01FC 01FF 01FD 01FE 01FF 01FE Pop up POP A (X,Y,PSW)

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 21

8.2 Program Memory

A 16-bit program counter is capable of addressing up to 64K bytes, but this device has 4K bytes program memory space only physically implem ented. Accessing a location above FFFF H will cause a wrap-around to 0000H. Figure 8-5 , shows a map of Program Memory. After reset, the CPU begins execution from reset vector which is stored in address FFFE H and FFFFH as shown in Figure 8-6 . As shown in Figure 8-5 , each area is assigned a fixed lo- cation in Program Memory. Program Memory area con- tains the user program Figure 8-5 Program Memory Map Page Call (PCALL) area cont ains subroutine program to reduce program byte length by using 2 bytes PCALL in- stead of 3 bytes CALL instruction. If it is frequently called, it is more useful to save program byte length. Table Call (TCALL) causes the CPU to jump to each TCALL address, where it commences the execution of the service routine. The Table Call service area spaces 2-byte for every TCALL: 0FFC0 H for TCALL15, 0FFC2 H for TCALL14, etc., as shown in Figure 8-7 . Example: Usage of TCALL The interrupt causes the CPU to jump to specific location, where it commences the executi on of the service routine. The External interrupt 0, for example, is assigned to loca- tion 0FFFCH. The interrupt service locations spaces 2-byte interval: 0FFFA H and 0FFFB H for External Interrupt 1, 0FFFCH and 0FFFDH for External Interrupt 0, etc. Any area from 0FF00H to 0FFFFH, if it is not going to be used, its service location is available as general purpose Program Memory. Figure 8-6 Interrupt Vector Area Interrupt Vector Area FEFFH FF00H FFC0H FFDFH FFE0H FFFFH PCALL area F000H TCALL area MC80F0104/0204, 4K FLASH LDA #5 TCALL 0FH ; 1BYTE INSTRUCTION :; INSTEAD OF 3 BYTES :; NORMAL CALL ;TABLE CALL ROUTINE FUNC_A: LDA LRG0 RET FUNC_B: LDA LRG1 RET ;TABLE CALL ADD. AREA ORG 0FFC0H ; TCALL ADDRESS AREA DW FUNC_A DW FUNC_B 0FFE0H Address Vector Area Memory EA EC EE FA FC FE Basic Interval Timer Watchdog Timer Interrupt A/D Converter External Interrupt 3 Serial Input/Output (SIO) External Interrupt 1 External Interrupt 0 RESET External Interrupt 2 Timer/Counter 3 Interrupt Timer/Counter 0 Interrupt UART Rx interrupt UART Tx interrupt Timer/Counter 1 Interrupt Timer/Counter 2 Interrupt

MC80F0104/0204 Preliminary 22 Mar. 2005 Ver 0.2 Figure 8-7 PCALL and TCALL Memory Area PCALL→ rel 4F35 PCALL 35H TCALL→ n 4A TCALL 4 0FFC0H Address Program Memory 0FF00H Address PCALL Area Memory 0FFFFH PCALL Area (256 Bytes) * means that the BRK software interrupt is using same address with TCALL0. NOTE: TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK * CA CB CC CD CE CF DA DB DC DD DE DF ~~ ~ NEXT 0FF35H 0FF00H 0FFFFH 11111111 11010110 01001010 PC: FH FH DH 6H ~~ ~ 250FFD6H 0FF00H 0FFFFH NEXT 0FFD7H 0D125H Reverse

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 23 Example: The usage soft ware example of Vector address for MC80F0204. ;Interrupt Vector Table ORG 0FFE0H DW BIT_TIMER ; BIT DW WDT ; WDT DW ADC ; AD Converter DW Not_used ; DW TIMER3 ; Timer-3 DW TIMER2 ; Timer-2 DW TIMER1 ; Timer-1 DW TIMER0 ; Timer-0 DW SIO ; Serial Interface DW TX ; UART Tx DW RX ; UART Rx DW INT3 ; Ext Int.3 DW INT2 ; Ext Int.2 DW INT1 ; Ext Int.1 DW INT0 ; Ext Int.0 DW RESET ; Reset ORG 0F000H ; 4K bytes ROM Start address ; MAIN PROGRAM * RESET: DI ;Disable All Interrupt ;RAM Clear Routine LDX #0 RAM_Clear0: LDA #0 ;Page0 RAM Clear(0000h ~ 00BFh) STA {X}+ CMPX #0C0h BNE RAM_Clear0 LDM RPR,#1 ;Page Select SETG LDX #0C0h RAM_Clear1: LDA #0 STA {X}+ CMPX #00h BNE RAM_Clear1 RAM_Clear_Finish: CLRG ;Page0 Select LDX #0FFh ;Initial Stack Pointer TXSP ;Initialize IO LDM R0, #0 ;Normal Port R0 LDM R0IO,#0FFH ;Normal Port R0 Direction

MC80F0104/0204 Preliminary 24 Mar. 2005 Ver 0.2

8.3 Data Memory

Figure 8-8 shows the internal Data Memory space availa- ble. Data Memory is divided into three groups, a user RAM, control registers, and Stack memory. Figure 8-8 Data Memory Map User Memory The MC80F0104/0204 has 256 × 8 bits for the user mem- ory (RAM). RAM pages are selected by RPR (See Figure 8-9 ). Note: After setting RPR(RAM Page Select Register), be sure to execute SETG instruction. When ex ecuting CLRG instruction, be selected PAGE0 regardless of RPR. Control Registers The control registers are us ed by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and I/O ports. The control registers are in address range of 0C0 H to 0FFH. Note that unoccupied addre sses may not be implemented on the chip. Read accesses to th ese addresses will in gen- eral return random data, and write accesses will have an in- determinate effect. More detailed informations of each register are explained in each peripheral section. Note: Write only registers can not be accessed by bit manipula- tion instruction. Do not use read-modify-write instruction. Use byte manipulation instruction, for example “LDM”. Example; To write at CKCTLR LDM CKCTLR,#0AH ;Divide ratio(÷32) Stack Area The stack provides the area where the return address is saved before a jump is perfo rmed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return instruction [RETI] restor es the contents of the pro- gram counter and flags. The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save. Refer to Figure 8-4 on page 20. Figure 8-9 RPR(RAM Page Select Register) User Memory Control Registers 0000H 00BFH 00C0H PAGE0 PAGE1 (When “G-flag=0”, this page0 is selected) or Stack Area User Memory 00FFH 0100H 01FFH (192Bytes) (64Bytes) Not Available 01BFH 01C0H System clock source select 000 : PAGE0 001 : PAGE1 INITIAL VALUE: ---- -000B ADDRESS: 0E1HRPR 010 : Not used 011 : Not used 76543210 R/W R/W R/W RPR2-- RPR1 RPR0 100 : Not used others : Setting prohibited

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 25 Address Register Name Symbol R/W Initial Value Addressing Mode76543210 0 0 C 0 R 0 p o r t d a t a r e g i s t e r R 0 R / W 00000000 byte, bit1 0 0 C 1 R 0 p o r t I / O d i r e c t i o n r e g i s t e r R 0 I O W 00000000 byte2 00C2 R1 port data register R1 R/W - - - 0 0 0 0 0 byte, bit 00C3 R1 port I/O direction register R1IO W - - - 0 0 0 0 0 byte 0 0 C 6 R 3 p o r t d a t a r e g i s t e r R 3 R / W - -00000- b y t e , b i t 0 0 C 7 R 3 p o r t I / O d i r e c t i o n r e g i s t e r R 3 I O W 0000000- b y t e 0 0 C 8 P o r t 0 O p e n D r a i n S e l e c t i o n R e g i s t e r R 0 O D R / W 00000000 b y t e 00C9 Port 1 Open Drain Selection Register R1OD W - - - 0 0 0 0 0 byte 00CB Port 3 Open Drain Selection Register R3OD W - - - 0 0 0 0 - byte 0 0 D 0 T i m e r 0 m o d e c o n t r o l r e g i s t e r T M 0 R / W - -000000 b y t e , b i t 00D1 T i m e r 0 r e g i s t e r T 0 R 00000000 byteT i m e r 0 d a t a r e g i s t e r T D R 0 W 11111111 Timer 0 capture data register CDR0 R 0 0 000000 0 0 D 2 T i m e r 1 m o d e c o n t r o l r e g i s t e r T M 1 R / W 00000000 b y t e , b i t 00D3 T i m e r 1 d a t a r e g i s t e r T D R 1 W 11111111 b y t e T i m e r 1 P W M p e r i o d r e g i s t e r T 1 P P R W 11111111 b y t e 00D4 T i m e r 1 r e g i s t e r T 1 R 00000000 byte Timer 1 capture data register CDR1 R 0 0 000000 T i m e r 1 P W M d u t y r e g i s t e r T 1 P D R R / W 00000000 b y t e 00D5 Timer 1 PWM high register T1PWHR W - - - - 0 0 0 0 byte 0 0 D 6 T i m e r 2 m o d e c o n t r o l r e g i s t e r T M 2 R / W - -000000 b y t e , b i t 00D7 T i m e r 2 r e g i s t e r T 2 R 00000000 byteT i m e r 2 d a t a r e g i s t e r T D R 2 W 11111111 Timer 2 capture data register CDR2 R 0 0 000000 0 0 D 8 T i m e r 3 m o d e c o n t r o l r e g i s t e r T M 3 R / W 00000000 b y t e , b i t 00D9 T i m e r 3 d a t a r e g i s t e r T D R 3 W 11111111 byte T i m e r 3 P W M p e r i o d r e g i s t e r T 3 P P R W 11111111 00DA T i m e r 3 r e g i s t e r T 3 R 00000000 byteT i m e r 3 P W M d u t y r e g i s t e r T 3 P D R R / W 00000000 Timer 3 capture data register CDR3 R 0 0 000000 00DB Timer 3 PWM high register T3PWHR W - - - - 0 0 0 0 byte 0 0 E 0 B u z z e r d r i v e r r e g i s t e r B U Z R W 11111111 b y t e Table 8-1 Control Registers

MC80F0104/0204 Preliminary 26 Mar. 2005 Ver 0.2 0 0 E 1 R A M p a g e s e l e c t i o n r e g i s t e r R P R R / W -----0 0 0 b y t e , b i t 0 0 E 2 S I O m o d e c o n t r o l r e g i s t e r S I O M R / W 00000001 b y t e , b i t 00E3 SIO data shift register SIOR R/W Undefined byte, bit 00E6 UART mode register ASIMR R/W 0 0 0 0 - 0 0 - byte, bit 0 0 E 7 U A R T s t a t u s r e g i s t e r A S I S R R -----0 0 0 b y t e 00E8 UART Baud rate generator control register BRGCR R/W - 0 010000 b y t e , b i t 00E9 U A R T R e c e i v e b u f f e r r e g i s t e r R X B R R 00000000 byte U A R T T r a n s m i t s h i f t r e g i s t e r T X S R W 11111111 0 0 E A I n t e r r u p t e n a b l e r e g i s t e r h i g h I E N H R / W 00000000 b y t e , b i t 0 0 E B I n t e r r u p t e n a b l e r e g i s t e r l o w I E N L R / W 00000000 b y t e , b i t 00EC Interrupt request register high IRQH R/W 0 0 000000 b y t e , b i t 00ED Interrupt request register low IRQL R/W 0 0 000000 b y t e , b i t 0 0 E E I n t e r r u p t e d g e s e l e c t i o n r e g i s t e r I E D S R / W 00000000 b y t e , b i t 0 0 E F A / D c o n v e r t e r m o d e c o n t r o l r e g i s t e r A D C M R / W 00000001 b y t e , b i t 00F0 A/D converter result high register ADCRH R(W) 0 1 0 Undefined byte 00F1 A/D converter result lo w register ADCRL R Undefined byte 00F2 Basic interval timer register BITR R Undefined byte C l o c k c o n t r o l r e g i s t e r C K C T L R W 0-010111 00F4 W a t c h d o g t i m e r r e g i s t e r W D T R W 01111111 byte Watch dog timer data register WDTDR R Undefined 0 0 F 5 S t o p & s l e e p m o d e c o n t r o l r e g i s t e r S S C R W 00000000 b y t e 0 0 F 7 P F D c o n t r o l r e g i s t e r P F D R R / W -----0 0 0 b y t e , b i t 0 0 F 8 P o r t s e l e c t i o n r e g i s t e r 0 P S R 0 W 00000000 b y t e 00F9 Port selection register 1 PSR1 W - - - - 0 0 0 0 byte 0 0 F C P u l l - u p s e l e c t i o n r e g i s t e r 0 P U 0 W 00000000 b y t e 00FD Pull-up selection register 1 PU1 W - - - 0 0 0 0 0 byte 0 0 F F P u l l - u p s e l e c t i o n r e g i s t e r 3 P U 3 W - -00000- b y t e Address Register Name Symbol R/W Initial Value Addressing Mode 76543210 Table 8-1 Control Registers The ‘byte’ means registers are controlled by only byte manipulation instruction. Do not use bit manipulation 1. The ‘byte, bit’ means registers are controlled by both bit and byte manipulation instruction. instruction such as SET1, CLR1 etc. If bit manipulation instruction is used on these registers, content of other seven bits are may varied to unwanted value. *The mark of ‘-’ means this bit location is reserved. Caution) The R/W register except T1PDR and T3PDR are both can be byte and bit manipulated.

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 27 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0C0H R0 R0 Port Data Register 0C1H R0IO R0 Port Direction Register 0C2H R1 R1 Port Data Register 0C3H R1IO R1 Port Direction Register 0C6H R3 R3 Port Data Register 0C7H R3IO R3 Port Direction Register 0C8H R0OD R0 Open Drain Selection Register 0C9H R1OD R1 Open Drain Selection Register 0CBH R3OD R3 Open Drain Selection Register 0D0H TM0 - - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST 0D1H T0/TDR0/ CDR0 Timer0 Register / Timer0 Data Register / Timer0 Capture Data Register 0D2H TM1 POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST 0D3H TDR1/ T1PPR Timer1 Data Register / Timer1 PWM Period Register 0D4H T1/CDR1 Timer1 Register / Timer1 Capture Data Register 0D5H PWM1HR - - - - Timer1 PWM High Register 0D6H TM2 - - CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST 0D7H T2/TDR2/ CDR2 Timer2 Register / Timer2 Data Register / Timer2 Capture Data Register 0D8H TM3 POL 16BIT PWM3E CAP3 T3CK1 T3CK0 T3CN T3ST 0D9H TDR3/ T3PPR Timer3 Data Register / Timer3 PWM Period Register 0DAH T3/CDR3/ T3PDR Timer3 Register / Timer3 Capture Data Register / Timer3 PWM Duty Register 0DBH PWM3HR - - - - Timer3 PWM High Register 0E0H BUZR BUCK1 BUCK0 BUR5 BUR4 BUR3 BUR2 BUR1 BUR0 0E1H RPR - - - - - RPR2 RPR1 RPR0 0E2H SIOM POL IOSW SM1 SM0 SCK1 SCK0 SIOST SIOSF 0E3H SIOR SIO Data Shift Register 0E6H ASIMR TXE RXE PS1 PS0 - SL ISRM - 0E7H ASISR - - - - - PE FE OVE 0E8H BRGCR - TPS2 TPS1 TPS0 MLD3 MLD2 MLD1 MLD0 0E9H RXR UART Receive Buffer Register TXR UART Transmit Shift Register 0EAH IENH INT0E INT1E INT2E INT3E RXE TXE SIOE T0E 0EBH IENL T1E T2E T3E T4E ADCE WDTE WTE BITE Table 8-2 Control Register Function Description

MC80F0104/0204 Preliminary 28 Mar. 2005 Ver 0.2 0ECH IRQH INT0IF INT1IF INT2IF INT3IF RXIF TXIF SIOIF T0IF 0EDH IRQL T1IF T2IF T3IF T4IF ADCIF WDTIF WTIF BITIF 0EEH IEDS IED3H IED3L IED2H IED2L IED1H IED1L IED0H IED0L 0EFH ADCM ADEN ADCK ADS3 ADS2 ADS1 ADS0 ADST ADSF 0F0H ADCRH PSSEL1 PSSEL0 ADC8 - - - ADC Result Reg. High 0F1H ADCRL ADC Result Register Low 0F2H BITR1 Basic Interval Timer Data Register CKCTLR1 ADRST - RCWDT WDTON BTCL BTS2 BTS1 BTS0 0F4H WDTR WDTCL 7-bit Watchdog Timer Register WDTDR Watchdog Timer Data Register (Counter Register) 0F5H SSCR Stop & Sleep Mode Control Register 0F7H PFDR - - - - - PFDEN PFDM PFDS 0F8H PSR0 PWM3O PWM1O EC1E EC0E INT3E INT2E INT1E INT0E 0F9H PSR1 - - - - AVREFS BUZO T2O T0O 0FCH PU0 R0 Pull-up Selection Register 0FDH PU1 R1 Pull-up Selection Register 0FFH PU3 R3 Pull-up Selection Register 1. The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR. Caution) The registers of dark-shaded area can not be accessed by bit manipulation instruction such as "SET1, CLR1", but should be accessed by register operation instruction such as "LDM dp,#imm". Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Table 8-2 Control Register Function Description

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 29

8.4 Addressing Mode

The HMS800 series MCU uses six addressing modes;

• Register addressing
• Immediate addressing
• Direct page addressing
• Absolute addressing
• Indexed addressing
• Register-indirect addressing

8.4.1 Register Addressing

Register addressing accesses the A, X, Y, C and PSW.

8.4.2 Immediate Addressing → #imm

In this mode, second byte (o perand) is accessed as a data immediately. Example:

0435 ADC #35H

When G-flag is 1, then RAM address is defined by 16-bit address which is composed of 8-bit RAM paging register (RPR) and 8-bit immediate data. Example: G=1 E45535 LDM 35H,#55H

8.4.3 Direct Page Addressing→ dp

In this mode, a address is specified within direct page. Example; G=0 C535 LDA 35H ;A ←RAM[35H] 8.4.4 Absolute Addressing → !abs Absolute addressing sets co rresponding memory data to Data, i.e. second byte (Ope rand I) of command becomes lower level address and thir d byte (Operand II) becomes upper level address. With 3 bytes command, it is possible to access to whole memory area. ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR, SBC, STA, STX, STY Example; 0735F0 ADC !0F035H ;A ←ROM[0F035H] The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135 H regard- less of G-flag. A+35H+C → A04 MEMORY E40F100H data ← 55H ~~ ~ data0135H 350F102H 550F101H data 35H 0E551H data → A ➊~~ ~ ~C50E550H 070F100H ~~ ~ data0F035H F00F102H 350F101H A+data+C → A address: 0F035

MC80F0104/0204 Preliminary 30 Mar. 2005 Ver 0.2 983501 INC !0135H ;A ←ROM[135H]

8.4.5 Indexed Addressing

X indexed direct page (no offset) → {X} In this mode, a address is specified by the X register. ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Example; X=15 H, G=1 D4 LDA {X} ;ACC ←RAM[X]. X indexed direct page, auto increment→ {X}+ In this mode, a address is sp ecified within direct page by the X register and the content of X is increased by 1. LDA, STA Example; G=0, X=35 H DB LDA {X}+ X indexed direct page (8 bit offset) → dp+X This address value is the second byte (Operand) of com- mand plus the data of X-register. And it assigns the mem- ory in Direct page. ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY, XMA, ASL, DEC, INC, LSR, ROL, ROR Example; G=0, X=0F5H C645 LDA 45H+X Y indexed direct page (8 bit offset) → dp+Y This address value is the second byte (Operand) of com- mand plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead of X. Y indexed absolute → !abs+Y Sets the value of 16-bit absolute address plus Y-register data as Memory.This addressing mode can specify memo- ry in whole area. Example; Y=55 H 980F100H ~~ ~ data135H 010F102H 350F101H data+1 → data address: 0135 data 115H 0E550H data → A ~~ ~ data DB 35H data → A ~~ ~ 36H → X data 3AH 0E551H data → A➋ ~~ ~ ~C60E550H 45H+0F5H=13AH

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 31 D500FA LDA !0FA00H+Y

8.4.6 Indirect Addressing

Direct page indirect → [dp] Assigns data address to us e for accomplishing command which sets memory data (or pair memory) by Operand. Also index can be used with Index register X,Y. JMP, CALL Example; G=0 3F35 JMP [35H] X indexed indirect → [dp+X] Processes memory data as Data, assigned by 16-bit pair memory which is determined by pair data [dp+X+1][dp+X] Operand plus X-register data in Direct page. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, X=10 H

1625 ADC [25H+X]

Y indexed indirect → [dp]+Y Processes memory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Di- rect page plus Y-register data. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, Y=10 H

1725 ADC [25H]+Y

Absolute indirect → [!abs] The program jumps to address specified by 16-bit absolute address. JMP Example; G=0 D50F100H data → A ~~ ~ data0FA55H 0FA00H+55H=0FA55H FA0F102H 000F101H 0A35H jump to ~~ ~ 0FA00H E336H 0E30AH NEXT ~~ ~ address 0E30AH 0535H 0E005H~~ ~ 0FA00H E036H 0E005H data ~~ ~ ➌ A + data + C → A 25 + X(10) = 35H➊ 0525H 0E005H + Y(10) ~~ ~ 0FA00H E026H 0E015H data ~~ ~ = 0E015H A + data + C → A

MC80F0104/0204 Preliminary 32 Mar. 2005 Ver 0.2 1F25E0 JMP [!0C025H] 250E025H jump to ~~ ~ 0FA00H E70E026H 0E725H NEXT ~~ ~ ~1F PROGRAM MEMORY address 0E30AH

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 33 9. I/O PORTS The MC80F0104/0204 has three ports (R0, R1 and R3). These ports pins may be multiplexed with an alternate function for the peripheral features on the device. All port can drive maximum 20mA of high current in output low state, so it can directly drive LED device. All pins have data direction registers which can define these ports as output or input. A “1” in the port direction register configure the corresponding port pin as output. Conversely, write “0” to the corresponding bit to specify it as input pin. For example, to use the even numbered bit of R0 as output ports and the odd numbered bits as input ports, write “55 H” to address 0C1H (R0 port direction reg- ister) during initial setting as shown in Figure 9-1 . All the port direction registers in the MC80F0104/0204 have 0 written to them by reset function. On the other hand, its initial status is input. Figure 9-1 Example of port I/O assignment

9.1 R0 and R0IO register

R0 is an 8-bit CMOS bidi rectional I/O port (address 0C0H). Each I/O pin can independently used as an input or an output through the R0IO register (address 0C1H). When R00 through R07 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up selection register 0 (PU0). Each I/O pin of R0 port can be used to open drain output port by setting the corresponding bit of the open drain selection register 0 (R0OD). I: INPUT PORT WRITE “55H” TO PORT R0 DIRECTION REGISTER 0 1 0 1 0 1 0 1 I O I O I O I O R0 data R1 data R0 direction R1 direction 0C0H 0C1H 0C2H 0C3H 76543210 BIT 76543210 PORT O: OUTPUT PORT R0 Data Register ADDRESS: 0C0H RESET VALUE: 00H R07 R06 R05 R04 R03 R02 R01 R00 Port Direction R0 Direction Register R0IO ADDRESS: 0C1H RESET VALUE: 00H 0: Input 1: Output Input / Output data R0 Pull-up PU0 ADDRESS: 0FCH RESET VALUE: 00HSelection Register 0: Disable 1: Enable Pull-up Resister Selection R0 Open Drain R0OD ADDRESS: 0C8H RESET VALUE: 00HSelection Register 0: Disable 1: Enable Open Drain Resister Selection PSR0 ADDRESS: 0F8H RESET VALUE: 0000 0000B INT2E Port / INT Selection 0: R11, R12, R03, R00 1: INT0, INT1,INT2, INT3 INT0EINT1EINT3EPWM3OE EC0EEC1E Port / EC Selection 0: R04, R07 1: EC0, EC1 Port / PWM Selection 0: R10, R11 1: PWM1O, PWM3O PWM1OE PSR1 ADDRESS: 0F9H RESET VALUE: ---- 0000B BUZOE R12/BUZO Selection 0: R12 port (Turn off buzzer) 1: BUZO port (Turn on buzzer) T0OET2OEAVREFS - - - - Port / TO Selection 0: R04, R07 1: EC0, EC1R10 / AVREF Selection 0: R10 port 1: AVREF port

MC80F0104/0204 Preliminary 34 Mar. 2005 Ver 0.2 Figure 9-2 R0 Port Register In addition, Port R0 is multiplexed with various alternate functions. The port selection register PSR0 (address 0F8H) and PSR1 (address 0F9H) control the selection of alternate functions such as external in terrupt 3 (INT3), external in- terrupt 2 (INT2), event counter input 0 (EC0), timer 0 out- put (T0O), timer 2 output (T2O) and event counter input 1 (EC1). When the alternate fu nction is selected by writing “1” in the corresponding bit of PSR0 or PSR1, port pin can be used as a corresponding alternate features regardless of the direction register R0IO. The ADC input channel 1~7 (AN1~AN7), SIO data input (SI), SIO data output (SOUT) and UART data input (RXD), UART data output (TXD) and UART clock input (ACLK) can be selected by setting ADCM(00EF H), SI- OM(00E2 H) and ASIMR(00E6 H) register to enable the corresponding peripheral oper ation and select operation mode.

9.2 R1 and R1IO register

R1 is a 5-bit CMOS bidirectional I/O port (address 0C2H). Each I/O pin can independently used as an input or an out- put through the R1IO register (address 0C3 H). When R10 through R14 pins are used as input ports, an on-chip pull- up resistor can be connected to them in 1-bit units with a pull-up selection register 1 (PU1). Each I/O pin of R0 port can be used to open drain output port by setting the corre- sponding bit of the open drain selection register 1 (R1OD). In addition, Port R1 is multiplexed with various alternate functions. The port selection register PSR0 (address 0F8 and PSR1 (address 0F9H) control the selection of alternate functions such as Analog reference voltage input (AVREF), external interrupt 0 (INT0), external interrupt 1 (INT1), PWM 1 output (PWM1O), PWM 3 output (PWM3O) and buzzer output (BUZO). When th e alternate function is se- lected by writing “1” in the corresponding bit of PSR0 or PSR1, port pin can be used as a corresponding alternate features regardless of the direction register R1IO. The ADC input channel 0 (AN0) can be selected by setting ADCM(00EF H) register to enable ADC and select channel 0 . Port Pin Alternate Function R00 R01 R02 R03 R04 R05 R06 R07 INT3 (External interrupt 3) SCK (SIO clock input/output) AN1(ADC Input channel 1) SI (SIO data input) AN2 (ADC Input channel 2) SOUT (SIO data output) AN3 (ADC Input channel 3) INT2 (External interrupt 2) AN4 (ADC Input channel 4) EC0 (Event counter input 0) RXD (UART data input) AN5 (ADC Input channel 5) T0O (Timer output 0) TXD (UART data output) AN6 (ADC Input channel 6) T2O (Timer output 2) ACLK (UART clock input) AN7 (ADC Input channel 7) EC1 (Event counter input 1) Port Pin Alternate Function R10 R11 R12 AN0 (ADC input channel 0) AVREF (Analog reference voltage) PWM1O (PWM 1 output) INT0 (External Interrupt 0) PWM3O (PWM 3 output) INT1 (External Interrupt 1) BUZO (Buzzer output)

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 35 Figure 9-3 R1 Port Register R1 Data Register ADDRESS: 0C2H RESET VALUE: ---0 0000B - - - R14 R13 R12 R11 R10 Port Direction R1 Direction Register R1IO ADDRESS: 0C3H RESET VALUE: ---0 0000B 0: Input 1: Output Input / Output data R1 Pull-up PU1 ADDRESS: 0FDH RESET VALUE: ---0 0000BSelection Register 0: Disable 1: Enable Pull-up Resister Selection - - - - - - R1 Open Drain R1OD ADDRESS: 0C9H RESET VALUE: ---0 0000BSelection Register 0: Disable 1: Enable Open Drain Resister Selection PSR0 ADDRESS: 0F8H RESET VALUE: 0000 0000B INT2E Port / INT Selection 0: R11, R12, R03, R00 1: INT0, INT1,INT2, INT3 INT0EINT1EINT3EPWM3OE EC0EEC1E Port / EC Selection 0: R04, R07 1: EC0, EC1 Port / PWM Selection 0: R10, R11 1: PWM1O, PWM3O PWM1OE PSR1 ADDRESS: 0F9H RESET VALUE: ---- 0000B BUZOE R12/BUZO Selection 0: R12 port (Turn off buzzer) 1: BUZO port (Turn on buzzer) T0OET2OEAVREFS - - - - Port / TO Selection 0: R04, R07 1: EC0, EC1R10 / AVREF Selection 0: R10 port 1: AVREF port - - -

MC80F0104/0204 Preliminary 36 Mar. 2005 Ver 0.2

9.3 R3 and R3IO register

R3 is a 5-bit CMOS bidirectional I/O port (address 0C6H). Each I/O pin (except R35) can independently used as an in- put or an output through the R3IO register (address 0C7H). R35 is an input only port. When R31 through R35 pins are used as input ports, an on-chip pull-up resistor can be con- nected to them in 1-bit units with a pull-up selection regis- ter 3 (PU3). R31 through R34 pins can be used to open drain output port by setting the corresponding bit of the open drain selection register 3 (R3OD). In addition, Port R3 is multiplexed with alternate func- tions. R31 and R32 can be used as ADC input channel 14 and 15 by setting ADCM to enable ADC and select chan- nel 14 and 15. R33, R34 and R35 is multiplexed with X IN, XOUT, and RESET pin. These pins can be used as general I/O pins by setting writing option described in "23. Device Configura- tion Area" on page 102. Port Pin Alternate Function R31 R32 AN14 (ADC input channel 14) AN15 (ADC input channel 15) R3 Data Register ADDRESS: 0C6H RESET VALUE: --00 000-B - -R 3 5 R 3 4 R 3 3 R32 R31 - Port Direction R3 Direction Register R3IO ADDRESS: 0C7H RESET VALUE: ---0 000-B 0: Input 1: Output Input / Output data - - - Input data R3 Pull-up PU3 ADDRESS: 0FFH RESET VALUE: --00 000-BSelection Register 0: Disable 1: Enable Pull-up Resister Selection - - R3 Open Drain R3OD ADDRESS: 0CBH RESET VALUE: ---0 000-BSelection Register 0: Disable 1: Enable Open Drain Resister Selection

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 37 10. CLOCK GENERATOR As shown in Figure 10-1 , the clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and the peripheral hardware. It con- tains main-frequency clock oscillator. The system clock operation can be easily obtained by attaching a crystal or a ceramic resonator between the X IN and XOUT pin, respec- tively. The system clock can also be obtained from the ex- ternal oscillator. In this case, it is necessary to input a external clock signal to the X IN pin and open the XOUT pin. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuit- ry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. To the peripheral block, the clock among the not-divided original clock, clocks divided by 1, 2, 4,..., up to 4096 can be provided. Peripheral clock is enabled or disabled by STOP instruction. The peripheral clock is controlled by clock control register (CKC TLR). See "11. BASIC IN- TERVAL TIMER" on page 39 for details.Figure 10-1 Block Diagram of Clock Generator

10.1 Oscillation Circuit

XIN and XOUT are the input and output, respectively, a in- verting amplifier which can be set for use as an on-chip os- cillator, as shown in Figure 10-2 . Figure 10-2 Oscillator Connections Note: When using a system clock oscillator, carry out wiring in the broken line area in Figure 10-2 to prevent any effects from wir- ing capacities. - Minimize the wiring length. - Do not allow wiring to intersect with other signal conductors. - Do not allow wiring to come near changing high current. - Set the potential of the grounding position of the oscillator capac- itor to that of V SS. Do not ground to any ground pattern where high current is present. - Do not fetch signals from the oscillator. Internal PRESCALER Peripheral clock PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 fEX (Hz) PS0 PS3 PS2 PS4PS1 PS10PS9PS5 PS6 PS7 Frequency period 4M 1M 500K 250K2M 125K 62.5K 250n 500n 1u 2u 4u 8u 16u 32u 64u 256u 128u 3.906K7.183K15.63K31.25K PS8 ÷2048 ÷4096 PS12PS11 1.953K 976 512u 1.024m Main OSC SLEEP fEX system clock PS12PS11 XIN Clock Pulse Generator (÷2) Stop OSC Circuit XOUT STOP INOSC ONP Circuit MUX INOSC fXIN INCLKInt OSC Circuit INOSC INOSC (IN4MCLK/IN2MCLK/ 7 ~ 3 2 ~ 0 Configuration Option Register (20FFH) IN4MCLKXO/IN2MCLKXO) Xout Xin Vss

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 39 11. BASIC INTERVAL TIMER The MC80F0104/0204 has one 8-bit Basic Interval Timer that is free-run and can not stop. Block diagram is shown in Figure 11-1 . In addition, the Basic Interval Timer gen- erates the time base for wa tchdog timer counting. It also provides a Basic interval timer interrupt (BITIF). The 8-bit Basic interval timer register (BITR) is increased every internal count pulse wh ich is divided by prescaler. Since prescaler has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 of the oscillator frequency. As the count overflow from FFH to 00H, this overflow causes the interrupt to be generated. The Basic Interval Timer is controlled by the clock control register (CKCTLR) shown in Figure 11-2. If the RCWDT bit is set to “1”, the clock source of the BITR is changed to the internal RC oscillation. When write "1" to bit BTCL of CKCTLR, BITR register is cleared to "0" and restart to count-up. The bit BTCL be- comes "0" after one machine cycle by hardware. If the STOP instruction execut ed after writing "1" to bit RCWDT of CKCTLR, it goes into the internal RC oscillat- ed watchdog timer mode. In this mode, all of the block is halted except the internal RC oscillator, Basic Interval Timer and Watchdog Timer. More detail informations are explained in Power Saving Function. The bit WDTON de- cides Watchdog Timer or the normal 7-bit timer. Source clock can be selected by lower 3 bits of CKCTLR. BITR and CKCTLR are located at same address, and ad- dress 0F2 H is read as a BITR, and written to CKCTLR. Note: All control bits of Basic interval timer are in CKCTLR reg- ister which is located at same address of BITR (address ECH). Ad- dress EC H is read as BITR, written to CKCTLR. Therefore, the CKCTLR can not be accessed by bit manipulation instruction. Figure 11-1 Block Diagram of Basic Interval Timer MUX Basic Interval BITR Select Input clock 3 Basic Interval Timer source clock 8-bit up-counter BCK[2:0] BTCL ÷1024 ÷512 ÷256 ÷128 ÷64 ÷32 ÷16 To Watchdog timer (WDTCK) CKCTLR clear overflow Internal bus line clock control register [0F2H] [0F2H] BITIF Read XIN PIN Prescaler Timer Interrupt Internal RC OSC RCWDT RCWDT

MC80F0104/0204 Preliminary 40 Mar. 2005 Ver 0.2 Table 11-1 Basic Interval Timer Interrupt Period Figure 11-2 BITR: Basic Interval Timer Mode Register Example 1: Interrupt request flag is generated every 8.192ms at 4MHz. LDM CKCTLR,#1BH SET1 BITE EI Example 2: Interrupt request flag is generated every 8.192ms at 8MHz. LDM CKCTLR,#1CH SET1 BITE EI CKCTLR [2:0] Source clock Interrupt (overflow) Period (ms) @ f XIN = 8MHz 000 001 010 011 100 101 110 111 f XIN÷8 fXIN÷16 fXIN÷32 fXIN÷64 fXIN÷128 fXIN÷256 fXIN÷512 fXIN÷1024 0.256 0.512 1.024 2.048 4.096 8.192 16.384 32.768 BTCL 76543210 RCWDT-ADRST BTS1 Basic Interval Timer source clock select 000: fXIN ÷ 8 001: fXIN ÷ 16 010: fXIN ÷ 32 011: fXIN ÷ 64 100: fXIN ÷ 128 101: fXIN ÷ 256 110: fXIN ÷ 512 111: fXIN ÷ 1024 Clear bit 0: Normal operation (free-run) 1: Clear 8-bit counter (BITR) to “0”. This bit becomes 0 automatically INITIAL VALUE: 0-01 0111B ADDRESS: 0F2H after one machine cycle, and starts counting. CKCTLR INITIAL VALUE: Undefined ADDRESS: 0F2HBITR Both register are in same address, when write, to be a CKCTLR, when read, to be a BITR. Caution: 8-BIT FREE-RUN BINARY COUNTER WDTON BTS0BTS2 BTCL BTCL 76543210 Watchdog timer Enable bit 0: Operate as 7-bit Timer See the section “Watchdog Timer”. Address Trap Reset Selection 0: Enable Address Fail Reset 1: Disable Address Fail Reset 1: Enable Watchdog Timer operation 0: Disable Internal RC Watchdog Timer 1: Enable Internal RC Watchdog Timer RC Watchdog Selection bit

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 41 12. WATCHDOG TIMER The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and re- sumes the CPU to the normal state. The watchdog timer signal for detecting malfunction can be selected either a re- set CPU or a interrupt request. When the watchdog timer is not being used for malfunc- tion detection, it can be used as a timer to generate an in- terrupt at fixed intervals. The watchdog timer has two types of clock source. The first type is an on-chip RC oscillator which does not re- quire any external components. This RC oscillator is sepa- rate from the external oscillator of the X IN pin. It means that the watchdog timer will run, even if the clock on the XIN pin of the device has been stopped, for example, by en- tering the STOP mode. The other type is a prescaled sys- tem clock. The watchdog timer consists of 7-bit binary counter and the watchdog timer data regist er. When the value of 7-bit binary counter is equal to the lower 7 bits of WDTR, the interrupt request flag is generated. This can be used as Watchdog timer interrupt or reset the CPU in accordance with the bit WDTON. Note: Because the watchdog timer counter is enabled after clear- ing Basic Interval Timer, after the bit WDTON set to "1", maximum error of timer is depend on prescale r ratio of Basic Interval Timer. The 7-bit binary counter is cleared by setting WDTCL(bit7 of WDTR) and the WDTCL is cleared aut omatically after 1 machine cycle. The RC oscillated watchdog timer is activated by setting the bit RCWDT as shown below. LDM CKCTLR,#3FH; enable the RC-OSC WDT LDM WDTR,#0FFH ; set the WDT period LDM SSCR, #5AH ;ready for STOP mode STOP ; enter the STOP mode NOP NOP ; RC-OSC WDT running The RC-WDT oscillation period is vary with temperature, VDD and process variations from part to part (approxi- mately, 33~100uS). The following equation shows the RCWDT oscillated watchdog timer time-out. TRCWDT=CLKRCWDT×28×WDTR + (CLKRCWDT×28)/2 where, CLKRCWDT = 33~100uS In addition, this watchdog timer can be used as a simple 7- bit timer by interrupt WDTIF. The interval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is as below. T WDT = (WDTR+1) × Interval of BIT Figure 12-1 Block Diagram of Watchdog Timer to reset CPU BASIC INTERVAL TIMER Count enable Watchdog 7-bit compare data comparator Watchdog Timer interrupt clear clear WDTIF Counter (7-bit) WDTCL “0” “1” WDTON in CKCTLR [0F2H] OVERFLOW Watchdog Timer Register WDTR Internal bus line [0F4H] source

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 43 Figure 12-3 Watchdog timer Timing If the watchdog timer output becomes active, a reset is gen- erated, which drives the RESET pin low to reset the inter- nal hardware. The main clock oscillator al so turns on when a watchdog timer reset is generated in sub clock mode. n Source clock Binary-counter WDTR WDTIF interrupt WDTR ← “1000_0011B” Match Detect Counter Clear 1 2 30 BIT overflow WDT reset reset Counter Clear

MC80F0104/0204 Preliminary 44 Mar. 2005 Ver 0.2 13. TIMER/EVENT COUNTER TheMC80F0104/0204 has Four Timer/Counter registers. Each module can generate an interrupt to indicate that an event has occurred (i.e. timer match). Timer 0 and Timer 1 are can be used either two 8-bit Tim- er/Counter or one 16-bit Timer/Counter with combine them. Also Timer 2 and Timer 3 are same. Timer 4 is 16- bit Timer/Counter. In the “timer” function, the register is increased every in- ternal clock input. Thus, one can think of it as counting in- ternal clock input. Since a least clock consists of 2 and most clock consists of 2048 oscillator periods, the count rate is 1/2 to 1/2048 of the oscillator frequency. In the “counter” function, the re gister is increased in re- sponse to a 0-to-1 (rising edge) transition at its correspond- ing external input pin, EC0 or EC1. In addition the “capture” function, the register is increased in response external or inte rnal clock sources same with timer or counter function. When external clock edge input, the count register is captured into Timer data register cor- respondingly. When external clock edge input, the count register is captured into capture data register CDRx. Timer 0 and Timer 1 is shared with "PWM" function and "Compare output" function. It has six operating modes: "8- bit timer/counter", "16-bit timer/counter", "8-bit capture", "16-bit capture", "8-bit co mpare output", and "10-bit PWM" which are selected by bit in Timer mode register TM0 and TM1 as shown in Table 13-1, Figure 13-1 . Timer 2 and Timer 3 is shared with "PWM" function and "Compare output" function. It has six operating modes: "8- bit timer/counter", "16-bit timer/counter", "8-bit capture", "16-bit capture", "8-bit co mpare output", and "10-bit PWM" which are selected by bit in Timer mode register TM2 and TM3 as shown in Table 13-2, Figure 13-2 . Table 13-1 Operation Modes of Timer 0, 1 16BIT CAP0 CAP1 PWM1E T0CK [2:0] T1CK [1:0] PWM1O TIMER 0 TIMER 1 0 0 0 0 XXX XX 0 8-bit Timer 8-bit Timer 0 0 1 0 111 XX 0 8-bit Event counter 8-bit Capture 0 1 0 0 XXX XX 1 8-bit Capture (internal clock) 8-bit Compare Output

0 X 0 1 XXX XX 1 8-bit Timer/Counter 10-bit PWM

1 0 0 0 XXX 11 0 16-bit Timer 1 0 0 0 111 11 0 16-bit Event counter 1 1 1 0 XXX 11 0 16-bit Capture (internal clock) 1. X means the value of “0” or “1” corresponds to user operation. 16BIT CAP2 CAP3 PWM3E T2CK [2:0] T3CK [1:0] PWM3O TIMER 2 TIMER 3 0 0 0 0 XXX XX 0 8-bit Timer 8-bit Timer 0 0 1 0 111 XX 0 8-bit Event counter 8-bit Capture 0 1 0 0 XXX XX 1 8-bit Capture (internal clock) 8-bit Compare Output 1 0 0 0 XXX 11 0 16-bit Timer 1 0 0 0 111 11 0 16-bit Event counter 1 1 1 0 XXX 11 0 16-bit Capture (internal clock) Table 13-2 Operating Modes of Timer 2, 3

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 45 Figure 13-1 TM0, TM1 Registers BTCL 76543210 16BITPOL T1CN INITIAL VALUE: 00H ADDRESS: 0D2H TM1 T1STT1CK0T1CK1PWM1E CAP1 Bit Name Bit Position Description POL TM1.7 0: PWM Duty Active Low 1: PWM Duty Active High 16BIT TM1.6 0: 8-bit Mode 1: 16-bit Mode PWM1E TM1.5 0: Disable PWM 1: Enable PWM CAP1 TM1.4 0: Timer/Counter mode 1: Capture mode selection flag T1CK1 T1CK0 TM1.3 TM1.2 00: 8-bit Timer, Clock source is fXIN 01: 8-bit Timer, Clock source is fXIN ÷ 4 10: 8-bit Timer, Clock source is fXIN ÷ 16 11: 8-bit Timer, Clock source is Using the Timer 2 Clock T1CN TM1.1 0: Timer count pause 1: Timer count start T1ST TM1.0 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again. BTCL 543210 -- T 0 C N INITIAL VALUE: --00 0000B ADDRESS: 0D0H TM0 T0STT0CK0T0CK1CAP0 T0CK2 Bit Name Bit Position Description CAP0 TM0.5 0: Timer/Counter mode 1: Capture mode selection flag T0CK2 T0CK1 T0CK0 TM0.4 TM0.3 TM0.2 000: 8-bit Timer, Clock source is f XIN ÷ 2 001: 8-bit Timer, Clock source is fXIN ÷ 4 010: 8-bit Timer, Clock source is fXIN ÷ 8 011: 8-bit Timer, Clock source is fXIN ÷ 32 100: 8-bit Timer, Clock source is fXIN ÷ 128 101: 8-bit Timer, Clock source is fXIN ÷ 512 110: 8-bit Timer, Clock source is fXIN ÷ 2048 111: EC0 (External clock) T0CN TM0.1 0: Timer count pause 1: Timer count start T0ST TM0.0 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again. 76543210 INITIAL VALUE: 0FFH ADDRESS: 0D1H TDR0 Read: Count value read Write: Compare data write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 76543210 INITIAL VALUE: 0FFH ADDRESS: 0D3H TDR1 R/W R/W R/W R/W R/W R/W R/W R/W

MC80F0104/0204 Preliminary 46 Mar. 2005 Ver 0.2 Figure 13-2 TM2, TM3 Registers BTCL 76543210 16BITPOL T3CN INITIAL VALUE: 00H ADDRESS: 0D8H TM3 T3STT3CK0T3CK1PWM3E CAP3 Bit Name Bit Position Description POL TM3.7 0: PWM Duty Active Low 1: PWM Duty Active High 16BIT TM3.6 0: 8-bit Mode 1: 16-bit Mode PWM3E TM3.5 0: Disable PWM 1: Enable PWM CAP3 TM3.4 0: Timer/Counter mode 1: Capture mode selection flag T3CK1 T3CK0 TM3.3 TM3.2 00: 8-bit Timer, Clock source is fXIN 01: 8-bit Timer, Clock source is fXIN ÷ 4 10: 8-bit Timer, Clock source is fXIN ÷ 16 11: 8-bit Timer, Clock source is Using the Timer 2 Clock T3CN TM3.1 0: Timer count pause 1: Timer count start T3ST TM3.0 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again. BTCL 543210 -- T 2 C N INITIAL VALUE: --00 0000B ADDRESS: 0D6H TM2 T2STT2CK0T2CK1CAP2 T2CK2 Bit Name Bit Position Description CAP2 TM2.5 0: Timer/Counter mode 1: Capture mode selection flag T2CK2 T2CK1 T2CK0 TM2.4 TM2.3 TM2.2 000: 8-bit Timer, Clock source is f XIN ÷ 2 001: 8-bit Timer, Clock source is fXIN ÷ 4 010: 8-bit Timer, Clock source is fXIN ÷ 8 011: 8-bit Timer, Clock source is fXIN ÷ 16 100: 8-bit Timer, Clock source is fXIN ÷ 64 101: 8-bit Timer, Clock source is fXIN ÷ 256 110: 8-bit Timer, Clock source is fXIN ÷ 1024 111: EC1 (External clock) T2CN TM2.1 0: Timer count pause 1: Timer count start T2ST TM2.0 0: When cleared, stop the counting. 1: When set, Timer 0 Count Register is cleared and start again. 76543210 INITIAL VALUE: 0FFH ADDRESS: 0D7H TDR2 Read: Count value read Write: Compare data write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 76543210 INITIAL VALUE: 0FFH ADDRESS: 0D9H TDR3 R/W R/W R/W R/W R/W R/W R/W R/W

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 47 13.1 8-bit Timer / Counter Mode The MC80F0104/0204 has four 8-bit Timer/Counters, Timer 0, Timer 1, Timer 2, Timer 3. The Timer 0, Timer 1 are shown in Figure 13-3 and Timer 2, Timer 3 are shown in Figure 13-4 . The “timer” or “counter” functi on is selected by control registers TM0, TM1, TM2, TM3 as shown in Figure 13-1 . To use as an 8-bit timer/counter mode, bit CAP0, CAP1, CAP2, or CAP3 of TMx shou ld be cleared to “0” and 16BIT and PWM1E or PWM3E of TM1 or TM3 should be cleared to "0" (Figure 13-3 ). These timers have each 8-bit count register and data regist er. The count register is in- creased by every internal or external clock input. The inter- nal clock has a prescaler divide ratio option of 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048 or external clock (select- ed by control bits TxCK0, TxCK1, TxCK2 of register TMx). Figure 13-3 8-bit Timer/Counter 0, 1 EC0 PIN ÷ 2 ÷ 4 ÷ 8 XIN PIN MUX Prescaler clear 0: Stop 1: Clear and start T0ST T0CK[2:0] 111 000 001 010 T0CN MUX T1IF clear 0: Stop 1: Clear and start T1ST T1CK[1:0] TIMER 1 INTERRUPT ÷ 1 ÷ 2 ÷ 8 TDR0 (8-bit) TDR1 (8-bit) T1 (8-bit) T0 (8-bit) Comparator Comparator TIMER 0 TIMER 1 BTCL 76543210 --T 0 C N INITIAL VALUE: --00 0000B ADDRESS: 0D0H TM0 T0STT0CK0T0CK1CAP0 T0CK2 -- X X XX X means don’t care ÷ 32 ÷ 128 ÷ 512 ÷ 2048 011 100 101 110 T0IF TIMER 0 INTERRUPT T1CN INITIAL VALUE: 00H ADDRESS: 0D2H TM1 X means don’t care BTCL 76543210 16BITPOL T1CN T1ST T1CK0T1CK1PWM1E CAP1 X0 XX XX00 EDGE DETECTOR F/F R05 / T0O

MC80F0104/0204 Preliminary 48 Mar. 2005 Ver 0.2 Figure 13-4 8-bit Timer/Counter 2, 3 EC1 PIN ÷ 2 ÷ 4 ÷ 8 XIN PIN MUX Prescaler clear 0: Stop 1: Clear and start T2ST T2CK[2:0] 111 000 001 010 T2CN MUX T3IF clear 0: Stop 1: Clear and start T3ST T3CK[1:0] TIMER 3 INTERRUPT ÷ 1 ÷ 4 ÷ 16 TDR2 (8-bit) TDR3 (8-bit) T3 (8-bit) T2 (8-bit) Comparator Comparator TIMER 2 TIMER 3 BTCL 76543210 --T 2 C N INITIAL VALUE: --000000B ADDRESS: 0D6H TM2 T2STT2CK0T2CK1CAP2 T2CK2 -- X X XX X means don’t care ÷ 16 ÷ 64 ÷ 256 ÷ 1024 011 100 101 110 T2IF TIMER 2 INTERRUPT T3CN INITIAL VALUE: 00H ADDRESS: 0D8H TM3 X means don’t care BTCL 76543210 16BITPOL T3CN T3ST T3CK0T3CK1PWM3E CAP3 X0 XX XX00 EDGE DETECTOR F/F R06 / T2O

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 49 Example 1: Timer0 = 2ms 8-bit timer mode at 4MHz Timer1 = 0.5ms 8-bit timer mode at 4MHz Timer2 = 1ms 8-bit timer mode at 4MHz Timer3 = 1ms 8-bit timer mode at 4MHz LDM TDR0,#249 LDM TDR1,#249 LDM TDR2,#249 LDM TDR3,#249 LDM TM0,#0000_1111B LDM TM1,#0000_1011B LDM TM2,#0000_1111B LDM TM3,#0000_1011B SET1 T0E SET1 T1E SET1 T2E SET1 T3E EI Example 2: Timer0 = 8-bit event counter mode Timer1 = 0.5ms 8-bit timer mode at 4MHz Timer2 = 8-bit event counter mode Timer3 = 1ms 8-bit timer mode at 4MHz LDM TDR0,#249 LDM TDR1,#249 LDM TDR2,#249 LDM TDR3,#249 LDM TM0,#0001_1111B LDM TM1,#0000_1011B LDM TM2,#0001_1111B LDM TM3,#0000_1011B SET1 T0E SET1 T1E SET1 T2E SET1 T3E EI These timers have each 8-bit count register and data regis- ter. The count register is increased by every internal or ex- ternal clock input. The internal clock has a prescaler divide ratio option of 2, 4, 8, 32, 128, 512, 2048 selected by con- trol bits T0CK[2:0] of register TM0 or 1, 2, 8 selected by control bits T1CK[1:0] of register TM1, or 2, 4, 8, 16, 64, 256, 1024 selected by control bits T2CK[2:0] of register TM2, or 1, 4, 16 selected by control bits T3CK[1:0] of reg- ister TM3. In the Timer 0, timer register T0 increases from H until it matches TDR0 and then reset to 00 H. The match output of Timer 0 generates Timer 0 interrupt (latched in T0IF bit). In counter function, the coun ter is increased every 0-to-1 (rising edge) transition of EC0 pin. In order to use counter function, the bit EC0 of the Port Selection Register (PSR0.4) is set to "1". The Timer 0 can be used as a counter by pin EC0 input, but Timer 1 can not. Likewise, In order to use Timer2 as counter function, the bit EC1 of the Port Selection Register (PSR0.5) is set to "1". The Timer 2 can be used as a counter by pin EC1 input, but Timer 3 can not. 13.1.1 8-bit Timer Mode In the timer mode, the internal clock is used for counting up. Thus, you can think of it as counting internal clock in- put. The contents of TDRn are compared with the contents of up-counter, T n. If match is found, a timer n interrupt (TnIF) is generated and the up-counter is cleared to 0. Counting up is resumed after the up-counter is cleared. As the value of TDRn is changeable by software, time in- terval is set as you want. Figure 13-5 Timer Mode Timing Chart 0 n-2 20n 3n-1 n Source clock Up-counter TDR1 T1IF interrupt Start count 1 23 1 4 Match Detect Counter Clear ~~ ~

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 51 Figure 13-8 Count Operation of Timer / Event counter Timer 1 (T1IF) Interrupt TDR1 TIME Occur interrupt Occur interrupt stop clear & start disable enable Start & Stop T1ST T1CN Control count up-count T1ST = 0 T1ST = 1 T1CN = 0 T1CN = 1

MC80F0104/0204 Preliminary 52 Mar. 2005 Ver 0.2 13.2 16-bit Timer / Counter Mode The Timer register is being run with all 16 bits. A 16-bit timer/counter register T0, T1 are incremented from 0000H until it matches TDR0, TDR1 and then resets to 0000 H. The match output generates Timer 0 interrupt. The clock source of the Timer 0 is selected either internal or external clock by bit T0CK[2:0]. In 16-bit mode, the bits T1CK[1:0] and 16BIT of TM1 should be set to "1" respec- tively as shown in Figure 13-9 . Likewise, A 16-bit timer/counter register T2, T3 are incre- mented from 0000 H until it matches TDR2, TDR3 and then resets to 0000H. The match output generates Timer 2 inter- rupt. The clock source of the Timer 2 is selected either internal or external clock by bit T2CK[2:0]. In 16-bit mode, the bits T3CK[1:0] and 16BIT of TM3 should be set to "1" respec- tively as shown in Figure 13-10 . Even if the Timer 0 (including Timer 1) is used as a 16-bit timer, the Timer 2 and Timer 3 can still be used as either two 8-bit timer or one 16-bit timer by setting the TM3. Re- versely, even if the Timer 2 (including Timer 3) is used as a 16-bit timer, the Timer 0 and Timer 1 can still be used as 8-bit timer independently. Figure 13-9 16-bit Timer/Counter for Timer 0, 1 clear 0: Stop 1: Clear and start T0ST T0CN TDR1 + TDR0 Comparator TIMER 0 + TIMER 1 → TIMER 0 (16-bit) Higher byte Lower byte (16-bit) COMPARE DATA T1 + T0 (16-bit) (Not Timer 1 interrupt) EDGE BTCL 76543210 --T 0 C N INITIAL VALUE: --00 0000B ADDRESS: 0D0H TM0 T0STT0CK0T0CK1CAP0 T0CK2 -- X X XX X means don’t care INITIAL VALUE: 00H ADDRESS: 0D2H TM1 X means don’t care BTCL 76543210 16BITPOL T1CN T1ST T1CK0T1CK1PWM1E CAP1 X1 XX 1100 EC0 PIN ÷ 2 ÷ 4 ÷ 8 XIN PIN MUX Prescaler T0CK[2:0] 111 000 001 010 ÷ 32 ÷ 128 ÷ 512 ÷ 2048 011 100 101 110 DETECTOR T0IF TIMER 0 INTERRUPT

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 53 Figure 13-10 16-bit Timer/Counter for Timer 2, 3 13.3 8-bit Compare Output (16-bit) TheMC80F0104/0204 has Timer Compare Output func- tion. To pulse out, the timer match can goes to port pin( T0O or T2O) as shown in Figure 13-3 or Figure 13-4 . Thus, pulse out is generated by the timer match. These op- eration is implemented to pin, R05/AN5//T0O/TXD or R06/AN6/T2O/ACK. In this mode, the bit T0OE or T2OE bit of Port Selection register1 (PSR1.0 or PSR1.1) should be set to "1". This pin output the signal having a 50 : 50 duty square wave, and output frequency is same as below equation. 13.4 8-bit Capture Mode The Timer 0 capture mode is set by bit CAP0 of timer mode register TM0 (bit CAP1 of timer mode register TM1 for Timer 1) as shown in Figure 13-11 . Likewise, the Tim- er 2 capture mode is set by bit CAP2 of timer mode register TM2 (bit CAP3 of timer mode register TM3 for Timer 3) as shown in Figure 13-12 . clear 0: Stop 1: Clear and start T2ST T2CN TDR3 + TDR2 Comparator TIMER 2 + TIMER 3 → TIMER 2 (16-bit) Higher byte Lower byte (16-bit) COMPARE DATA T3 + T2 (16-bit) (Not Timer 3 interrupt) EDGE BTCL 76543210 --T 2 C N INITIAL VALUE: --000000B ADDRESS: 0D6H TM2 T2STT2CK0T2CK1CAP2 T2CK2 -- X X XX X means don’t care INITIAL VALUE: 00H ADDRESS: 0D8H TM3 X means don’t care BTCL 76543210 16BITPOL T3CN T3ST T3CK0T3CK1PWM3E CAP3 X1 XX 1100 EC1 PIN ÷ 2 ÷ 4 ÷ 8 XIN PIN MUX Prescaler T2CK[2:0] 111 000 001 010 ÷ 16 ÷ 64 ÷ 256 ÷ 1024 011 100 101 110 DETECTOR T2IF TIMER 2 INTERRUPT fCOMP Oscillation Frequency

MC80F0104/0204 Preliminary 54 Mar. 2005 Ver 0.2 The Timer/Counter register is increased in response inter- nal or external input. This counting function is same with normal timer mode, and Timer interrupt is generated when timer register T0 (T1, T2, T3) increases and matches TDR0 (TDR1, TDR2, TDR3). This timer interrupt in capture mode is very useful when the pulse width of captured sign al is more wider than the maximum period of Timer. For example, in Figure 13-14 , the pulse width of captured signal is wider than the timer data value (FF H) over 2 times. When external interrupt is occurred, the captured value (13 H) is more little than wanted value. It can be ob- tained correct value by counting the number of timer over- flow occurrence. Timer/Counter still does the above, but with the added fea- ture that a edge transition at external input INTx pin causes the current value in the Timer x register (T0,T1,T2,T3), to be captured into registers CDRx (CDR0, CDR1, CDR2, CDR3), respectively. After cap tured, Timer x register is cleared and restarts by hardware. It has three transition modes: "falling edge", "rising edge", "both edge" which are selected by interrupt edge selection register IEDS. Re- fer to “18.4 External Interrupt” on page 86. In addition, the transition at INTn pin generate an interrupt. Note: The CDRn and TDRn are in same address.In the capture mode, reading operation is read the CDRn, not TDRn because path is opened to the CDRn.

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 55 Figure 13-11 8-bit Capture Mode for Timer 0, 1 INT0IF 0: Stop 1: Clear and start T0ST INT0 INTERRUPT T0CN CDR0 (8-bit) T0 (8-bit) “01” “10” “11” Capture IEDS[1:0] EC0 PIN ÷ 2 ÷ 4 ÷ 8 XIN PIN MUX Prescaler T0CK[2:0] 111 000 001 010 MUX T1CK[1:0] ÷ 1 ÷ 2 ÷ 8 ÷ 32 ÷ 128 ÷ 512 ÷ 2048 011 100 101 110 INT0 PIN INT1IF 0: Stop 1: Clear and start T1ST INT1 INTERRUPT T1CN CDR1 (8-bit) T1 (8-bit) “01” “10” “11” Capture IEDS[3:2] INT1 PIN BTCL 76543210 --T 0 C N INITIAL VALUE: --00 0000B ADDRESS: 0D0H TM0 T0STT0CK0T0CK1CAP0 T0CK2 -- X X XX X means don’t care INITIAL VALUE: 00H ADDRESS: 0D2H TM1 X means don’t care BTCL 76543210 16BITPOL T1CN T1ST T1CK0T1CK1PWM1E CAP1 X0 XX XX01 Edge Detector clear clear

MC80F0104/0204 Preliminary 56 Mar. 2005 Ver 0.2 Figure 13-12 8-bit Capture Mode for Timer 2, 3 INT2IF 0: Stop 1: Clear and start T2ST INT2 INTERRUPT T2CN CDR2 (8-bit) T2 (8-bit) “01” “10” “11” Capture IEDS[5:4] EC1 PIN ÷ 2 ÷ 4 ÷ 8 XIN PIN MUX Prescaler T2CK[2:0] 111 000 001 010 MUX T3CK[1:0] ÷ 1 ÷ 4 ÷ 16 ÷ 16 ÷ 64 ÷ 256 ÷ 1024 011 100 101 110 INT2 PIN INT3IF 0: Stop 1: Clear and start T3ST INT3 INTERRUPT T3CN CDR3 (8-bit) T3 (8-bit) “01” “10” “11” Capture IEDS[7:6] INT3 PIN BTCL 76543210 --T 2 C N INITIAL VALUE: --00 0000B ADDRESS: 0D6H TM2 T2STT2CK0T2CK1CAP2 T2CK2 -- X X XX X means don’t care INITIAL VALUE: 00H ADDRESS: 0D8H TM3 X means don’t care BTCL 76543210 16BITPOL T3CN T3ST T3CK0T3CK1PWM3E CAP3 X0 XX XX01 Edge Detector clear clear

MC80F0104/0204 Preliminary 58 Mar. 2005 Ver 0.2 13.5 16-bit Capture Mode 16-bit capture mode is the same as 8-bit capture, except that the Timer register is being run will 16 bits. The clock source of the Timer 0 is selected either internal or external clock by bit T0CK[2:0]. In 16-bit mode, the bits T1CK1, T1CK0, CAP1 and 16BIT of TM1 should be set to "1" re- spectively as shown in Figure 13-15 . The clock source of the Timer 2 is selected either internal or external clock by bit T2CK[2:0]. In 16-bit mode, the bits T3CK1,T3CK0, CAP3 and 16BIT of TM3 should be set to "1" respectively as shown in Figure 13-16 . Figure 13-15 16-bit Capture Mode of Timer 0, 1 0: Stop 1: Clear and start T0ST T0CN Capture CDR1 + CDR0 Higher byte Lower byte (16-bit) CAPTURE DATA TDR1 + TDR0 (16-bit) INT0IF INT0 INTERRUPT “01” “10” “11” IEDS[1:0] EC0 PIN ÷ 2 ÷ 4 ÷ 8 XIN PIN MUX Prescaler T0CK[2:0] 111 000 001 010 ÷ 32 ÷ 128 ÷ 512 ÷ 2048 011 100 101 110INT0 PIN BTCL 76543210 --T 0 C N INITIAL VALUE: --00 0000B ADDRESS: 0D0H TM0 T0STT0CK0T0CK1CAP0 T0CK2 -- X X XX X means don’t care INITIAL VALUE: 00H ADDRESS: 0D2H TM1 X means don’t care BTCL 76543210 16BITPOL T1CN T1ST T1CK0T1CK1PWM1E CAP1 X1 XX 1101 Edge Detector clear

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 59 Figure 13-16 16-bit Capture Mode of Timer 2, 3 Example 1: Timer0 = 16-bit timer mode, 0.5s at 4MHz LDM TM0,#0000_1111B;8uS LDM TM1,#0100_1100B;16bit Mode LDM TDR0,#<62499 ;8uS X 62500 LDM TDR1,#>62499 ;=0.5s SET1 T0E EI Example 2: Timer0 = 16-bit event counter mode LDM PSR0,#0001_0000B;EC0 Set LDM TM0,#0001_1111B;CounterMode LDM TM1,#0100_1100B;16bit Mode LDM TDR0,#<0FFH ; LDM TDR1,#>0FFH ; SET1 T0E EI Example 3: Timer0 = 16-bit capture mode LDM PSR0,#0000_0001B;INT0 set LDM TM0,#0010_1111B;CaptureMode LDM TM1,#0100_1100B;16bit Mode LDM TDR0,#<0FFH ; LDM TDR1,#>0FFH ; LDM IEDS,#01H;Falling Edge SET1 T0E EI 0: Stop 1: Clear and start T2ST T2CN Capture CDR3 + CDR2 Higher byte Lower byte (16-bit) CAPTURE DATA TDR3 + TDR2 (16-bit) INT2IF INT2 INTERRUPT “01” “10” “11” IEDS[5:4] EC1 PIN ÷ 2 ÷ 4 ÷ 8 XIN PIN MUX Prescaler T2CK[2:0] 111 000 001 010 ÷ 16 ÷ 64 ÷ 256 ÷ 1024 011 100 101 110INT2 PIN BTCL 76543210 --T 2 C N INITIAL VALUE: --00 0000B ADDRESS: 0D6H TM2 T2STT2CK0T2CK1CAP2 T2CK2 -- X X XX X means don’t care INITIAL VALUE: 00H ADDRESS: 0D8H TM3 X means don’t care BTCL 76543210 16BITPOL T3CN T3ST T3CK0T3CK1PWM3E CAP3 X1 XX 110 1 Edge Detector clear

MC80F0104/0204 Preliminary 60 Mar. 2005 Ver 0.2

13.6 PWM Mode

TheMC80F0104/0204 has high speed PWM (Pulse Width Modulation) functions which shared with Timer1 or Timer3. In PWM mode, R10 / PWM1O or R11 / PWM3O pin out- put up to a 10-bit resolution PWM output. These pins should be configured as a PWM output by setting "1" bit PWM1OE and PWM3OE in PSR0 register. The period of the PWM1 output is determined by the T1PPR (T1 PWM Period Register) and T1PWHR[3:2] (bit3,2 of T1 PWM High Register) and the duty of the PWM output is determined by the T1PDR (T1 PWM Duty Register) and T3PWHR[1:0] (bit1,0 of T1 PWM High Register). The period of the PWM3 output is determined by the T3PPR (T3 PWM Period Register) and T3PWHR[3:2] (bit3,2 of T3 PWM High Register) and the duty of the PWM output is determined by the T3PDR (T3 PWM Duty Register) and T3PWHR[1:0] (bit1,0 of T3 PWM High Register). The user writes the lower 8-bit period value to the T1(3)PPR( and the higher 2-bit period value to the T1(3)PWHR[3:2]. And writes duty value to the T1(3)PDR and the T1(3)PWHR[1:0] same way. The T1(3)PDR is configured as a double buffering for glitchless PWM output. In Figure 13-18 , the duty data is transferred from the master to the slave when the period data matched to the counted value. (i.e. at the beginning of next duty cycle) PWM1(3) Period = [PWM1(3)HR[3:2]T(2)3PPR] X Source Clock PWM1(3) Duty = [PWM3HR[1:0]T3PDR] X Source Clock The relation of frequency and resolution is in inverse pro- portion. Table 13-3 shows the relation of PWM frequency vs. resolution. If it needed more higher frequency of PWM, it should be reduced resolution. The bit POL of TM1 or TM3 decides the polarity of duty cycle. If the duty value is set same to the period value, the PWM output is determined by the bit POL (1: High, 0: Low). And if the duty value is set to "00 H", the PWM output is deter- mined by the bit POL (1: Low, 0: High). It can be changed duty value when the PWM output. How- ever the changed duty value is output after the current pe- riod is over. And it can be maintained the duty value at present output when changed only period value shown as Figure 13-20 . As it were, the absolute duty time is not changed in varying frequency. But the changed period val- ue must greater than the duty value. Note: If changing the Timer1 to PWM function, it should be stop the timer clock firstly, and then set period and duty register value. If user writes register values while timer is in operation, these reg- ister could be set with certain values. Ex) Sample Program @4MHz 2uS LDM TM1,#1010_1000b ; Set Clock & PWM3E LDM T1PPR,#199 ; Period :400uS=2uSX(199+1) LDM T1PDR,#99 ; Duty:200uS=2uSX(99+1) LDM PWM1HR,00H LDM TM1,#1010_1011b ; Start timer1 Resolution Frequency T1CK[1:0] = 00(250nS) T1CK[1:0] = 01(500nS) T1CK[1:0] = 10(2uS) 10-bit 3.9kHz 0.98kHz 0.49kHz 9-bit 7.8kHz 1.95kHz 0.97kHz 8-bit 15.6kHz 3.90kHz 1.95kHz 7-bit 31.2kHz 7.81kHz 3.90kHz Table 13-3 PWM Frequency vs. Resolution at 4MHz

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 61 Figure 13-17 PWM1 Mode T1ST 0 : Stop 1 : Clear and Start Clear SQ R POL PWM1OE [PSR0.6] Period High Duty High Bit Manipulation Not Available INITIAL VALUE: 00H ADDRESS: 0D2H TM1 BTCL 76543210 16BITPOL T3CN T3ST T3CK0T3CK1PWM1E CAP3 X0 XX XX10 R/W R/W R/W R/W R/W R/W R/W R/W INITIAL VALUE: ---- 0000B ADDRESS: 0D5H T1PWHR X:The value "0" or "1" corresponding your operation. BTCL 76543210 -- T3PWHR1 T3PWHR0T3PWHR2T3PWHR3- - -- X X XX- - - - - -W W W W INITIAL VALUE: 0FFH ADDRESS: 0D3H T1PPR BTCL 76543210 WWWWWWWW INITIAL VALUE: 00H ADDRESS: 0D4H T1PDR BTCL 76543210 R/W R/W R/W R/W R/W R/W R/W R/W X:The value "0" or "1" corresponding your operation. T1PDR(8-bit) T1PDR(8-bit) T1PWHR[1:0] Slave Master T1PPR(8-bit) T1PWHR[1:0] ComparatorT1CN ÷ 1 ÷ 2 ÷ 8XIN PIN MUX Prescaler T1CK[1:0]T0 clock source [T0CK] T1(8-bit)2-bit Comparator R10 / PWM1O PIN

MC80F0104/0204 Preliminary 62 Mar. 2005 Ver 0.2 Figure 13-18 PWM3 Mode T3ST 0 : Stop 1 : Clear and Start Clear SQ R POL PWM3O [PSR0.7] Period High Duty High Bit Manipulation Not Available INITIAL VALUE: 00H ADDRESS: 0D8H TM3 BTCL 76543210 16BITPOL T3CN T3ST T3CK0T3CK1PWM3E CAP3 X0 XX XX10 R/W R/W R/W R/W R/W R/W R/W R/W INITIAL VALUE: ---- 0000B ADDRESS: 0DBH T3PWHR X:The value "0" or "1" corresponding your operation. BTCL 76543210 -- T3PWHR1 T3PWHR0T3PWHR2T3PWHR3- - -- X X XX- - - - - -W W W W INITIAL VALUE: 0FFH ADDRESS: 0D9H T3PPR BTCL 76543210 WWWWWWWW INITIAL VALUE: 00H ADDRESS: 0DAH T3PDR BTCL 76543210 R/W R/W R/W R/W R/W R/W R/W R/W X:The value "0" or "1" corresponding your operation. T3PDR(8-bit) T3PDR(8-bit) T3PWHR[1:0] Slave Master T3PPR(8-bit) T3PWHR[1:0] ComparatorT3CN ÷ 1 ÷ 4 ÷ 16XIN PIN MUX Prescaler T3CK[1:0]T2 clock source [T2CK] T3(8-bit)2-bit Comparator R11 / PWM3O PIN

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 65 (3) I/O operation The analog input pins AN0 ~ AN7,AN14 and AN15 also have function as input/output port pins. When A/D conver- sion is performed with any pin, be sure not to execute a PORT input instruction with the selected pin while conver- sion is in progress, as this may reduce the conversion res- olution. Also, if digital pulses are ap plied to a pin adjacent to the pin in the process of A/D conversion, the expected A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion. (4) AV DD pin input impedance A series resistor string of approximately 5KΩ is connected between the AVREF pin and the VSS pin. Therefore, if the output impedance of the analog power source is high, this will result in parallel connection to the series resistor string between the AV REF pin and the VSS pin, and there will be a large analog supply voltage error Figure 14-3 A/D Block Diagram AN0 / AVREF Sample & Hold AN1 AN7 AN14 Successive Approximation ADCIF ADC Result Register ADC INTERRUPTMUX Resistor Ladder Circuit VDD ADS[3:0] (ADCM[5:2]) Circuit ADEN ADC Result Register ADC8 01 2389 ADCRL (8-bit) 10-bit ADCR ADCRH ADCRL (8-bit)ADCRH ADCR (10-bit) 10-bit ADCR 10-bit Mode 8-bit Mode AN15 AVREFS (PSR1.3)

MC80F0104/0204 Preliminary 66 Mar. 2005 Ver 0.2 Figure 14-4 A/D Converter Control & Result Register BTCL 76543210 ADEN ADST A/D status bit Analog input channel select INITIAL VALUE: 0000 0001B ADDRESS: 0EFH ADCM ADSF A/D converter Clock Source Divide Ratio Selection bit 0: Clock Source fPS 1: Clock Source fPS ÷ 2 R/W R/W R/W R/W R/W R 0000: Channel 0 (AN0) 0001: Channel 1 (AN1) 0010: Channel 2 (AN2) 0011: Channel 3 (AN3) 0110: Channel 6 (AN6) 0111: Channel 7 (AN7) 1000 ~ 1101: Not available 0: A/D conversion is in progress 1: A/D conversion is completed A/D start bit Setting this bit starts an A/D conversion. After one cycle, bit is cleared to “0” by hardware. ADS1 ADS0 ADS3 ADS2ADCK 1110: Channel 14 (AN14) A/D converter Enable bit 0: A/D converter module turn off and current is not flow. 1: Enable A/D converter INITIAL VALUE: Undefined ADDRESS: 0F1HADCRL A/D Conversion Low Data R/W R/W BTCL 76543210 PSSEL1ADCRH - -ADC8 -PSSEL0 INITIAL VALUE: 010- ----B ADDRESS: 0F0H A/D Conversion High Data A/D Conversion Clock (fPS) Source Selection 00: fXIN ÷ 4 01: fXIN ÷ 8 10: fXIN ÷ 16 11: fXIN ÷ 32 BTCL 76543210 - - -RRWW RRRRRRRR ADCK PSSEL1 PSSEL0 PS Clock Selection 0 0 0 PS = f XIN ÷ 4 0 0 1 PS = f XIN ÷ 8 0 0 0 PS = f XIN ÷ 16 0 0 1 PS = f XIN ÷ 32 1 1 0 PS = f XIN ÷ 8 1 1 1 PS = f XIN ÷ 16 1 1 0 PS = f XIN ÷ 32 1 1 1 PS = f XIN ÷ 64 PS : Conversion Clock ADC 8-bit Mode select bit 0: 10-bit Mode 1: 8-bit Mode W 0100: Channel 4 (AN4) 0101: Channel 5 (AN5) 1111: Channel 15 (AN15)

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 67 15. SERIAL INPUT/OUTPUT (SIO) The serial Input/Output is used to transmit/receive 8-bit data serially. The Serial Input/Output (SIO) module is a se- rial interface useful for communicating with other periph- eral of microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. This SIO is 8-bit clock synchronous type and consists of serial I/O data register, serial I/O mode register, clock selection circuit, octal counter and control circuit as illustrated in Figure 15-1 . The SO pin is designed to input and output. So the Serial I/O(SIO) can be operated with minimum two pin. Pin R00/SCK, R01/SI, and R02/ SO pins are controlled by the Serial Mode Register. The contents of the Serial I/O data register can be written into or read out by software. The data in the Serial Data Regis- ter can be shifted synchronously with the transfer clock signal. Figure 15-1 SIO Block Diagram ÷ 4 ÷ 16XIN PIN Prescaler MUX SCK[1:0] SCK PIN SIO Shift Input shift register SIOR Clock Clock Octal Serial communication Interrupt SIOIF Internal Bus SIOSF Counter SCK[1:0] “11” overflow not “11” Complete Timer0 Overflow SI PIN IOSW SO PIN SOUT IOSW CONTROL CIRCUIT “0” “1” POL Start SIOST clear SM0 (3-bit)

MC80F0104/0204 Preliminary 68 Mar. 2005 Ver 0.2 Serial I/O Mode Register (SIOM) controls serial I/O func- tion. According to SCK1 and SCK0, the internal clock or external clock can be selected. Serial I/O Data Register (SIOR) is an 8-bit shift register. First LSB is send or is received. Figure 15-2 SIO Control Register

15.1 Transmission/Receiving Timing

The serial transmission is started by setting SIOST(bit1 of SIOM) to “1”. After one cycl e of SCK, SIOST is cleared automatically to “0”. At the default state of POL bit clear, the serial output data from 8-bit shift register is output at falling edge of SCLK, and input data is latched at rising edge of SCLK pin (Refer to Figure 15-3 ). When transmis- sion clock is counted 8 times, serial I/O counter is cleared as ‘0”. Transmission clock is halted in “H” state and serial I/O interrupt (SIOIF) occurred. BTCL 76543210 IOSWPOL SIOST Serial transmission status bit Serial transmission Clock selection INITIAL VALUE: 0000 0001B ADDRESS: 0E2H SIOM SIOSF Serial Input Pin Selection bit 0: SI Pin Selection 1: SO Pin Selection R/W R/W R/W R/W R/W R 00: fXIN ÷ 4 01: fXIN ÷ 16 10: TMR0OV(Timer0 Overflow) 11: External Clock 0: Serial transmission is in progress 1: Serial transmission is completed Serial transmission start bit Setting this bit starts an Serial transmission. After one cycle, bit is cleared to “0” by hardware. SCK1 SCK0 SM1 SM0 R/W Serial transmission Operation Mode 00: Normal Port(R42,R43,R44) 01: Sending Mode(SCK,R43,SO) 10: Receiving Mode(SCK,SI,R44) 11: Sending & Receiving Mode(SCK,SI,SO) INITIAL VALUE: Undefined ADDRESS: 0E3HSIOR BTCL 76543210 R/W R/W R/W R/W R/W R/WR/W R/W Sending Data at Sending Mode Receiving Data at Receiving Mode Serial Clock Polarity Selection bit 0: Data Transmission at Falling Edge Received Data Latch at Rising Edge 1: Data Transmission at Rising Edge Received Data Latch at Falling Edge R/W

MC80F0104/0204 Preliminary 70 Mar. 2005 Ver 0.2

15.2 The usage of Serial I/O

1. Select transmission/receiving mode. 2. In case of sending mode, write data to be send to SIOR. 3. Set SIOST to “1” to start serial transmission. 4. The SIO interrupt is generated at the completion of SIO and SIOIF is set to “1”. In SIO interrupt service routine, correct transmission should be tested. 5. In case of receiving mode, the received data is acquired by reading the SIOR. Note: When external clock is used, the frequency should be less than 1MHz and recommended duty is 50%. If both transmission mode is selected and transmission is performed simultaneously, error may be occur.

15.3 The Method to Test Correct Transmission

Figure 15-5 Serial IO Method to Test Transmission LDM SIOR,#0AAh ;set tx data LDM SIOM,#0011_1100b ;set SIO mode NOP LDM SIOM,#0011_1110b ;SIO Start Serial I/O Interrupt Service Routine SIOE = 0 Write SIOM Normal Operation Overrun Error Abnormal SIOSF - SIOE: Interrupt Enable Register High IENH(Bit1) - SIOIF: Interrupt Request Flag Register High IRQH(Bit1) SIOIF

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 71 16. UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART)

16.1 UART Serial Interface Functions

The Universal Asynchronous Receiver / Transmitter (UART) enables full-duplex operation wherein one byte of data after the start bit is transmitted and received. The on- chip baud rate generator dedicated to UART enables com- munications using a wide range of selectable baud rates. In addition, a baud rate can also be defined by dividing clocks input to the ACLK pin. The UART driver consists of RXR, TXR, ASIMR, ASISR and BRGCR register. Universal asynchronous serial I/O mode (UART) can be selected by ASIMR register. Figure 16-1 shows a block diagram of the UART driver. Figure 16-1 UART Block Diagram (ASISR) Transmit Shift Register Internal Data Bus TxD PIN RxD PIN TxE RxE ACLK PIN fXIN ÷2 ~ fXIN÷128 (TXR) Transmit Controller (Parity Addition) Receive Buffer Register (RXR) Receive Shift Register (RX) Receive Controller (Parity Check) Baud Rate Generator 210 PE FE OVE INT_TX (UART tramsmit interrupt) INT_RX (UART receive interrupt)

MC80F0104/0204 Preliminary 72 Mar. 2005 Ver 0.2 Figure 16-2 Baud Rate Generator Block Diagram

16.2 Serial Interface Configuration

The UART interface consists of the following hardware. Transmit shift register (TXR) This is the register for setting transmit data. Data written to TXR is transmitted as serial data. When the data length is set as 7 bit, bit 0 to 6 of the data written to TXR are trans- ferred as transmit data. Writing data to TXR starts the transmit operation. TXR can be written by an 8 bit memory manipulation in- struction. It cannot be read. The RESET input sets TXR to 0FFH. Receive buffer register (RXR) This register is used to hold receive data. When one byte of data is received, one byte of new receive data is transferred from the receive shift register (RXSR). When the data length is set as 7 bits, receive data is sent to bits 0 to 6 of RXR. In this case, the MSB of RXR always becomes 0. RXR can be read by an 8 bit memory manipulation instruc- tion. It cannot be written. The RESET input sets RXR to 00H. Receive shift register This register converts serial data input via the RXD pin to paralleled data. When one byte of data is received at this register cannot be manipulated directly by a program. Asynchronous serial interface mode register (ASIMR) This is an 8 bit register that controls UART serial transfer operation. ASIMR is set by a 1 bit or 8 bit memory manip- ulation intruction. The RESET input sets ASIMR to 0000_-00-B. Figure 16-3 shows the format of ASIMR The RXD / R04 and TXD / R05 pin function selection is shown in Table 16-2. Note: Do not switch the operation mode until the current serial transmit/receive operation has stopped. MUX RECEIVE RxE Tx_Clock Rx_Clock TxE SEND 5-bit counter Decoder 5-bit counter match match (BRGCR) - TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 ACLK PIN fXIN÷2 ~ fXIN÷128 Internal Data Bus (Divider) (Divider) Item Configuration Register Transmit shift register (TXR) Receive buffer register (RXR) Receive shift register Control register Serial interface mode register (ASIMR) Serial interface status register (ASISR) Baud rate generator control register (BRGCR) Table 16-1 Serial Interface Configuration

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 73 Figure 16-3 Asynchronous Serial Interface Mode register (ASIMR) Format BTCL 76543210 RXETXE ISRM UART Stop Bit Length for Specification for Transmit Data bit INITIAL VALUE: 0000 -00-B ADDRESS: 0E6H ASIMR - R/W R/W - R/W R/W - 0: 1 bit 1: 2 bit UART Receive interrupt request is issued when an error occurs bit - SL PS1 PS0 R/W UART Parity Bit Specification bit 00: No parity 01: Zero parity always added during transmission. 10: Odd parity 11: Even parity UART Tx/Rx Enable bit R/W 0: Receive Completion Interrupt Control When Error occurs 1: Receive completion interrupt request is not issued when an error occur No parity detection during reception (parity errors do not occur) 00: Not used UART 01: UART Receive only Mode 10: UART Transmit only Mode 11: UART Receive & Transmit Mode TXE (ASIMR.7) RXE(ASIMR.6) EC0(PSR0. 4) Operation Mode RXD/R04 TXD/R05

00 X1 Operation Stop R04 R05

0 1 0 UART mode (Receive only) RXD R05 1 0 X UART mode (Transmit only) R04 TXD 1 1 0 UART mode (Transmit and receive) RXD TXD Table 16-2 UART mode and RXD/TXD pin function 1. X:The value "0" or "1" corresponding your operation

MC80F0104/0204 Preliminary 74 Mar. 2005 Ver 0.2 Asynchronous serial interface status register (ASISR) When a receive error occurs during UART mode, this reg- ister indicates the type of error. ASISR can be read by an 8 bit memory manipulation instruction. The RESET input sets ASISR to ----_-000B. Figure 16-4 shows the format of ASISR.. Figure 16-4 Asynchronous Serial Interface Status Register (ASISR) Format BTCL 76543210 -- FE UART Frame Error Flag INITIAL VALUE: ---- -000B ADDRESS: 0E7H ASISR OVE RRR 0: No Frame error 1: Framing errorNote1 (stop bit not detected) UART Parity Error Flag - PE - - UART Overrun Error Flag 0: No overrun error 1: Overrun errorNote2 0: No parity error 1: Parity error (Transmit data parity not matched) Note 1. Even if a stop bit length is set to 2 bits by setting bit2(SL) in ASIMR, stop bit detection during a recive operation only applies to a stop bit length of 1bit. 2. Be sure to read the contents of the receive buffer register(RXR) when an overrun error has occurred. Until the contents of RXR are read, futher overrun errors will occur when receiving data. (Next receive operation was completed before data was read from receive buffer register (RXR))

MC80F0104/0204 Preliminary 76 Mar. 2005 Ver 0.2

16.3 Communication operation

The transmit operation is enabled when bit 7 (TXE) of the asynchronous serial interface mode register (ASIMR) is set to 1. The transmit operat ion is started when transmit data is written to the transmit shift register (TXR). The tim- ing of the transmit completion interrupt request is shown in Figure 16-6 . The receive operation is enab led when bit 6 (RXE) of the asynchronous serial interface mode register (ASIMR) is set to 1, and input via the RxD pin is sampled. The serial clock specified by ASIMR is used to sample the RxD pin. Once reception of one data frame is completed, a receive completion interrupt request (INT_RX) occurs. Even if an error has occurred, the receive data in which the error oc- curred is still transferred to RXR. When ASIMR bit 1 (IS- RM) is cleared to 0 upon o ccurrence of an error, and INT_RX occurs. When ISRM bit is set to 1, INT_RX does not occur in case of error occu rrence. Figure 16-6 shows the timing of the asynchronous serial interface receive completion interrupt request. Figure 16-6 UART data format and interrupt timing diagram D0 D1 TxD TX D2RxD D4D3 D6D5 D7 Parity INTERRUPT Stop 1 data frame character bits 1 data frame consists of following bits. - Start bit : 1 bit - Character bits : 8 bits - Parity bit : Even parity, Odd parity, Zero parity, No parity - Stop bit(s) : 1 bit or 2 bits RX INTERRUPT Start 1. Stop bit Length : 1 bit D0 D1 TxD TX D2RxD D4D3 D6D5 D7 Parity INTERRUPT Stop 1 data frame character bits RX INTERRUPT Start 2. Stop bit Length : 2 bit D0 D1 TxD TX D2RxD D4D3 D6D5 D7 INTERRUPT 1 data frame character bits RX INTERRUPT Start 3. Stop bit Length : 1 bit, No parity Stop

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 77

16.4 Relationship between main clock and baud rate

The transmit/receive clock that is used to generate the baud rate is obtained by dividing the main system clock. Trans- mit/Receive clock generation for baud rate is made by us- ing main system clock which is divided. The baud rate generated from the main system clock is determined ac- cording to the following formula. Figure 16-7 Relationship between main clock and Baud Rate Baud Rate (bps) fXIN=11.05 92M fXIN=10.0M f XIN=8.0M f XIN=4.0M f XIN=2.0M BRGCR ERR(%) BRGCR ERR(%) BRGCR ERR(%) BRGCR ERR (%) BRGCR ERR(%) 600 - - - - - - 7AH 0.16 6AH 0.16 1200 - - - - 7AH 0.16 6AH 0.16 5AH 0.16 38400 32H 0.00 30H 1.73 2AH 0.16 1AH 0.16 - - 57600 28H 0.00 26H 1.35 21H 2.11 11H 2.12 - - 76800 22H 0.00 20H 1.73 1AH 0.16 - - - - 115200 18H 0.00 16H 1.36 11H 2.12 - - - - 2. fSCK : Source clock for 5 bit counter 3. n : Value set via TPS0 to TPS2 ( 0 ≤ n ≤ 7 ) 4. k : Source clock for 5 bit counter ( 0 ≤ k ≤ 14 ) Remarks 1. f XIN : Main system clock oscillation frequency When ACLK is selected as the source clock of the 5-bit counter, substitute the input clock frequency to ACLK pin for in the above expression. Baud Rate = fXIN ÷ ( 2n+1(k+16) )

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 79 The 6-bit counter is cleared and starts the counting by writ- ing signal at BUZR register. It is incremental from 00H un- til it matches 6-bit BUR value. When main-frequency is 4MHz, buzzer frequency is shown as below Table 17-1. BUR [5:0] BUR[7:6] BUR [5:0] BUR[7:6] 00 01 10 11 00 01 10 11 250.000 125.000 83.333 62.500 50.000 41.667 35.714 31.250 125.000 62.500 41.667 31.250 25.000 20.833 17.857 15.625 62.500 31.250 20.833 15.625 12.500 10.417 8.929 7.813 31.250 15.625 10.417 7.813 6.250 5.208 4.464 3.906 7.576 7.353 7.143 6.944 6.757 6.579 6.410 6.250 3.788 3.676 3.571 3.472 3.378 3.289 3.205 3.125 1.894 1.838 1.786 1.736 1.689 1.645 1.603 1.563 0.947 0.919 0.893 0.868 0.845 0.822 0.801 0.781 27.778 25.000 22.727 20.833 19.231 17.857 16.667 15.625 13.889 12.500 11.364 10.417 9.615 8.929 8.333 7.813 6.944 6.250 5.682 5.208 4.808 4.464 4.167 3.906 3.472 3.125 2.841 2.604 2.404 2.232 2.083 1.953 6.098 5.952 5.814 5.682 5.556 5.435 5.319 5.208 3.049 2.976 2.907 2.841 2.778 2.717 2.660 2.604 1.524 1.488 1.453 1.420 1.389 1.359 1.330 1.302 0.762 0.744 0.727 0.710 0.694 0.679 0.665 0.651 14.706 13.889 13.158 12.500 11.905 11.364 10.870 10.417 7.353 6.944 6.579 6.250 5.952 5.682 5.435 5.208 3.676 3.472 3.289 3.125 2.976 2.841 2.717 2.604 1.838 1.736 1.645 1.563 1.488 1.420 1.359 1.302 5.102 5.000 4.902 4.808 4.717 4.630 4.545 4.464 2.551 2.500 2.451 2.404 2.358 2.315 2.273 2.232 1.276 1.250 1.225 1.202 1.179 1.157 1.136 1.116 0.638 0.625 0.613 0.601 0.590 0.579 0.568 0.558 10.000 9.615 9.259 8.929 8.621 8.333 8.065 7.813 5.000 4.808 4.630 4.464 4.310 4.167 4.032 3.906 2.500 2.404 2.315 2.232 2.155 2.083 2.016 1.953 1.250 1.202 1.157 1.116 1.078 1.042 1.008 0.977 4.386 4.310 4.237 4.167 4.098 4.032 3.968 3.907 2.193 2.155 2.119 2.083 2.049 2.016 1.984 1.953 1.096 1.078 1.059 1.042 1.025 1.008 0.992 0.977 0.548 0.539 0.530 0.521 0.512 0.504 0.496 0.488 Table 17-1 buzzer frequency (kHz unit)

MC80F0104/0204 Preliminary 80 Mar. 2005 Ver 0.2 18. INTERRUPTS TheMC80F0104/0204 interrupt circuits consist of Inter- rupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, Priority circ uit, and Master enable flag (“I” flag of PSW). Fifteen in terrupt sources are provided. The configuration of interrupt circuit is shown in Figure 18-1 and interrupt priority is shown in Table 18-1. The External Interrupts INT0 ~ INT3 each can be transi- tion-activated (1-to-0 or 0-to-1 transition) by selection IEDS register. The flags that actually genera te these interrupts are bit INT0IF, INT1IF, INT2IF and INT3IF in register IRQH. When an external interrupt is generated, the generated flag is cleared by the hardware when the service routine is vec- tored to only if the interrupt was transition-activated. The Timer 0 ~ Timer 3 Interrupts are generated by T0IF, T1IF, T2IF and T3IF which is set by a match in their re- spective timer/counter register. The Basic Interval Timer Interrupt is generated by BITIF which is set by an overflow in the timer register. The AD converter Interrupt is generated by ADCIF which is set by finishing the analog to digital conversion. The Watchdog timer is generated by WDTIF and WTIF which is set by a match in Watchdog timer register. Figure 18-1 Block Diagram of Interrupt UART Rx INT2 INT1 INT0 INT0IF IENH Interrupt Enable Interrupt Enable IRQH IRQL Internal bus line Register (Lower byte) Internal bus line Register (Higher byte) Release STOP/SLEEP To CPU Interrupt Master Enable Flag I-flag IENL Priority Control I-flag is in PSW, it is cleared by “DI”, set by “EI” instruction. When it goes interrupt service, I-flag is cleared by hardware, thus any other interrupt are inhibited. When interrupt service is completed by “RETI” instruction, I-flag is set to “1” by hardware. [0EAH] [0ECH] [0EDH] INT1IF INT2IF INT3IF UARTRIF T0IF SIOIF INT3 UART Tx Timer 0 Serial UARTTIF Timer 1 T1IF T3IF Timer 2 Timer 3 T2IF A/D Converter ADCIF BITIF Watchdog Timer BIT WDTIF [0EBH] Communication Interrupt Vector Address Generator

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 81 The Basic Interval Timer Interrupt is generated by BITIF which is set by a overflow in the timer counter register. The UART receive or transmit interrupts are generated by UARTRIF or UARTTIF are set by completion of UART data reception or transmission. The SIO interrupt is generated by SIOIF which is set by completion of SIO data reception or transmission. The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW on Figure 8-3 ), the interrupt en- able register (IENH, IENL), and the interrupt request flags (in IRQH and IRQL) except Power-on reset and software BRK interrupt. The Table 18-1 shows the Interrupt priori- ty. Vector addresses are shown in Figure 8-6 . Interrupt enable registers are shown in Figure 18-2 . These registers are composed of interrupt enable flags of each interrupt source and these flags determines whether an interrupt will be ac- cepted or not. When enable flag is “0”, a corresponding in- terrupt source is prohibited. Note that PSW contains also a master enable bit, I-flag, wh ich disables all interrupts at once. Figure 18-2 Interrupt Enable Flag Register Reset/Interrupt Symbol Priority Hardware Reset External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 UART Rx Interrupt UART Tx Interrupt Serial Input/Output Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 Timer/Counter 3 ADC Interrupt Watchdog Timer Basic Interval Timer RESET INT0 INT1 INT2 INT3 INT_RX INT_TX SIO Timer 0 Timer 1 Timer 2 Timer 3 ADC WDT BIT Table 18-1 Interrupt Priority INT3E R/W INT0E Timer/Counter 0 interrupt enable flag INITIAL VALUE: 0000 0000B ADDRESS: 0EAH IENH INT1E MSB LSB SIOE T0EUARTREINT2E R/W R/W Serial Communication interrupt enable flag UART Tx interrupt enable flag External interrupt 0 enable flag UART Rx interrupt enable flag R/W R/WR/W R/W R/W External interrupt 1 enable flag External interrupt 2 enable flag External interrupt 3 enable flag R/W T1E INITIAL VALUE: 000- 00-0B ADDRESS: 0EBH IENL T2E MSB R/W Timer/Counter 3 interrupt enable flag R/W R/W Timer/Counter 2 interrupt enable flag Timer/Counter 1 interrupt enable flag LSB R/W ADCE WDTE R/WR/W R/W T3E - - BITE Basic Interval Timer interrupt enable flag Watchdog timer interrupt enable flag A/D Converter interrupt enable flag UARTTE

MC80F0104/0204 Preliminary 82 Mar. 2005 Ver 0.2 Figure 18-3 Interrupt Request Flag Register

18.1 Interrupt Sequence

An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to “0” by a reset or an in- struction. Interrupt acceptance sequence requires 8 cycles of fXIN (2µs at f XIN=4MHz) after the completion of the current instruction execution. The interrupt service task is terminated upon execution of an interrupt return instruc- tion [RETI].

18.1.1 Interrupt acceptance

1. The interrupt master enable flag (I-flag) is cleared to “0” to temporarily disable the acceptance of any follow- ing maskable interrupts. When a non-maskable inter- rupt is accepted, the ac ceptance of any following interrupts is temporarily disabled. 2. Interrupt request flag for the interrupt source accepted is cleared to “0”. 3. The contents of the prog ram counter (return address) and the program status word are saved (pushed) onto the stack area. The stack pointer decreases 3 times. 4. The entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. The instruction stored at th e entry address of the inter- rupt service program is executed. INT3IF R/W INT0IF Timer/Counter 0 interrupt request flag INITIAL VALUE: 0000 0000B ADDRESS: 0ECH IRQH INT1IF MSB LSB SIOIF T0IFUARTRIF UARTTIFINT2IF R/W R/W Serial Communication interrupt request flag UART Txx interrupt request flag External interrupt 3 request flag UART Rx interrupt request flag R/W R/WR/W R/W R/W External interrupt 2 request flag External interrupt 1 request flag External interrupt 0 request flag R/W T1IF INITIAL VALUE: 000- 00-0B ADDRESS: 0EDH IRQL T2IF MSB Timer/Counter 3 interrupt request flag R/W R/W Timer/Counter 2 interrupt request flag Timer/Counter 1 interrupt request flag LSB ADCIF WDTIF R/WR/W R/W T3IF - - BITIF Basic Interval Timer interrupt request flag Watchdog timer interrupt request flag A/D Converter interrupt request flag

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 83 Figure 18-4 Timing chart of Interrupt Acceptance and Interrupt Return Instruction A interrupt request is not accepte d until the I-flag is set to “1” even if a requested inte rrupt has higher priority than that of the current interrupt being serviced. When nested interrupt service is required, the I-flag should be set to “1” by “EI” instru ction in the interrupt service program. In this case, acceptabl e interrupt sources are se- lectively enabled by the individual interrupt enable flags.

18.1.2 Saving/Restoring General-purpose Register

During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. These regist ers are saved by the software if necessary. Also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory area for saving registers. The following method is used to save/restore the general- purpose registers. Example: Register save us ing push and pop instruc- tions General-purpose register save/r estore using push and pop instructions; V.L. System clock Address Bus PC SP SP-1 SP-2 V.H. New PC V.L.Data Bus Not used PCH PCL PSW ADL OP codeADH Instruction Fetch Internal Read Internal Write Interrupt Processing Step Interrupt Service Task ADL and ADH are start addresses of interrupt service routine as vector contents. Basic Interval Timer 012H 0E3H 0FFE0H 0FFE1H 0EH 2EH 0E312H 0E313H Entry Address Correspondence between vector table address for BIT interrupt and the entry address of the interrupt service program. Vector Table Address INTxx: PUSH A PUSH X PUSH Y ;SAVE ACC. ;SAVE X REG. ;SAVE Y REG. interrupt processing POP Y POP X POP A RETI ;RESTORE Y REG. ;RESTORE X REG. ;RESTORE ACC. ;RETURN

MC80F0104/0204 Preliminary 84 Mar. 2005 Ver 0.2

18.2 BRK Interrupt

Software interrupt can be invoked by BRK instruction, which has the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distin- guish BRK from TCALL 0. Each processing step is determined by B-flag as shown in Figure 18-5 . Figure 18-5 Execution of BRK/TCALL0

18.3 Multi Interrupt

If two requests of different pr iority levels are received si- multaneously, the request of hi gher priority level is ser- viced. If requests of the inte rrupt are received at the same time simultaneously, an inte rnal polling sequence deter- mines by hardware which requ est is serviced. However, multiple processing through software for special features is possible. Generally when an interrupt is accepted, the I- flag is cleared to disable an y further interrupt. But as user sets I-flag in interrupt routin e, some further interrupt can main task interrupt service task saving registers restoring registers acceptance of interrupt interrupt return B-FLAG BRK INTERRUPT ROUTINE RETI TCALL0 ROUTINE RET BRK or TCALL0

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 85 be serviced even if certain interrupt is in progress. Figure 18-6 Execution of Multi Interrupt Example: During Timer1 interrupt is in progress, INT0 in- terrupt serviced without any suspend. TIMER1: PUSH A PUSH X PUSH Y LDM IENH,#80H ;Enable INT0 only LDM IENL,#0 ;Disable other int. EI ;Enable Interrupt LDM IENH,#0FFH ;Enable all interrupts LDM IENL,#0FFH POP Y POP X POP A RETI enable INT0 TIMER 1 service INT0 service Main Program service Occur TIMER1 interrupt Occur INT0 EI disable other enable INT0 enable other In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting the interrupt enable registers IENH,IENL and master enable “EI” in the TIMER1 routine.

MC80F0104/0204 Preliminary 86 Mar. 2005 Ver 0.2

18.4 External Interrupt

The external interrupt on INT0, INT1, INT2 and INT3 pins are edge triggered depending on the edge selection register IEDS (address 0EE H) as shown in Figure 18-7 . The edge detection of external interrupt has three transition activated mode: rising edge, falling edge, and both edge. Figure 18-7 External Interrupt Block Diagram INT0 ~ INT3 are multiplexed with general I/O ports (R11, R12, R03, R00). To use as an external interrupt pin, the bit of port selection register PSR 0 should be set to “1” corre- spondingly. Example: To use as an INT0 and INT2 ;** Set external interrupt port as pull-up state. LDM PU1,#0000_0101B ; Set port as an external interrupt port LDM PSR0,#0000_0101B ;** Set Falling-edge Detection LDM IEDS,#0001_0001B Response Time The INT0 ~ INT3 edge are latched into INT0IF ~ INT3IF at every machine cycle. The values are not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to th e requested service routine will be the next instruction to be executed. The DIV itself takes twelve cycles. Thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. Figure 18-8 shows interrupt response timings. Figure 18-8 Interrupt Response Timing Diagram INT0IFINT0 pin INT0 INTERRUPT INT1IFINT1 pin INT1 INTERRUPT INT2IFINT2 pin INT2 INTERRUPT IEDS [0EEH] INT3IFINT3 pin INT3 INTERRUPT Edge selection Register 2 2 2 2 Interrupt goes active Interrupt latched Interrupt processing Interrupt routine 8 fXINmax. 12 fXIN

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 87 Figure 18-9 IEDS register and Port Selection Register PSR0 BTCL WWWWWWWW EC1EPWM1OPWM3O INT1E 0: R11 1: INT0 INITIAL VALUE: 00H ADDRESS: 0F8HPSR0 EC0E INT0E INT2EINT3E 0: R12 1: INT1 0: R03 1: INT2 0: R00 1: INT3 0: R11 1: PWM3O 0: R07 1: EC1 0: R04 1: EC0 LSBMSB BTCL WWWWWWWW IED2HIED3LIED3H IED0H INITIAL VALUE: 00H ADDRESS: 0EEHIEDS IED2L IED0L IED1LIED1H LSBMSB Edge selection register 00: Reserved 01: Falling (1-to-0 transition) 10: Rising (0-to-1 transition) 11: Both (Rising & Falling) INT0 INT1INT2INT3 0: R10 1: PWM1O

MC80F0104/0204 Preliminary 88 Mar. 2005 Ver 0.2 19. POWER SAVING OPERATION TheMC80F0104/0204 has two power-down modes. In power-down mode, power consumption is reduced considerably. For applications where power consumption is a critical factor, device provides two kinds of power sav- ing functions, STOP mode and SLEEP mode. Table 19-1 shows the status of each Power Saving Mode. SLEEP mode is entered by the SSCR register to “0Fh”., and STOP mode is entered by STOP instruction after the SSCR regis- ter to “5Ah”.

19.1 Sleep Mode

In this mode, the internal oscillation circuits remain active. Oscillation continues and peripherals are operate normally but CPU stops. Movement of all peripherals is shown in Table 19-1. SLEEP mode is entered by setting the SSCR register to “0Fh”. It is released by Reset or interrupt. To be released by interrupt, interrupt should be enabled before SLEEP mode. Figure 19-1 STOP and SLEEP Control Register Release the SLEEP mode The exit from SLEEP mode is hardware reset or all inter- rupts. Reset re-defines all the Control registers but does not change the on-chip RAM. Interrupts allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. If I- flag = 0, the chip will resu me execution starting with the instruction following the SLEEP instruction. It will not vector to interrupt service routine. (refer to Figure 19-4 ) When exit from SLEEP mode by reset, enough oscillation stabilizing time is required to normal operation. Figure 19- 3 shows the timing diagram. When released from the SLEEP mode, the Basic interval timer is activated on wake-up. It is increased from 00 H until FF H. The count overflow is set to start normal operation. Therefore, before SLEEP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized. By interrupts, exit from SLEEP mode is shown in Figure 19-2 . By reset, exit from SLEEP mode is shown in Figure 19-3 . 76543210 INITIAL VALUE: 0000 0000B ADDRESS: 0F5HSSCR W Power Down Control 5AH: STOP mode 0FH: SLEEP mode W W W W W W W NOTE : To get into STOP mode, SSCR must be set to 5AH just before STOP instruction execution. At STOP mode, Stop & Sleep Control Register (SSCR) value is cleared automatically when released. To get into SLEEP mode, SSCR must be set to 0FH.

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 89 Figure 19-2 SLEEP Mode Release Timing by External Interrupt Figure 19-3 Timing of SLEEP Mode Release by Reset

19.2 Stop Mode

In the Stop mode, the main oscillator, system clock and pe- ripheral clock is stopped, but RC-oscillated watchdog tim- er continue to operate. With the clock frozen, all functions are stopped, but the on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. Oscillator stops and the systems internal operations are all held up.

• The states of the RAM, registers, and latches valid immediately before the system is put in the STOP state are all held.
• The program counter stop the address of the instruction to be executed after the instruction "STOP" which starts the STOP operating mode. Note: The Stop mode is activated by execution of STOP instruc- tion after setting the SSCR to “5AH”. (This register should be writ- ten by byte operation. If this register is set by bit manipulation instruction, for example "set1" or "clr1" instruction, it may be undes- ired operation) In the Stop mode of operation, VDD can be reduced to min- imize power consumption. Care must be taken, however, to ensure that VDD is not reduced before the Stop mode is invoked, and that V DD is restored to its normal operating level, before the Stop mode is terminated. Oscillator (XIN pin) Normal Operation SLEEP Operation External Interrupt Internal Clock SLEEP Instruction Executed Normal Operation SLEEP Instruction Stabilization Time tST = 65.5mS @4MHz Internal RESET RESET Oscillator (XIN pin) ~~CPU Clock ~~~ Execution Normal Operation SLEEP Operation Normal Operation

MC80F0104/0204 Preliminary 90 Mar. 2005 Ver 0.2 The reset should not be activated before VDD is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize. Note: After STOP instruction, at least two or more NOP instruc- tion should be written. Ex) LDM CKCTLR,#0FH ;more than 20ms LDM SSCR,#5AH STOP NOP ;for stabilization time NOP ;for stabilization time In the STOP operation, the dissipation of the power asso- ciated with the oscillator and the internal hardware is low- ered; however, the power dissipation associated with the pin interface (depending on the external circuitry and pro- gram) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level (V DD/VSS); however, when the input level gets high- er than the power voltage level (by approximately 0.3 to 0.5V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring to fix the level by pull-up or other means. Release the STOP mode The source for exit from STOP mode is hardware reset, ex- ternal interrupt, Timer(EC0,1 ), Watch Timer, WDT, SIO or UART. Reset re-defines al l the Control registers but does not change the on-chip RA M. External interrupts al- low both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. If I- flag = 0, the chip will resu me execution starting with the instruction following the STOP instruction. It will not vec- tor to interrupt service routine. (refer to Figure 19-4 ) When exit from Stop mode by external interrupt, enough oscillation stabilizing time is required to normal operation. Figure 19-5 shows the timing diagram. When released from the Stop mode, the Basic interval timer is activated on wake-up. It is increased from 00 H until FF H. The count overflow is set to start normal operation. Therefore, before STOP instruction, user must be set its relevant prescaler di- vide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized. Peripheral STOP Mode SLEEP Mode CPU Stop Stop RAM Retain Retain Basic Interval Timer Halted Operates Continuously Watchdog Timer Stop (Only operates in RC-WDT mode) Stop Timer/Counter Halted (Only when the event counter mode is enabled, timer operates normally) Operates Continuously Buzzer, ADC Stop Stop SIO Only operate with external cloc k Only operate with external clock UART Only operate with external cloc k Only operate with external clock Oscillator Stop (XIN=L, XOUT=H) Oscillation I/O Ports Retain Retain Control Registers Retain Retain Internal Circuit Stop mode Sleep mode Prescaler Retain Active Address Data Bus Retain Retain Release Source Reset, Timer(EC0,1), SIO, UART(using ACLK), Watchdog Timer (RC-WDT mode), External Interrupt Reset, All Interrupts Table 19-1 Peripheral Operation During Power Saving Mode

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 91 By reset, exit from Stop mode is shown in Figure 19-6 . Figure 19-4 STOP Releasing Flow by Interrupts Figure 19-5 STOP Mode Release Timing by External Interrupt IENH or IENL ? STOP INSTRUCTION STOP Mode Interrupt Request STOP Mode Release I-FLAG Interrupt Service Routine Next INSTRUCTION Master Interrupt Enable Bit PSW[2] Corresponding Interrupt Enable Bit (IENH, IENL) Before executing Stop instruction, Basic Interval Timer must be set Oscillator (XIN pin) n 0BIT Counter n+1 n+2 n+3 Normal Operation Stop Operation Normal Operation

1 FE FF 0 12

~~ ~ tST > 20ms External Interrupt Internal Clock Clear STOP Instruction Executed ~~~ properly by software to get stabilization time which is longer than 20ms. by software Stabilization Time

MC80F0104/0204 Preliminary 92 Mar. 2005 Ver 0.2 Figure 19-6 Timing of STOP Mode Release by Reset

19.3 Stop Mode at Internal RC-Oscillated Watchdog Timer Mode

In the Internal RC-Oscillated Watchdog Timer mode, the on-chip oscillator is stopped. But internal RC oscillation circuit is oscillated in th is mode. The on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction regis- ters. The Internal RC-Oscillated Watchdog Timer mode is acti- vated by execution of STOP instruction after setting the bit RCWDT of CKCTLR to "1". (This register should be writ- ten by byte operation. If this register is set by bit manipu- lation instruction, for example "set1" or "clr1" instruction, it may be undesired operation) Note: Caution: After STOP instruction, at least two or more NOP instruction should be written Ex) LDM WDTR,#1111_1111B LDM CKCTLR,#0010_1110B LDM SSCR,#0101_1010B STOP NOP ;for stabilization time NOP ;for stabilization time The exit from Internal RC-Oscillated Watchdog Timer mode is hardware reset or external interrupt or watchdog timer interrupt (at RC-watchdog timer mode). Reset re-de- fines all the Control registers but does not change the on- chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal in terrupt response takes place. In this case, if the bit WDTON of CKCTLR is set to "0" and the bit WDTE of IENH is set to "1", the device will execute the watchdog timer interrupt service routine(Figure 8-6 ). However, if the bit WDTON of CKCTLR is set to "1", the device will generate the internal Reset signal and execute the reset processing(Figure 19-8 ). If I-flag = 0, the chip will resume execution starting with the instruction follow- ing the STOP instruction. It will not vector to interrupt ser- vice routine.(refer to Figure 19-4 ) When exit from Stop mode at Internal RC-Oscillated Watchdog Timer mode by external interrupt, the oscilla- tion stabilization time is required to normal operation. Fig- ure 19-7 shows the timing diagram. When release the Internal RC-Oscillated Watchdog Timer mode, the basic interval timer is activated on wake-up. It is increased from H until FFH. The count overflow is set to start normal op- eration. Therefore, before ST OP instruction, user must be set its relevant prescaler divi de ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized. By reset, exit from internal RC- Oscillated Watchdog Timer mode is shown in Figure 19-8 STOP Mode Time can not be control by software Oscillator (XI pin) ~~~ STOP Instruction Execution Stabilization Time tST = 65.5mS @4MHz Internal Clock Internal ~~ ~ RESET RESET

MC80F0104/0204 Preliminary 94 Mar. 2005 Ver 0.2

19.4 Minimizing Current Consumption

The Stop mode is designed to reduce power consumption. To minimize current drawn during Stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical. Figure 19-9 Application Example of Unused Input Port Figure 19-10 Application Example of Unused Output Port Note: In the STOP operation, the power dissipation associated with the oscillator and the inter nal hardware is lowered; however, the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power volt- age level (V DD/VSS); however, when the input level becomes high- er than the power voltage level (by approximately 0.3V), a current begins to flow. Therefore, if cutting off the output transistor at an I/ O port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring it to fix the level by pull-up or other means. It should be set properly in order that current flow through port doesn't exist. First consider the port setting to input mode. Be sure that there is no current flow after considering its relationship with external circuit. In input mode, the pin impedance INPUT PIN VDD GND i VDD X Weak pull-up current flows VDD internal pull-up INPUT PIN i VDD X Very weak current flowsVDD O O OPEN OPEN i=0 O i=0 O GND When port is configured as an input, input level should be closed to 0V or 5V to avoid power consumption. OUTPUT PIN GND i In the left case, much current flows from port to GND. X ON OFF OUTPUT PIN GND i In the left case, Tr. base current flows from port to GND. i=0 X OFF ON VDD L ON OFF OPEN GND VDD L ON OFF To avoid power consumption, there should be low output ON OFF O O VDD O to the port .

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 95 viewing from external MCU is very high that the current doesn’t flow. But input voltage level should be V SS or VDD. Be careful that if unspecified voltage, i. e. if uncertain voltage level (not VSS or VDD) is applied to input pin, there can be little current (max. 1mA at around 2V) flow. If it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. The port setting to High or Low is decided by considering its rela- tionship with external circuit. For example, if there is ex- ternal pull-up resistor then it is set to output mode, i.e. to High, and if there is external pull-down register, it is set to low.

MC80F0104/0204 Preliminary 96 Mar. 2005 Ver 0.2 20. RESET The MC80F0104/0204 supports various kinds of reset as below.

• Power-On Reset (POR)
• RESET (external reset circuitry)
• Watchdog Timer Timeout Reset
• Power-Fail Detection (PFD) Reset
• Address Fail Reset Figure 20-1 RESET Block Diagram The on-chip POR circuit holds down the device in RESET until VDD has reached a high enough level for proper op- eration. It will eliminate external components such as reset IC or external resistor and capacitor for external reset cir- cuit. In addition that the RESET pin can be used to normal input port R35 by setting “POR” and “R35EN” bit Config- uration Area(20FFH) in the Flash programming. When the device starts normal operati on, its operating parmeters (voltage, frequency, temperature...etc) must be met. .Table 20-1 shows on-chip hardware initialization by reset action. Table 20-1 Initializing Internal Status by Reset Action The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, within the operating voltage range and oscillation stable, it is applied, and the internal state is initialized. After reset, 65.5ms (at

4 MHz) add with 7 oscillator periods are required to start

execution as shown in Figure 20-2 . Internal RAM is not affected by reset. When V DD is turned on, the RAM content is inde terminate. Therefore, this RAM should be initialized before read or tested it. When the RESET pin input goes to high, the reset opera- tion is released and the program execution starts at the vec- tor address stored at addresses FFFEH - FFFFH. A connection for simple power-on-reset is shown in Figure 20-1 . POR (Power-On Reset) Address Fail reset PFD (Power-Fail Detection) WDT (WDT Timeout Reset) S R Q BIT Internal RESET RESET Clear Overflow Noise Canceller On-chip Hardware Initial Value On-chip Hardware Initial Value Program counter (PC) (FFFFH) - (FFFEH) Peripheral clock Off RAM page register (RPR) 0 Watchdog timer Disable G-flag (G) 0 Control registers Refer to Table 8-1 on page 25 Operation mode Main-frequency cl ock Power fail detector Disable

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 99 Figure 21-3 Power Fail Processor Situations (at 4MHz operation) Internal RESET Internal RESET Internal RESET VDD VDD VDD VPFDMAX VPFDMIN VPFDMAX VPFDMIN VPFDMAX VPFDMIN 65.5mS 65.5mS t < 65.5mS 65.5mS When PFDM = 1

MC80F0104/0204 Preliminary 100 Mar. 2005 Ver 0.2 22. COUNTERMEASURE OF NOISE

22.1 Oscillation Noise Protector

The Oscillation Noise Protector (ONP) is used to supply stable internal system clock by excluding the noise which could be entered into oscillator and recovery the oscillation fail. This function could be enabled or disabled by the “ONP” bit of the Device configuration area (20FF H) for the MC80F0204, “ONP” option bits MASK option. The ONP function is like below. - Recovery the oscillation wave crushed or loss caused by high frequency noise. - Change system clock to the internal oscillation clock when the high frequency noise is continuing. - Change system clock to the internal oscillation clock when the X IN/XOUT is shorted or opened, the main oscillation is stopped except by stop instruction and the low frequency noise is entered. Figure 22-1 Block Diagram of ONP & OFP and Respective Wave Forms LF Noise HF Noise CancellerHF Noise Observer Mux CLK ChangerInternal OSC OFP OFP o/f CKPS10 FINTERNAL INT_CLK XIN_NF XIN ONP IN4(2)MCLK(XO) (8-Bit counter) en ONP OFP en en S S ONPb = 0 LF_on = 1 IN_CLK = 0 CLK_CHG XIN_NF INT_CLK reset INT_CLK OFP_EN CHG_END CLK_CHG fINTERNAL ~~ ~~ High Frq. Noise XIN ~~ Noise Cancel INT_CLK 8 periods (250ns × 8 =2us) Low Frq. Noise or Oscillation Fail Clock Change Start(XIN to INT_CLK) PS10(INT_CLK/512) 256 periods (250ns × 512 × 256 =33 ms) Clock Change End(INT_CLK to XIN)) Observer

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 101

22.2 Oscillation Fail Processor

The oscillation fail processor (OFP) can change the clock source from external to intern al oscillator when the oscil- lation fail occured. This function could be enabled or dis- abled by the “OFP” bit of the Device Configuration Area (MASK option for MC80C0104/0204). And this function can recove r the external clock source when the external clock is recovered to normal state. IN4(2)MCLK/CLKXO(XO) Option The “IN4MCLK(XO)”, “IN2MCLK(XO)” bit of the De- vice Configuration Area (MASK option for MC80C0104/ 0204) enables the function to operate the device by using the internal oscillator clock in ONP block as system clock. There is no need to connect the x-tal, resonator, RC and R externally. The user on ly to connect the X IN pin to V DD. After selecting the this option, the period of internal oscil- lator clock could be checked by X OUT outputting clock di- vided the internal oscillator clock by 4.

MC80F0104/0204 Preliminary 102 Mar. 2005 Ver 0.2 23. Device Configuration Area The Device Configuration Area can be programmed or left unprogrammed to select de vice configuration such as POR, ONP, CLK option and secu rity bit. This area is not accessible during normal execu tion but is readable and writable during FLASH program / verify mode. Figure 23-1 Device Configuration Area 76543210 INITIAL VALUE: 00H ADDRESS: 20FFHConfiguration Option Bits Oscillation confuguration 000 : IN4MCLK (Internal 4MHz Oscillation & R33/R34 Enable) 001 : IN2MCLK (Internal 2MHz Oscillation & R33/R34 Enable) CLK2ONP OFP LOCK POR R35EN CLK1 CLK0 010 : EXRC (External R/RC Oscillation & R34 Enable) 011 : X-tal (Crystal or Resonator Oscillation) 100 : IN4MCLKXO (internal 4MHz Oscillation & R33 Enable & XOUT = f SYS ÷ 4) 101 : IN2MCLKXO (internal 2MHz Oscillation & R33 Enable & XOUT = fSYS ÷ 4) 110 : EXRCXO (External R/RC Oscillation & XOUT = fSYS ÷ 4) 111 : Prohibited RESET/R35 Port configuration 0 : R35 Port Disable (Use RESET) 1 : R35 Port Ensable (Disable RESET) POR Use 0 : Disable POR Reset 1 : Ensable POR Reset Security Bit 0 : Enable reading User Code 1 : Disable reading User Code OFP use 0 : Disable OFP (Clock Changer) 1 : Enable OFP (Clock Changer) ONP disable 0 : Enable ONP (Enable OFP, Internal 4MHz/2MHz oscillation) 1 : Disable ONP (Disable OFP, Internal 4MHz/2MHz oscillation)

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 103 24. MASK Option (MC80C0104/0204) The MC80C0104/0204 has several MASK option which configures the package type or use of some special features of the device. The Mask option of the MASK order sheet should be checked to select device configuration such as package type, Oscillation selection, oscillation noise pro- tector, oscillation fail protector, internal 4MHz, amount of noise to be cancelled. Table 24-1 MASK options Option Check Operation Remark MASK Option Package

16 PDIP 16PDIP type package select This option is valid only for the

MC80C010416SOP 16SOP type package select ONP Yes ONP Enable OSC Noise Protector (ONP) Operation En/Disable BitNo ONP Disable OFP Yes Enables Oscillation Fail Processor (ONP clock changer) Change the Inter clock when oscillation failed No Disables Oscillation Fail Processor (ONP clock changer ) POR Yes Enables POR To select Power-on Reset No Disables POR R35EN Yes R35 port Enable (Disable RESET ) To use R35 port as normal input portNo R35 port Disable (Use RESET ) CLK option Crystal Crystal Oscillation To select Oscillation Type EXRC External R/RC oscillation & R33 Enable IN4MCLK Internal 4MHz Oscillation & R33/R34 Enable IN2MCLK Internal 2MHz Oscillation & R33/R34 Enable EXRCXO External R/RC oscillation & R33 Enable X OUT Pin : System clock ÷ 4 IN4MCLKXO Internal 4MHz Oscillation & R33 Enable XOUT Pin : System clock ÷ 4 IN2MCLKXO Internal 2MHz Oscillation & R33 Enable XOUT Pin : System clock ÷ 4

MC80F0104/0204 Preliminary 104 Mar. 2005 Ver 0.2 25. Emulator EVA. Board Setting

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 105 DIP Switch and VR Setting Before execute the user program, keep in your mind the be- low configuration DIP S/W, VR Description ON/OFF Setting - This connector is only used for a device over 32 PIN. For the MC80F0104/0204. - This connector is only used for a device under 32 PIN. For the MC80F0208/0216/0224. SW2 Eva. select switch Must be OFF position. ON : For the MC80F0208/0216/0224. OFF : For the MC80F0104/0204. AVDD pin select switch These switches select the AVDD source. ON & OFF : Use Eva. VDD OFF & ON : Use User AVDD 4 This switch select the /Reset source. Normally OFF. EVA. chip can be reset by external user tar- get board. ON : Reset is available by either user target system board or Emulator RESET switch. OFF : Reset the MCU by Emulator RESET switch. Does not work from user target board. 5 This switch select the Xout signal on/off. Normally OFF. MCU XOUT pin is disconnected internally in the Emulator. Some circumstance user may connect this circuit. ON : Output XOUT signal OFF : Disconnect circuit SW3 1 This switch select Eva. B/D Power supply source. Normally MDS. This switch select Eva. B/D Power supply source. SW4 1 This switch select the R22 or SX OUT. This switch select the R21 or SXIN. These switchs select the Normal I/O port (off) or Sub-Clock (on). It is reserved for the MC80F0448. ON : SXOUT, SXIN OFF : R22, R21 Don’t care. OFF ON OFF OFF ON Use Eva. VDD Use User’s VDD Use MDS Power MDS USER MDS USER Use User’s Power

MC80F0104/0204 Preliminary 106 Mar. 2005 Ver 0.2 SW5 (switch 1 & 2) These switches select the R33 or X IN (switch 3 & 4) These switches select the R34 or XOUT (switch 5 & 6) These switches select the R35 or /Reset This switch select the Normal I/O port (off) or special function select (on). ON & OFF : R33,R34,R35 Port selected. OFF & ON : X IN, XOUT, /Reset selected. - This is External oscillation socket (CAN Type. OSC) This is for External Clock (CAN Type. OSC). DIP S/W, VR Description ON/OFF Setting

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 107 26. IN-SYSTEM PROGRAMMING (ISP)

26.1 Getting Started / Installation

The following section details the procedure for accomplishing the installation procedure. 1. Connect the serial(RS-232 C) cable between a target board and the COM port of your PC. 2. Configure the COM port of your PC as following. 3. Turn your target B/D power switch ON. Your target B/ D must be configured to enter the ISP mode. 4. Run the MagnaChip ISP software. 5. Press the Reset Button in the ISP S/W. If the status win- dows shows a message as "Connected", all the condi- tions for ISP are provided.

26.2 Basic ISP S/W Information

Baudrate 115,200 Data bit 8 Parity No Stop bit 1 Flow control No

MC80F0104/0204 Preliminary 108 Mar. 2005 Ver 0.2 Function Description Load HEX File Load the data from the selected file storage into the memory buffer. Save HEX File Save the current data in your memory buff er to a disk storage by using the Intel Motorolla HEX format. Erase Erase the data in your target MCU before programming it. Blank Check Verify whether or not a device is in an erased or unprogrammed state. Program This button enables you to place new data fr om the memory buffer into the target device. Read Read the data in the target MCU into the buffer for examination. The checksum will be displayed on the checksum box. Verify Assures that data in the device matches data in the memory buffer. If your device is secured, a verification error is detected. Option Write Progam the configuration data of target MCU. The security locking is performed with this button. Option Set the configuration data of target MCU. The security locking is set with this button. AUTO Erase & Program & Verify. Auto Option Write If selected with check mark, the option write is performed after erasure and write. Edit Buffer Modify the data in the selected address in your buffer memory Fill Buffer Fill the selected area with a data. Goto Display the selected page. OSC. ______ MHz Enter your target system’s oscillator value with discarding below point. Checksum Display the checksum(Hexdecimal) after reading the target device. Com Port Select serial port. Baud Rate Select UART baud rate. Select Device Sele ct target device. Page Up Key Display the previous page of your memory buffer. Page Down Key Display the higher page than the current location. Table 26-1 ISP Function Description

Preliminary MC80F0104/0204 Mar. 2005 Ver 0.2 109

26.3 Hardware Conditions to Enter the ISP Mode

The In-System Programming (IS P) is performed without removing the microcontroller from the system. The In- System Programming (ISP) facility consists of a series of internal hardware resources coupled with internal firm- ware through the serial port. The In-System Programming (ISP) facility has made in-circuit programming in an em- bedded application possible with a minimum of additional expense in components and circuit board area. The boot loader can be executed by holding ALE high, RESET /VPP as +9V, and ACLK with the OSC. 1.8432MHz. The ISP function uses five pins: TxD, RxD, ALE, ACLK and RE- SET/VPP. Note: Considerations to implement ISP function in a user target board

• The ACLK must be connected to the specifed oscillator.
• Connect the +9V to RESET/Vpp pin directly.
• T h e A L E pin must be pulled high.
• The main clk must be higher than 2MHz. VDD RESET XIN XOUT VSS R05 / TxD R04 / RxD R05 / ACLK R10 ISP Configuration High(1) VDD(+5V) +9VALE RESET / VPP 12 0 MC80F0204 X-TAL 2MHz~12MHz MCU_TxD MCU_RxD ACLK_CLK

MC80F0104/0204 Preliminary 110 Mar. 2005 Ver 0.2

26.4 Reference ISP Circuit Diagram and MagnaChip Supplied ISP Board

The ISP software and hardware circuit diagram are provided at www.magnachipmcu.com . To get a ISP B/D, contact to sales de- partment. The following circuit diagram is for reference use.. Figure 26-1 Reference ISP Circuit Diagram Figure 26-2 MagnaChip supplied ISP Board T1IN T2IN R1OUT R2OUT C1+ C1- C2+ C2- T1OUT T2OUT R1IN R2IN VCC GND CON1 Female DB9 VSS VDD External VDD RESET/VPP MCU_TxD MCU_RxD VDD VSS 10uF/16V 0.1uF MAX232 ACLK_CLK Vcc Out Gnd OSC 1.8432MHz 22Ω0.1uF 100Ω The ragne of VDD must be from 4.5 to 5.5V and ISP function is not supported under 2MHz system clock. If the user supplied VDD is out of range, the external power is needed instead of the target system VDD. VDD(+5V) VSS VDD(+5V) VSS V SSVSS VSS VDD(+5V) 61uF 1uF 0.1uF 1uF 1uF * VPP : VDD + 4V To PC To MCU GND TxD RxD + + For the ISP operation, power consumption required is minimum 30mA. VDD VSS DTR VSS VSS 10uF 100Ω 1.2kΩ 10kΩ 10kΩ 2Ν2907

Mar. 2005 Ver 0.2 i MC80F0104/0204 Preliminary A. INSTRUCTION MAP LOW HIGH 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 000 - SET1 dp.bit BBS A.bit,rel BBS dp.bit,rel ADC #imm ADC dp ADC dp+X ADC !abs ASL A ASL dp TCALL SETA1 .bit BIT dp POP A PUSH A BRK

001 CLRC SBC

#imm SBC dp SBC dp+X SBC !abs ROL A ROL dp TCALL CLRA1 .bit COM dp POP X PUSH X BRA rel

010 CLRG CMP

#imm CMP dp CMP dp+X CMP !abs LSR A LSR dp TCALL NOT1 M.bit TST dp POP Y PUSH Y PCALL Upage

011 DI OR

#imm OR dp OR dp+X OR !abs ROR A ROR dp TCALL OR1 OR1B CMPX dp POP PSW PUSH PSW RET

100 CLRV AND

#imm AND dp AND dp+X AND !abs INC A INC dp TCALL AND1 AND1B CMPY dp CBNE dp+X TXSP INC X

101 SETC EOR

#imm EOR dp EOR dp+X EOR !abs DEC A DEC dp TCALL EOR1 EOR1B DBNE dp XMA dp+X TSPX DEC X

110 SETG LDA

#imm LDA dp LDA dp+X LDA !abs TXA LDY dp TCALL LDC LDCB LDX dp LDX dp+Y XCN DAS

111 EI LDM

dp,#imm STA dp STA dp+X STA !abs TAX STY dp TCALL STC M.bit STX dp STX dp+Y XAX STOP LOW HIGH 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111

000 BPL

dp.bit BBC A.bit,rel BBC dp.bit,rel ADC {X} ADC !abs+Y ADC [dp+X] ADC [dp]+Y ASL !abs ASL dp+X TCALL JMP !abs BIT !abs ADDW dp LDX #imm JMP [!abs]

001 BVC

{X} SBC !abs+Y SBC [dp+X] SBC [dp]+Y ROL !abs ROL dp+X TCALL CALL !abs TEST !abs SUBW dp LDY #imm JMP [dp]

010 BCC

{X} CMP !abs+Y CMP [dp+X] CMP [dp]+Y LSR !abs LSR dp+X TCALL

5 MUL TCLR1

!abs CMPW dp CMPX #imm CALL [dp]

011 BNE

{X} OR !abs+Y OR [dp+X] OR [dp]+Y ROR !abs ROR dp+X TCALL DBNE Y CMPX !abs LDYA dp CMPY #imm RETI

100 BMI

{X} AND !abs+Y AND [dp+X] AND [dp]+Y INC !abs INC dp+X TCALL

9 DIV CMPY

!abs INCW dp INC Y TAY

101 BVS

{X} EOR !abs+Y EOR [dp+X] EOR [dp]+Y DEC !abs DEC dp+X TCALL XMA {X} XMA dp DECW dp DEC Y TYA

110 BCS

{X} LDA !abs+Y LDA [dp+X] LDA [dp]+Y LDY !abs LDY dp+X TCALL LDA {X}+ LDX !abs STYA dp XAY DAA

111 BEQ

{X} STA !abs+Y STA [dp+X] STA [dp]+Y STY !abs STY dp+X TCALL STA {X}+ STX !abs CBNE dp XYX NOP

ii Mar. 2005 Ver 0.2 MC80F0104/0204 Preliminary B. INSTRUCTION SET 1. ARITHMETIC/ LOGIC OPERATION NO. MNEMONIC OP CODE BYTE NO CYCLE NO OPERATION FLAG NVGBHIZC 1 ADC #imm 04 2 2 Add with carry. 2A D C d p 0 5 2 3 A ← ( A ) + ( M ) + C

3 ADC dp + X 06 2 4

4 ADC !abs 07 3 4 NV--H-ZC 5 ADC !abs + Y 15 3 5

6 ADC [ dp + X ] 16 2 6

7 ADC [ dp ] + Y 17 2 6

8A D C { X } 1 4 1 3

9 AND #imm 84 2 2 Logical AND

10 AND dp 85 2 3 A ← ( A ) ∧ ( M )

11 AND dp + X 86 2 4

12 AND !abs 87 3 4 N-----Z- 13 AND !abs + Y 95 3 5

14 AND [ dp + X ] 96 2 6

15 AND [ dp ] + Y 97 2 6

16 AND { X } 94 1 3

17 ASL A 08 1 2 Arithmetic shift left

18 ASL dp 09 2 4 N-----ZC

19 ASL dp + X 19 2 5

20 ASL !abs 18 3 5

21 CMP #imm 44 2 2 Compare accumulator contents with memory contents

22 CMP dp 45 2 3 ( A ) - ( M )

23 CMP dp + X 46 2 4

24 CMP !abs 47 3 4 N-----ZC 25 CMP !abs + Y 55 3 5

26 CMP [ dp + X ] 56 2 6

27 CMP [ dp ] + Y 57 2 6

28 CMP { X } 54 1 3

29 CMPX #imm 5E 2 2 Compare X contents with memory contents

30 CMPX dp 6C 2 3 ( X ) - ( M ) N-----ZC

31 CMPX !abs 7C 3 4

32 CMPY #imm 7E 2 2 Compare Y contents with memory contents

33 CMPY dp 8C 2 3 ( Y ) - ( M ) N-----ZC

34 CMPY !abs 9C 3 4

35 COM dp 2C 2 4 1’S Complement : ( dp ) ← ~( dp ) N-----Z-

36 DAA DF 1 3 Decimal adjust for addition N-----ZC

37 DAS CF 1 3 Decimal adjust for subtraction N-----ZC

38 DEC A A8 1 2 Decrement N-----Z-

39 DEC dp A9 2 4 M ← ( M ) - 1

40 DEC dp + X B9 2 5 N-----Z-

41 DEC !abs B8 3 5

42 DEC X AF 1 2

43 DEC Y BE 1 2

44 DIV 9B 1 12 Divide : YA / X Q: A, R: Y NV--H-Z-

“0” C 7654321

Mar. 2005 Ver 0.2 iii MC80F0104/0204 Preliminary NO. MNEMONIC OP CODE BYTE NO CYCLE NO OPERATION FLAG NVGBHIZC

45 EOR #imm A4 2 2 Exclusive OR

46 EOR dp A5 2 3 A ← ( A ) ⊕ ( M )

47 EOR dp + X A6 2 4

48 EOR !abs A7 3 4 N-----Z- 49 EOR !abs + Y B5 3 5

50 EOR [ dp + X ] B6 2 6

51 EOR [ dp ] + Y B7 2 6

52 EOR { X } B4 1 3

53 INC A 88 1 2 Increment N-----Z-

54 INC dp 89 2 4 M ← ( M ) + 1

55 INC dp + X 99 2 5 N-----Z-

56 INC !abs 98 3 5

57 INC X 8F 1 2

58 INC Y 9E 1 2

59 LSR A 48 1 2 Logical shift right

60 LSR dp 49 2 4 N-----ZC

61 LSR dp + X 59 2 5

62 LSR !abs 58 3 5

63 MUL 5B 1 9 Multiply : YA ← Y × A N-----Z-

64 OR #imm 64 2 2 Logical OR

65 OR dp 65 2 3 A ← ( A ) ∨ ( M )

66 OR dp + X 66 2 4

67 OR !abs 67 3 4 N-----Z- 68 OR !abs + Y 75 3 5

69 OR [ dp + X ] 76 2 6

70 OR [ dp ] + Y 77 2 6

71 OR { X } 74 1 3

72 ROL A 28 1 2 Rotate left through carry

73 ROL dp 29 2 4 N-----ZC

74 ROL dp + X 39 2 5

75 ROL !abs 38 3 5

76 ROR A 68 1 2 Rotate right through carry

77 ROR dp 69 2 4 N-----ZC

78 ROR dp + X 79 2 5

79 ROR !abs 78 3 5

80 SBC #imm 24 2 2 Subtract with carry

81 SBC dp 25 2 3 A ← ( A ) - ( M ) - ~( C )

82 SBC dp + X 26 2 4

83 SBC !abs 27 3 4 NV--HZC 84 SBC !abs + Y 35 3 5

85 SBC [ dp + X ] 36 2 6

86 SBC [ dp ] + Y 37 2 6

87 SBC { X } 34 1 3

88 TST dp 4C 2 3 Test memory contents for negative or zero

( dp ) - 00 H N-----Z-

89 XCN CE 1 5 Exchange nibbles within the accumulator

A7~A4 ↔ A3~A0 N-----Z- “0” C7654321 0C 7654321 0C7654321

iv Mar. 2005 Ver 0.2 MC80F0104/0204 Preliminary 2. REGISTER / MEMORY OPERATION NO. MNEMONIC OP CODE BYTE NO CYCLE NO OPERATION FLAG NVGBHIZC

1 LDA #imm C4 2 2 Load accumulator

2 LDA dp C5 2 3 A ← ( M )

3 LDA dp + X C6 2 4

4 LDA !abs C7 3 4 5 LDA !abs + Y D5 3 5 N-----Z-

6 LDA [ dp + X ] D6 2 6

7 LDA [ dp ] + Y D7 2 6

8L D A { X } D 4 1 3

9 LDA { X }+ DB 1 4 X- register auto-increment : A ← ( M ) , X ← X + 1

11 LDX #imm 1E 2 2 Load X-register

12 LDX dp CC 2 3 X ← ( M ) N-----Z-

13 LDX dp + Y CD 2 4

14 LDX !abs DC 3 4

15 LDY #imm 3E 2 2 Load Y-register

16 LDY dp C9 2 3 Y ← ( M ) N-----Z-

17 LDY dp + X D9 2 4

18 LDY !abs D8 3 4

19 STA dp E5 2 4 Store accumulator contents in memory

20 STA dp + X E6 2 5 ( M ) ← A

21 STA !abs E7 3 5

23 STA [ dp + X ] F6 2 7

24 STA [ dp ] + Y F7 2 7

25 STA { X } F4 1 4

26 STA { X }+ FB 1 4 X- register auto-increment : ( M ) ← A, X ← X + 1

27 STX dp EC 2 4 Store X-register contents in memory

29 STX !abs FC 3 5

30 STY dp E9 2 4 Store Y-register contents in memory

32 STY !abs F8 3 5

33 TAX E8 1 2 Transfer accumulator contents to X-register : X ← A N-----Z-

34 TAY 9F 1 2 Transfer accumulator contents to Y-register : Y ← A N-----Z-

35 TSPX AE 1 2 Transfer stack-pointer contents to X-register : X ← sp N-----Z-

36 TXA C8 1 2 Transfer X-register contents to accumulator: A ← X N-----Z-

37 TXSP 8E 1 2 Transfer X-register contents to stack-pointer: sp ← X N-----Z-

38 TYA BF 1 2 Transfer Y-register contents to accumulator: A ← Y N-----Z-

41 XMA dp BC 2 5 Exchange memory contents with accumulator

42 XMA dp+X AD 2 6 ( M ) ↔ A N-----Z-

43 XMA {X} BB 1 5

Mar. 2005 Ver 0.2 v MC80F0104/0204 Preliminary 3. 16-BIT OPERATION 4. BIT MANIPULATION NO. MNEMONIC OP CODE BYTE NO CYCLE NO OPERATION FLAG NVGBHIZC 1A D D W d p 1 D 2 5 16-Bits add without carry YA ← ( YA ) + ( dp +1 ) ( dp ) NV--H-ZC 2C M P W d p 5 D 2 4 Compare YA contents with memory pair contents : (YA) − (dp+1)(dp) N-----ZC

3 DECW dp BD 2 6 Decrement memory pair

4 INCW dp 9D 2 6 Increment memory pair

5L D Y A d p 7 D 2 5 Load YA YA ← ( dp +1 ) ( dp ) N-----Z- 6S T Y A d p D D 2 5 Store YA 7S U B W d p 3 D 2 5 16-Bits substact without carry YA ← ( YA ) - ( dp +1) ( dp) NV--H-ZC NO. MNEMONIC OP CODE BYTE NO CYCLE NO OPERATION FLAG NVGBHIZC

3 BIT dp 0C 2 4 Bit test A with memory : MM----Z-

4 BIT !abs 1C 3 5 Z ← ( A ) ∧ ( M ) , N ← ( M7 ) , V ← ( M6 )

8 CLRG 40 1 2 Clear G-flag : G ← “0” --0-----

9 CLRV 80 1 2 Clear V-flag : V ← “0” -0--0---

20 SETG C0 1 2 Set G-flag : G ← “1” --1-----

22 TCLR1 !abs 5C 3 6 Test and clear bits with A : 23 TSET1 !abs 3C 3 6 Test and set bits with A :

vi Mar. 2005 Ver 0.2 MC80F0104/0204 Preliminary 5. BRANCH / JUMP OPERATION NO. MNEMONIC OP CODE BYTE NO CYCLE NO OPERATION FLAG NVGBHIZC 2 BBC dp.bit,rel y3 3 5/7 if ( bit ) = 0 , then pc ← ( pc ) + rel 4 BBS dp.bit,rel x3 3 5/7 if ( bit ) = 1 , then pc ← ( pc ) + rel

5 BCC rel 50 2 2/4 Branch if carry bit clear

6 BCS rel D0 2 2/4 Branch if carry bit set

7 BEQ rel F0 2 2/4 Branch if equal

8 BMI rel 90 2 2/4 Branch if minus

9 BNE rel 70 2 2/4 Branch if not equal

10 BPL rel 10 2 2/4 Branch if minus

11 BRA rel 2F 2 4 Branch always

12 BVC rel 30 2 2/4 Branch if overflow bit clear

13 BVS rel B0 2 2/4 Branch if overflow bit set

14 CALL !abs 3B 3 8 Subroutine call

15 CALL [dp] 5F 2 8 M( sp)←( pcH ), sp←sp - 1, M(sp)← (pcL), sp ←sp - 1,

17 CBNE dp+X,rel 8D 3 6/8 if ( A ) ≠ ( M ) , then pc ← ( pc ) + rel. 19 DBNE Y ,rel 7B 2 4/6 if ( M ) ≠ 0 , then pc ← ( pc ) + rel. 20 JMP !abs 1B 3 3 Unconditional jump

22 JMP [dp] 3F 2 4

23 PCALL upage 4F 2 6

M(sp) ←( pcH ), sp ←sp - 1, M(sp) ← ( pcL ), sp ← sp - 1, pcL ← ( upage ), pcH ← ”0FFH” .

24 TCALL n nA 1 8

Table call : (sp) ←( pcH ), sp ← sp - 1, M(sp) ← ( pcL ),sp ← sp - 1, pcL ← (Table vector L), pcH ← (Table vector H)

Mar. 2005 Ver 0.2 vii MC80F0104/0204 Preliminary 6. CONTROL OPERATION & etc. NO. MNEMONIC OP CODE BYTE NO CYCLE NO OPERATION FLAG NVGBHIZC

1 BRK 0F 1 8

Software interrupt : B ← ”1”, M(sp) ← (pcH), sp ←sp-1, M(s) ← (pcL), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1, pcL ← ( 0FFDEH ) , pcH ← ( 0FFDFH) . ---1-0--

2 DI 60 1 3 Disable interrupts : I ← “0” -----0--

3 EI E0 1 3 Enable interrupts : I ← “1” -----1--

5 POP A 0D 1 4 sp ← sp + 1, A ← M( sp )

7 POP Y 4D 1 4 sp ← sp + 1, Y ← M( sp )

8 POP PSW 6D 1 4 sp ← sp + 1, PSW ← M( sp ) restored

9 PUSH A 0E 1 4 M( sp ) ← A , sp ← sp - 1

11 PUSH Y 4E 1 4 M( sp ) ← Y , sp ← sp - 1

12 PUSH PSW 6E 1 4 M( sp ) ← PSW , sp ← sp - 1

13 RET 6F 1 5 Return from subroutine

14 RETI 7F 1 6

sp ← sp +1, PSW ← M( sp ), sp ← sp + 1, pcL ← M( sp ), sp ← sp + 1, pcH ← M( sp ) restored

viii Mar. 2005 Ver 0.2 MC80F0104/0204 Preliminary

MASK ORDER & VERIFICATION SHEET MC80C0104 - 1. Customer Information Company Name 2. Device Information 3. Marking Specification 4. Delivery Schedule Customer Sample Date YYYY MM DD Risk Order YYYY MM DD Quantity MagnaChip Confirmation Application Order Date YYYY MM DD Tel: Fax: Name & Signature: Package 16PDIP 16SOP MC80C0104x-xxx YYWW KOREA 5. ROM Code Verification Verification Date: YYYY MM DD Approval Date: YYYY MM DD Please confirm our verification data. I agree with your verification data and confirm you to make mask set. Check Sum: Tel: Fax: Name & Signature: Tel: Fax: Name & Signature: Set “00” in this area 0000H F000H FFFFH .OTP file data EFFFH Mask Data File Name: ( .OTP) (Please check mark into ) #1 index mark pcs pcs Check Sum: ( ) Customer should write inside thick line box. This box is written after “5.Verification”. POR Yes No OFP Use Yes No Notice : Unused user ROM area should be filled with “00H” ONP Use Yes No Crystal IN4M IN4MXOCLK IN2M IN2MXO EXRC EXRCXO R35 Use Yes No

MASK ORDER & VERIFICATION SHEET MC80C0204 - 1. Customer Information Company Name 2. Device Information 3. Marking Specification 4. Delivery Schedule Customer Sample Date YYYY MM DD Risk Order YYYY MM DD Quantity MagnaChip Confirmation Application Order Date YYYY MM DD Tel: Fax: Name & Signature: Package 20PDIP 20SOP MC80C0204x-xxx YYWW KOREA 5. ROM Code Verification Verification Date: YYYY MM DD Approval Date: YYYY MM DD Please confirm our verification data. I agree with your verification data and confirm you to make mask set. Check Sum: Tel: Fax: Name & Signature: Tel: Fax: Name & Signature: Set “00” in this area 0000H F000H FFFFH .OTP file data EFFFH Mask Data File Name: ( .OTP) (Please check mark into ) #1 index mark pcs pcs Check Sum: ( ) Customer should write inside thick line box. This box is written after “5.Verification”. POR Yes No OFP Use Yes No Notice : Unused user ROM area should be filled with “00H” ONP Use Yes No Crystal IN4M IN4MXOCLK IN2M IN2MXO EXRC EXRCXO R35 Use Yes No