MC7447AVU1167NB

MPC7447AEC NXP | Alldatasheet

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© Freescale Semiconductor, Inc., 2006. All rights reserved. Freescale Semiconductor Technical Data This document is primarily concerned with the PowerPC™ MPC7447A; however, unless otherwise noted, all information here also applies to the MPC7447. The MPC7447A is an implementation of the PowerPC microprocessor family of reduced instruction set computer (RISC) microprocessors. This document describes pertinent electrical and physical characteristics of the MPC7447A. For functional characteristics of the processor, refer to the MPC7450 RISC Microprocessor Family Reference Manual. To locate any published updates for this document, refer to the Freescale website located at http://www.freescale.com. 1O v e r v i e w The MPC7447A is the fifth implementation of the fourth-generation (G4) microprocessors from Freescale. The MPC7447A implements the full PowerPC 32-bit architecture and is targeted at networking and computing systems applications. The MPC7447A consists of a processor core and a 512-Kbyte L2. Figure 1 shows a block diagram of the MPC7447A. The core is a high-performance superscalar design supporting a double-precision floating-point unit and a SIMD multimedia unit. The memory storage subsystem supports the MPX bus protocol and a subset of the 60x bus protocol to main memory and other system resources. MPC7447AEC Rev. 5, 01/2006

Contents

1. Comparison with the MPC7447, MPC7445, and MPC7447A RISC Microprocessor Hardware Specifications

2 Freescale Semiconductor

Figure 1. MPC7447A Block Diagram

• Time Base Counter/Decrementer  Clock Multiplier  JTAG/COP Interface  Thermal/Power Management  Performance Monitor  Dynamic Frequency Switching (DFS)  Temperature Diode x ÷ FPSCRFPSCR PA + x ÷ Instruction Unit Instruction Queue (12-Word) 96-Bit (3 Instructions) Reservation Integer 128-Bit (4 Instructions) 32-Bit Floating- Point Unit 64-Bit Reservation Load/Store Unit (EA Calculation) Finished 32-Bit (16-Entry) Tags 32-Kbyte D Cache 36-Bit 64-Bit Integer Stations (2) Reservation Station Reservation Stations (2) FPR File

16 Rename

The Castout Queue and Push Queue share resources such that they have a combined total of 6 entries. The Castout Queue itself is limited to 9 entries, ensuring 1 entry will be available for a push.

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 3

Features

The MPC7447A is a footprint-compatible, drop-in replacement in an MPC7447 application if the core power supply is 1.3 V . 2F e a t u r e s This section summarizes features of the MPC7447A implementation of the PowerPC architecture. Major features of the MPC7447A are as follows:  High-performance, superscalar microprocessor — Up to four instructions can be fetched from the instruction cache at a time. — Up to 12 instructions can be in the instruction queue (IQ). — Up to 16 instructions can be at some stage of execution simultaneously. — Single-cycle execution for most instructions — One instruction per clock cycle throughput for most instructions — Seven-stage pipeline control  Eleven independent execution uni ts and three register files — Branch processing unit (BPU) features static and dynamic branch prediction – 128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a cache of branch instructions that have been encountered in branch/loop code sequences. If a target instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can be made available from the instruction cache. Typically, a fetch that hits the BTIC provides the first four instructions in the target stream. – 2048-entry branch history table (BHT) with 2 bits per entry for four levels of prediction—not taken, strongly not ta ken, taken, and strongly taken – Up to three outstanding speculative branches – Branch instructions that do not update the count register (CTR) or link register (LR) are often removed from the instruction stream. – Eight-entry link register stack to predict the target address of Branch Conditional to Link Register (bclr) instructions — Four integer units (IUs) that share 32 GPRs for integer operands – Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except multiply, divide, and move to/from special-purpose register instructions. – IU2 executes miscellaneous instructions including the CR logical operations, integer multiplication and division instructions, and move to/from special-purpose register instructions. — Five-stage FPU and a 32-entry FPR file – Fully IEEE 754-1985–compliant FPU for both single- and double-precision operations – Supports non-IEEE mode for time-critical operations – Hardware support for denormalized numbers – Thirty-two 64-bit FPRs for single- or double-precision operands

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

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— Four vector units and 32-entry vector register file (VRs) – V ector permute unit (VPU) – V ector integer unit 1 (VIU1) handles short-latency AltiV ec™ integer instructions, such as vector add instructions (for example, vaddsbs, vaddshs, and vaddsws). – V ector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as vector multiply add instructions (for example, vmhaddshs, vmhraddshs, and vmladduhm). – V ector floating-point unit (VFPU) — Three-stage load/store unit (LSU) – Supports integer, floating-point, and vector instruction load/store traffic – Four-entry vector touch queue (VTQ) supports all four architected AltiV ec data stream operations – 3-cycle GPR and AltiVec load latency (byt e, half word, word, vector) with 1-cycle throughput – 4-cycle FPR load latency (single, double) with 1-cycle throughput – No additional delay for misaligned access within double-word boundary – Dedicated adder calculates effective addresses (EAs) – Supports store gathering – Performs alignment, normalization, and precision conversion for floating-point data – Executes cache control and TLB instructions – Performs alignment, zero padding, and sign extension for integer data – Supports hits under misses (multiple outstanding misses) – Supports both big- and little-endian modes, including misaligned little-endian accesses  Three issue queues, FIQ, VIQ, and GIQ, can accept as many as one, two, and three instructions, respectively, in a cycle. Instruction dispatch requires the following: — Instructions can only be dispatched from the three lowest IQ entries—IQ0, IQ1, and IQ2. — A maximum of three instructions can be di spatched to the issue queues per clock cycle. — Space must be available in the CQ for an instruction to dispatch. (This includes instructions that are assigned a space in the CQ but not in an issue queue.)  Rename buffers — 16 GPR rename buffers — 16 FPR rename buffers — 16 VR rename buffers  Dispatch unit — Decode/dispatch stage fully decodes each instruction  Completion unit — The completion unit retires an instruction from the 16-entry completion queue (CQ) when all instructions ahead of it have been completed, the instruction has finished execution, and no exceptions are pending.

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 5 — Guarantees sequential programming model (precise exception model) — Monitors all dispatched instructions and retires them in order — Tracks unresolved branches and flushes instructions after a mispredicted branch — Retires as many as three instructions per clock cycle  Separate on-chip L1 instruction and data caches (Harvard architecture) — 32-Kbyte, eight-way set-associative instruction and data caches — Pseudo least-recently-used (PLRU) replacement algorithm — 32-byte (eight-word) L1 cache block — Physically indexed/physical tags — Cache write-back or write-through operation progr ammable on a per-page or per-block basis — Instruction cache can provide four instructions per clock cycle; data cache can provide four words per clock cycle — Caches can be disabled in software. — Caches can be locked in software. — MESI data cache coherency maintained in hardware — Separate copy of data cache tags for efficient snooping — Parity support on cache and tags — No snooping of instruction cache except for icbi instruction — Data cache supports AltiVec LRU and transient instructions — Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word forwarding is used for AltiV ec loads and instruction fetches. Other accesses use critical double-word forwarding.  Level 2 (L2) cache interface — On-chip, 512-Kbyte, eight-way set-associative unified instruction and data cache — Fully pipelined to provide 32 bytes per clock cycle to the L1 caches — A total 9-cycle load latency for an L1 data cache miss that hits in L2 — Cache write-back or write-through operation progr ammable on a per-page or per-block basis — 64-byte, two-sectored line size — Parity support on cache  Separate memory management units (MMUs) for instructions and data — 52-bit virtual address, 32- or 36-bit physical address — Address translation for 4-Kbyte pages, va riable-sized blocks, and 256-Mbyte segments — Memory programmable as write-back/write-thr ough, caching-inhibited/caching-allowed, and memory coherency enforced/memory coherency not enforced on a page or block basis — Separate IBATs and DBA Ts (eight each) also defined as SPRs — Separate instruction and data translation lookaside buffers (TLBs) – Both TLBs are 128-entry, two-way set-associative, and use an LRU replacement algorithm.

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

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– TLBs are hardware- or software-reloadable (tha t is, a page table search is performed in hardware or by system software on a TLB miss).  Efficient data flow — Although the VR/LSU interface is 128 bits, the L1/L2 bus interface allows up to 256 bits. — The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs. — The L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1 cache. — As many as eight outstanding out-of-order cache misses are allowed between the L1 data cache and the L2 bus. — As many as 16 out-of-order transactions can be present on the MPX bus. — Store merging for multiple store misses to the same line. Only coherency action taken (address-only) for store misses merged to all 32 bytes of a cache block (no data tenure needed). — Three-entry finished store queue and five-ent ry completed store queue between the LSU and the L1 data cache — Separate additional queues for efficient bu ffering of outbound data (such as castouts and write-through stores) from the L1 data cache and L2 cache  Multiprocessing support features include the following: — Hardware-enforced, MESI cache coherency protocols for data cache — Load/store with reservation instruction pair for atomic memory references, semaphores, and other multiprocessor operations  Power and thermal management — A new dynamic frequency switching (DFS) featur e allows processor core frequency to be halved through software to reduce power consumption. — The following three power-saving modes are available to the system: – Nap—Instruction fetching is halted. Only the clocks for the time base, decrementer, and JTAG logic remain running. The part goes into the doze state to snoop memory operations on the bus and then back to nap using a QREQ /QACK processor-system handshake protocol. – Sleep—Power consumption is further reduced by disabling bus snooping, leaving only the PLL in a locked and running state. All internal functional units are disabled. – Deep sleep—When the part is in the sleep state, the system can disable the PLL. The system can then disable the SYSCLK source for greater system power savings. Power-on reset procedures for restarting and relocking the PLL must be followed upon exiting the deep sleep state. — Instruction cache throttling provides control of instruction fetching to limit device temperature. — A new temperature diode can determine the temperature of the microprocessor. — Support for core voltage derating to further reduce power consumption  Performance monitor can be used to help debug system designs and improve software efficiency.  In-system testability and debugging features through JTAG boundary-scan capability  Testability — LSSD scan design

3 Comparison with the MPC7447, MPC7445, and

Table 1. Microarchitecture Comparison

8 Freescale Semiconductor

Table 1. Microarchitecture Comparison (continued)

4 General Parameters

1.2 V ± 50 mV DC (derated)

2.5 V ± 5% DC

5 Electrical and Thermal Characteristics

5.1 DC Electrical Characteristics

Table 2. Absolute Maximum Ratings 1

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Figure 2 shows the undershoot and overshoot voltage on the MPC7447A. Figure 2. Overshoot/Undershoot Voltage

1. Functional and tested operating conditions are given in Ta ble 4. Absolute maximum ratings are stress ratings only, and

permanent damage to the device. maximum of 20 ms during the power-on reset and power-down sequences.

1. Caution: OVDD must not exceed VDD/AVDD by more than 2.0 V during normal operation; this limit may be exceeded for a

maximum of 20 ms during the power-on reset and power-down sequences.

1. BVSEL must be set to 0, such that the bus is in 1.8-V mode.
2. BVSEL must be set to HRESET

or 1, such that the bus is in 2.5-V mode.

1. Caution: Vin must not exceed OVDD by more than 0.3 V at any time including during power-on reset.
2. Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.

Table 2. Absolute Maximum Ratings 1 (continued)

Table 4 provides the recommended operating conditions for the MPC7447A. Table 5 provides the package thermal characteristics for the MPC7447A. Table 3. Input Threshold Voltage Settings

1. Caution: The input threshold selection must agree with the OV DD voltages supplied. See notes in Ta ble 2.
2. If used, pull-down resistors should be less than 250 Ω.

Table 4. Recommended Operating Conditions 1

1. These are the recommended and tested operating conditions. In addition, these devices also support voltage

and those specified in Section 5.3 is not guaranteed.

1. This voltage is the input to the filter discussed in Section 9.2, “PLL Power Supply Filtering,” and not necessarily the

voltage at the AVDD pin, which may be reduced from V DD by the filter.

1. VDD and AVDD may be reduced in order to reduce power consumption if further maximum core frequency

constraints are observed. See Section 5.3, “Voltage and Frequency Derating,” for specific information. Table 5. Package Thermal Characteristics 1

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Table 6 provides the DC electrical characteristics for the MPC7447A.

1. Refer to Section 9.8, “Thermal Management Information,” for details about thermal management.
2. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance.

1. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
2. Per JEDEC JESD51-6 with the board horizontal.
3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

1. This is the thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

θJC for the part is less than 0.1°C/W. Table 6. DC Electrical Specifications At recommended operating conditions. See Table 4. Table 5. Package Thermal Characteristics 1 (continued)

1. Nominal voltages; see Table 4 for recommended operating conditions.
2. For processor bus signals, the reference is OVDD
3. Excludes test signals and IEEE 1149.1 boundary scan (JTAG) signals
4. The leakage is measured for nominal OV

example, both OVDD and VDD vary by either +5% or –5%).

1. Capacitance is periodically sampled rather than 100% tested.
2. Excludes signals with internal pullups: BVSEL, LSSD_MODE

Table 7. Power Consumption for MPC7447A Table 6. DC Electrical Specifications (continued) At recommended operating conditions. See Table 4.

14 Freescale Semiconductor

5.2 AC Electrical Characteristics

5.2.1 Clock AC Specifications

forth, and may be less than the value given in Table 8.

1. These values specify the power consumption for the core power supply (V DD) at nominal voltage and apply

case power consumption for AVDD < 3 mW.

1. Typical power is an average value measured at the nominal recommended VDD (see Ta ble 4) and 65°C while

running the Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz.

1. Maximum power is the average measured at nominal VDD and maximum operating junction temperature (see

execution units maximally busy.

1. Doze mode is not a user-definable state; it is an intermediate state between full-power and either nap or sleep

mode. As a result, power consumption for this mode is not tested.

1. Power consumption for these devices is artificially constrained during screening to assure lower power

consumption than other speed grades. Table 7. Power Consumption for MPC7447A (continued)

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5.2.2 Processor Bus AC Specifications

Table 9. Processor Bus AC Timing Specifications 1 At recommended operating conditions. See Table 4.

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sampled twice, once before and once after HRESET negation. Figure 5. Mode Input Sample Timing Diagram Figure 6 provides the input/output timing diagram for the MPC7447A. Figure 6. Input/Output Timing Diagram

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Figure 8 provides the JTAG clock input timing diagram. Figure 8. JTAG Clock Input Timing Diagram Figure 9 provides the TRST timing diagram. Figure 9. TRST Timing Diagram Figure 10 provides the boundary-scan timing diagram. Figure 10. Boundary-Scan Timing Diagram

Figure 11 provides the test access port timing diagram. Figure 11. Test Access Port Timing Diagram

5.3 Voltage and Frequency Derating

affected; all other parameter specifications are unaffected. Table 11. Supported Voltage, Core Frequency, and Power Consumption Derating

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6 Pin Assignments

the HCTE package to indicate the direction of the top surface view. Figure 12. Pinout of the MPC7447A, 360 HCTE Package as Viewed from the Top Surface

7 Pinout Listings

MPC7447 are unterminated as required by the MPC7457 RISC Microprocessor Hardware Specifications. Section 9.4, “Connection Recommendations,” for additional information. on a board designed for an MPC7447A but populated with an MPC7447. Table 12. Pinout Listing for the MPC7447A, 360 HCTE Package

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Table 12. Pinout Listing for the MPC7447A, 360 HCTE Package (continued)

26 Freescale Semiconductor

1. OVDD supplies power to the processor bus, JT AG, and all control signals; VDD supplies power to the processor core and the

in or supply voltages see Ta bl e 4.

1. Unused address pins must be pulled down to GND and corresponding address parity pins pulled up to OV DD.
2. These pins require weak pull-up resistors (for example, 4.7 KΩ) to maintain the control signals in the negated state after they

have been actively negated and released by the MPC7447A and other bus masters.

1. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at HRESET going
2. This signal must be negated during reset, by pull-up resistor to OV DD or negation by ¬HRESET (inverse of HRESET), to
3. These signals must be pulled down to GND if unused, or if the MPC7447A is in 60x bus mode.
4. These input signals are for factory use only and must be pulled down to GND for normal machine operation.

; however, other configurations will not adversely affect performance. NCs on the MPC7447, MPC7445, and MPC7441 have now been defined for other purposes. 12.These input signals are for factory use only and must be pulled up to OV DD for normal machine operation. 13.This pin can externally cause a performance monitor event. Counting of the event is enabled through software. , to ensure proper operation. “Connection Recommendations,” for more information. must be connected directly to OVDD or left unconnected. of the processor. These pins may be left unterminated if unused. level present inside the device package. If unused, they must be connected directly to V DD or left unconnected. voltage level present inside the device package. If unused, they must be connected directly to GND or left unconnected.

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 27 Package Description

8 Package Description

The following sections provide the package parameters and mechanical dimensions for the HCTE package.

8.1 Package Parameters for the MPC7447A, 360 HCTE BGA

The package parameters are as provided in the following list. The package type is 25 × 25 mm, 360-lead high coefficient of thermal expansion ceramic ball grid array (HCTE). Package outline 25 × 25 mm Interconnects 360 (19 × 19 ball array – 1) Pitch 1.27 mm (50 mil) Minimum module height 2.72 mm Maximum module height 3.24 mm Ball diameter 0.89 mm (35 mil) Coefficient of thermal expansion 12.3 ppm/°C

28 Freescale Semiconductor

8.2 Mechanical Dimensions for the MPC7447A, 360 HCTE BGA

Figure 13. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7447A,

1. Dimensions in millimeters.
2. Top side A1 corner index is a

a ball missing from the array.

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 29 Package Description

8.3 Package Parameters for the MPC7447A, 360 HCTE LGA

The package parameters are as provided in the following list. The package type is 25 × 25 mm, 360 high coefficient of thermal expansion ceramic land grid array (HCTE). Package outline 25 × 25 mm Interconnects 360 (19 × 19 ball array – 1) Pitch 1.27 mm (50 mil) Minimum module height 1.92 mm Maximum module height 2.20 mm Coefficient of thermal expansion 12.3 ppm/°C

30 Freescale Semiconductor

8.4 Mechanical Dimensions for the MPC7447A, 360 HCTE LGA

Figure 14. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7447A,

1. Dimensions in millimeters.
2. Top side A1 corner index is a

a pad missing from the array.

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 31 Package Description

8.5 Package Parameters for the MPC7447A, 360 HCTE

The package parameters are as provided in the following list. The package type is 25 × 25 mm, 360 lead-free high coefficient of thermal expansion ceramic ball grid array (HCTE). Package outline 25 × 25 mm Interconnects 360 (19 × 19 ball array – 1) Pitch 1.27 mm (50 mil) Minimum module height 2.32 mm Maximum module height 2.80 mm Ball diameter 0.75 mm (30 mil) Coefficient of thermal expansion 12.3 ppm/°C

32 Freescale Semiconductor

8.6 Mechanical Dimensions for the MPC7447A, 360 HCTE

Figure 15. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7447A,

360 HCTE RoHS-Compliant BGA Package

1. Dimensions in millimeters.
2. Top side A1 corner index is a

a ball missing from the array.

1. Dimension A1 represents the

8.7 Substrate Capacitors for the MPC7447A, 360 HCTE

Figure 16. Substrate Bypass Capacitors for the MPC7447A, 360 HCTE

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9 System Design Information

9.1 Clocks

9.1.1 PLL Configuration

frequency must meet the minimum core frequency requirements described in Table 8. Table 13. MPC7447A Microprocessor PLL Configuration Example for 1420-MHz Parts

Table 13. MPC7447A Microprocessor PLL Configuration Example for 1420-MHz Parts (continued)

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9.1.2 System Bus Clock (SYSCLK) and Spread Spectrum Sources

listed in Table 14 are observed.

00110 PLL bypass PLL off, SYSCLK clocks core circuitry directly

11110 PLL off PLL off, no core clocking occurs

1. Ratios below 5:1 require an AACK delay See MPC7450 RISC Microprocessor Family Reference Manual , Section
2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core,

AC Specifications,” for valid SYSCLK, core, and VCO frequencies.

1. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled.

processor is clocked at SYSCLK frequency. This mode is intended for factory use and emulator tool use only. Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.

1. In PLL-off mode, no clocking occurs inside the MPC7447A regardless of the SYSCLK input.

9.2 PLL Power Supply Filtering

Figure 17. PLL Power Supply Filter Circuit

9.3 Decoupling Recommendations

utilizing short traces to minimize inductance. Table 14. Spread Specturm Clock Source Recommendations At recommended operating conditions. See Ta ble 4.

1. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO

frequencies, must meet the minimum and maximum specifications given in Table 8.

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

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These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic surface mount technology (SMT) capacitors should be used to minimize lead inductance. Orientations where connections are made along the length of the part, such as 0204, are preferable but not mandatory. Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993) and contrary to previous recommendations for decoupling Freescale microprocessors, multiple small capacitors of equal value are recommended over using multiple values of capacitance. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the V DD and OVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low equivalent series resistance (ESR) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors are: 100–330 µF (A VX TPS tantalum or Sanyo OSCON).

9.4 Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unless otherwise noted, unused active-low inputs should be tied to OVDD, and unused active-high inputs should be connected to GND. All NC (no connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, OVDD, and GND pins in the MPC7447A. For backward compatibility with the MPC7447, MPC7445, and MP7441, or for migrating a system originally designed for one of these devices to the MPC7447A, the new power and ground signals (formerly NC, see Table 12) may be left unconnected. There is no performance degradation associated with leaving these pins unconnected. However, future devices may require these additional power and ground signals to be connected to achieve maximum performance, and it is recommended that new designs include the additional connections to facilitate future upgrades. See also Section 7, “Pinout Listings,” for additional information.

9.5 Output Buffer DC Impedance

The MPC7447A processor bus drivers are characterized over process, voltage, and temperature. To measure Z0, an external resistor is connected from the chip pad to OVDD or GND. The value of each resistor is varied until the pad voltage is OVDD/2. Figure 18 shows the driver impedance measurement. The output impedance is the average of two components—the resistances of the pull-up and pull-down devices. When data is held low, SW2 is closed (SW1 is open), and RN is trimmed until the voltage at the pad equals OVDD/2. RN then becomes the resistance of the pull-down devices. When data is held high, SW1 is closed (SW2 is open), and RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2.

Figure 18. Driver Impedance Measurement and is relatively unaffected by bus voltage.

9.6 Pull-Up/Pull-Down Resistor Requirements

stronger: 4.7 KΩ–1 KΩ) if it is used by the system. This pin is CKSTP_OUT. If pull-down resistors are used to configure BVSEL, the resistors should be less than 250Ω (see Table 12). switching due to ground bounce, power supply noise or noise coupling. Table 15. Impedance Characteristics

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

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During inactive periods on the bus, the address and transfer attributes may not be driven by any master and may, therefore, float in the high-impedance state for relatively long periods of time. Because the MPC7447A must continually monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on the MPC7447A or by other receivers in the system. These signals can be pulled up through weak (10-KΩ) pull-up resistors by the system, address bus driven mode enabled (see the MPC7450 RISC Microprocessor Family Users’ Manual for more information on this mode), or they may be otherwise driven by the system during inactive periods of the bus to avoid this additional power draw. Preliminary studies have shown the additional power draw by the MPC7447A input receivers to be negligible and, in any event, none of these measures are necessary for proper device operation. The snooped address and transfer attribute inputs are: A[0:35], AP[0:4], TT[0:4], CI , WT, and GBL. If address or data parity is not used by the system, and respective parity checking is disabled through HID1, the input receivers for those pins are disabled and do not require pull-up resistors, and may be left unconnected by the system. If extended addressing is not used (HID0[XAEN] = 0), A[0:3] are unused and must be pulled low to GND through weak pull-down resistors; additionally, if address parity checking is enabled (HID1[EBA] = 1) and extended addressing is not used, AP[0] must be pulled up to OVDD through a weak pull-up resistor. If the MPC7447A is in 60x bus mode, DTI[0:3] must be pulled low to GND through weak pull-down resistors. The data bus input receivers are normally turned off when no read operation is in progress and, therefore, do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require pull-ups, or that those signals be otherwise driven by the system during inactive periods. The data bus signals are: D[0:63] and DP[0:7].

9.7 JTAG Configuration Signals

Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1 specification but is provided on all processors that implement the PowerPC architecture. While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset. Because the JTAG interface is also used for accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not practical. The COP function of these processors allows a remote computer system (typically a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 19 allows the COP port to independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used, TRST should be tied to HRESET through a 0-Ω isolation resistor so that it is asserted when the system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during power-on. Although Freescale recommends that the COP header be designed into the system as shown in Figure 19, if this is not possible, the isolation resistor will allow future access to TRST in the case where a JTAG interface may need to be wired onto the system in debug situations.

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 41 System Design Information The COP header shown in Figure 19 adds many benefits—breakpoints, wa tchpoints, register and memory examination/modification, and other standard debugger features are possible through this interface—and can be as inexpensive as an unpopulated footprint for a header to be added when needed. The COP interface has a standard header for connection to the target system, based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector key. There is no standardized way to number the COP header shown in Figure 19; consequently, many different pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in Figure 19 is common to all known emulators. The QACK signal shown in Figure 19 is usually connected to the PCI bridge chip in a system and is an input to the MPC7447A informing it that it can go into the quiescent state. Under normal operation this occurs during a low-power mode selection. In order for COP to work, the MPC7447A must see this signal asserted (pulled down). While shown on the COP header, not all emulator products drive this signal. If the product does not, a pull-down resistor can be populated to assert this signal. Additionally, some emulator products implement open-drain type outputs and can only drive QACK asserted; for these tools, a pull-up resistor can be implemented to ensure this signal is negated when it is not being driven by the tool. Note that the pull-up and pull-down resistors on the QACK signal are mutually exclusive and it is never necessary to populate both in a system. To preserve correct power-down operation, QACK should be merged through logic so that it also can be driven by the PCI bridge.

42 Freescale Semiconductor

Figure 19. JTAG Interface Connection

2 KΩ 10 KΩ

10 KΩ 4

2 KΩ 3

1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the MPC7447A. Connect

pin 5 of the COP header to OVDD with a 10-KΩ pull-up resistor.

1. Key location; pin 14 is not physically present on the COP header.
2. Component not populated. Populate only if debug tool does not drive QACK
3. Populate only if debug tool uses an open-drain type output and does not actively negate QACK .
4. If the JT AG interface is implemented, connect HRESET from the target source to TRST from the COP

HRESET from the target source to TRST of the part through a 0- Ω isolation resistor.

1. The COP port and target board should be able to independently assert HRESET and TRST to the

processor in order to fully control the processor as shown above.

9.8 Thermal Management Information

several features designed to assist with thermal management, including DFS and the temperature diode. “Power Consumption with DFS Enabled,” for specific information regarding power reduction and DFS. the force on the die should not exceed ten pounds. Figure 20. BGA Package Exploded Cross-Sectional View with Several Heat Sink Options solution is recommended, as shown in Figure 21 below.

44 Freescale Semiconductor

Figure 21. LGA Package Exploded Cross-Sectional View with Several Heat Sink Options

60 Alhambra Road

performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost.

9.8.1 Internal Package Conduction Resistance

Figure 22. C4 Package with Heat Sink Mounted to a Printed-Circuit Board thermal resistances are the dominant terms.

9.8.2 Thermal Interface Materials

joint results in a thermal resistance approximately seven times greater than the thermal grease joint.

46 Freescale Semiconductor

requirements, manufacturability, service temperature, dielectric properties, cost, and so on. Figure 23. Thermal Performance of Select Thermal Interface Material

9.8.3 Heat Sink Selection Example

Table 4. The temperature of air cooling the component greatly depends on the ambient inlet air temperature the maximum value of Table 4.

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interconnect technology, system air temperature rise, altitude, and so on. well as system-level designs. direction and 3.8 W/(m  K) in the direction of the z-axis. Figure 24. Recommended Thermal Model of MPC7447A

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 49 System Design Information

9.8.4 Temperature Diode

The MPC7447A has a temperature diode on the microprocessor that can be used in conjunction with other system temperature monitoring devices (such as Analog Devices, ADT7461™). These devices use the negative temperature coefficient of a diode operated at a constant current to determine the temperature of the microprocessor and its environment. For proper operation, the monitoring device used should auto-calibrate the device by canceling out the V BE variation of each MPC7447A’s internal diode. The following are the specifications of the MPC7447A on-board temperature diode: 0.40 V <Vf <0.90 V Operating range 2–300 μA Diode leakage < 10 nA @ 125 C Ideality factor (n) over 5–150 μA @ 60 C: 1.0275 ± 0.9 % Ideality factor is defined as the deviation from the ideal diode equation: Where: Ifw = Forward current Is = Saturation current Vd = V oltage at diode BM: this does not show up in any equations. Vf = V oltage forward biased q = Charge of electron (1.6 x 10 -19 C) n = Ideality factor (normally 1.0) K = Boltzman’s constant (1.38 x 10-23 Joules/K) T = Temperature (Kelvins) Another useful equation is : Where: VH = Diode voltage while I H is flowing VL = Diode voltage while I L is flowing IH = Larger diode bias current IL = Smaller diode bias current Ifw = I s e – 1 qVf___ nKT VH – VL = n ln KT__ q IH__ IL

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9.8.5 Dynamic Frequency Switching (DFS)

DFS can be found in the MPC7450 RISC Microprocessor Family Reference Manual.

9.8.5.1 Power Consumption with DFS Enabled

The above is an approximation only. Power consumption with DFS enabled is not tested or guaranteed.

9.8.5.2 Bus-to-Core Multiplier Constraints with DFS

DFS is not available for all bus-to-core multipliers as configured by PLL_CFG[0:4] during hard reset. feature is limited to integer PLL multipliers of 4x and higher. The complete listing is shown in Table 16. Table 16. Valid Divide Ratio Configurations

9.8.5.3 Minimum Core Frequency Requirements with DFS

operation of the device is not guaranteed at core frequencies below the specified minimum fcore. Table 16. Valid Divide Ratio Configurations (continued)

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10 Document Revision History

Table 17 provides a revision history for this hardware specification. special part numbers require an additional document called a hardware specification addendum. Table 17. Document Revision History 4 09/23/2005 Added RoHS BGA case outlines and part numbers. cycle-to-cycle jitter (instead of long- and short-term jitter); changed jitter bandwidth recommendations. Added information for LGA package. specifications remain unchanged for TS , ARTRY, and SHD[0:1].

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 53

Ordering Information

11.1 Part Numbers Fully Addressed by This Document

Table 18 provides the Freescale part numbering nomenclature for the MPC7447A.

11.2 Part Numbers Not Fully Addressed by This Document

Parts with application modifiers or revision levels not fully addressed in this specification document are described in separate hardware specification addenda which supplement and supersede this document. As such parts are released, these specifications will be listed in this section. Table 18. Part Numbering Nomenclature Table 19. Part Numbers Addressed by MC7447A xxnnnn Nx Series Hardware Specification Addendum

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

54 Freescale Semiconductor

11.3 Part Marking

Parts are marked as the example shown in Figure 25. Figure 25. Part Marking for BGA and LGA Device Table 20. Part Numbers Addressed by MC7447AT xxnnnnNx Series Hardware Specification Addendum YWWLAZ is the assembly traceability code. MMMMMM is the M00 (mask) number.

MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5 Freescale Semiconductor 55 THIS PAGE INTENTIONALLY LEFT BLANK

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