MC72000

MC72000 FREESCALE | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 156

Technical content

Ordering Information

MC72000 -40° C to 85° C MAPBGA – 100

Package Information

(MAPBGA–100) This document contains information on a new product. Specifications and information herein are subject to change without notice. © Motorola, Inc., 2003. All rights reserved. Preliminary The MC72000 Integrated Bluetooth™ Radio provides a complete, low-power Bluetooth radio solution. The design is based on Motorola’s third-generation Bluetooth architecture that has set a high standard for interoperability, complete functionality, and compliance with the Bluetooth specification. The MC72000 Integrated Bluetooth Radio from Motorola implements the RF and baseband host controller interface (HCI) of the Bluetooth protocol in a small 7 mm x 7 mm BGA package. The MC72000 is the ideal solution for low-power, short-range Bluetooth applications with small size constraints and includes superior performance features like a dedicated Bluetooth audio processor module and on-chip memory. Debug and production test are fully supported through the joint test action group (JTAG) interface. The RF portion of the radio provides a unique combination of high sensitivity, excellent C/I performance, and low power consumption. These performance parameters are extremely important to maintaining a robust link in high RF interference environments created by devices such as mobile phones, high density Bluetooth networks, 802.11b networks, and microwave ovens. The MC72000 uses an innovative, highly advanced packaging technique to combine two die—the RF and baseband functions—into a single, cost-effective package. Motorola’s optimized two-chip architecture avoids compromises between cost and performance that other one-chip solutions must make. With Motorola’s integrated solution, customers get the best of both. Each die is implemented in its optimal process technology to deliver low cost, low power, and small size. Advance Information Data Sheet MC72000/D Rev. 2.6, 1/2003 MC72000 Integrated Bluetooth™ Radio

Contents

1 MC72000 Features . . . . 2

3 Electrical

5 System Description . . . 27

6 Radio Functional

7 Hardware Functional

8 Bluetooth Baseband

10 Applications

Evaluation Printed Circuit

12 Mechanical Outline

(Package Appendix A: Radio Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2 MC72000 Advance Information Data Sheet MOTOROLA

1 MC72000 Features

• Low Current Drain • Power Down Modes for Power Conservation • Low IF Receiver with On-Chip Filters • Fully Integrated Demodulator with ADC • Direct Launch Transmitter • Multi-Accumulator, Dual-Port, Fractional-N Synthesizer • RSSI with ADC • Bluetooth Class 2 Radio (Class 1 supported using external PA) • Crystal Independent (12 to 15 MHz) Reference O scillator or 12 to 26 MHz if supplied externally • Power Supply Range: 2.5 V to 3.1 V Baseband Controller • Bluetooth Specifi cation 1.1 Compliant — Point-to-multipoint with 7 slaves — All connection types — All packet types — All power saving modes — Master/Slave switch —E n c r y p t i o n — HCI UART transport layer • Outstanding Audio Performance — Sample rate synchronization between CODECs an d Bluetooth clock domains to avoid clicking effects — 3 Simultaneous SCO channels supported — All Bluetooth encoding/decoding schemes supported (CVSD, A-Law, µ-Law) — Very low audio delay to avoid the need for echo cancellation • Support for 8, 16, 32, and 64 kHz Sample Rate CODECs • Bluetooth Link Controller • Bluetooth Audio Signal Processor • ARM7 Processor Complex •P e r i p h e r a l s — High-speed UART (up to 2 Mbps) — High-speed SSI (up to 2 Mbps) — High-speed SPI (up to 2 Mbps) • Embedded Memory —S R A M ( 6 4 K ) — ROM (256 K) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

2 System Overview

This section provides a brief description of the system for the MC72000. Figure 1. MC72000 Example Application Block Diagram

2.1 RF Signal Path

The switch for the RX and TX, the bandpass filter, and the antenna are all found in the RF signal path.

2.2 Interfaces

There are four bi-directional interfaces and one reset that only the host can initiate. • The SSI interface is used for audio purposes. • The SPI is used for comm unication with the SEEPROM. • The GPIO pins are used for different configurations set by the MC72000.

2.3 Clocks/Crystals

32.768 KHz

Freescale Semiconductor, Inc.

4 MC72000 Advance Information Data Sheet MOTOROLA

Electrical Characteristics

• The reference clock (12-26 MHz) is used when the MC72000 is active. Note that for a crystal connected to the on-chip oscillator, the frequency range is 12-15 MHz as shown in Figure 1. • The low power clock (32.768 kHz) is also included and may have high initial tolerance.

3 Electrical Characteristics

The absolute maximum ratings given in Table 1 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent damage to the device. WARNING: This device contains protective circui try to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to the high-impedance ci rcuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either VDD or GND), except for JTAG signals. Refer to Section 10.12, “JTAG Interface,” for details on how to handle JTAG signals.

3.1 Electrical Characteristics

The following tables provide information on the electrical characteristics of the MC72000. Table 1. Absolute Maximum Ratings Table 2. ESD Protection Characteristics Freescale Semiconductor, Inc.

MOTOROLA MC72000 Advance Information Data Sheet 5 Preliminary Table 3. Recommended Operating Conditions Table 4. Digital DC Electrical Specifications Freescale Semiconductor, Inc.

6 MC72000 Advance Information Data Sheet MOTOROLA

BB Digital Pins (IOH = -3mA) IO Digital Pins (IOH = -3mA) RF Digital Pins (IOH = -100µA) VOH 0.8 x VDD_BB 0.8 x VDD_IO 0.8 x VCC_RF VDD_BB VDD_IO VCC_RF V Output Voltage Low BB Digital Pins (IOL = 3mA) IO Digital Pins (IOL = 3mA) RF Digital Pins (IOL = 100µA) VOL 0.2 x VDD_BB 0.2 x VDD_IO 0.2 x VDD_RF V Internal Pull-up Device Current IO Digital pins at VILMAX IO Digital pins at VIHMIN MODE1, TTS, TMS, TDI at VILMAX MODE1, TTS, TMS, TDI at VIHMIN IIOPUL IIOPUH IBBPUL IBBPUH -50 -30 µA Internal Pull-down Device Current RESET_BB, TCK, TRST_B at VILMAX RESET_BB, TCK, TRST_B at VIHMIN IBBPDL IBBPDH µA Input Capacitance BB Digital Pins IO Digital Pins CBBIN CIOIN pF Table 5. EPA DAC Electrical Specifications Table 4. Digital DC Electrical Specifications (Continued) Freescale Semiconductor, Inc.

MOTOROLA MC72000 Advance Information Data Sheet 7 Preliminary Table 6. Power Consumption Characteristics Freescale Semiconductor, Inc.

8 MC72000 Advance Information Data Sheet MOTOROLA

Transmit, 1 slot ACL Transmit, 3 slot ACL Transmit, 5 slot ACL Transmit, HV1 Transmit, HV2 Transmit, HV3 Transmit, Continuous Receive, 1 slot ACL Receive, 3 slot ACL Receive, 5 slot ACL Receive, HV1 Receive, HV2 Receive, HV3 Receive, Continuous Standby Mode (No RF activity) Sniff Mode, 0.5s Sniff Mode, 1.0s Sniff Mode, 2.0s Hold Mode Inquiry Scan Mode, 1.28s interval Page Scan Mode, 1.28s interval Inquiry and Page Scan Mode, 1.28s interval ICCBBtx1 ICCBBtx3 ICCBBtx5 ICCBBtxHV1 ICCBBtxHV2 ICCBBtxHV3 ICCBBtxc ICCBBrx1 ICCBBrx3 ICCBBrx5 ICCBBrxHV1 ICCBBrxHV2 ICCBBrxHV3 ICCBBrxc ICCBBstby ICCBBs0.5 ICCBBs1.0 ICCBBs2.0 ICCBBhold ICCBBis ICCBBps ICCBBips TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD mA IO Power Supply Current Transmit, 1 slot ACL Transmit, 3 slot ACL Transmit, 5 slot ACL Transmit, HV1 Transmit, HV2 Transmit, HV3 Transmit, Continuous Receive, 1 slot ACL Receive, 3 slot ACL Receive, 5 slot ACL Receive, HV1 Receive, HV2 Receive, HV3 Receive, Continuous Standby Mode (No RF activity) Sniff Mode, 0.5s Sniff Mode, 1.0s Sniff Mode, 2.0s Hold Mode Inquiry Scan Mode, 1.28s interval Page Scan Mode, 1.28s interval Inquiry and Page Scan Mode, 1.28s interval ICCIOtx1 ICCIOtx3 ICCIOtx5 ICCIOtxHV1 ICCIOtxHV2 ICCIOtxHV3 ICCIOtxc ICCIOrx1 ICCIOrx3 ICCIOrx5 ICCIOrxHV1 ICCIOrxHV2 ICCIOrxHV3 ICCIOrxc ICCIOstby ICCIOs0.5 ICCIOs1.0 ICCIOs2.0 ICCIOhold ICCIOis ICCIOps ICCIOips 0.6 0.6 0.6 0.4 TBD TBD 0.6 0.6 0.6 0.6 0.4 TBD TBD 0.6 TBD TBD TBD TBD TBD TBD TBD TBD 0.6 0.6 0.6 0.4 TBD TBD 0.6 0.6 0.6 0.6 0.4 TBD TBD 0.6 TBD TBD TBD TBD TBD TBD TBD TBD mA Table 6. Power Consumption Characteristics (Continued) Freescale Semiconductor, Inc.

MOTOROLA MC72000 Advance Information Data Sheet 9 Preliminary Table 6 shows the overall current consumed by the MC72000 in many well-known scenarios as well as detailed current in real-time specific modes. The first row in Table 6 shows the maximum peak and typical average total current consumed by the device in most scenarios used by PDAs, cell phone design, and other audio-capable devices such as headsets. The current specified in this row is the total current consumed through the three power groups of the MC72000 (i.e., the voltage relationship between the three different supply voltages in these three groups are ignored). Power dissipated by the MC72000 may, therefore, be different than the direct power consumption calculated on the total current consumption. In order to find current values for special scenarios not covered by the typical values of total current consumption, the current consumed in each of the three power groups are also defined in a variety of usages. Each value represents the current consumed in between a repeatedly symmetrical timeframe, for example, the BB power supply current for transmitting one-slot ACL packets is defined as the time from start of TX burst to the start of RX burst, as the same current consumption is repeated again in the next TX slot. This also applies to all currents defined for receiving packets regardless of packet type. See example below in Figure 2. The repeatedly symmetrical pattern definition for the listed scenarios are shown in Table 7. Figure 2. Power Consumption Characteristics Table 7. Real-time Current Consumption Definitions Freescale Semiconductor, Inc.

10 MC72000 Advance Information Data Sheet MOTOROLA

Table 8. Receiver AC Electrical Specifications

2110 MHz - 2170 MHz (WCDMA-FDD)2

2010 MHz - 2025 MHz (WCDMA-TDD)2

1900 MHz - 1920 MHz (WCDMA-TDD)2

869 MHz - 894 MHz (GSM 850)3

921 MHz - 960 MHz (GSM 900)3

1805 MHz - 1880 MHz (DCS1800)3

1930 MHz - 1990 MHz (PCS1900)3

Freescale Semiconductor, Inc.

MOTOROLA MC72000 Advance Information Data Sheet 11 Preliminary Receiver Blocking Performance4 (See Figure 11) Bluetooth 30 MHz to 1.999 GHz 2.0 GHz to 2.399 GHz 2.498 GHz to 2.999 GHz 3.0 GHz to 12.75 GHz GSM/DCS and UMTS uplink5

1920 MHz - 1980 MHz (WCDMA-FDD)

2010 MHz - 2025 MHz (WCDMA-TDD)

1900 MHz - 1920 MHz (WCDMA-TDD)

824 MHz - 849 MHz (GSM 850)

876 MHz - 915 MHz (GSM 900)

1710 MHz - 1785 MHz (DCS1800)

1850 MHz - 1910 MHz (PCS1900)

-21 -20 -23 -18 -11 -16 -23 -16 TBD TBD -15 -16 -15 -10 -11 -15 > -10 > -27 > -27 > -10 dBm RSSI Conversion Value, (R4/6 and R9/8 = 1) RF level at LNA input to maintain conversion value of: 1000 (binary) 1111 RSSI -60 -56 -70 -52 -66 dBm RSSI Resolution, (R4/6 and R9/8 = 1) RSSI res -1 . 8- d B / b i t RSSI Dynamic Range 20 - - dB RSSI Average Supply Current, (R4/6 and R9/8 = 1) -4 0- µ A 1. Measured at f2 – f1 = 5.0 MHz in accordance with Bluetooth specification. 2. Equivalent noise floor to 5 MHz bandwidth 3. Equivalent noise floor to 200 kHz bandwidth 4. As allowed by the Bluetooth specif ication, up to five exceptions may be taken for spurious response. 5. Measured according to Bluetoot h Specification, but using a corre ct modulated and bursting GSM/DCS/ UMTS interfering signal, based on one timeslot. Table 8. Receiver AC Electrical Specifications (Continued) Freescale Semiconductor, Inc.

12 MC72000 Advance Information Data Sheet MOTOROLA

Table 9. Transmitter AC Electrical Specifications

2110 MHz - 2170 MHz (WCDMA-FDD)1

2010 MHz - 2025 MHz (WCDMA-TDD)1

1900 MHz - 1920 MHz (WCDMA-TDD)1

869 MHz - 894 MHz (GSM 850)2

921 MHz - 960 MHz (GSM 900)2

1805 MHz - 1880 MHz (DCS1800)2

1930 MHz - 1990 MHz (PCS1900)2

1. Equivalent noise floor to 5 MHz bandwidth
2. Equivalent noise floor to 200 kHz bandwidth

Freescale Semiconductor, Inc.

MOTOROLA MC72000 Advance Information Data Sheet 13 Preliminary Table 10. MC72000 Receive Characteristics Table 11. Reference Oscillator Electrical Specifications Freescale Semiconductor, Inc.

14 MC72000 Advance Information Data Sheet MOTOROLA

Input Impedance at XBASE (Reference Frequency = 12 to

26 MHz, R11/0 = 0 or 1)

1.0 + Parallel Trim Capaci- tance pF kΩ Input Phase Noise at XBASE (Reference Frequency = 12 to 26 MHz, R11/0 = 0 or 1) 100 Hz 1 kHz 10 kHz 100 kHz

1 MHz

-70 -90 -105 -110 -130 dBc/ Hz Duty Cycle for External Reference TBD 50 TBD % Input Bias Voltage (XBASE) - 1.2 - V Start-up Time (using Crystal) TWAIT -7 . 5-M s Table 12. Low Power Oscillator Electrical Specifications Table 11. Reference Oscillator Electrical Specifications (Continued) Freescale Semiconductor, Inc.

MOTOROLA MC72000 Advance Information Data Sheet 15 Preliminary Input Impedance at EXTAL_BB Parallel Capacitance Parallel Resistance TBD TBD Duty Cycle for External Reference TBD 50 TBD % Start-up Time (using Crystal) TLPWAIT 5- 7 0 0 m s Table 13. Data Clock PLL Electrical Specifications Table 12. Low Power Oscillator Electrical Specifications (Continued) Freescale Semiconductor, Inc.

16 MC72000 Advance Information Data Sheet MOTOROLA

The following figure shows a typical test circuit schematic. Figure 3. Typical Test Circuit Schematic Freescale Semiconductor, Inc.

4 Package Pinout

Low power and small PCB footprints ar e critical for certain applications. glueless interface to peripherals.

4.1 Pin Assignment Listing

organized into functional groups. with respect to the ball assignment in the column Ball #. • The Power Group column lists the Supply Power Group assignment. • The Pin Type column shows the type of internal circuitry to the chip. • The Reset State column lists the pin input/output direction at chip RESET_BB. available. Some selections are test- or development-mode specific. Table 14. Pin Names and Functions Freescale Semiconductor, Inc.

18 MC72000 Advance Information Data Sheet MOTOROLA

Table 14. Pin Names and Functions (Continued) Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

20 MC72000 Advance Information Data Sheet MOTOROLA

Freescale Semiconductor, Inc.

4.2 Pin Descriptions

and UART; and UART, SPI1, and TIM including the GPIO shared package pins. control for each pin is in normal function mode, alternate function mode 2, or GPIO mode. any input data from the pad is passed to the peripheral. supplies any data to be output. to the pad and any input data from the pad is passed to the peripheral. Freescale Semiconductor, Inc.

22 MC72000 Advance Information Data Sheet MOTOROLA

Information,” for details on how to isolate and identify the correct configuration for the power supply pins. Table 15. Pin Descriptions DCLF1 Data Clock Loop Filter charge pump output for external loop filter. to minimize transmit phase noise. must be left open if external (not crystal) reference frequency is used. feed-point in case of using external (not crystal) reference frequency. RFTEST+ This pin is for factory use only. It must be left open. RFTEST- This pin is for factory use only. It must be left open. and gain. The cascode output drives the primary of an on-chip balun single-ended. PAOUT+ Positive differential PA output. An external differential-to-single-ended matching network is desired. switch requiring complementary drive. linearly scaled to a maximum VCC_RF of 3.1 V. be fed to this pin, while leaving XTAL pin open. the rising edge of TCK. Leave open if JTAG is unused. controller state machine. TDO changes on the falling edge of TCK. Freescale Semiconductor, Inc.

controllers to initialize the test controller. Leave open or pull-down if JTAG is unused. TCK. Leave open or pull-up if JTAG is unused. be entered from the serial debug input line. start reading data at address 0x0000_0000, since this is where the ARM7 reset vector is located. RESET input will be qualified as valid if it will be asserted for at least three CLK cycles. disables the reference clock. Table 15. Pin Descriptions (Continued) Freescale Semiconductor, Inc.

24 MC72000 Advance Information Data Sheet MOTOROLA

SSI_STD Normal mode The serial tr ansmit data signal is used to transmit serial data. GPIO_B2 Alternate Function 1 (GPIO) GPIO_2 on Port B. BT_TP2 Alternate Function 2 B luetooth test port signal. SSI_SRD Normal mode The serial receive data signal is used to receive serial data. GPIO_B5 Alternate Function 1 (GPIO) GPIO_5 on Port B. BT_TP5 Alternate Function 2 B luetooth test port signal. GPIO_B10 Alternate Function 1 (GPIO) Note: GPIO_10 on Port B. UART_TXD Alternate Function 2 Note: Transmit data serial (output signal). GPIO_B12 Alternate Function 1 (GPIO) GPIO_12 on Port B. UART_RXD Alternate Function 2 Receive data serial (input signal) . UART_TXD Normal mode UART transm it data serial (output signal). GPIO_C0 Alternate Function 1 (GPIO) GPIO_0 on Port C. device can transmit when it has data to send. Freescale Semiconductor, Inc.

GPIO_C1 Alternate Function 1 (GPIO) GPIO_1 on Port C. SPI1_REQ Alternate Function 2 External da ta transfer rate control for SPI1. UART_RXD Normal mode UART receive data serial (input signal). GPIO_C2 Alternate Function 1 (GPIO) GPIO_2 on Port C. TIM_0_I Alternate Function 2 Input signal to timer 0. MC72000 can transmit when it has data to send. GPIO_C3 Alternate Function 1 (GPIO) GPIO_3 on Port C. TIM_1_I Alternate Function 2 Input signal to timer 1. GPIO_C4 Alternate Function 1 (GPIO) GPIO_4 on Port C. slave mode, SPI1_SCK is an input clock signal to the SPI. GPIO_C5 Alternate Function 1 (GPIO) GPIO_5 on Port C. Alternate Function 2 Indicates data is valid on the external bus when show cycle is used. GPIO_C6 Alternate Function 1 (GPIO) GPIO_6 on Port C. ABORT Alternate Function 2 Indicates the current memory access cannot be completed. Freescale Semiconductor, Inc.

26 MC72000 Advance Information Data Sheet MOTOROLA

Figure 4. MC72000 Package Pinout (Top View) GPIO_C7 Alternate Function 1 (GPIO) GPIO_7 on Port C. REFCLK Alternate Function 2 RF reference clock input (12-32 MHz). GPIO_C8 Alternate Function 1 (GPIO) GPIO_8 on Port C. TIM_0_O Alternate Function 2 O utput signal from timer 0. GPIO_C9 Alternate Function 1 (GPIO) GPIO_9 on Port C. XACK Alternate Function 2 External acknowledge signal. OSC32K Normal mode Buffered output from the 32.768 kHz on-chip oscillator. GPIO_C10 Alternate Function 1 (GPIO) GPIO_10 on Port C. TIM_1_O Alternate Function 2 O utput signal from timer 1. Freescale Semiconductor, Inc.

5 System Description

includes a section listing other documents of relevance (see Section 5.2, “Document References”).

5.1 MC72000 S ystem Description

The detailed MC72000 design is shown in the block diagram in Figure 5. are clocks and not crystals as in Figure 1. Figure 5. MC72000 Block Diagram The following sections describe the different blocks of the MC72000.

5.1.1 ARM7 Processor

power control, protocol behavior, and packet formatting.

24 MHz Data

4 MHz

6 MHz IF

Freescale Semiconductor, Inc.

28 MC72000 Advance Information Data Sheet MOTOROLA

The program execution in the MC72000 Bluetooth Baseband Controller is predominantly ROM-based, with internal RAM for data storage, application code, and ROM code patching. However, it is necessary to download the application software and configuration data into RAM from an external interface. This is done either as individual files when needed, as a complete image at power up containing all the files from a host system, or from a low-cost serial EEPROM (four-wire connection) connected to the serial peripheral interface (SPI).

5.1.2 Baseband Processor

The baseband processor digitally demodulates the signal at the output of the radio discriminator. Rather than immediately making a threshold decision based on the amplitude of the signal, it analyzes the waveform shape over more than one symbol before it makes a decision. This feature allows the Maximum Likelihood Sequence Estimation and Joint Detection algorithms (JD/MLSE) to improve adjacent channel rejection and signal acquisition. Without the joint detection and MLSE algorithms, it is possible to have high sensitivity but low throughput because of false/missing acquisitions and high interference. Joint detection provides simultaneous frequency and timing acquisition on the entire header rather than relying on just the synchronization portion.

5.1.2.1 Bluetooth Link Controller

The Bluetooth link controller module (BTLC) handles all link controller specific functions. Raw data can be read from/written to the module, and the BTLC takes care of transmission-related timing, as well as data signal processing functions like encryption and cyclic redundancy check (CRC)/header error correction (HEC) generation. Embedded in the BTLC are also the dedicated Bluetooth timers, which maintain an accurate estimate of time in both the native and the remote module. A small, dedicated Bluetooth serial peripheral interface controller handles all serial communication with the radio part of the MC72000 Integrated Bluetooth Radio. The functionality of the baseband will be elaborated on in Section 8, “Bluetooth Baseband Functionality Overview.”

5.1.3 Bluetooth Radio

The design is based on Motorola's third-generation Bluetooth architecture that has set the industry standard for interoperability, complete functionality, and compliance with the Bluetooth specification. The radio portion of MC72000 exhibits superior RF performance with small size and low cost. A minimum of external components are required to complete the RF link of a Bluetooth system, while maintaining superior performance.

5.1.3.1 Receiver

The receiver is a 6 MHz low-IF frequency type using analog image cancellation. The LO is set to either high-side or low-side injection so that the image will fall within the ISM band when the frequency to be received is set to edge of the ISM band. The integrated Bluetooth baseband automatically decides the use of high-side or low-side injection to the receiver, based on the active receive channel. The low-power integrated LNA and BPF exhibits the excellent sensitivity and noise rejection performance, which is further improved by the total system solution using the JD/MLSE baseband signal processing. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA MC72000 Advance Information Data Sheet 29 Preliminary

5.1.3.2 Transmitter

The shape of the transmit pulse as required by the Bluetooth specification is controlled by a look-up table that directly modulates the high frequency and accuracy main fractional VCO. The gain of the transmitter is adjustable, and pin connections for controlling an external PA are provided for Class 1 operation. The output of the PA is differential and, therefore, requires a balun that may be implemented in stripline or by using a discrete balun. The GPO pin controls the external antenna switch, which is set automatically by the internal sequence manager, and therefore requires no baseband interruption. As the transmitter section is a direct launch transmitter operating directly at the transmit frequency, the out-of-band spurious emissions are reduced to a minimum to comply with sensitive environments and strict requirements for other applications like cell phones, PDAs, and computer accessories.

5.1.4 Clock and Reset Module

The clock and reset module (CRM) is dedicated to handling all clock, reset, and power management features in the MC72000 Bluetooth Baseband Controller. It ensures that the different clock and reset signals are stable before they are fed to the internal logic in the MC72000 Bluetooth Baseband Controller. The CRM is designed to make full use of the facilities supplied by the Bluetooth standard to conserve power, while still maintaining a Bluetooth link. Two reference clocks are used to drive the MC72000: one for low power mode (32.768 kHz), and one for accurate transmit, receive, and timing operation. Reference frequency can be chosen to cover a great variety of typical reference frequencies used in cell phones, PDAs, and other equipment. This is due to an internal data clock VCO ensuring that the ARM7 processor always runs at the correct frequency. The internal crystal oscillator that feeds its clock to the data clock VCO and the radio portion covers the full supply and temperature range with its very low-noise and trimable reference frequency based on an external crystal. The oscillator may also be driven using an external reference clock from other applications with minimum load to the external application. The CRM module also includes a watchdog to safeguard against potential software failures.

5.1.5 High-Speed UART

The universal asynchronous receiver/transmitter (UART) module provides one of the main interfaces to the MC72000 Bluetooth Baseband Controller. The generated baud rate is based on a configurable divisor and input clock. The UART transmit and receive buffer sizes are 32 bytes each.

5.1.6 High-Speed CSPI

The MC72000 Bluetooth Baseband Controller contains one configurable serial peripheral interface (CSPI) module, CSPI1. CSPI1 may be connected to a variety of SEEPROM and serial flash devices. They are described in Section 10.8.7, “Possible EEPROM Types.” The CSPI module is master/slave configurable, equipped with 16 byte data out buffers (transmit and receive FIFOs), and allows the MC72000 Bluetooth Baseband Controller to interface with external CSPI master or slave devices. It enables fast data communication with a fewer number of software interrupts by incorporating the SPIRDY and SS control signals. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

30 MC72000 Advance Information Data Sheet MOTOROLA

5.1.7 High-Speed SSI

The synchronous serial interface module (SSI) is a full-duplex serial port allowing digital signal processors (DSPs) to communicate with a variety of serial devices, including industry-standard CODECs, other DSPs, microprocessors, and peripherals. The SSI is typically used to transfer samples in a periodic manner and consists of a variety of registers that handle port, status, control, transmit and receive, serial clock generation, and frame synchronization.

5.1.8 Bluetooth Audio Signal Processor

High audio quality is of great importance to the end user. Section 10.9, “Audio,” describes the audio features. A dedicated Bluetooth audio signal-processing module (BTASP) has been designed to give users superior audio performance. The BTASP module handles all filtering, interpolation, as well as encoding/decoding with a minimum of processor intervention. The internal voice-processing unit converts raw 16-bit PCM voice data and compressed voice data to uncompressed voice. Compression modes are A-Law, µ-Law, and CVSD. It performs filtering and accepts CODEC rates of 8, 16, 32, and 64 kbits/sec. An external CODEC connected to the synchronous serial interface (SSI) is required for voice processing, if needed.

5.1.9 Timer

The dual timer module (TMR) is a general purpose module, used for timing control and application-specific tasks. The TMR can also be configured to perform pulse width modulation (PWM) or put into a quadrature-count mode if needed. The TMR contains two identical 16-bit counter/timer groups, each of which supports counting, prescaling, comparing, loading, capturing, and holding options.

5.1.10 General Purpose Input/Output

The MC72000 Bluetooth Baseband Controller supports a maximum of 16 GPIO lines grouped in two ports. Port B contains 6 lines, Port C contains 10 lines. These ports can be configured as GPIO pins or dedicated peripheral interface pins.

5.1.11 JTAG Test Interface Controller

The JTIC interface offers full JTAG and boundary scan capabilities for debug and production test purposes, as well as access to the JTAG interface on the ARM. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Radio Functional Description MOTOROLA MC72000 Advance Information Data Sheet 31 Preliminary

5.2 Document References

The following is a list of documents providing additional information or implementation guidance for different systems. MC72000-related documents: 1. Motorola Bluetooth File System, Overview Application Note (document number 94001481001) 2. Motorola Bluetooth File System, Host-based General Application Note (document number 94001481003) 3. Motorola Bluetooth File System, Host Based One File Application Note (document number 94001481004) 4. Motorola Bluetooth File System, Embedded File System Application Note (document number 94001481002) 5. Motorola Bluetooth Solutions, Bluetooth Qualification Application Note (document number AN2386/D) 6. UART/SSI Configuration User´s Guide (document number 94001481900) 7. Vendor-Specific HCI Reference (public) (document number 79000001800). 8. Specification of the Bluetooth System (22 Feb. 2001, v.1.1)—official book available from: http://www.bluetooth.com. Implementation-related documents: 1. Bluetooth IC File System File Formats Application Note (document number 94001481200). 2. MC72000 Implementation for Cellular Phones Application Note (document number 94001481800) 3. MC71000/MC72000 Wake-Up, Reset, and Host Clock Request Sequences Application Note (document number AN2340/D) 4. Production Test Application Note (document number 94001481100)

6 Radio Functional Description

NOTE: In the following description, control bits contained in the MC72000 Radio Register Map for various functions wi ll be identified by register number and bit number(s). For example, bit R4/8 references bit 8 of register 4 while R5/9-3 identifies bits 9 through 3, inclusive, of register 5 (decimal notation). Unless otherwise noted, a default register map configuration as listed in Figure 94 is assumed. The info rmation contained in this section will describe in detail how to calculat e and find the appropriate values of the MC72000 Radio Register Map in your specific setup. The information that concerns the radio performance and its ability to function, consisting of the MC72000 Radio Register Map and a Main Synthesizer Channel Table, is gathered and assembled in the File410x.vfs in the Motorola Bluetooth File System. Refer to Section 5.2, “Document References,” for details on the file system. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

32 MC72000 Advance Information Data Sheet MOTOROLA

Radio Functional Description

6.1 RF Receive Chain

The MC72000 is placed into the receive mode from the idle mode by asserting the internal RXTXEN master signal after setting the Radio Receive Enable bit (R2/13), clearing the Radio Transmit Enable bit (R2/14), and clearing the Radio Narrow Bandwidth Enable bit (R2/12). The data represents a 6-Bit, 2’s-complement digital value and is sampled four times for every data bit. Once the receive cycle is complete, the RXTXEN master signal to the radio is deasserted and the MC72000 begins an internal power down sequence. This is all controlled by the internal baseband processor. The receive chain is optimized to provide high adjacent channel rejection, which is the most important specification in a high interference environment. This is accomplished by setting the IF bandpass filter to 720 kHz and then using Maximum Likelihood Sequence Estimation (MLSE) in baseband processing to remove the effects of intersymbol interference. A low voltage SPI interface is used between the radio and the baseband processor. The baseband synchronizes the radio timing through the master RXTXEN signal to the radio. A logic low transition on this signal indicates the beginning of idle state, while a logic high transition indicates either transmit or a receive cycle.

6.2 RF Transmit Chain

The MC72000 is placed into the transmit mode from the idle mode by setting the Radio Transmit Enable bit (R2/14), setting the Radio Narrow Bandwidth Enable bit (R2/12), and clearing the Radio Receive Enable bit (R2/13) of the Radio Register Map, then asserting the RTXEN pin of the device. Once the data stream has been transmitted, the RTXEN pin is deasserted and the MC72000 begins an internal power down sequence. Since RF power is still present at the PA output, no SPI operations or additional cycles between the radio and the baseband processor can be performed until a certain amount of time has passed after the deassertion of RXTXEN. At this time, RF power is at a substantially low enough level so as not to produce undesired emissions. The internal baseband processor also handles this timing.

6.3 Receiver

The MC72000 receiver is intended to be used in Time Division Duplex (TDD), Frequency Hopping Spread Spectrum (FHSS) Bluetooth applications. The receiver uses a low intermediate frequency (IF) of 6.0 MHz and is capable of receiving up to 1.0 Mbit/s Gaussian Frequency Shift Keyed (GFSK) serial data through the entire 2.4 GHz Industrial, Scientific, and Medical (ISM) band. The output of the receiver is a demodulated, serial bit stream of 24 Mbit/s data. This data represents a 4X over sample by a 6-bit D/A of the actual demodulated analog data recovered from the desired channel. A detailed discussion of each of the functional blocks within the receiver is provided in the following sections.

6.3.1 LNA

The first portion of the receiver chain is the Low Noise Amplifier (LNA). The LNA is a bipolar cascode design and provides gain with low noise at RF frequencies. The LNA is designed with a single-ended (unbalanced) input and is converted to a differential (balanced) output by means of an on-chip, integrated balun. For optimum performance, the LNA input impedance must be matched to the complex conjugate of the source impedance (usually 50 Ω). The LNA of the MC72000 exhibits two distinctly different impedances depending upon whether the LNA is active or disabled. During a receive cycle, the S11 of the LNA is shown in the Table 16. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

The LNA can be matched to 50 Ω by a simple capacitor/inductor network as shown in Figure 6. Figure 6. Simple Capacitor/Inductor Network becomes the value shown in Table 16. immediately after the deassertion of the RTXEN pin or during any Idle or Transmit mode.

6.3.2 High/Low Image Reject Mixer (I/R Mixer)

on-chip voltage controlled oscillator (VCO). Table 16. S11 for LNA During Receive

2.45 GHz TBD TBD

Table 17. S11 for LNA Disabled Freescale Semiconductor, Inc.

34 MC72000 Advance Information Data Sheet MOTOROLA

Figure 7. High-Side and Low-Side Mixer Injection The mixer delivers approximately 15.8 dB of voltage gain and 22 dB of image rejection.

6.3.3 Bandpass Filter (BPF)

advantages are increased sensitivity, adjacent channel interference performance, and ease of manufacture. referenced as the JD/MLSE and is incorporated into all Motorola Bluetooth basebands. after the deassertion of the RTXEN pin or during any Idle or Transmit mode.

6.3.4 Limiter with Received Signal Strength Indicator (RSSI)

while in Idle mode. The RSSI is updated approximately 40 µs after receiving the first bit in a receive cycle. Freescale Semiconductor, Inc.

6.3.5 Demodulator

24 MHz clock output accompanies the demodulated data.

6.3.5.1 Receiver Characteristics

Figure 8. RF Level vs. RSSI at Temperature Figure 9. RF Level vs. RSSI at V CCRF Figure 10. Receive Sensitivity vs. Temperature Figure 11. Blocking Performance vs. Continuous Freescale Semiconductor, Inc.

36 MC72000 Advance Information Data Sheet MOTOROLA

Figure 12. C/I Performance for Channel 3 (2.405 GHz, High-Side Injection) Figure 13. C/I Performance for Channel 75 (2.477 GHz, Low-Side Injection) Figure 14. C/I Performance for Channel 39 (2.405 GHz, High-Side Injection) Freescale Semiconductor, Inc.

6.4 Transmitter

6.4.1 Transmit Synchronization Delay

manipulate the delay as necessary, up to TXsync maximum. Figure 15. C/I Performance for Channel 39 (2.405 GHz, High-Side Injection) Figure 16. C/I Performance vs. Temperature Freescale Semiconductor, Inc.

38 MC72000 Advance Information Data Sheet MOTOROLA

Radio Functional Description

6.4.2 Main Synthesizer Operation

The internal local oscillator (LO) of the MC72000 is derived from the external reference frequency by means of a 3-accumulator, fractional-N synthesizer. The external low pass filter (C14/R1 of Figure 3) has a corner frequency of approximately 140 kHz. The external low pass filter requires two or three passive components, dependent on the reference frequency. fdev is the nominal transmit ROM frequency deviation (typically 157500 Hz). I is the integer portion of the fractional synthesizer. R is the numerator portion of the fractional synthesizer. frefExternal is the external reference frequency. LO is the desired local oscillator frequency then, I = (LO/frefExternal - fdev/frefExternal) - 3 R = REM(LO/frefExternal - fdev/frefExternal) x 216 where the INT function is the integer portion of the result and REM is the remainder portion of the result. An example is shown below: fdev = 157500 Hz LO = 2.441 GHz frefExternal = 13 MHz then, I = INT(2.441 GHz/13 MHz - 157.5 kHz/13 MHz) - 3 = 18410 R = REM(2.441 GHz/13 MHz - 157.5 kHz/13 MHz) x 216 = 4961810 Accuracy to at least 10 decimal places is suggested.

6.4.3 Transmit ROM Operation

The MC72000 uses a look-up table (LUT or Transmit ROM) to shape incoming transmit data bits and produce a Gaussian filtered mask with BT=0.5. The value of the current data bit, along with knowledge of the previous two bits, determines a unique trajectory for shaping. Only four unique trajectories are required to implement this filter, and due to the symmetrical nature of the Gaussian response, these trajectories can be reduced to a single quadrant. Furthermore, without compromising accuracy, this table can be reduced to only 11 values. The output of the LUT is fed to the accumulators of the fractional synthesizer. The seven MSBs are eventually fed to the second port of the main VCO during transmit operation (see Figure 17). For receive operation, the output of the LUT is constantly held to the value contained in R1C1. These 11 trajectory constants are listed in Table 18 (see also Figure 94, Radio Register Map). The actual value to place in the LUT is calculated as: LUT RxCxb10 = (fdev/frefExternal) x 216 x (RxCx constant) This number is then rounded and converted to binary: LUT RxCxb2 = INT((LUT RxCxb10+2)/4) where the INT function is the integer portion of the result. As an example for calculating the LUT value for R4C2 and frefExternal = 13 MHz: LUT R4C2b10 = (157.5 kHz/13.0 MHz) x 216 x 0.5229292198 = 415.2 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

The following table lists all values of RxCx for supported reference.

6.4.4 M-Dual Port Multiplier and B-Dual Port Multiplier

15-8), determines the slope, and B-Dual Port Digital Multiplier Value (R8/7-0), determines the intercept. Table 20 contains slope and intercept point values across all supported input reference frequencies.

6.4.5 Dual-Port Programmable Delay (R7/15-11)

Delay = 10.5 / (frefExternal) - 28 ns. Table 18. RxCx Constants Freescale Semiconductor, Inc.

40 MC72000 Advance Information Data Sheet MOTOROLA

Consult Table 19 for the closest available value. Table 20 lists all values of the programmable delay for supported reference frequencies. Table 19. Dual-Port Programmable Delay Values Freescale Semiconductor, Inc.

Table 20. Register Settings and Component Values vs. Reference Frequency

12 MHz

13 MHz

14.40 MHz

15.26 MHz

16.80 MHz

19.22 MHz

19.44 MHz

19.68 MHz

19.88 MHz

26 MHz

Freescale Semiconductor, Inc.

42 MC72000 Advance Information Data Sheet MOTOROLA

Figure 17. Main PLL Synthesizer Block Diagram Table 20. Register Settings and Component Values vs. Reference Frequency (Continued) Freescale Semiconductor, Inc.

6.4.6 Programmable LPA

The output power of the LPA can be varied by programming PA Bias Adjust (R5/2-0) in the register map. external power amplifier not shown here. Refer to Section 10.6, “Class 1 Operation,” for more detail. Figure 18 and Figure 19 provide additional LPA characteristic data.

6.4.7 External Balun

impedance, S22 of the PA during active and inactive cycles. Table 21. RF Power Out vs. PA Bias Adjust Freescale Semiconductor, Inc.

44 MC72000 Advance Information Data Sheet MOTOROLA

Figure 20. Balun Physical Dimensions Figure 18. RF Output Power vs. Carrier Figure 19. RF Output Power vs. Temperature Table 22. S22 for PA During Transmit Freescale Semiconductor, Inc.

6.5 Crystal Oscillator

to register map location Xtal Trim (R6/14-10). Typical stray capacitance is on the order of 1.0 pF. duty cycle in Table 11. Additional characteristic data is shown in the following figures. Table 23. Examples of Programmable XTAL Trim Capacitances Figure 21. Oscillator Open Loop Gain vs. Figure 22. Oscillator Negative Resistance vs. Freescale Semiconductor, Inc.

46 MC72000 Advance Information Data Sheet MOTOROLA

6.6 Data Clock Operation

this 24 MHz clock frequency. The general model for the phase lock loop (PLL) is shown in Figure 27. proves to be adequate for any value of external reference frequency that is an integral multiple of 20 kHz. from An Improved PLL Design Method Application Note (document number AN1253/D). Figure 23. Oscillator Negative Resistance vs. Figure 24. Oscillator Negative Resistance vs. Figure 25. Crystal Start-up Time vs. Capacitor Figure 26. Crystal Frequency Pulling vs.

13 MHz Crystal Reference

initial frequency for R/14-10 = 12 (decimal). Freescale Semiconductor, Inc.

frequencies above 20 MHz, R = 65010 and N = 60010. represent frefInternal and achieve CLK. Table 24 provides the appropriate values for various frefInternal. Additional data clock characteristic data is shown in Figure 28 and Figure 29. Figure 27. General Model for the PLL Table 24. Data Clock R and N Counter Values for 20 kHz frefInternal with 1.0 kHz LBW Freescale Semiconductor, Inc.

48 MC72000 Advance Information Data Sheet MOTOROLA

6.7 External Antenna Switch

“Applications Information,” for further information.

6.8 General Purpose Output (GPO) Pin

6.9 External Power Ampl ifier Enable (EPAEN) Pin

The External Power Amplifier Enable (EPAEN) output of MC72000 is located at Pin K2 of the device. amplifier; or it may serve as a complementary driver to a dual port antenna switch as shown in Figure 92. If EPAEN is not required for the desired application, it may be disabled by setting R11/6 to zero. Figure 28. Data Clock Start-up Time vs. Figure 29. Data Clock Start-up Time vs. Capacitor Freescale Semiconductor, Inc.

Figure 30. Ramp Generator (Transmit Cycle) Timing Diagram

7 Hardware Functional Description

7.1 Clock Reset Module (CRM)

are fed to the internal logic in the MC72000.

7.1.1 Features

Freescale Semiconductor, Inc.

50 MC72000 Advance Information Data Sheet MOTOROLA

7.1.2 Modes of Operation

the switch over to the REFCLK signal. The MC72000 system clock operates on the 12-32 MHz reference clock (REFCLK) from the radio. internal wake up timer or one of the four external wake up interrupts.

7.1.2.1 External Clock Control Register

REFCLK which is also stopped in sleep mode. signal. The CLK1 output will be low when CLK1_DIV is disabled. Table 25. CLK1_DIV Values

000 CLK1 Disabled (Low) NA

Freescale Semiconductor, Inc.

Hardware Functional Description MOTOROLA MC72000 Advance Information Data Sheet 51 Preliminary

7.2 Universal Asynchronous Receiver/Transmitter (UART)

7.2.1 Overview

Th UART transmits and receives a character length of eight bits. For transmission, data is passed to a transmitter FIFO (first in, first out), of 32 bytes/characters in depth, from the peripheral data bus. This data is passed to the shift register and shifted serially out on the TXD pin. For reception, data is received serially from the RXD pin and stored in a receiver FIFO of 32 bytes/characters in depth. The received data is retrieved from the receiver FIFO on the peripheral data bus. The receiver and transmitter FIFOs contain a maskable interrupt that can be configured to interrupt when it reaches a certain level. The UART-generated baud rate is based upon a configurable divisor and the input clock. It can be configured to send one or two stop bits as well as odd, even, or no parity. The receiver detects framing errors, start bit errors, breaks, parity errors, and overrun errors. The fractional divider is set up by writing an INCrement and MODulo value to registers. It is important that the UART is disabled (RXE and TXE equal 0) before writing new values to the INC/MOD registers. After writing to the registers, the receiver and/or transmitter can be enabled (RXE and TXE equal 1). NOTE: When the UART is disabled (RXE and TXE equal 0), both the RX and the TX buffers are flushed, and the status register is updated. For test purposes, the RXD and TXD pins can be connected internally to each other for loop-back test.

7.2.2 Features

The UART provides the following features: • 8 data bits • 1 or 2 stop bits • Programmable parity (even, odd, and none) • Four-wire serial interface (RXD, TXD, RTS, and CTS) • Hardware flow control support for RTS and CTS signals • Sense programmable RTS/CTS pins (high true/low true) • Status flags for various flow control and FIFO states • V oting logic for improved noi se immunity (16X/8X oversampling) • Two maskable interrupt s (IPI_RXRDY , IPI_TXRDY) • Time-out interrupt timer, which times out after ei ght non-present characters (interrupt on RXRDY) • 32-byte receive FIFO and 32-byte transmit FIFO • Receiver and transmitter enable/disable • Low-power modes • Fractional divider to generate any baud rate between 1,200 baud and 1,843.2 kbaud • Software reset Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

52 MC72000 Advance Information Data Sheet MOTOROLA

7.2.3 Fractional Divider

The internal baud rate generator is shown in Figure 31. Figure 31. UART Baud Rate Generator Freescale Semiconductor, Inc.

7.2.4 General UART Definitions

These general UART definitions will help in understanding the following sections. bit must begin with a one to zero transition and is preceded by at least one bit time of logic one. to signal the end of a message or the beginning of a new message. format is one start bit followed by eight data bits (LSB first) terminated by one stop bit. is set up to expect two stop bits, and only the first stop bit is received, then this is not a framing error. an entire frame is received.An additional stop bit and parity bit may also be included. Table 26. Standard Baud Rates1

1. Fractional divider values are shown for the 16 times oversampling mode.
2. At this baud rate, only 8 x oversampling is possible because (12 MHz/921600) < 16.
3. At this baud rate, only 8 x oversampling is possible because (24 MHz/1843200) < 16.

Freescale Semiconductor, Inc.

54 MC72000 Advance Information Data Sheet MOTOROLA

Figure 32. General UART Connection

7.2.4.1 RTS — Request to Send

a transmission upon assertion or to enable a transmission upon deassertion.

7.2.4.2 CTS — Clear to Send

7.2.4.3 Transmitter

stops and waits for RTS to again become asserted (low).

7.2.4.4 Receiver

(FCp) = 0 (active low RTS/CTS signals). Freescale Semiconductor, Inc.

the RXFIFO empties below the programmed trigger level.

7.2.4.5 Receiving a Break Condition

condition is detected by the receiver, the UART will interpret this as a framing error.

7.2.4.6 Voting Logic

value, which is two out of the three samples. receiver shift register data is parallel shifted to the receiver FIFO.

7.2.5 UART Registers

The following paragraphs provide detailed descriptions of UART registers.

7.2.5.1 UART Control Register (UCON)

UCON is used to specify transmission parameters, such as flow control, stop bits, parity, and so on. Table 27. Majority Vote Results Freescale Semiconductor, Inc.

56 MC72000 Advance Information Data Sheet MOTOROLA

Hardware Functional Description 1 = Test (loop-back) mode 0 = Normal operation MRXR—Mask RXRDY Interrupt This active low bit enables an interrupt when the receiver has data in the RXFIFO above watermark, or there is data in the FIFO and the UART is idle for more than 8 frames. The fill level in the RXFIFO at which an interrupt is generated is controlled by the RXLEVEL bits. While negated, this interrupt is disabled (masked). 1 = RXRDY interrupt masked 0 = RXRDY interrupt enabled MTXR—Mask TXRDY Interrupt This active low bit enables an interrupt when the transmitter has data in the TXFIFO below the watermark or is completely empty. The fill level in the TXFIFO at which an interrupt is generated is controlled by the TXLEVEL bits. While negated, this interrupt is disabled (masked). 1 = TXRDY interrupt masked 0 = TXRDY interrupt enabled FCE—Flow Control Enable This bit controls whether the MC72000 will use flow control. When flow control is disabled, the UART will ignore the RTS input and assert the CTS pin low. 1 = Enabled 0 = Disabled FCP—Flow Control When flow control is used, this bit indicates the polarity of the RTS/CTS bits. 1 = Assert RTS to stop transmission 0 = Deassert RTS to enable transmission xTIM—Times of Oversampling The xTIM bit indicates how much oversampling will be used. 1 = 8 times oversampling 0 = 16 times oversampling SEL—GPIO Input Select The SEL bit indicates which of the MC72000 GPIO pins will be used as the RTS/RXD output signals from the UART. 1 = RTS_2/RXD_2 0 = RTS_1/RXD_1 TX_OEN_B— Tri-state enable for TXD/CTS The bit indicates: 1 = Tri-state TXD and CTS output pads 0 = Enable TXD and CTS output pads CONTX—Continuous TX (Test Mode) Only used in test mode, when this bit is enabled, the UART will continuously transmit characters. 1 = Enable 0 = Disable SB—Set Break When set, TXD is pulled low to signal a break. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Hardware Functional Description MOTOROLA MC72000 Advance Information Data Sheet 57 Preliminary 1 = Set break 0 = No break ST2—Stop Bits This bit controls the number of stop bits transmitted after a character. While HIGH, two stop bits are sent. While LOW, one stop bit is sent. This bit has no effect on the receiver which expects one or more stop bits. 1 = Two stop bits 0 = One stop bit EP—Even Parity This bit controls the sense of the parity generator and checker. While LOW, odd parity is generated and expected. While HIGH, even parity is generated and expected. This bit has no function if PEN is low. 1 = Even parity 0 = Odd parity PEN—Parity Enable This active HIGH bit controls the parity generator in the transmitter and parity checker in the receiver. While asserted, they are enabled. While negated, they are disabled. 1 = Enable parity 0 = Disable parity RXE—RX Enable This active HIGH bit enables the receiver. When the receiver is enabled, if the RXD line is already low, the receiver does not recognize break characters, since it requires a valid one-to-zero transition before it can accept any character. If disabled during a reception, the receiver will complete the current reception then disable. 1 = Receiver enabled 0 = Receiver disabled TXE—TX Enable This active HIGH bit enables the transmitter. If disabled during a transmission, the UART will immediately return TXD to idle (1). The transmitter FIFO cannot be written to when this bit is cleared. 1 = Transmitter enabled 0 = Transmitter disabled NOTE: The SEL bit is used to select be tween using the RTS_2/RXD_2 and RTS_1/RXD_1 ports on the UART module. In the MC72000, these ports are connected to the GPIO ports B and C. RTS_2/RXD_2 are connected as alternate functions to GPIO port B (GPIO_B11 and GPIO_B12) and are called UART-RTS/UART-RXD. GPIO_B11 and GPIO_B12 must be set to alternate function 2 mode in order to use RTS_2/RXD_2. RTS_1/RXD_1 are connected to pins RTS_/RXD on GPIO port C and no configuration is necessary to use these pins.

7.2.5.2 UART Status Register (USTAT)

USTAT indicates interrupts and any errors that have been detected during transmission, such as FIFO buffer overflow or underflow, parity error, and frame, start, or stop bit error. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

58 MC72000 Advance Information Data Sheet MOTOROLA

Hardware Functional Description NOTE: Bits[7:6] are cleared when the re spective condition allows it. Status bits[5:0] are cleared when the register is read. TXRdy—Transmitter is Causing an Interrupt 1 = Interrupt pending 0 = No interrupt RXRDY—Receiver is Causing an Interrupt 1 = Interrupt pending 0 = No interrupt RUE—RX FIFO Underrun Error This read-only bit indicates, while HIGH, that the RXFIFO underrun error occurred. This occurs when software reads more from the FIFO than is actually present. This bit is updated and valid for each received character. This bit is set for the last character written to the FIFO indicating that all characters following this character will be ignored if a write is not performed by software. The RUE bit is cleared by UART reset or by reading the USTAT register. 1 = Error occurred 0 = No error ROE—RX FIFO Overrun Error This read-only bit indicates, while HIGH, that the RXFIFO ignored data to prevent overwriting the data in the FIFO. Under normal circumstances, this bit should never be set. It indicates that the user’s software is not keeping up with the incoming data rate. This bit is updated and valid for each received character. This bit is set for the last character written to the FIFO indicating that all characters following this character will be ignored if a read is not performed by software. The ROE bit is cleared by UART reset or by reading the USTAT register. 1 = Error occurred 0 = No error TOE—TX FIFO Overrun Error This flag bit is set when the UDATA register is filled and ready to transfer to the TXFIFO register and the register is already full. This error occurs when the software writes more data than is room for in the FIFO. The transmit data is not transferred in this case. A transmit overrun error does not cause any interrupts. The TOE bit is cleared by UART reset or by reading the USTAT register. 1 = Error occurred 0 = No error USTATBase + $004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 TXRD Y RXRD Y RUE ROE TOE FE PE SE W RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = writes have no effect and terminate without transfer error exception Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Hardware Functional Description MOTOROLA MC72000 Advance Information Data Sheet 59 Preliminary FE—Frame/Stop Bit Error This read-only bit indicates, while HIGH, that the current character had a framing error (missing stop bit or break condition). The data is possibly corrupted. This bit is updated for each character read from the FIFO. The FE bit is cleared by UART reset or by reading the USTAT register. 1 = Framing error occurred 0 = No framing error PE—Parity Error This read-only bit indicates, while HIGH, that the current character was detected with a parity error. The data is possibly corrupted. This bit is updated for each character read from the FIFO. While parity is disabled, this bit always reads zero. The PE bit is cleared by UART reset or by reading the USTAT register. 1 = Parity error occurred 0 = No parity error SE—Start Bit Error This read-only bit indicates, while HIGH, that the current character had a framing error (missing start bit.) The data is possibly corrupted. This can occur when a start bit (RXD = 0) is found, but is not verified at the center of the bit (for example, glitch). This bit is updated for each character read from the FIFO. The SE bit is cleared by UART reset or by reading the USTAT register. 1 = Start bit error occurred 0 = No start bit error

7.2.5.3 UART Data Register (UDATA)

UDATA fills the UART transmit FIFO buffer with bytes that are to be transmitted, and to read the received bytes from the UART receive FIFO buffer. It is possible to read/write 1 byte per access. RXDATA[7:0]—Received Byte This bit field contains the 8-bit data that has been received. TXDATA[7:0]—Byte To Transmit This bit field contains the 8-bit data to be transmitted.

7.2.5.4 UART Buffer Control Registers

The UART buffers use threshold values to generate interrupts. These thresholds can be used to specify that an interrupt should be generated before the transmit FIFO has become completely empty, or some time UDATABase + $008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 RXDATA W TXDATA RST 0 0 0 0 0 0 0 0 Undefined = writes have no effect and terminate without transfer error exception Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

60 MC72000 Advance Information Data Sheet MOTOROLA

Hardware Functional Description before the receive FIFO has been completely filled. These early warnings allow relaxed interrupt response times.

7.2.5.4.1 UART RXBUFFER C ontrol Register (URXCON)

The RXLEVEL register is used to set the threshold for the interrupt that is generated when the receive buffer is full. The RXFULLCNT register contains the number of bytes that are currently buffered in the receive FIFO. RXFULLCNT[5:0]—Receive buffer full level This value indicates the number of bytes currently buffered in the receive FIFO buffer. The number of bytes is between 0 (empty) and 32 (full) bytes. RXLEVEL[5:0]—Receive buffer level When the number of bytes in the receive FIFO exceeds the value specified by RXLEVEL, an interrupt is generated.

7.2.5.4.2 UART TXBUFFER Co ntrol Register (UTXCON)

UTXCON sets the threshold for the interrupt that is generated when the transmit buffer becomes empty. The TXEMPTYCNT register contains the number of bytes that can still be written to the UART transmit FIFO. Data can be written to the transmit buffer while this number is non-zero. TXEMPTYCNT[7:0]—Transmit Buffer Empty Level This value indicates the number of empty bytes currently available in the transmit FIFO buffer. The number of free bytes is between 0 (full) and 32 (empty) bytes. URXCONBase + $00C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 RXFULLCNT W RXLEVEL RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = writes have no effect and terminate without transfer error exception UTXCON Base + $010 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 TXEMPTYCNT W TXLEVEL RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = writes have no effect and terminate without transfer error exception Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Hardware Functional Description MOTOROLA MC72000 Advance Information Data Sheet 61 Preliminary TXLEVEL[7:0]—Transmit Buffer Level When the number of free bytes in the transmit FIFO buffer exceeds the value specified by TXLEVEL, an interrupt is generated.

7.2.5.4.3 UART CTS Level C ontrol Register (UCTS)

UCTS sets the threshold for the CTS control flow signal. If the remote UART continues to send limited amounts of data after detecting the deasserted CTS signal, the local receive buffer can handle the additional data if CTS_LEVEL is set to a suitable value. CTS_LEVEL[7:0]—CTS Buffer Level When the number of bytes in the receiver (RX) FIFO exceeds this value, the CTS signal is deasserted.

7.2.5.5 UART Baud Rate Divider Register (UBR)

The fractional divider registers are used to select the receive and transmit baud rate. The following sections describe the fractional divider registers. The FRACDIV_DIV register is used to select the divisor for the fractional division divider. See Section 7.2.3, “Fractional Divider,” for an explanation of the value to be written to the register. The FRACDIV_INC register is used to select the modulus value for the fractional division divider. See Section 7.2.3, “Fractional Divider,” for an explanation of the value to be written to the register. UBRINC — INC Value This value is used to select the baud rate. See Section 7.2.3, “Fractional Divider,” for more information. UBRMOD — MOD Value This value is used to select the baud rate. See Section 7.2.3, “Fractional Divider,” for more information. UCTSBase + $014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W RST 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 CTS_LEVEL W CTS_LEVEL RST 0 0 0 0 0 0 0 0 = writes have no effect and terminate without transfer error exception UBR Base + $018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R UBRINC W UBRINC RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R UBRMOD W UBRMOD RST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = writes have no effect and terminate without transfer error exception Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

62 MC72000 Advance Information Data Sheet MOTOROLA

7.2.6 FIFO Operation

The operation of the transmit and receive FIFOs is shown in Figure 33. Figure 33. RX and TX FIFO-Related Levels

7.2.7 Flow Control

The operation of the transmit and receive Flow Control is shown in Figure 34. so the remote unit can transmit when it has data. pin is 0 when control[FCP]=0).

32 Empty

24 TXLEVEL (Write only)

0 Full

28 CTSLEVEL (Write only)

24 RXLEVEL (Write only)

Freescale Semiconductor, Inc.

Figure 34. Flow Control

7.3 Configurable Serial Peripheral Interface (CSPI)

and enables fast data communication with a fewer number of software interrupts.

7.3.1 Features

7.3.2 Modes of Operation

(FCp) = 0 (active low RTS/CTS signals). Freescale Semiconductor, Inc.

64 MC72000 Advance Information Data Sheet MOTOROLA

7.3.3 Block Diagram

Figure 35 shows the CSPI block diagram. Figure 35. CSPI Block Diagram Freescale Semiconductor, Inc.

7.3.4 Signal Description

Table 28 shows the signals used to control the serial peripheral interface master.

7.3.5 Detailed Signal Descriptions

The following section provides detailed signal descriptions.

7.3.5.1 SPI_CK — SPI CLOCK

the master and slave CSPIs exchange data in BITCOUNT serial clock cycles. regardless of the state of the GPIO data direction register of the shared I/O port.

7.3.5.2 MISO — SPI Master In/Slave Out

simultaneously receives data on its MISO pin and transmits data from its MOSI pin. multiple-slave system, a logic one on the SS_B pin puts the MISO pin in a high-impedance state. regardless of the state of the GPIO data direction register of the shared I/O port.

7.3.5.3 MOSI — SPI Master Out/Slave In

simultaneously transmits data from its MOSI pin and receives data on its MISO pin. regardless of the state of the GPIO data direction register of the shared I/O port. Table 28. Serial Peripheral Interface Master Control Signals mode, SPI_CK is an input clock signal to the CSPI. Freescale Semiconductor, Inc.

66 MC72000 Advance Information Data Sheet MOTOROLA

7.3.5.4 SS_B — SPI Slave Select

pin is always configured as an input. It cannot be used as a general purpose I/O. transmission. However, it can remain low between word transmissions for the PHA = 0 format. regardless of the state of the GPIO data direction register of the shared I/O port.

7.3.5.5 DATAREADY_B — SPI Data Ready

is ready to deliver some new data to the master. DATAREADY_B pin regardless of the state of the GPIO data direction register of the shared I/O port.

7.3.6 Memory Map and Registers

be written with zero for future compatibility. Table 29. CSPI Memory Map Freescale Semiconductor, Inc.

7.3.7 Register Descriptions

7.3.7.1 RX Data Register (RXDATAREG)

Figure 36. RX Data Register (RXDATAREG) DATA has no meaning if the RR bit in the interrupt control/status register is clear.

7.3.7.2 TX Data Register (TXDATAREG)

Figure 37. TX Data Register (TXDATAREG) TXDATAREG is a 32-bit write-only data register. The lower 16 bits is the top of the 8 x 16 TXFIFO. bit is clear. The upper 16 bits are reserved bits and are always read as 0. Freescale Semiconductor, Inc.

68 MC72000 Advance Information Data Sheet MOTOROLA

7.3.7.3 Control Register (CONTROLREG)

Figure 38. Control Register (CONTROLREG) when SPIEN = 1 to ensure that the internal counters and control logic are properly reset. the DRCTL[2:0] bit rate encoding. they are don’t care. Table 31 shows the SPIRDY[1:0] encoding. This bit selects the CSPI mode. Table 30. DRCTL[2:0] Bit Rate Encoding

000 Divide by 4

001 Divide by 8

010 Divide by 16

011 Divide by 32

100 Divide by 64

101 Divide by 128

110 Divide by 256

111 Divide by 512

Table 31. SPIRDY Control Encoding

00 Don’t care DATAREADY_B

01 Falling edge trigger input

10 Active low level trigger input

11 Reserved

Freescale Semiconductor, Inc.

This bit enables the serial peripheral interface. This bit must be asserted before an exchange is initiated. is set is not allowed and may cause the CSPI to enter an invalid state. enabled. This bit is cleared automatically when all data in the TXFIFO and shift register is shifted out. In slave mode, this bit must be clear. This bit selects the polarity of SS_B signal in both master and slave mode. This bit selects the output waveform for SS_B signal in master mode. This bit controls RXFIFO advancement in slave mode. This bit controls the clock/data phase relationship. This bit controls the polarity of the SCLK signal. This bit field selects the length of the transfer. A maximum of 16 bits can be transferred. bits (n = BITCOUNT) are shifted out. The next 16-bit word is then loaded to shift register. loaded to the RXFIFO. When the SSCTL bit is 1, this field is a don’t care. Table 32 shows the BITCOUNT[3:0] encoding. Table 32. BITCOUNT[3:0] Encoding Freescale Semiconductor, Inc.

70 MC72000 Advance Information Data Sheet MOTOROLA

7.3.7.4 Interrupt Control/Status Register (INTREG)

Figure 39. Interrupt Control/Status Register (INTREG) INTREG is a 32-bit register. The high 16 bits are reserved bits and are always read as 0. The TE bit is forced to 0 when the SPIEN is zero and will change to 1 after SPIEN is set. To make sure no data transaction is on-going, read the XCH bit in the CONTROLREG. The TH bit is forced to 0 when the SPIEN is zero and will change to 1 after SPIEN is set. RR—RXFIFO Data Ready Status. Table 32. BITCOUNT[3:0] Encoding (Continued) Freescale Semiconductor, Inc.

Hardware Functional Description MOTOROLA MC72000 Advance Information Data Sheet 71 Preliminary RO—RXFIFO Overflow This bit indicates that the RXFIFO has overflowed. At least one new written data word is lost. The RO flag is automatically cleared after a data read. 1 = RXFIFO has overflowed At least one data word in the RXFIFO is overwritten 0 = RXFIFO has not overflowed BO—Bit Count Overflow This bit is set when the CSPI is in Slave CSPI FIFO advanced by SS_B rising edge mode and the slave is receiving more than 16 bits in one burst. This bit is cleared after a data read from the SPIRXD register. Because there are no error bits associated with individual RXFIFO data words this means that the entire RXFIFO contents are suspect. 1 = At least one data word in the RXFIFO had a bit count overflow error 0 = No bit count overflow TEEN—TXFIFO Empty Interrupt Enable 1 = Enable 0 = Disable THEN—TXFIFO Half Interrupt Enable 1 = Enable 0 = Disable TFEN—TXFIFO Full Interrupt Enable 1 = Enable 0 = Disable RREN—RXFIFO Data Ready Interrupt Enable 1 = Enable 0 = Disable RHEN—RXFIFO Half Interrupt Enable 1 = Enable 0 = Disable RFEN—RXFIFO Full Interrupt Enable 1 = Enable 0 = Disable ROEN—RXFIFO Overflow Interrupt Enable 1 = Enable 0 = Disable BOEN—Bit Count Overflow Interrupt Enable 1 = Enable 0 = Disable Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

72 MC72000 Advance Information Data Sheet MOTOROLA

7.3.7.5 CSPI Test Register (TESTREG)

Figure 40. CSPI Test Register (TESTREG) TESTREG is a 32-bit register that controls how the serial peripheral interface operates and reports status. The high 16 bits are reserved bits and are always read as 0. This bit is used for test purposes only. This bit is used for test purposes only. This bit field indicates the state machine status. These bits are used for test purposes only. Table 33. SSTATUS[3:0] Encoding

0000 IDLE waiting for EXCH or SLAVE_ENABLE

0001 EXCH Waiting for DATAREADY_B

0010 SSB0 Set SS_B active

0011 T2 SS_B output low to first SPI_CK edge

0100 BUSY Delay SPI_CK edge

0101 ACTIVE Start data

0110 WAITCNT Count data bits

0111 CK2SSB1 Last SCLK edge to SS_B output high delay

1000 T3 Insert SS_B high value

1001 SSB1 Slave Sele ct is disabled

1010 WAITCNT2 SS_B output pulse width

1011 READY Wait for DATAREADY_B active

Freescale Semiconductor, Inc.

7.3.7.6 CSPI Sample Period Control Register (PERIODREG)

Figure 41. CSPI Sample Period Control Register (PERIODREG) PERIODREG is a 32-bit register that controls the time inserted between data transactions in master mode. Table 34. RXCNT[3:0] Encoding

0000 RXFIFO is empty

Table 35. TXCNT[3:0] Encoding

0000 TXFIFO is empty

Freescale Semiconductor, Inc.

74 MC72000 Advance Information Data Sheet MOTOROLA

clock but each 32 kHz clock will not produce a new transmitted data word. Table 36 shows WAIT bit field encoding.

7.3.7.7 CSPI Soft Reset Register (RESETREG)

Figure 42. CSPI Soft Reset Register (RESETREG) CSPI are reset including the CONTROLREG. attempt is made to write the CONTROLREG to initiate CSPI operation after the START bit is written.

7.3.8 Functional Description

7.3.8.1 General

peripheral devices. Software can poll the CSPI status flags or CSPI operation can be interrupt-driven. Figure 43 shows the generic CSPI timing. Table 36. WAIT Encoding Freescale Semiconductor, Inc.

slave is enabled to prevent SPI_CK from appearing as a clock edge. The following section describes the operation of the CSPI module. Figure 43. CSPI Generic Timing The CSPI does not consume any power when it is disabled.

7.3.8.2 Phase/Polarity Configurations

The serial peripheral interface master uses the SPI_CK signal to transfer data in and out of the shift register. serial peripheral devices on the market.

7.3.8.3 Master Mode Operation

program the sample period control register to a fixed data transfer rate. MOSI pin under the control of the serial clock. the SPI_CK pin, the baud rate generator of the master also controls the shift register of the slave peripheral. Freescale Semiconductor, Inc.

76 MC72000 Advance Information Data Sheet MOTOROLA

bit by reading the RX data register.

7.3.8.4 Slave Mode Operation

be at logic zero. SS_B must remain low until the transmission is complete. increments the TXFIFO and RXFIFO. must read the receive data FIFO register before another full word enters the shift register. less than one-fourth the bus speed.

7.3.9 Timing Diagrams

Figure 44. Master CSPI Timing Using DATAREADY_B Edge Trigger Freescale Semiconductor, Inc.

78 MC72000 Advance Information Data Sheet MOTOROLA

7.4 Synchronous Serial Interface (SSI)

7.4.1 Overview

transmitter and receiver sections with independent clock generation and frame synchronization.

7.4.2 Features

7.4.3 Block Diagram

and frame sync generation for the transmit and receive sections. 4.WAIT = Number of sysclk or 32.768 kHz clocks per sample period control register. Table 37. CSPI Timing Freescale Semiconductor, Inc.

Figure 49. SSI Block Diagram Freescale Semiconductor, Inc.

80 MC72000 Advance Information Data Sheet MOTOROLA

7.4.4 Signal Descriptions

7.4.4.1 External Signals

7.4.4.1.1 STCK — SS I Transmit Clock

transmit and receive sections.

7.4.4.1.2 STFS — SSI Transmit Frame Sync

frame sync can occur one bit before the transfer of data or right at the start of the data transfer.

7.4.4.1.3 SRCK — SSI Receive Clock

reception of data, otherwise, it is inactive (low). In synchronous mode, this pin is not used and can be configured as a GPIO pin.

7.4.4.1.4 SRFS — SSI Receive Frame Sync

frame sync can occur one bit before the transfer of data or right at the start of the data transfer. In synchronous mode, this pin is not used and can be configured as a GPIO pin.

7.4.4.1.5 STXD — SSI Transmit Data

data is being transmitted and is inactive (high-Z) between data word transmissions.

7.4.4.1.6 SRXD — SSI Receive Data

This pin is used to bring serial data into the receive data shift register (RXSR). Table 38. Signal Properties STXD output SSI Transmit Data high-Z Since SSIEN bit of STXCR register is reset to 0. Freescale Semiconductor, Inc.

Hardware Functional Description MOTOROLA MC72000 Advance Information Data Sheet 81 Preliminary

7.4.4.2 SSI Configurations

Figure 50 shows the main SSI configurations. These pins support all transmit and receive functions with continuous or gated clock as shown. Section 7.4.6, “Functional Description,” describes the clock, frame sync, and data timing relationships in each of the modes available. Note that gated clock implementations do not require the use of the frame sync pins. In this case, these pins can be used as GPIO pins, if needed. NOTE: The GPIO is a separate module which alternatively controls the function and state of the I/O pins. See the GP IO module definition for alternate functions of the I/O pins defined here. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

82 MC72000 Advance Information Data Sheet MOTOROLA

Figure 50. Synchronous SSI Configurations—Continuous and Gated Clock Freescale Semiconductor, Inc.

7.4.5 Memory Map and Registers

7.4.5.1 SSI Memory Map

Table 39 shows the SSI memory map. Note there are four registers that are not accessible. All registers in the SSI are 16-bit accessible only.

7.4.5.2 Register Descriptions

The following sections describe the SSI registers.

7.4.5.2.1 SSI Transmit Data Register (STX)

of the STX register. The unused bits (least significant portion) of the STX register are ignored. If the transmit interrupt is enabled, the interrupt is asserted when the STX register becomes empty (TDE=1). Enable SSI (SSIEN=1) before writing to STX. Table 39. SSI Memory Map Freescale Semiconductor, Inc.

84 MC72000 Advance Information Data Sheet MOTOROLA

Figure 51. STX Register Diagram

7.4.5.2.2 SSI Transmit FI FO Register (TXFIFO)

this register is bypassed and the contents of STX are transferred into the TXSR. FIFO falls below the selected threshold. When both TXFIFO and STX are full, any further write will overwrite the contents of TXFIFO and STX. Enable SSI before writing to TXFIFO and STX.

7.4.5.2.3 SSI Transmit Shift Register (TXSR)

the SHFD bit of the SCR2 is cleared. If this bit is set, the least significant bit (LSB) is shifted out first. See Figure 52 and Figure 53 for more information. Freescale Semiconductor, Inc.

Figure 52. Transmit Data Path (TSHFD=0) Figure 53. Transmit Data Path (TSHFD=1)

7.4.5.2.4 SSI Receive Data Register (SRX)

significant portion) are read as 0s. If the receive data full interrupt is enabled, the interrupt is asserted whenever the SRX register becomes full. Freescale Semiconductor, Inc.

86 MC72000 Advance Information Data Sheet MOTOROLA

Figure 54. SRX Register Diagram

7.4.5.2.5 SSI Receive FI FO Register (RXFIFO)

then held in the FIFO if the data in the SRX has not yet been read. the receive shift register (RXSR) data is automatically transferred into the SRX.

7.4.5.2.6 SSI Receive Shift Register (RXSR)

shifted in depending on the WL[1:0] control bits. For receiving 8, 10, or 12 bits data, LSB bits are set to zero. See Figure 55 and Figure 56 for more information. Figure 55. Receive Data Path (RSHFD=0) Freescale Semiconductor, Inc.

Figure 56. Receive Data Path (RSHFD=1)

7.4.5.2.7 SSI Transmit and Receive Control Registers (STXCR, SRXCR)

Figure 57. STXCR Register Diagram Figure 58. SRXCR Register Diagram of the prescaler for those cases where a slower bit clock is desired. Freescale Semiconductor, Inc.

88 MC72000 Advance Information Data Sheet MOTOROLA

0 = When the PSR bit is cleared, the fixed prescaler is bypassed. of 8, 10, 12, or 16 bits can be selected. Table 40 shows WL[1:0] bit field encoding. control the frame sync pulse length when the TFSL bit is cleared. periodic data word transfer. A bit-length sync must be used in this case. special case (on demand mode) that is not supported in this implementation. Table 40. WL[1:0] Encoding Freescale Semiconductor, Inc.

generate different bit clocks.

7.4.5.2.8 SSI Control/St atus Register (SCSR)

SSI Status flag is updated when SSI is enabled. or write to either the SRX or STX register. Figure 59. SCSR Register Diagram cleared, data is received MSB first. If the RSHFD bit is set, the LSB is received first. Table 41. SSI Bit Clock as a Function of Peripheral Clock and Prescale Modulus Freescale Semiconductor, Inc.

90 MC72000 Advance Information Data Sheet MOTOROLA

Hardware Functional Description NOTE: The CODEC device labels the MSB as bit 0, whereas the SSI labels the LSB as bit 0. Therefore, when using a standard CODEC, the SSI MSB (or CODEC bit 0) is shifted out first, and the RSHFD bit should be cleared. RSCKP—Receive Clock Polarity This bit controls which bit clock edge is used to latch in data for the receive section. 1 = The rising edge of the clock is used to latch the data in 0 = The data is latched in on the falling edge of the clock RDMAE—Receive DMA Enable This bit is Reserved and should always be written 0. TDMAE—Transmit DMA Enable This bit is Reserved and should always be written 0. RFSI—Receive Frame Sync Invert This bit selects the logic of frame sync I/O for the receive section. 1 = The frame sync is active low 0 = The frame sync is active high RFSL—Receive Frame Sync Length This bit selects the length of the frame sync signal to be generated or recognized for the receive section. See Figure 60 for an example timing diagram of the FS options. 1 = A one clock bit-long frame sync is selected 0 = A one word-long frame sync is selected The length of a word-long frame sync is the same as the length of the data word selected by WL[1:0]. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Hardware Functional Description MOTOROLA MC72000 Advance Information Data Sheet 91 Preliminary REFS—Receive Early Frame Sync This bit controls when the frame sync is initiated for the receive section. See Figure 60 for an example timing diagram of the FS options. 1 = The frame sync is initiated one bit before the data is received The frame sync is disabled after one bit-for-bit length frame sync and after one word-for-word length frame sync. 0 = When the REFS bit is cleared, the frame sync is initiated as the first bit of data is received RDR—Receive Data Ready Flag This flag bit is set when receive data register (SRX) or receive FIFO (RXFIFO) is loaded with a new value. RDR is cleared when the CPU reads the SRX register. If RXFIFO is enabled, RDR is cleared when receive FIFO is empty. If the RIE bit is set, a receive data interrupt request is issued when the RDR bit is set. The interrupt request vector depends on the state of the receiver overrun (ROE) bit (in the SCSR). The RDR bit is cleared by POR and SSI reset. TDE—Transmit Data Register Empty This flag bit is set when there is no data waiting to be transferred to the TXSR register. If the transmit FIFO (TXFIFO) is enabled, this occurs when there is at least one empty slot in STX or TXFIFO. If the TXFIFO is not enabled, this occurs when the STX is empty, that is, when the contents of the STX register are transferred into the transmit shift register (TXSR). When set, the TDE bit indicates that data should be written to the STX register or to the STSR before the transmit shift register becomes empty, or an underrun error will occur. The TDE bit is cleared when data is written to the STX register or to the STSR to disable transmission of the next time slot. If the TIE bit is set, an SSI transmit data interrupt request is issued when the TDE bit is set. The vector of the interrupt depends on the state of the TUE bit (in the SCSR). The TDE bit is set by power-on and SSI reset. ROE—Receive Overrun Error This flag bit is set when the receive shift register (RXSR) is filled and ready to transfer to the SRX register or the RXFIFO register (when enabled), and these registers are already full. If the receive FIFO is enabled, this is indicated by the receive FIFO full (RFF) bit else this is indicated by the receive data ready (RDR) bit being set. The RXSR is not transferred in this case. NOTE: When using the RXFIFO with a watermark other than 8, the ROE bit does not mean that data has been lost. The RXCNT field of the SFCSR should be checked to determine the likelihood of actual data loss. A receive overrun error does not cause any interrupts. However, when the ROE bit is set, it causes a change in the interrupt vector used, allowing the use of a different interrupt handler for a receive overrun condition. If a receive interrupt occurs with the ROE bit set, the receive data with exception status interrupt is generated. If a receive interrupt occurs with the ROE bit cleared, the receive data interrupt is generated. The ROE bit is cleared by power-on or SSI reset and is cleared by reading the SCSR with the ROE bit set, followed by reading the SRX register. Clearing the RE bit does not affect the ROE bit. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

92 MC72000 Advance Information Data Sheet MOTOROLA

Hardware Functional Description TUE—Transmitter Underrun Error This flag bit is set when the TXSR is empty (no data to be transmitted), as indicated by the TDE bit being set, and a transmit time slot occurs. When a transmit underrun error occurs, the previously sent data is retransmitted. A transmit time slot in the normal mode occurs when the frame sync is asserted. In network mode, each time slot requires data transmission and, therefore, may cause a TUE error. The TUE bit does not cause any interrupts. However, the TUE bit does cause a change in the interrupt vector used for transmit interrupts so that a different interrupt handler can be used for a transmit underrun condition. If a transmit interrupt occurs with the TUE bit set, the transmit data with exception status interrupt is generated. If a transmit interrupt occurs with the TUE bit cleared, the transmit data interrupt is generated. The TUE bit is cleared by power-on or SSI reset. The TUE bit is also cleared by reading the SCSR with the TUE bit set, followed by writing to the STX register or to the STSR. TFS—Transmit Frame Sync When set, this flag bit indicates that a frame sync occurred during transmission of the last word written to the STX register. As shown in Figure 60b, data written to the STX register during the time slot when the TFS bit is set is transmitted during the second time slot (in network mode) or in the next first time slot (in normal mode). In network mode, the TFS bit is set during transmission of the first slot of the frame. It is then cleared when starting transmission of the next slot. The TFS bit is cleared by power-on or SSI reset. RFS—Receive Frame Sync When set, this flag bit indicates that a frame sync occurred during receiving of the next word into the SRX register, as shown in Figure 60c. In network mode, the RFS bit is set while the first slot of the frame is being received. It is cleared when the next slot of the frame begins to be received. The RFS bit is cleared by power-on or SSI reset. RFF—Receive FIFO Full This flag bit is set when the receive section is programmed with the receive FIFO enabled, and the data level in the RXFIFO reaches the selected receive FIFO watermark (RFWM) threshold. When set, RFF indicates that data can be read via the SRX register. NOTE: An interrupt is only generated if both the RFF and RIE bits are set if RXFIFO is enabled. The RFF bit is cleared in normal operation by reading the SRX register. The RFF is also cleared by power-on reset or disabling the SSI. When RXFIFO is completely full, all further received data is ignored until data is read. TFE—Transmit FIFO Empty This flag bit is set when the transmit section is programmed with the TXFIFO enabled and the data level in the TXFIFO falls below the selected transmit FIFO watermark (TFWM) threshold. When set, the TFE bit indicates that data can be written to the TXFIFO register. The TFE bit is cleared by writing data to the STX register until the TXFIFO data content level reaches the watermark level. NOTE: An interrupt is generated only if bo th the TFE and the TIE bits are set if transmit FIFO is enabled. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

The TFE bit is set by power-on reset and when SSI is disabled. Figure 60. Frame Sync Timing Options

7.4.5.2.9 SSI Contro l Register 2 (SCR2)

can function, the chip level interrupt priority register (IPR) must be set to enable SSI interrupts. described in the following sections. Freescale Semiconductor, Inc.

94 MC72000 Advance Information Data Sheet MOTOROLA

Figure 61. SCR2 Register Diagram depends on whether the receive FIFO is enabled or not. clears the RFF bit, thus clearing the interrupt. these interrupts are generated. interrupt trigger depends on whether the transmit FIFIO is enabled or not. One value can be written to the STX register when this interrupt occurs. Table 42. SSI Receive Data Interrupts1 1.See Table 37 for a complete list of interrupts. Freescale Semiconductor, Inc.

which these interrupts are generated and lists the interrupt vectors. This control bit enables the receive portion of the SSI. to last bit, then the word will be received. It is recommended to clear this bit when clearing SSIEN. (TXSR) and also enables the internal gated clock. 1 = On the next frame boundary, the transmit portion of the SSI is enabled. 0 = Transmitter continues to send the data currently in the TXSR and then disables the transmitter. the TDE bit is cleared but data is not transferred to the TXSR. during any valid time slots. This bit should be cleared when clearing SSIEN. Table 43. SSI Transmit Data Interrupts1 1.See Table 37 for a complete list of interrupts. Freescale Semiconductor, Inc.

96 MC72000 Advance Information Data Sheet MOTOROLA

This control bit enables the FIFO register for the receive section. generated when enabled by the RIE bit. by the SSI (interrupts need to be enabled). This control bit enables the FIFO register for the transmit section. 0 = FIFO register is not used. 1 = Clock is generated internally and output to the SRCK pin. drive this pin to clock the RXSR. Table 44 shows the clock pin configuration options. RXDIR and SYN must both be high for the SSI to be in gated clock mode. This control bit selects the direction and source of the clock used to clock the TXSR. 1 = Clock is generated internally and is output to the STCK pin. drive this pin to clock the TXSR. Table 44 shows the clock configuration options. sections share a common clock pin and frame sync pin. Table 44. Clock Pin Configuration Freescale Semiconductor, Inc.

Hardware Functional Description MOTOROLA MC72000 Advance Information Data Sheet 97 Preliminary Table 44 shows the clock configuration options. TSHFD—Transmit Shift Direction This bit controls whether the MSB or LSB is transmitted first for the transmit section. 1 = LSB is transmitted first. 0 = Data is transmitted MSB first. NOTE: The CODEC device labels the MSB as bit 0, whereas the SSI labels the LSB as bit 0. Therefore, when using a standard CODEC, the SSI MSB (or CODEC bit 0) is shifted out first, and the TSHFD bit should be cleared. TSCKP—Transmit Clock Polarity This control bit determines which bit clock edge is used to clock out data in the transmit section. 1 = Falling edge of the bit clock is used to clock the data out. 0 = Data is clocked out on the rising edge of the bit clock. SSIEN—SSI Enable This control bit enables and disables the SSI. 1 = SSI is enabled. When enabled, causes an output frame sync to be generated when set up for internal frame sync or causes the SSI to wait for the input frame sync when set up for external frame sync. 0 = SSI is disabled and held in a reset condition. When disabled, all output pins are tri-stated, the status register bits are preset to the same state produced by the power-on reset, and the control register bits are unaffected. The contents of the STX, TXFIFO, and RXFIFO are cleared when this bit is reset. When SSI is disabled, all internal clocks are disabled except clocks required for register access. When clearing SSIEN, it is recommended to also clear RE and TE. NET—Network Mode This control bit selects the operational mode of the SSI. 1 = Network mode is selected. 0 = Normal mode is selected. TFSI—Transmit Frame Sync Invert This control bit selects the logic of frame sync I/O. 1 = Frame sync is active low. 0 = Frame sync is active high. TFSL—Transmit Frame Sync Length This control bit selects the length of the frame sync signal to be generated or recognized. See Figure 60 for an example timing diagram of the FS options. 1 = A one-clock-bit-long frame sync is selected. 0 = A one-word-long frame sync is selected. The length of this word-long frame sync is the same as the length of the data word selected by WL[1:0]. The frame sync is deasserted after one bit for bit length frame sync and after one word for word length frame sync. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

98 MC72000 Advance Information Data Sheet MOTOROLA

for an example timing diagram of the FS options. 1 = Frame sync is initiated one bit before the data is transmitted. 0 = Frame sync is initiated as the first bit of data is transmitted.

7.4.5.2.10 SSI Time Sl ot Register (STSR)

avoiding overflow/underflow during inactive time slots. Figure 62. STSR Register Diagram

7.4.5.2.11 SSI FIFO Control/ Status Register (SFCSR)

of the amount of data contained in each FIFO. Figure 63. SFCSR Register Diagram RFCNT[3:0] bit field encoding. Table 45. RFCNT[3:0] Encoding Freescale Semiconductor, Inc.

TFCNT[3:0] bit field encoding. RFWM[3:0] bit field encoding and Table 48 shows the status of RFF for all data levels of the RXFIFO. Table 46. TFCNT[3:0] Encoding Table 47. RFWM[3:0] Encoding

0000 Reserved

0001 RFF set when at least one data word has been written to the RXFIFO. 0010 RFF set when 2 or more data words have been written to the RXFIFO. 0011 RFF set when 3 or more data words have been written to the RXFIFO. 0100 RFF set when 4 or more data words have been written to the RXFIFO. 0101 RFF set when 5 or more data words have been written to the RXFIFO. 0110 RFF set when 6 or more data words have been written to the RXFIFO. 0111 RFF set when 7 or more data words have been written to the RXFIFO. 1000 RFF set when 8 data words have been written to the RXFIFO. Table 45. RFCNT[3:0] Encoding (Continued) Freescale Semiconductor, Inc.

100 MC72000 Advance Information Data Sheet MOTOROLA

bit field encoding and Table 50 shows the status of TFE for all data levels of the TXFIFO. Table 48. Status of Receive FIFO Full Flag Table 49. TFWM[3:0] Encoding 0001 TFE set when there is 1 em pty slot in TXFIFO (default). Transmit FIFO empty is set when TXFIFO <= 7 data. 0010 TFE set when there are 2 or more empty slots in TXFIFO. Transmit FIFO empty is set when TXFIFO <= 6 data. 0011 TFE set when there are 3 or more empty slots in TXFIFO. Transmit FIFO empty is set when TXFIFO <= 5 data. 0100 TFE set when there are 4 or more empty slots in TXFIFO. Transmit FIFO empty is set when TXFIFO <= 4 data. 0101 TFE set when there are 5 or more empty slots in TXFIFO. Transmit FIFO empty is set when TXFIFO <= 3 data. 0110 TFE set when there are 6 or more empty slots in TXFIFO. Transmit FIFO empty is set when TXFIFO <= 2 data. 0111 TFE set when there are 7 or more empty slots in TXFIFO. Transmit FIFO empty is set when TXFIFO = 1 data. 1000 TFE set when there are 8 empty slots in TXFIFO. Transmit FIFO empty is set when TXFIFO = 0 data. Table 50. Status of Transmit FIFO Empty Flag Freescale Semiconductor, Inc.

7.4.5.2.12 SSI Test Register (STR)

This register controls test features and is not normally used. Figure 64. STR Register Diagram 1 = SSI test features enabled. 0 = SSI test features disabled. 1 = Enables RX_CLK loop back to RX_CLK. 1 = Enables RX_FRM loop back to TX_FRM. These bit field indicates the receiver state machine status. These bits are used for test purpose only. 1 = Enables TXD loop back to RXD. 1 = Enables TX_CLK loop back to RX_CLK. 1 = Enables TX_FRM loop back to RX_FRM. This bit field indicates the transmitter state machine status. These bits are used for test purposes only. Table 50. Status of Transmit FIFO Empty Flag (Continued) Freescale Semiconductor, Inc.

102 MC72000 Advance Information Data Sheet MOTOROLA

7.4.5.2.13 SSI Option Register (SOR)

Figure 65. SOR Register Diagram This control bit selects the direction and source of the receive frame sync signal. 1 = Receive frame sync is generated internally and output to the SRFS pin. This control bit selects the direction and source of the transmit frame sync signal. 1 = Transmit frame sync is generated internally and output to the STFS pin. This bit is used to initialize the state machine to reset state. 1 = Reset the TX and RX state machines. Setting this bit must be followed by a write of zero before the state machine with operate. 0 = State machine is allowed to operate. This bit field controls the number of wait states to be added to the transaction between the CPU and SSI. The MC72000 does not use wait states and as such these should always be written 0. 1 = Resets the accumulation of data in SRX and RXFIFO on frame synchronization. 0 = Data must be read to be cleared from the registers.

7.4.5.2.14 Transmit Slot Mask Registers (TSMA, TSMB)

Figure 66. TSMA Register Diagram Freescale Semiconductor, Inc.

Figure 67. TSMB Register Diagram generates the appropriate transmit status. disable control bit for transmission in slot number N. 1 = Transmit sequence proceeds normally. slot number N and flags are set appropriately. 0 = Transmit data signal of the transmitter is tri-stated during transmit time slot number N. Data is not transferred to the TXSR and, therefore, transmit status flags are not changed. is not affected by the new TSM setting. If the TSM is read, it shows the current setting. how many of these control bits are actually used.

7.4.5.3 Receive Slot Mask Registers (RSMA, RSMB)

Figure 68. RSMA Register Diagram Freescale Semiconductor, Inc.

104 MC72000 Advance Information Data Sheet MOTOROLA

Figure 69. RSMB Register Diagram disable control bit for time slot number N. 1 = Receive sequence proceeds normally. Data is received during slot number N, and the RDR flag is set. and, therefore, the RDR and ROE flags are not set. received is not affected by the new RSM setting. If the RSM is read, it shows the current setting. how many of these control bits are actually used.

7.4.5.3.1 SSI Frame St atus Register (SFSR)

Figure 70. SFSR Register Diagram receive word count clock (see Figure 78). Freescale Semiconductor, Inc.

transmit word count clock (see Figure 77).

7.4.6 Functional Description

7.4.6.1 General

SSI control registers (see Section 7.4.5.2, “Register Descriptions”). manner, where data is transferred at regular intervals, such as at the sampling rate of an external CODEC. whether data is being transmitted or received.

7.4.6.1.1 Normal Mode

external clock on the STCK or SRCK pin). • The number of bits per sample (WL[1:0] bits). • The number of time slots per frame (DC[4:0] bits). Table 51. SSI Operating Modes

1. In synchronous mode, the transmitter and receiver use a common clock and frame synchronization signal. In

asynchronous mode, the transmitter and receiver operate independently, on their own clocks and frame syncs.

1. In continuous mode the clocks run all the time. In gated clock mode, the clock operates only when there is data
2. In normal mode, the SSI only transmits during the first time-slot of each I/O frame. In network mode, any number
3. Use of gated clock is not allowed in network mode.

Freescale Semiconductor, Inc.

106 MC72000 Advance Information Data Sheet MOTOROLA

1. Set the SCSR, STXCR, SCR2, and SOR registers to select normal mode operation, define
2. Enable SSI enabled (SSIEN = 1).
3. Enable TXFIFO (TFEN=1) and configure the transmit watermark (TFWM=n) if this
4. Write data to transmit data register (STX).
5. Enable transmit interrupts.
6. Set the TE bit (TE = 1) to enable the tr ansmitter on the next frame sync boundary.

Figure 71 and Table 52 describe the functions performed during transmit operation in this mode. Figure 71. Normal Mode Transmit Timing— Continuous Clock (WL=8-bit words, DC=1) Table 52. Normal Mode Transmit Operations

2 Data transferred to TXSR From STX From TXFIFO

3 STXD output pin is enabled1 and the first bit of

4 Flag status update The TDE bit is set The TFE bit is set if the level of data in the

Freescale Semiconductor, Inc.

1. Set the SCSR, SRXCR, SCR2, and SOR registers to select normal mode operation, define
2. Enable RXFIFO (RFEN=1) and configure re ceive watermark (RFWM=n) if RXFIFO is
3. Enable receive interrupts.
4. Set the RE bit (RE = 1) to enable the receiv er operation on the next frame sync boundary.

Figure 72 and Table 53 describes the functions performed during receive operation in this mode.

9 Repeat at step 1 on the next frame sync 3

1.The STXD output signal is disabled except during the data transmission period. happens when the TUE bit is set. Freescale Semiconductor, Inc.

108 MC72000 Advance Information Data Sheet MOTOROLA

Figure 72. Normal Mode Receive Timing—Continuous Clock (WL= 8-bit words, DC=1) Table 53. Normal Mode Receive Operations

1 Leading edge of frame sync occurs on the

the middle of the last receive bit.

4 Flag status update The RDR bit is set The RFF bit is set if the level of data in the

happens when the ROE bit is set.

7 Repeat at step 1 on the next frame sync 2

Freescale Semiconductor, Inc.

completed, the clock is stopped. intervals in gated clock mode. occurs, all ensuing transfers will be out of synchronization. Figure 73 shows a gated clock timing diagram with comments in Table 55. Table 54. Transmit and Receive Enables in Gated Clock Mode Freescale Semiconductor, Inc.

110 MC72000 Advance Information Data Sheet MOTOROLA

Figure 73. Normal Mode Timing—Gated Clock Table 55. Gated Clock Operations

1 Clocks occur on STCK to clock data out on the

when the clock is generated internally.

3 All other timing of transmit and receive

Freescale Semiconductor, Inc.

7.4.6.1.2 Network Mode

that is connected to an existing TDM network and occupies a few time slots. external clock on the STCK and/or SRCK pins). • The number of bits per sample (WL[1:0] bits). • The number of time slots per frame (DC[4:0] bits). notes which are contained in Table 56 and Table 57. the normal end of the list bit time is. what happens when the ROE bit is set. Table 55. Gated Clock Operations (Continued) Freescale Semiconductor, Inc.

112 MC72000 Advance Information Data Sheet MOTOROLA

The transmit portion of the SSI is enabled when the SSIEN and the TE bits in the SCR2 are both set. However, when the TE bit is set, the transmitter is enabled only after detection of a new frame boundary.

1. Set the SCSR, STXCR, SCR2, and SOR registers to select network mode operation, define
2. Enable TXFIFO (TFEN=1) and configure the transmit watermark (TFWM=n) if this
3. Write data to transmit data register (STX).
4. Enable transmit interrupts.
5. Set the TE bit (TE = 1) to enable the tr ansmitter on the next frame sync boundary.

Figure 74. Network Mode Transmit Timing Freescale Semiconductor, Inc.

• Write the data register with data to enable transmission in the next time slot. • Write the time slot register to disabl e transmission in the next time slot. The receiver portion of the SSI is enabled when both the SSIEN and the RE bits in the SCR2 are set. However, when the RE bit is set, the receiver is enabled only after detection of a new frame boundary.

1. Set the SCSR, SRXCR, SCR2, and SOR registers to select network mode operation, define

Table 56. Notes for Transmit Timing in Figure 74 1 Example of a 5 time-slot frame, transmitting in time-slots 0 and 3.

2 STFS Example with word-length frame sync and standard timing (TFSI=0, TFSL=0,

TEFS=0). Frame timing begins with the rising edge of STFS.

4 STX/STSR

bit will be set and the hardware will operate as if the STX register had been written. again. Note that this may lead to drive conflicts on the transmit data line.

5 TXSR

one bit per rising edge of STCK. Freescale Semiconductor, Inc.

114 MC72000 Advance Information Data Sheet MOTOROLA

1. Enable RXFIFO (RFEN=1) and configure re ceive watermark (RFWM=n) if RXFIFO is
2. Enable receive interrupts.
3. Set the RE bit (RE = 1) to enable the receiv er operation on the next frame sync boundary.

Figure 75. Network Mode Receive Timing Table 57. Notes for Receive Timing in Figure 75

2 SRCK The figure shows the transmit and receive timing as the same, although this is not

REFS=0). Frame timing begins with the rising edge of SRFS.

5 RXSR

register SRX register At the word clock, the data in the RXSR register is transferred to the SRX register. Freescale Semiconductor, Inc.

• Read SRX and use the data. • Read SRX and ignore the data. • Do nothing—the receiver overrun exception occu rs at the end of the current time slot.

7.4.6.1.3 Synchronous/Asyn chronous Operating Modes

by the transmitter configuration. The SYN bit in SCR2 selects synchronous or asynchronous operation. Figure 76. Synchronous Mode Interrupt Timing description of interrupt processing). Table 57. Notes for Receive Timing in Figure 75 (Continued) Freescale Semiconductor, Inc.

116 MC72000 Advance Information Data Sheet MOTOROLA

7.4.6.1.4 Network Mode with Mask Registers Implemented

enhancements incorporate the mask registers (TSM and RSM) and the frame status register (SFSR). portion of the figure are shown in Table 58. five as in the previous example where the TSM register is not used. Figure 77. Network Mode Transmit Timing with Mask Register Freescale Semiconductor, Inc.

on the 0 time-slots, no status flags change, and no interrupts are generated. of the figure are shown in Table 59. five as in the previous example where the RSM register is not used. Table 58. Notes for Transmit Timing with Mask Register in Figure 77 1 Example of a 5 time-slot frame, transmitting in time-slots 0 and 3. TEFS=0). Frame timing begins with the rising edge of STFS. complete description of interrupt processing).

4 STX\\STSR

pin is tri-stated and the time-slot is ignored. has not been written in the previous time-slot, the previous data is reused. line, if another device is transmitting data during this time-slot. one bit per rising edge of STCK. Freescale Semiconductor, Inc.

118 MC72000 Advance Information Data Sheet MOTOROLA

Figure 78. Network Mode Receive Timing with Mask Register Table 59. Notes for Receive Timing with Mask Register in Figure 78 REFS=0). Frame timing begins with the rising edge of SRFS.

9 RXSR

register, for enabled time-slots. the time-slots as they occur so it knows which data it is processing. description of interrupt processing). Freescale Semiconductor, Inc.

7.4.7 Resets

7.4.7.1 General

The SSI is affected by power-on reset and SSI reset. the present SSI control bits and without affecting the other peripherals.

1. Issue a power-on or SSI reset.
2. Program the SSI control registers.
3. Set the SSIEN bit in SCR2.

changing any of the following control bits listed in Table 60. These control bits should not be changed during SSI operation.

7.4.8 Clocks

Table 60. SSI Control Bits Requiring Reset before Change Freescale Semiconductor, Inc.

120 MC72000 Advance Information Data Sheet MOTOROLA

• Bit clock—Used to serially clock the da ta bits in and out of the SSI port. • Word clock—Used to count the number of data bits per word (8, 10, 12, or 16 bits). • Frame clock—Used to count th e number of words in a frame. Figure 79. SSI Clocking (8-bit words, 3 time-slots/frame) Figure 80. SSI Clock Generation

7.4.8.1 Description of Clock Operation

The following section describes clock operation.

7.4.8.1.1 SSI Clock and Fr ame Sync Generation

Table 61. Clock Summary bit of the SCR2 register can invert the clock if needed. bit of the SCSR register can invert the clock if needed. TFSI bit can invert this signal if needed. definition of the REFS bit of the SCSR register for timing options. Freescale Semiconductor, Inc.

122 MC72000 Advance Information Data Sheet MOTOROLA

7.4.9 Interrupts

7.4.9.1 General

The SSI can generate four interrupt vectors as shown in Table 25.

7.4.9.2 Description of Interrupt Operation

The following section describes interrupt operation.

7.4.9.2.1 Receive Da ta with Exception

7.4.9.2.2 Receive Data

interrupt will occur for each data word received.

7.4.9.2.3 Transmit Da ta with Exception

status bit is set and the transmit data exception interrupt occurs.

7.4.9.2.4 Transmit Data

interrupt will not occur until the transmit watermark level is reached. Table 62. Interrupt Summary Freescale Semiconductor, Inc.

7.4.10 SSI Timing Diagrams

Figure 83. SSI Transmitter Internal Clock Timing Figure 84. SSI Transmitter External Clock Timing Freescale Semiconductor, Inc.

124 MC72000 Advance Information Data Sheet MOTOROLA

Figure 85. SSI Receiver Internal Clock Timing Figure 86. SSI Receiver External Clock Timing Table 63. SSI Timing

110 Clock cycle 1 (SYSCLK/4) 166 ns

111 Clock high period 83 ns

112 Clock low period 83 ns

Freescale Semiconductor, Inc.

114 STCK high to STFS (bl) high 2 ns

124 STCK high to STD valid ns

125 STCK High to STD not valid ns

128 Clock cycle period 3 166 CPmax ns

129 Clock high period 83 ns

130 Clock low period 83 ns

136 STFS (bl) hold after STCK low 2 5C P m a x - 2 0n s

137 SRFS (bl) hold after SRCK low 2 5C P m a x - 2 0n s

140 STFS (wl) hold after STCK low 2 5C P m a x - 2 0n s

141 SRFS (wl) hold after SRCK low 2 5C P m a x - 2 0n s

Table 63. SSI Timing (Continued) Freescale Semiconductor, Inc.

126 MC72000 Advance Information Data Sheet MOTOROLA

7.4.10.1 Frame Sync/Clock Phasing

longer critical with respect to the rising edge of STCK. This is shown in Figure 87. Figure 87. SSI Frame Sync versus Clock Timing Diagram

7.4.10.2 External Frame Sync Setup

and before the first frame sync.

7.4.10.3 Max External Clock Rate

The maximum allowable rate for an external clock source is 1/4 of the peripheral clock, or up to 2 Mbits/s.

8 Bluetooth Baseba nd Functionality Overview

This section describes the features of the Bluetooth baseband stack, which is included in the MC72000. Bluetooth v1.1 specification. firmware patches resident in an attached EEPROM to be applied.

149 SRD hold after STCK low 5 CPmax-20 ns

1. Based on SYSCLK of 24 MHz (from MC72000 BT radi o). All the timings for the SSI are given for a

frame sync FSR/FST in the tables and in the figures.

1. bl = bit length; wl = word length
2. CPmax = clock period max for system

Freescale Semiconductor, Inc.

8.1 Link Controller Features

additional fields, which have been included to provide additional overview. Table 64. Overview of Link Controller Features Freescale Semiconductor, Inc.

128 MC72000 Advance Information Data Sheet MOTOROLA

Table 64. Overview of Link Controller Features (Continued) Freescale Semiconductor, Inc.

1. The 23-channel frequency hopping system is fully

testing has not been performed.

1. This value can be adjusted down to reduce the

amount of RAM used on the MC72000. Freescale Semiconductor, Inc.

130 MC72000 Advance Information Data Sheet MOTOROLA

8.2 Link Manager Features

Bluetooth SIG’s PICS Proforma for LM, Annex B, Version 0.92. Table 65. Overview of Link Manager Features Freescale Semiconductor, Inc.

Table 65. Overview of Link Manager Features (Continued) Freescale Semiconductor, Inc.

132 MC72000 Advance Information Data Sheet MOTOROLA

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

134 MC72000 Advance Information Data Sheet MOTOROLA

9 HCI Features

1. Power control is enabled if supported by hardware (use next
2. The ROM version supports Best-Effort Quality of Service

Freescale Semiconductor, Inc.

• 23- and 79-channel frequency hopping. • Support of all connection types. • Support of all packet types. • Host controller HCI flow control. • Authentication and pairing. • Radio TX power status and control. Table 66. HCI Commands and Events Freescale Semiconductor, Inc.

136 MC72000 Advance Information Data Sheet MOTOROLA

Table 66. HCI Commands and Events (Continued) Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

138 MC72000 Advance Information Data Sheet MOTOROLA

Freescale Semiconductor, Inc.

10 Applications Information

The following sections provide applications information for the MC72000.

10.1 General Purpose Output

actively used to drive a peripheral, R2/8 in the Radio Register Map is considered a don’t care.

10.2 General Purpose Output Invert

R2/8. This is a useful feature when an inverter is not available. It can serve as a complement to GPO Invert. Freescale Semiconductor, Inc.

140 MC72000 Advance Information Data Sheet MOTOROLA

10.3 External Power Amplifier Enable

The External Power Amplifier Enable (EPAEN) bit, R6/15, can be used in two applications. It may serve as a complementary driver to a dual-port antenna. This is accomplished when External PA Enable Invert, R3/10, is set to logic one. In this configuration, EPAEN assumes the inverted value of GPO, which is the second driver for the antenna switch. EPAEN may also assist in Class 1 operation by setting bit R11/6 to logic high. This setting allows the MC72000 to drive an external power amplifier. Setting bits R11/6 and R3/10 to zero disables EPAEN.

10.4 External Power Amplifier DAC

The Bluetooth specification for Class 1 Power implementation requires power control from 4.0 dBm (or less) to 20 dBm (max) power. The MC72000 external power amplifier digital to analog converter (EPADRV) output (Pin K6) provides a voltage reference for power control of an external power amplifier (PA), if desired. The EPADRV output is enabled when External PA DAC Enable (R11/7) is set to one. Setting R11/7 to zero pulls the EPADRV output to ground. When enabled, the EPADRV output voltage is controlled by the PA DAC setting (R3/5-0). The minimum EPADRV output voltage is 0 VDC and the maximum output voltage is 3.2 VDC. The 6-bit resolution of the PA DAC setting corresponds to approximately 50 mV/bit. When using a VCCRF < 3.2 Vdc, the maximum EPADRV output voltage is reduced to VCCRF (i.e., the full-scale output of the PA DAC is referenced to 3.2 V). To obtain optimum functionality of EPADRV with an external PA, this feature should be utilized with the External PA Enable. Refer to Section 10, “Applications Information,” for additional usage information. The output of the EPADRV, when enabled, is gated by the MC72000 sequence manager. During a sleep, idle, or RX cycle, the output is set to zero volts. The programmed value of the output voltage is only achieved during an active TX cycle as shown in Figure 30.

10.5 PIN Implementation of Antenna Switch

An alternative approach to using an RF switch is to utilize a PIN diode technique as shown in Figure 88. When both PIN diodes are in the high resistance (i.e., un-biased) state, the transmitter is isolated from the antenna and LNA input. Conversely, when both PIN diodes are in the low resistance (i.e., forward-biased) state, the l/4 section appears as an open circuit from the transmitter output to the LNA input, and the transmitter output is coupled directly to the antenna through the bandpass filter. For receive mode, GPO is set low. For transmit mode, GPO is set high. Some advantages to this implementation include very low current consumption while in receive or idle mode, moderate current consumption while in transmit mode, high receiver isolation, and low cost. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Figure 88. PIN Implementation of Antenna Switch

10.6 Class 1 Operation

(H 0.1 ìF). Approximately 44 ìs is available to fully charge this capacitor (see Figure 30).

10.7 Manufacturer Code

1149.1 specification. This is also known as the Bluetooth address. Figure 89. Manufacturer Identification Code

4 Bits 16 Bits 4 Bits =0 7 Bits

Freescale Semiconductor, Inc.

142 MC72000 Advance Information Data Sheet MOTOROLA

10.8 File System

stack, and filesystem passes through (see Figure 90). (document number AN2340/D) for a thorough explanation. Figure 90. File System Overview

10.8.1 UART Interface Telegrams

• HCI ACL: Data transport — ty pically a file from another unit. • HCI SCO: Audio transport — ty pically sound from another unit. a spontaneous reaction to something happening in the MC72000. Freescale Semiconductor, Inc.

MOTOROLA MC72000 Advance Information Data Sheet 143 Preliminary

10.8.2 UART Interface Hardware

The UART driver uses the following signals: • GND for common ground reference point. • TxD/RxD for serial data. • RTS/CTS lines as normal HW-handshake (Optional). • DTR/DSR lines as Sleep mode request / grand (Optional). However, the interface can be configured to be a 2, 4 or 6 wire interface. For more details, see document MC71000/MC72000 Wake-Up, Reset, and Host Clock Request Sequences Application Note (document number AN2340/D).

10.8.3 UART Driver

The UART driver is highly dependent on the HW and the operating system of the host system. However, it must conform to the following rules: 1. Transmit and receive at 9600Baud, 8Bit, 1 StopBit, NoParity. 2. Ability to change Baudrate, if needed, in this application. 3. Support handshake on RTS/CTS lines, if needed, in this application. Refer to MC71000/ MC72000 Wake-Up, Reset, and Host Clock Request Sequences Application Note (document number AN2340/D) for more details. 4. Support sleepmode, if needed, in this application. Refer to MC71000/MC72000 Wake-Up, Reset, and Host Clock Request Sequences Application Note (document number AN2340/ D) for more details. 5. A delay of more than 300 mS between characters in a command results in a “Hardware Error” event returned, telling to retransmit the last telegram. This will impact general speed and should be avoided.

10.8.4 Parser/Router

There are three possible ways to implement the file system. Each has great impact on the way the Parser / Router part has to be implemented, as well as cost and hardware. For details, see the following subsections.

10.8.4.1 General File System on Host

This saves the EEPROM and can use an existing file system on the host. The router must do the following things: 1. Sort all commands/events/ACL/SCO and send it to correct receiver. 2. Send host connect after reset. 3. Change baud rate after host connect, if needed. 4. Resend telegrams on “Hardware error” event received, if needed. 5. Keep track of number of pending commands. The parser has to do the following things: 1. Translate received file system even ts into local file system calls. 2. Send correct command, with data , on received file system events. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

144 MC72000 Advance Information Data Sheet MOTOROLA

1. No action necessary on “Command Complete” events. Some way of reprogramming the files on the host must be considered. For more details, see Motorola Bluetooth File System, Host-based General Application Note (document number 94001481003)

10.8.4.2 One-File File System Downloaded to RAM in MC72000

This will download an image of all files to RAM in MC72000. This saves the EEPROM and no parser/ router must be present when running application and upper stack code. The download of this image is done once under the initialization of the MC72000. This functionality will be available from ROM 2.1. No EEPROM is needed, but the host must have initialization software that can make host connect and send one file after all resets. Furthermore, the host must store link keys, if needed, and send those after each reset. For more details, see Motorola Bluetooth File System, Host Based One File Application Note (document number 94001481004).

10.8.4.3 File System in EEPROM on MC72000

An EEPROM containing the files is connected to the MC72000. The parser/router part does not exist in this configuration and the upper stack are directly connected to the UART driver. Some way of reprogramming the EEPROM normally must be considered. This can be done through JTAG with special programming, or directly through UART interface with a parser program. This solution will add the cost of an EEPROM but will keep the host software simple. For more details, see Motorola Bluetooth File System, Embedded File System Application Note (document number 94001481002). Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

10.8.5 Files

To make the MC72000 as flexible as possible, the following files have been defined as shown in Table 67. System, Embedded File System Application Note (document number 94001481002) for more details. All files are created by tools or provided by Motorola.

10.8.6 File Loading

ROM, with a UART application (see Figure 91 for an example). Table 67. Filename Description 1000 Boot image This file is the boo t program that controls startup. errors in existing functions in ROM or RAM. 3000 OEM application The application file cont ains the customer specific application. 3500 Headset config. Configuration for a headset application. 3600 UART config. Configuration for a UART-based application.

4100 Radio parameters/patch Radio register values in different setups and software patch code for

4200 Production data Hardware name stri ng, serial number, revision etc. 5500 ROM image The ROM image file is a copy of complete EEPROM. 6500 RAM image The image of a file system to be accessed from RAM. Freescale Semiconductor, Inc.

146 MC72000 Advance Information Data Sheet MOTOROLA

Figure 91. File Loading Example 94001481002) for more details.

10.8.7 Possible EEPROM Types

the one chosen by Motorola. Customers can change this by changing a number in a file. Table 68. EEPROMs Freescale Semiconductor, Inc.

10.9 Audio

Bluetooth is the Bluetooth Audio Signal Processor (BTASP) that has been designed into the MC72000. software so the synchronization and choice of CODEC is highly flexible. Table 68. EEPROMs (Continued) Freescale Semiconductor, Inc.

148 MC72000 Advance Information Data Sheet MOTOROLA

BTASP key features: • Overall system pass-band is 280 Hz to 3. 45 kHz (-3 dB), measured with white noise. • Out-of-band attenuation above 4 kHz is at least 80 dB, measured with white noise. • SNR at 1.020 kHz with maximal signal level (max . volume setting) is above 60 dB, measured with a 1.020 kHz fixed sine. • The latency measured with a short sine pulse (one-way latency) is as follows: — Using HV1 packets: 4.9 ms — Using HV2 packets: 6.1 ms — Using HV3 packets: 7.4 ms • Phase jitter: < 5° C measured for a 1.020 kHz sine.

10.10 Timing and Low Power Mode

The timing for the Power on reset (POR) and the implementation of the low power modes is thoroughly described in MC71000/MC72000 Wake-Up, Reset, and Host Clock Request Sequences Application Note (document number AN2340/D).

10.11 UART Interface

The host interface is a standard HCI UART (H:4) transport layer, where all communication from application, upper stack and file system passes through. The UART transport layer supports baud rate ranging from 1200 to 1843200 bit/s. The MC72000 UART interface can be configured to be a 4-, 5-, or 6-wire interface. The default baud rate upon start up can be configured. See Motorola Bluetooth File System, Overview Application Note (document number 94001481001), UART/SSI Configuration User´s Guide (document number 94001481900) and Motorola Bluetooth File System, Host-based General Application Note (document number 94001481003) for more details.

10.12 JTAG Interface

The JTIC interface intended for debug and production test purposes, may be wired to an external JTAG controller. In this case, refer to the external document Production Test Application Note (document number 94001481100) in Section 5.2, “Document References,” and other implementation guidance documents in this section. If JTAG is omitted from design, all JTAG interface pins must be left open. TRST_B may be pulled-down and TMS may be pulled-up to enhance reliability, and to ensure that the JTAG interface stays disabled at all times. All JTAG input pins has internal pull-up/downs and cannot be disabled as normal GPIO pins can. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MOTOROLA MC72000 Advance Information Data Sheet 149 Preliminary

10.13 Production Test

All issues regarding the production with regards to vendor-specific command and setup are explained thoroughly in Production Test Application Note (document number 94001481100)

10.14 Bluetoot h Qualification

For information on Bluetooth Qualification, see Motorola Bluetooth Solutions, Bluetooth Qualification application note (document number AN2386/D). Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

150 MC72000 Advance Information Data Sheet MOTOROLA

Figure 92. Application Example Evaluation Schematic Freescale Semiconductor, Inc.

12 Mechanical Outline (Package Information)

Figure 93. 100 MAPBGA Package Diagram 7 mm x 7 mm x 1.6 mm Freescale Semiconductor, Inc.

152 MC72000 Advance Information Data Sheet MOTOROLA

Appendix A: Radio Register Map Appendix A: Radio Register Map The following figure shows the MC72000 Radio Register Map. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Appendix A: Radio Register Map MOTOROLA MC72000 Advance Information Data Sheet 153 Preliminary Register Address Register Number MSB Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Bit 0 $01 1 MSB LSB Rx Test $37FA 0 01101111111101 0 Tx Test $C1D2 1 10000011101001 0 $02 2 Sleep Enable Tx Enable Rx Enable Narrow Bandwidth Enable High/Low Injection Enable General Purpose Output MSB LSB Rx Test $2CB9 0 01011001011100 1 Tx Test $55B8 0 10101011011100 0 $03 3 External PA Enable Invert General Purpose Output Invert MSB LSB $4180 0 10000011000000 0 $04 4 RSSI Read Enable $78D9 0 11110001101100 1 $05 5 MSB PA Bias Adjust LSB $28BA 0 01010001011101 0 $06 6 External PA Enable = GPO MSB LSB z LSB $C28A 1 10000101000101 0 $07 7 MSB LSB MSB LSB $9CB0 1 00111001011000 0 $08 8 MSB LSB MSB LSB $B862 1 01110000110001 0 $09 9 RSSI Enable $7FDF 0 11111111101111 1 $0A 10 $5FFF 0 10111111111111 1 $0B 11 External PA DAC Enable External PA Enable Xtal Boost Enable Xtal Enable $FF6F 1 11111110110111 1 $0C 12 MSB LSB MSB LSB $C6C6 1 10001101100011 0 $0D 13 MSB LSB MSB LSB $C0C5 1 10000001100010 1 $0E 14 MSB LSB MSB LSB $6825 0 11010000010010 1 $0F 15 MSB LSB MSB LSB $B498 1 01101001001100 0 $10 16 MSB LSB MSB LSB $9668 1 00101100110100 0 $11 17 MSB LSB MSB LSB $65AD 0 11001011010110 1 M-Dual Port Digital Multiplier Value For Tx PLL ROM_r4_c4

16 Bit Frac-N Numerator Divide Value - num

Frac-N Integer Divide Value PA DAC Setting ROM_r1_c1 Transmit Synchronization Time Delay Value Dual Port Programmable Delay For Tx PLL ROM_r2_c2 Xtal Trim DC Pll R Counter gp $00 Programmable Reset MC72000 Byte 0Byte 1 B-Dual Port Digital Multiplier Value For Tx PLL DC Pll N Counter ROM_r4_c3 ROM_r4_c2 ROM_r3_c3 ROM_r3_c2 ROM_r3_c4 ROM_r3_c1 ROM_r2_c4 ROM_r2_c3 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

154 MC72000 Advance Information Data Sheet MOTOROLA

Figure 94. MC72000 Radio Register Map Freescale Semiconductor, Inc.

MOTOROLA MC72000 Advance Information Data Sheet 155 Preliminary NOTES Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. The Bluetooth trademarks are owned by their proprietor and used by Motorola, Inc., under license. The ARM POWERED logo is the registered trademark of ARM Limited. ARM7 and ARM7TDMI-S are trademarks of ARM Limited. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. © Motorola, Inc. 2003 MC72000/D HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Preliminary Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...