MC68LC302 FREESCALE | Alldatasheet

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This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. Product Brief Low Cost Integrated Multiprotocol Processor MC68LC302 Freescale introduces the low cost version of the well-known MC68302 Integrated Multiprotocol Processor (IMP). It will be known as the MC68LC302, and will expand a family of devices based on the MC68302. Some features and pins have been removed while other features have been enhanced as compared to the original MC68302. Simply put, the MC68LC302 is a traditional MC68302 with a new static 68000 core, a new timer and low power modes, but without the third serial communication controller (SCC). It is packaged in a low profile 100 TQFP that requires less board space than the regular MC68302, as well as making it suitable for use in height restricted applications such as PCMCIA. 68000 SYSTEM BUS

4 SDMA

1 GENERAL-

3 TIMERS

4 CHIP SELECTS

1152 BYTES

20 ADDRESS

iconductor, I For More Information On This Product, Go to: www.freescale.com nc...

MC68LC302 PRODUCT INFORMATION

FEATURES

The features of the MC68LC302 are as follows. Bold face items show major differences from the MC68302.

  • On-Chip Static 68000 Core Supporting a 16- or 8-Bit M68000 Family System
  • SIB Including: — Independent Direct Memory Access (IDMA) Controller — Interrupt Controller with Two Modes of Operation — Parallel Input/Output (I/O) Ports, Some with Interrupt Capability — On-Chip 1152-Byte Dual-Port RAM — Three Timers Including a Watchdog Timer — New Periodic Interrupt Timer (PIT) — Four Programmable Chip-Select Lines with Wait-State Generator Logic — Programmable Address Mapping of the Dual-Port RAM and IMP Registers — On-Chip Clock Generator with Output Signal — On-Chip PLL Allows Operation with 32 kHz or 4 MHz Crystals — Glueless Interface to EPROM, SRAM, Flash EPROM, and EEPROM — Allows Boot in 8-bit Mode, and Running Switch to 16-bit Mode — System Control: System Status and Control Logic Disable CPU Logic (Slave Mode Operation) Hardware Watchdog New Low-Power (Standby) Modes with Wake-Up from Two Pins or PIT Freeze Control for Debugging (Available Only in the PGA Package) DRAM Refresh Controller
  • CP Including: — Main Controller (RISC Processor) Two Independent Full-Duplex Serial Communications Controllers (SCCs) — Supporting Various Protocols: High-Level/Synchronous Data Link Control (HDLC/SDLC) Universal Asynchronous Receiver Transmitter (UART) Binary Synchronous Communication (BISYNC) Transparent Modes Autobaud Support Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68LC302 PRODUCT INFORMATION MC68LC302 APPLICATIONS The MC68LC302 excels in several applications areas. First, any application using the MC68302,but not needing all three serial channels is a potential candidate for the MC68LC302. Note however, that the MC68LC302 sacrifices most of the provision for external bus mastership, thus the MC68LC302 may not be appropriate where the MC68302 is used as part of larger systems. Second, the MC68LC302 excels in low power and portable applications. The inclusion of a static 68000 core, coupled with the low power modes built into the device make it ideal for handheld, or other low power applications. The new 32 kHz or 4 MHz PLL option greatly reduces the total power budget of the designer’s board, and allows the MC68LC302 to be an effective device in low power systems. The MC68LC302 can then optionally generate a full frequency clock for use by the rest of the board. During low power modes, the new periodic interrupt timer (PIT) allows the device to awaken at regular intervals. In addition, two pins can awaken the device from low power modes. Third, given that the MC68LC302 is packaged in a 100TQFP package, it allows the MC68LC302 to be used in space critical applications, as well as height critical applications such as PCMCIA cards. Fourth, since the disable CPU mode (also known as slave mode) is still retained, the MC68LC302 can function as a fully intelligent DMA-driven peripheral chip containing serial channels, timers, chip selects, etc. DIFFERENCES BETWEEN THE MC68LC302 AND MC68302 The MC68LC302 has some specific differences from the MC68302. Even though the functionality of the processor and the peripherals remain the same, some of the flexibility has been removed due to the pin reduction from 132 on the original MC68302, to 100 pins on the MC68LC302. The following features have been removed or modified from the MC68302 in order to make the MC68LC302 possible.

  • SCC3 and its baud rate generator (BRG3) are removed.
  • External masters are not able to take the bus away from the MC68LC302 through the normal bus arbi- tration scheme as these pins no longer exist. An external master can still maintain bus mastership through a simple scheme using the HALT pin. This restriction does not apply when using the MC68LC302 in CPU disabled mode (slave mode), in which case BR, BG, and BGACK are all available. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68LC302 PRODUCT INFORMATION

  • The SCP pins are now muxed with PA8, PA9, and PA10. The TXD3, RXD3, and RCLK3 functions asso- ciated with SCC3 are eliminated.
  • The UDS , LDS, and R/W pins are not available except in slave mode, where they replace the IPL2-0 pins. Instead, the new pins WEH, WEL, and OE have been defined for glueless interfacing to memory.
  • PA12 is now muxed with the MODCLK pin, which is associated with the 32 KHz or 4 MHz PLL. The MOD- CLK pin is sampled after reset, and then becomes PA12.
  • New VCCSYN, GNDSYN, and XFC pins have been added in support of the on-chip PLL.
  • For purposes of emulation and development support only, a special 132 PGA version is supported. This version adds back the FC2-0, IAC, FRZ, and AVEC pins. The FC2-0 pins allow bus cycles to be distin- guished between program and data accesses, interrupt cycles, etc. The IAC, FRZ, and AVEC pins are provided so that emulation vendors can quickly retrofit their existing MC68302 emulator designs to sup- port the MC68LC302. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

MC68LC302 PRODUCT INFORMATION MC68LC302 PIN DESCRIPTION TCLK1/L1SY0/SDS1 BRG2/SDS2/PA7 WEL /WE (LDS/DS) EXTAL XFC XTAL A1-A19 Data Bus MC68LC302 Bus Control Interrupt Control Chip Select RESET HALT BUSW DISCPU IPL0/IRQ1 (BR) IPL2/IRQ7 (BG) IPL1/IRQ6 (BGACK) CS0 /IOUT2 CS3 -CS1 Address Bus RXD1/L1RXD RCLK1/L1CLK TXD1/L1TXD CD1 /L1SY1 CTS1 /L1GR RTS1 /L1RQ/GCIDCL IQGND(2) System Control IQVDD(2) CLKO Clock RXD2/PA0 RCLK2/PA2 TXD2/PA1 TCLK2/PA3 CTS2 /PA4 RTS2 /PA5 CD2 /PA6 SPRXD/PA8 SPCLK/PA10 SPTXD/PA9 MODCLKPA12 TIN1/PB3 TIN2/PB5 TOUT2 /PB6 WDOG /PB7 PB8 D0-D15 NMSI1/ ISDN I/F NMSI2/ PAIO PAIO/ SCP TIMER/PBIO PB9 PB10 PB11 Signals AS WEH /A0 (UDS/A0) DTACK OE (R/W) Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Table 1. MC68LC302 Ordering Information Table 2. Documentation Freescale Semiconductor, Inc.