MC6821

MC6821 MOTOROLA | Alldatasheet

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PERIPHERAL INTERFACE ADAPTER (PIA) The MC6821 Peripheral Interface Adapter provides the universal mos means of interfacing peripheral equipment to the M6800 family of (N-CHANNEL, SILICON-GATE, microprocessors. This device is capable of interfacing the MPU to DEPLETION LOAD) peripherals through two 8-bit bidirectional peripheral data buses and four control lines. No external logic is required for interfacing to most PERIPHERAL INTERFACE peripheral devices. ADAPTER The functional configuration of the PIA is programmed by the MPU during system initialization. Each of the peripheral data lines can be pro- grammed to act as an input or output, and each of the four con- trol/interrupt lines may be programmed for one of several contro! modes. This allows a high degree of flexibility in the overall operation of |... the interface. P- _.. © &.Bit Bidirectional Data Bus for Communication with the APTI! surrn Bit Bielrectional Date Bus for Commu Jn wi heer iil CERAMIC PACKAGE MPU U CASE 715 © Two Bidirectional 8-Bit Buses for Interface to Peripherals © Two Programmable Control Registers © Two Programmable Data Direction Registers $ SUFFIX © Four Individually-Controlled Interrupt Input Lines; Two bh CERDIP PACKAGE Usable as Peripheral Control Outputs CASE 74 @ Handshake Control Logic for Input and Output Peripheral _ Operation _<aitl 4] © High-impedance Three-State and Direct Transistor Drive SY P SUFFIX Peripheral Lines ay PLASTIC PACKAGE @ Program Controlled Interrupt and Interrupt Disable Capability © CMOS Drive Capability on Side A Peripheral Lines @ Two TTL Drive Capability on All A and B Side Buffers @ TTL-Compatible PIN ASSIGNMENT @ Static Operation VssY @ 4oficat PAO[] 2 39 fica2 PaAIg3 36 1ROA Pa2gs 37) iROB Pa3gs 36f1RSO ORDERING INFORMATION Paste 35DRs1 Frequency past? sa PRESET Ceramic O°C to 70°C | MCBBZIL Suttix 40°C to.a5°c | mceazice Pa7ys spor 0°C to 70°C || MCBBA2IL Pot} 10 aifioz ~40°C to 85°C | MCEBAZICL P oc 70°C | McEBBzIL Sign pos Cerdip 10 0°C 10 70°C | ~MCBB21S Pe2gi2 297104 S Suffix 10 40°C toasec | mcea2ics PB3f}13 28 fos 18 0°C to 70°C | -MCBBAZIS 4 18 49°C 10 85°C | MCSBAZICS pestis 271106 20 0°C to 70°C _|_MC68B21S Pastis 2617 Plastic 10 0°C 10 70°C | MCBB2IP paegis ashe P Suffix 1.0 40°C to.@s°C | MCEE2ICP : 15 0°C.to 70°C | MC68A21P Pe7q37 2ayicsi 15 40°C to 85°C | MCBBA2ICP cergs 23f1cs2 20 orc to 70°C | _Mc6aB21P celts zhcso Vec20 apRw 3-307 .

[Characteristics | Symbol_|_Vaue | Um] This device contains circuitry to protect the inputs against domage due to high stat [input Vonage Vin [0.310470] v ed Thar coer pe, Roweyer tis ate oeeug Temperature Range avoid applications of any voltage higher than MC6821C, Mc6saz1C = 40 to +85 maximum rated voltages to this high- strained to the range GNDS(Vin or THERMAL CHARACTERISTICS Vout) $ Vcc. [vane] Unused inputs must always be tied to an ea a appropiate logic votage level leg, ether Ceramic 50 , GND or Vcc). Plastic aN 100 cw Cerdip 6 POWER CONSIDERATIONS The average chip-junction temperature, Ty, in °C can be obtained from: Ty=Tat(Ppe6ya) (1) Where: Tam Ambient Temperature, °C 63a Package Thermal Resistance, Junction-to-Ambient, °C/W. Pp=PINT+PPORT PInT™ICC x VCC, Watts — Chip Internal Power PpoRT= Port Power Dissipation, Watts — User Determined For most applications PpgRT<PiNT and can be neglected. PPORT may become significant if the device is configured to drive Darlington bases or sink LED loads. An approximate relationship between Pp and Ty (if PpoRT is neglected) is: Pp=K-~=(Ty+273°C) (2) Solving equations 1 and 2 for K gives: K=Ppe(Ta+273°C)+6jaePp2 (3) Where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring Pp (at equilibrium) for a known Ta. Using this value of K the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of T,. DC ELECTRICAL CHARACTERISTICS (Vcc=5.0 Vdc +5%, Vgg=0, Ta=TL to TH unless otherwise noted) [Characters Symp ot [_in Tp ] Unit} 3 BUS CONTROL INPUTS (R/W, Enable, RESET, RSO, RS1, CSO, CS1, CS2) 3 [Hoput High Voltage en 20 ee V i [rout teatepe Curent Win=Oie 828i a i [ Capacitance Vin=0, Tas 25°C fMRI in a i INTERRUPT OUTPUTS (IRGA, IROB) [Beieut Cow Votege Woage 18 maT gS ay [ Bez Ourput Leakage Current tor ae] [ Copecianoe Winn 0, Ta= 25°C, TOMA tog Pp DATA BUS (00-07) [inpet High Vonege es [eee tow Venger isso ep [ Hez inout Leskepe Curent Wine a 924g pe a] [user Hah Vo Uhoag= =2059A) von vase = [Sabet Low Vege Thoege FBmA 0 [especianee WinaG, Tas aC, fe WRN a --} f= Psst

DC ELECTRICAL CHARACTERISTICS (Continued) a PERIPHERAL BUS (PAO-PA7, PBO-PB7, CAI, CA2, CBI, CB2) Input Leakage Current R/W, RESET, RSO, RS1, CSO, CS1, CS2, CAT. A (Vin = 0 t0 5.25 V) BI, Enable a [Hed nou Leakage Curent WigeOa waa ———_——~PBOBT. C82] tg] = a0 [input High Current Vie 2.4y) TT PADPAT, CAZ| Tin |= 200-400} = oA] [Bevington Dive CureniVom1SV) ——————~S—~« BB, CB] Tg _=10| = [= ae] [input Low Current Vins O4vy TC PADPAT, ABT i= [13 24 ma] ‘Output High Voltage (Load = — 200 pA) PAO-PA7, PBO-PB7, CA2, CB2 VOH Vsg+2.4 v ULoad= - 104A PAQ-PA7, CAZ Vec-1.0 [ Cutout Low Voltage Weoed=S.2 mA) a se [Capacitance Win=0.Ta= 25°C, f2V0MRI id in POWER REQUIREMENTS [nena over Diseaton Wesmrea TOO at BUS TIMING CHARACTERISTICS (See Notes 1 and 2) | 3 ea SS ee [Min [Max [Min [Max [Min [Max | Lt | crete tine ee ff 0 foe [10 fos | op a] [2 | Paise with, E Low i | =f =O = [__3_[ Pu width, € igh Ten [80] = 2 | Oe] [4 | Gioek Rise and Fal Tine dv | e- e - e| | __3_| Adress Hotd Time tan PO ep |_13 | Address Sewup Time Before tas] | — fo] et] a |_4 | chip Select Setup Time Before Es tcs_ fw | - | oo | - to] | ne] [18 J chip Seect Hola Time Tc PP = 0 = a] [_18 | Reed Date Hold Time tof 20] | 20 PY oO] eT ne] [21 wrte Baia Ho tine nw = Op a] |_30 | Output Date Delay Time toon = | 0] = Pe = eo os] L_31_[ Inout Data Setup Time tos fe] - [eT - [oT — po | “The data bus output buffers are no. longer sourcing or sinking current by TDHRMax (High Impedance). FIGURE 1 ~ BUS TIMING oJ @ © @ RIW, Addi EO 4 1, ress k7 r7 wworsineel | XXX eK | OS © H © a, al I MPU Read Data Non-Muxed ® I Read Data ni lead Data Non-Mu iF 1 Non-Muxed i: oe HO me OF Write Data MPU Write Data Non-Muxed Non-Muxed p on i OK Notes: 1. Voltage levels shown are V_$0.4 V, VH22.4 V, unless otherwise specified. 2. Measurement points shown are 0.8 V and 2.0 V, unless otherwise specified. 3-309

PERIPHERAL TIMING CHARACTERISTICS (Vcc=5.0 V +5%. Vss=0 V, TA=TL to TH unless otherwise specified) Symbo! BT Ee uni] eer | pool min [ Max | Min | Max | Min | Max | Fig. No. [Dee Seuptime Ys | of - fe | = Tro - [sf 8 [Data Hold Time ro t= pop -fo f= tls Delay Time, Enable Negative Transition to CA2 Negative Transition | tca2 | - [10] — |o670| — [os00[us| 37.8 | Delay Time, Enable Negative Transition to CA2 Positive Transition | Trasi |= [10] - 0670] — Josw[ys| 37 | Rise and Fall Times for CAT and CAg input Signals a ee Es se Delay Time from CA Active Transition to CA2 Positive Transition | tasz_]| - |20| - |135|— [10 [os[ 3.8 | Delay Time, Enable Negative Transition to CMOS Data Valid Delay Time, Enable Positive Transition to CBZ Negatve Transtion | tepz | — [ro | - [oer] - [08 fas] 11. 12] Delay Time, Data Valid to CB2 Negative Transition | wc | o|-| 0] - | af - [rs] 3.10 | Dalay Time, Enable Positive Transition to CB2 Positive Trananion | trsi | - [10] - joer] -| 08 [as] 3.11 | Control Output Pulse Width, CA2/CB2 | Pwer | 500 | = avs |= [aso = [ns [3.1 |

3 Rise and Fall Time for CB1 and CB2 Input Signals [uu |- [ro] -][my-fiota] 2 |

Delay Time, CBI Active Transition to CB2 Positive Transition [tase | —- | 20) - [135] - | 10 [us] 3.12 | [interapt Release Time, OA ang MOE un | - [10] - 110] - fom [as| 8. | [interrupt ResponseTime SSCS tvs | — PTT = POT [10 Ts 6.19 | [interrupt input Pulse time SSCS, | SOO | — | HOO] = [SOT = [nsf 13 | [RESET Low Times CSCSC~C~C~‘C~‘i tm (| 1 | = fw] = OST = Tos] | *The RESET line must be high a minimum of 1.0 us before addressing the PIA. FIGURE 3 — TTL EQUIVALENT FIGURE 2 — BUS TIMING TEST LOADS TEST LOAD (00-07) 50V (PAO-PA7, PBO-PB7, CA2, CB2) § RL=24 ke Sov Test Point MMD6150 RU= 1.25 ko or Equiv. =—'! MMD6150 c R Ten Poin & or Equiv. 130 pF 41.7 «9 T MMD7000 : or Equiv. c R Mm7000 = = or Equiv. C=30 pF, R=12k FIGURE 4 — CMOS EQUIVALENT FIGURE 5 — NMOS EQUIVALENT TEST LOAD TEST LOAD (PAO-PA7, CA2) 1G ony) Test Point 1.50 30 pF | Test Point $ = 100 oF T

~ = FIGURE 14 — TRO RELEASE TIME FIGURE 18 — RESET LOW TIME i bh TAL . Enable fl —— | RESET = UR ko ( “The RESET line must be a Vix for @ minimum of 1.0 us before addressing the PIA. Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted FIGURE 16 — EXPANDED BLOCK DIAGRAM tRQA 36 40 CAI Interrupt Stetus Contre Register A DO 33 | (CRA) | O1 32 ete Direction oz 31 Register A aed Butters (oee) U5 OS 28 D6 27 2 PAO Output 3 PAI 0? 26 Register a [J

6 PA2

5 PAS

6 PAS

. 7 PAS 4 Bus Input Register 8 PAS (BIR) 9 PA? Veo Pin 20 10 Pao Yes Pmt Output 11 Pet 4 Register 8 — 12 PB2 ££ cso 22 - Peripheral 13 p32 cs) 24 Interface 14 pea me Sz 23 Chie 15 PBS * Select oe RSO 36 ‘and 16 PBE q AS1 35 Rw 17 Pe? 3 RW 2 Controt . § Control Register B A q Register 8 (DORB) a tere, | 2 8 18 cet ae Interrupt Status ee 2A iRGB 37 Control B 19 ce2 ae

4 PIA INTERFACE SIGNALS FOR MPU

Sa f The PIA interfaces to the M6800 bus with an 8-bit bidirec- for the duration of the E pulse. The device is deselected Fe tional data bus, three chip select lines, two register select when any of the chip selects are in the inactive state, sg lines, two interrupt request lines, a read/write line, an enable es line and a reset line. To ensure proper operation with the Register Selects (RSO and RS1) — The two register = MC6800, MC6802, or MC6808 microprocessors, VMA select lines are used to select the various registers inside the a should be used as an active part of the address decoding. PIA. These two lines are used in Conjunction with internal

4 Control Registers to select a particular register that is to be

“e written or read. a Bidirectional Data (D0-D7) — The bidirectional data lines The register and chip select lines should be stable for the =4 9 {00-D7) allow the transfer of data between the MPU and the duration of the E pulse while in the read or write cycle. am PIA. The data bus output drivers are three-state devices that __ a remain in the high-impedance (off) state except when the Interrupt Request (TRQA and IROB) — The active low In- MPU performs a PIA read operation. The read/write line is in terrupt Request lines (TROA and IRQB) act to interrupt the x i the read (high) state when the PIA is selected for a read MPU either directly or through interrupt priority circuitry, x . operation These lines are “open drain’ ino load device on the chip). & This permits all interru Pt request lines to be tied together in a eF Enable (E) — The enable pulse, E, is the only timing wire-OR configuration. BE signal that is supplied to the PIA. Timing of all other signais Each Interrupt Request line has two internal interrupt flag is is referenced to the leading and trailing edges of the E pulse. bits that can cause the Interrupt Request line to go low. Each 3 flag bit is associated with a Particular peripheral interrupt = Read/Write (R/W) — This signal is generated by the line. Also, four interrupt enable bits are Provided in the PIA Ps MPU to control the direction of data transfers on the data which may be used to inhibit a particular interrupt from a as a bus. A low state on the PIA read/write line enables the input peripheral device. es buffers and data is transferred from the MPU to the PIA on Servicing an interrupt by the MPU may be accomplished aed the E signal if the device has been selected. A high on the by a software routine that, ona Prioritized basis, sequentially oe read/write line sets up the PIA for a transfer of data to the reads and tests the two control registers in each PIA for in- at bus. The PIA output buffers are enabled when the proper ad- terrupt flag bits that are set. = dress and the enable pulse E are present. The interrupt flags are cleared (zeroed) as @ result of an ei MPU Read Peripheral Data Operation of the corresponding 2a RESET — The active low RESET line is used to reset all data register. After being cleared, the interrupt flag bit can- = register bits in the PlA toa logical zero (low). This line can be ‘not be enabled to be set until the PIA is deselected during an & used as a power-on reset and as a master reset during E pulse. The E pulse is used to condition the interrupt control a system operation. lines (CA1, CA2, CB1, CB2). When these lines are used as ae __ interrupt inputs, at least one E pulse must occur from the in. a Chip Selects (CSO, CS1, and CS2) — These three input active edge to the active edge of the interrupt input signal to ea signals are_used to select the PIA. CSO and CS1 must be Condition the edge sense network. If the interrupt flag has iy high and CSZ must be low for selection of the device. Data been enabled and the edge sense circuit has been Properly = transfers are then performed under the control of the enable conditioned, the interrupt flag will be set on the next active & and read/write signals. The chip select lines must be stable transition of the interrupt input pin.

3 PIA PERIPHERAL INTERFACE LINES

3 The PIA provides two 8-bit bidirectional data buses and line while a “0” results in a “low.” Data in Output Register A ’ four interrupt/control lines for interfacing to peripheral May be read by an MPU “Read Peripheral Data A” ‘Operation = devices. when the corresponding lines are programmed as outputs. This data will be read Properly if the voltage on the a Section A Peripheral Data {PAO-PA7) — Each of the peripheral data lines is greater than 2.0 volts for a logic “1"" ay Peripheral data lines can be Programmed to act as an input or Outputand less than 0.8 volt for a logic “0” output. Loading Ba Output. This is accomplished by setting a "1" in the cor- the output lines such that the voltage on these lines does not “By responding Data Direction Register bit for those lines which reach full voltage causes the data transferred into the MPU cd are to be outputs. A “0” in a bit of the Data Direction on a Read operation to differ from that contained in the te Register causes the Corresponding peripheral data line to act respective bit of Output Register A. as as an input. During an MPU Read Peripheral Data Operation, = the data on peripheral lines Programmed to act as inputs ap- 3 pears directly on the corresponding MPU Data Bus lines. In Section B Peripheral Data (PBO-PB7) — The peripheral Fa the input mode, the internal Pullup resistor on these lines data lines in the B Section of the PIA can be Programmed to = represents a maximum of 1.5 standard TTL loads. act _as either inputs or outputs in a similar manner to PAO- £ The data in Output Register A will appear on the data lines PA7. They have three-state capabiity, allowing them to enter 2 that are programmed to be outputs. A logical 1” written in- @ high-impedance state when the peripheral data line is used ig to the register will Cause @ “high” on the corresponding data @S an input. In addition, data on the peripheral data lines 7 3-313

PBO-PB7 will be read properly from those lines programmed Peripheral control output. As an output, this line is compati- as Outputs even if the voltages are below 2.0 volts for a ble with standard TTL; as an input the internal pullup resistor “high” or above 0.8 V for a “low”. As outputs, these lines On this line represents 1.5 standard TTL loads. The function are compatible with standard TTL and may also be used as a of this signal line is programmed with Control Register A. source of at least 1 milliampere at 1.5 volts to directly drive the base of a transistor switch. Peripheral Control (CB2) — Peripheral Contro! line CB2 may also be programmed to act as an interrupt input or interrupt Input (CA1 and CB1) — Peripheral input lines Peripheral control output. As an input, this line has high in- CA1 and CB1 are input only lines that set the interrupt flags Put impedance and is compatible with standard TTL. As an of the control registers. .The active transition for these Output it is compatible with standard TTL and may also be signals is also programmed by the two control registers. used as a source of up to 1 milliampere at 1.5 volts to directly drive the base of a transistor switch. This line is programmed Peripheral Control (CA2) — The peripheral control line by Control Register B. CA2 can be programmed to act as an interrupt input or as a INTERNAL CONTROLS INITIALIZATION Notice the differences between a Port A and Port B read RESET . 7 . operation when in the output mode. When reading Port A, with ails P, APA BBOPBY. Cab any an a inoue, * we the actual pin is read, wnereas the B side read comes from an interrupts disabled. The PIA must be configured during the Ourput latch, ahead of the actual pin. festart program which follows the reset. There ore six locations within the PIA accessible to the CONTROL REGISTERS (CRA and CAB) MPU data bus: two Peripheral Registers, two Data Direction The two Control Registers (CRA and CRB) allow the MPU Registers, and two Control Registers. Selection of these to control the operation of the four peripheral control lines locations is controlled by the RSO and RS1 inputs together CAI, CA2, CB1, and CB2. In addition they allow the MPU to with bit 2 in the Control Register, as shown in Table 1. enable the interrupt lines and monitor the status of the inter- Details of possible configurations of the Data Direction Tupt flags. Bits 0 through 5 of the two registers may be writ- and Control Register are as follows: ten or read by the MPU when the proper chip select and : register select signals are applied. Bits 6 and 7 of the two registers are read only and are modified by external interrupts TABLE 1 ~ INTERNAL ADDRESSING occurring on control lines CA1, CA2, CB1, or CB2. The for- mat of the control words is shown in Figure 18. Register Bit Location Selected DATA DIRECTION ACCESS CONTROL BIT (CRA-2 and foto]. | one) [oo | 0 | x | dxte Ovection Regimes A] Bit 2, in each Control Register (CRA and CRB), deter- mines selection of either a Peripheral Output Register or the fo [is [x] x [ContorRegisterA id corresponding Data Direction E Register when the proper [+ | o | x [1 [PerpheraiResners | register select signals are applied to RSO and RS1. A “1” in [a [oo | x [0 | Bate Dvection Register _| bit 2 allows access of the Peripheral Interface Register, while | 20" causes the Data Direction Register to be addressed. X= Dont Care Interrupt Flags (CRA-6, CRA-7, CRB-6, and CRB-7) — The four interrupt flag bits are set by active transitions of signals on the four Interrupt and Peripheral Control lines when those lines are programmed to be inputs. These bits PORT A-B HARDWARE CHARACTERISTICS Cannot be set directly from the MPU Data Bus and are reset ‘As shown in Figure 17, the MC6821 has a pair of 1/0 ports marect By @ Read Peripheral Data Operation on the ap- whose characteristics differ greatly. The A side is designed prop " to drive CMOS logic to normal 30% to 70% levels, and incor- Control of CA2 and CB2 Peripheral Control Lines (CRA-3, Porates an internal pullup device that remains connected CRA-4, CRA-5, CRB-3, CRB-4, and CRB-5) — Bits 3, 4, and even in the input mode. Because of this, the A side requires 5 of the two control registers are used to control the CA2 and more drive current in the input mode than Port B. In con- CB2 Peripheral Control lines. These bits determine if the con- trast, the B side uses a normal three-state NMOS buffer trol lines will be an interrupt input or an output control which cannot pullup to CMOS levels without external signal. If bit CRA-5 (CRB-5) is low, CA2 (CB2) is an interrupt resistors. The B side can drive extra loads such as Darl- input line similar to CA1 (CB1). When CRA-5 (CRB-5) is ingtons without problem. When the PIA comes out of reset, high, CA2 (CB2) becomes an output signal that may be used the A port represents inputs with pullup resistors, whereas to control peripheral data transfers. When in the output the B side (input mode also) will float high or low, depending mode, CA2 and CB2 have siightly different loading upon the load connected to it. characteristics.

Control of CA1 and CB1 Interrupt Input Lines (CRA-0, enable the MPU interrupt signals TROA and iOS, respec- CRB-0, CRA-1, and CRB-1) — The two lowest-order bits of tively. Bits CRA-1 and CRB-1 determine the active transition the control registers are used to control the interrupt input of the interrupt input signals CA1 and CB1. lines CA1 and CB1. Bits CRA-O and CRB-O are used to FIGURE 17 — PORT A AND PORT B EQUIVALENT CIRCUITS Port A Port B Yec Vec “in N -_ = Port Pin DATA D f B a Data Direction t> Data iS DATA ) > 5 qD) Port Pin Direction D i, {| (1-»Output Pin) Data Direction {0--input Pin) (0 Input Pin) = (1 Output Pin) = ‘@ Dead of 8 5 7 data When “<] q in Output Mode Read A Data a Read of B (| p Data when To External tp in Input or a} Bus V Output Mode in Input Mode ° q Internal PIA Bus

ORDERING INFORMATION

Motorola Integrated Circuit —__J M6800 Family Blanks = 1.0 MHz A=15 MHz B=2.0 MHz Device Designation In M6800 Family Temperature Range Blank = 0°— + 70°C C= -40°— + 85°C Package P= Plastic $=Cerdip L=Cerarmic BETTER PROGRAM Better program processing is available on all types listed. Add ‘Suffix letters to part number. Level 1add"S" Level 2 add “D" Level 3. add “DS” . Level 1 “S" = 10 Temp Cycles — (-25 to 180°C); Hi Temp testing at Ta max Level 2D" = 168 Hour Burn-in at 125°C Level 3 “DS"' = Combination of Level 1 and 2. 3-315

Determine Active CA1 (CBI) Transition for Setting FIGURE 18 — CONTROL WORD FORMAT Interrupt Flag IROA(B)1 — (bit 7) b1=0: IRQA(B)1 set by high-to-low transition on CA1 (cB) bl=1: IRQA(B)t set by low-to-high transition on CAT CA1 (CB1) Interrupt Request Enable/ Disable (cei. bO=0: Disables IRQA(B) MPU Interrupt by CA1 (CBI) active transition.1 bO=1: Enable IRQA(B) MPU interrupt by CA1 (CB1) , active transition 'ROA(B) 1 Interrupt Flag (bit 7) 1, IRQA(B) will occur on next (MPU generated) positive Goes high on active transition of CA1 (CB1); Automa- transition of bO if CA1 (CB1) active transition oc- tically cleared by MPU Read of Output Register A(B). curred while interrupt was disabled. May also be cleared by hardware Reset. [wv [ws Tos Tom [= | » ~m Tow] Control Register [Taqaiait | IRQAIBI2 CA2 (CB2) DDR CAt (CBI) K} Flag Flag Control Access Control . IRQA(B)2 Interrupt Flag (bit 6) When CA2 (C82) is an input, IRQAIB) goes high on ac- Determines Whether Data Direction Register Or Output tive transition CA2 (CB2); Automatically cleared by Register is Addressed MPU Read of Output Register A(B). May also be b2=0: Data Direction Register selected cleared by hardware Reset. b2=1: Output Register selected CA2 (CB2) Established as Output (bS=1): IRQA(B) 2=0, not affected by CA2 (CB2) transitions, CA2 (CB2) Established as Output by b5=1 CA2 (CB2) Established as input by b5=0 (Note that operation of CA2 and CB2 output bS b4 bg functions are not identical) BS ca2 10 b3=0: Read Strobe with CAI Restore 0 CA2 (CB2) Interrupt Request Enable/Disable CA2 goes low on first high-to-low b3=0; Disables (ROA(B) MPU Interrupt by E transition following an MPU read CA2 (CB2) active transition. * of Output Register A; returned high b3=1: Enables IROA(B) MPU Interrupt by by next active CAI transition, as CA2 (CB2) active transition, specified by bit 1. “IRQA(B) will occur on next (MPU generat- b3=1: Read Strobe with E Restore ted) positive transition of b3 if CA2 (CB2) CA2 goes low on first high-to-low active transition occurred while interrupt E transition following an MPU read was disabled. of Output Register A; returned high Determines Active CA2 (CB2) Transition for by next high-to-fow E transition dur- Setting Interrupt Flag IRQAB)2 — (Bit b6) ing @ deselect. b4=0: IRQA(BI2 set by high-to-low transi- ce2 tion on CA2 (CB2). b3=0: Write Strobe with CB1 Restore bé=1: IRQA(BI2 set by low-to-high transi- CB2 goes low on first low-to-high tion on CA2 (CB2). E transition following an MPU write into Output Register B; returned high by the next active CB1 transi- tion as specified by bit 1. CRB-b7 must first be cleared by a read of data. b3= 1: Write Strobe with E Restore CB2 goes low on first low-to-high E transition following an MPU write into Output Register B; returned BB b4 bs high by the next low-to-high E tran- a sition following an E pulse which Occurred while the part was de- selected.

14 Set/Reset CA2 (CB2)

CA2 (CB2) goes low as MPU writes b3=0 into Control Register. CA2 (CB2) goes high as MPU writes b3= 1 into Control Register. _ - 7