MC68184

MC68184 MOTOROLA | Alldatasheet

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m= SEMICONDUCTOR oI TECHNICAL DATA MC68184 Technical Summary Broadband Interface Controller The MC68184 broadband interface controller (BIC) is a high-performance inter- face device for use with the MC68824 token bus controller (TBC) to implement the digital portion of the physical layer of a broadband IEEE 802.4 token bus node. The BIC manipulates both data and control for RF transmitter circuitry and RF receiver circuitry. The CMOS BIC supports data rates up to 10 Mbps using a duo-binary modulation technique. The BIC is available in a 40-pin plastic dual-in-line package. The MC68184 provides the following features: @ Implements Digital Portion of IEEE 802.4 Broadband Physical Layer @ Provides Station Management for Physical Layer © Supports Serial Data Rates up to 10 Mbps ® 20 Lines for Receiver/Transmitter Control with 13 User-Defined Outputs @ Includes Ability to Scramble and Descramblie Data @ Kicker Insertion and Deletion Capability ® Two Loopback Modes @ Interfaces via a Standard Serial Interface to MC68824 TBC @ Able to Connect Either Directly to TBC or to TBC through an Arbitrary | 3 Length of Cable This document contains information on a new product. Specifications and information herein are subject to change without notice. MOTOROLA M68000 FAMILY REFERENCE MANUAL 8-1

forms the media access control (MAC) function. binary signals corresponding to the coding rules listed in Table 1. Figure 1. Token Bus Node

1 Iwour2

Figure 2. BIC Functional Block Diagram

Table 1. IMPULSEO and IMPULSE1 Encoding signals are inputs to the decoder according to the encoding listed in Table 2. Table 2. LEVELO and LEVEL1 Encoding OUT1-IN/OUT8 and output lines OUT9-OUT13.

signals, 13 are user-defined signals. physical data indication channel. broadband allows 1, 5, or 10 MHz clocks. TXSYMO have the encoding listed in Table 3. Table 3. Request Channel SM Mode Encoding (SMREQ=0)

Table 4. Request Channel MAC Mode Encoding (SMREO = 1) Zero is the logical state zero. One is the logical state one. Nondata is a delimiter flag and is always requested in pairs. Pad-Idle is one symbol of preamble/ interframe idle. Silence is silence or pseudo-silence. plexed and have different meanings depending on the state of SMIND. networks allows 1, 5, or 10 MHz clocks. | 8 are encoded to confirm response to management commands. RXSYM1, and RXSYM0 is shown in Table 5. Table 5. Indication Channel SM Mode Encoding (SMIND = 0) *Indicates RXSYMO contains the SM RX data when responding to a serial data command.

Table 6. Indication Channel MAC Mode Encoding (SMIND = 1) Zero is the logical state zero. One is the logical state one. Silence is silence or pseudo-silence. The following paragraphs describe the RF transmitter signals. transmit clock (TXCLK) and the receive clock (RXCLK). The following paragraphs describe the RF receiver signals. circuitry. These signals are decoded by the BIC decoder as shown in Table 2.

The automatic gain control (AGC) HOLD is low whenever CARRIER DETECT is low. If CARRIER DETECT is high, then AGC HOLD will be high whenever a start delimiter is found on LEVELO and LEVEL1. A start delimiter consists of the following sequence of eight bits: 2-0 or 2-4, 2-0 or 2-4, 0, 2-0 or 2-4, 2-0 or 2- 4, 0, 0, 0. When CARRIER DETECT is high, AGC HOLD will be low if one of the following occurs: 24 of the same inputs are received on LEVELO and LEVEL1 (the encodings 2-0 and 2-4 are considered different inputs); if two, three, or four nondatas (2-0 or 2-4) are contained in bit positions 1, 2, 4, and 5 relative to the start delimiter; if the error corrector is disabled (bit 7 of register 1 is set) and a nondata in bit positions 3, 6, 7, or 8 not belonging to a kicker is present; if the descrambler disable bit is set (bit 4 of register 1) and a kicker is present; if a reset occurs. CONTROL SIGNALS The BIC has 20 control signals, 13 of which are user-defined. RESET RESET is a bidirectional signal. When RESET is driven low, the BIC will reset. RESET must be driven low at power-up and held low for at least 10 clock cycles after all clocks become stable. A pullup resistor (>150 k) is provided to drive this pin to the inactive state. In addition, when the BIC receives a reset command from the TBC, it will drive RESET low for as long as the reset command is asserted. JABBER TIME OUT The JABBER TIME OUT pin is an input to the BIC from the external jabber timer | 8 | circuitry. When JABBER TIME OUT is driven low, the BIC will drive IMPULSEO and IMPULSE1 high (silence state), drive TRANSMIT DISABLE and SMIND low, and drive RXSYM2, RXSYM1, and RXSYMO high. These pins will continue in these states until a reset is received by the BIC. The reset can occur by either driving the RESET pin low or sending a reset command to the BIC. A pullup resistor (>150 k{2) is provided to drive the JABBER TIME OUT pin to the inactive state. 8-8 M68000 FAMILY REFERENCE MANUAL MOTOROLA

No carrier is present when the CARRIER DETECT pin is driven low. This pin is driven by external circuitry that senses when the carrier is lost on the broadband cable. AGC HOLD will also be driven low when CARRIER DETECT is low. When CARRIER DETECT is low and the BIC is not in internal loopback mode nor in SM mode, then RXSYM2, RXSYM1, and RXSYM0 are driven high, meaning silence. If CARRIER DETECT is low and the BIC not in external loopback mode, then IMPULSEO and IMPULSE1 are driven high, meaning silence. FAULT DETECT The FAULT DETECT pin operates in the same manner as the JABBER TIME OUT pin. When FAULT DETECT is driven low, the BIC will drive IMPULSEO and IMPULSE1 high, drive TRANSMIT DISABLE and SMIND low, and drive RXSYM2, RXSYM1, and RXSYMO high. These pins will continue in these states until a reset is received by the BIC. The reset can occur by either driving the RESET pin low or sending a reset command to the BIC. An internal pullup resistor (>150 kQ) is provided to drive FAULT DETECT to the inactive state. EXTERNAL LOOPBACK The EXTERNAL LOOPBACK pin is driven high if, since the last reset, bits 1 and 2 of register 1 have been set to zero and one, respectively, and a loopback disable command has not been received by the BIC from the TBC. When EX- TERNAL LOOPBACK is high, the BIC is in external loopback mode. TRANSMIT DISABLE The TRANSMIT DISABLE pin is bidirectional. TRANSMIT DISABLE is driven active low by any one of the following conditions: during a reset; after a reset until a loopback command and an enable transmitter command are received from the TBC; while TXSYM3 is low; while a physical error is being reported (RXSYM2=1, RXSYM1=1, RXSYMO=1, and SMIND=0). Since a pullup resis- tor (>150 kQ) is provided, TRANSMIT DISABLE can also be driven low by an external source. When TRANSMIT DISABLE is driven active low, IMPULSEO and IMPULSE1 will be forced high (silence) unless the BIC is in external loop- back mode. In external loopback mode (EXTERNAL LOOPBACK signal high), the state of TRANSMIT DISABLE does not affect IMPULSEO or IMPULSE1. USER-DEFINED CONTROL SIGNALS The following paragraphs describe the user-defined control signals. MOTOROLA M68000 FAMILY REFERENCE MANUAL 8-9

These eight independent pins are bidirectional. Register 3E contains the state of these eight pins. Each pin can be individually programmed as an output to control the RF section. As inputs, these pins can be used to monitor the RF section. Register 3F determines if these pins are inputs or outputs. OUT9-OUT13 These five output signals are user-defined. OUT9, OUT10, and OUT11 are driven low when a reset is sent to the BIC; OUT12 and OUT13 are driven high when a reset is received by the BIC. These outputs can be used to control the RF section as required. BIC REGISTERS Five registers are present in the BIC. All registers are read/write except register 0, which is a read-only register. REGISTER 0 Register 0, an 8-bit, read-only register, has the following format: 0 — JABBER TIME OUT a This bit indicates the state of the JABBER TIME OUT pin prior to the last reset command from the TBC. When the JABBER TIME OUT pin becomes active, the BIC goes into physical error mode, which can only be exited by a reset to the BIC. Before the first reset command is given (after the BIC is powered up), this bit has no meaning. 1 — MODEM FAILURE - | 8 | This bit indicates the state of the FAULT DETECT pin prior to the last reset command from the TBC. Before the first reset command is given (after the BIC is powered up}, this bit has no meaning. 2 — INPUT FAILURE This bit indicates the state of the bad input (from the encoder) prior to the last reset command from the TBC. Before the first reset command is given (after the BIC is powered up), this bit has no meaning. 3 — MEDIUM FAILURE This bit indicates the inverse of the CARRIER DETECT pin. 8-10 M68000 FAMILY REFERENCE MANUAL MOTOROLA

enabled by an enable transmitter command. BIC will only activate the TRANSMIT DISABLE pin. This bit always reads as zero. enabled as listed in Table 7. Table 7. Loopback State When high, this bit disables the encoder scrambler and the kicker inserter. When high, this bit disables the decoder descrambler and kicker deleter.

5 — PSEUDO-SILENCE ADDER DISABLE When high, this bit disables the pseudo-silence adder in the encoder. The psuedo-silence adder only operates when the BIC is in internal loop- back or external loopback mode. 6 — PSEUDO-SILENCE SUBTRACTER DISABLE When high, this bit disables the pseudo-silence subtracter in the decoder. 7 — ERROR CORRECTOR DISABLE When high, this bit disables the decoder error corrector. REGISTER 3D Register 3D, an 8-bit read/write register, can disable functions of the BIC as well as control the state of the five user-defined output pins. Register 3D has the following format: 0 — DUO-BINARY DISABLE This bit disables the duo-binary encoder when high. 1 — BAD INPUT DISABLE This bit disables the bad input detector in the encoder when high. 2 — SYNCHRONIZER DISABLE This bit disables the encoder synchronizer when high. 3 — OUTS This bit controls the state of OUT9. When this bit is read, it indicates the actual TTL state of OUT9 and not the requested state. A reset forces OUTS low. 4— OUT10 This bit controls the state of OUT10. When this bit is read, it indicates the actual TTL state of OUT10 and not the requested state. A reset forces OUT11 low. 5 — 0UT11 This bit controls the state of OUT11. When this bit is read, it indicates the actual TTL state of OUT11 and not the requested state. A reset forces OUT11 low. 8-12 M68000 FAMILY REFERENCE MANUAL MOTOROLA

6 — OUT12 This bit controls the state of OUT12. When this bit is read, it indicates the actual TTL state of OUT12 and not the requested state. A reset forces OUT12 high. 7 — OUT13 This bit controls the state of OUT13. When this bit is read, it indicates the actual TTL state of OUT13 and not the requested state. A reset forces OUT13 high. REGISTER 3E Register 3E is an 8-bit read/write register that allows the control bits to be read or written. When read, this register always indicates the actual TTL state of the IN/OUT1-IN/OUTS8 pins. Writing to a bit of register 3E that has been defined as an input by the respective IN/OUT DIRECTION bit does not affect what is read. However, it will change the pin state when changed to an output. IN/ OUT1-IN/OUTS pins have internal pullup resistors. REGISTER 3F Register 3F, an 8-bit read/write register, determines if the IN/OUT pins are being read or written. Reset forces IN/OUT1-IN/OUTS pins low, defining IN/OUT1-IN/ OUTS8 as inputs. MOTOROLA 68000 FAMILY REFERENCE MANUAL 8-13

40-LEAD DUAL-IN-LINE PACKAGE TRANSMIT DISABLE [] 1 40 [] EXTERNAL LOOPBACK xsywo [] 2 39 [] ours Axsymt [] 3 38 {] ouriz Rxs¥M2 [] 4 37 [] IMPULSEO SMIND [] 5 36 [] IMPULSEt AXCLK [] 6 35 [] RESET test 7 34 [] IMPULSE cLock TXCLK [] 8 33 [] CARRIER DETECT SMREO [] 9 32 1] Yoo ec} TxSyM2 [] 10 Mcsai84 31 [] Vss (GND) Voo (Vee) (11 30 [] JABBER TIME OUT Vgg(GNO) [] 12 29 [] FAULT DETECT Txsymt [J 13 28 [] LEVELO TxsyMo [] 14 27 [] veveut iwours [] 15 26 [] Acc HOLD iwouT2 [J 16 25 [] ouTi1 ious [] 17 24 [J outio inoura [J 18 23 [] outs INOUTS [} 19 22 {] wouTe iwours [] 20 21 [] iwout7 8-14 M68000 FAMILY REFERENCE MANUAL MOTOROLA

44-LEAD PLASTIC LEADED CHIP CARRIER x ey Fi 2 2 ea geeEeeees nonononnenn Test (7 1 39[] ouTi3 Txeuk C] 1) ourz SMREG (J 1 IMPLUSEO Txysmz Cj 1 IMPLuse! Voo(Veo) Cf 1 RESET Vss(GND) C] Mc68184 1) IMPLUSE CLOCK Txsymt (J [) CARRIER DETECT Txsymo (J 1 Voo(Vec) iwouni C] 1 Vgs (GND) iwouTz [) JABBER TIME OUT iwours (417 29[0 FAULT DETECT 18 2B COO oooooc ERebeesesgas gegegessiae oO g MOTOROLA M68000 FAMILY REFERENCE MANUAL 8-15