MC68160A IDT | Alldatasheet

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Order this document by MC68160A/D Device Operating Temperature Range Package FB SUFFIX PLASTIC PACKAGE CASE 848D (LQFP-52)

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MC68160AFB T A = 0° to + 70°C LQFP 52 1 Enhanced Ethernet Transceiver The MC68160A Enhanced Ethernet Interface Circuit is a BiCMOS device which supports both IEEE 802.3 Access Unit Interface (AUI) and 10BASE-T Twisted Pair (TP) Interface media connections through external isolation transformers. It encodes NRZ data to Manchester data and supplies the signals which are required for data communication via 10BASE-T or AUI interfaces. The MC68160A gluelessly interface to the Ethernet controller contained in the MC68360 Quad Integrated Communications Controller (QUICC) device. The MC68160A also interfaces easily to most other industry-standard IEEE 802.3 LAN controllers. Prior to twisted pair data reception, Smart Squelch circuitr y qualifies input signals for correct amplitude, pulse width, and sequence requirements.

  • Automatic Twisted Pair Wiring Polarity Fault Detection and Correction Option
  • Automatic Port Selection Option with Status Output
  • Driver Pre-emphasis for Twisted Pair Output Data
  • Crystal Controlled Clock Oscillator or External Clock Generator Option
  • Digital Phase-Locked-Loop (DPLL) Timing Recovery and Data Decoding
  • Standby Mode with Reduced Power Consumption
  • Twisted Pair Signal Quality Error (Heartbeat) Test Option
  • Diagnostic Local Loop Back Option
  • Transmit, Receive and Collision Detection Status Output
  • Full-Duplex Operation Option on Twisted Pair Port
  • Twisted Pair Jabber Detection and Status Output
  • Link Integrity Testing and Status Output The sale and use of this product is licensed under technology covered by one or more Digital Equipment Corporation patents.  Motorola, Inc. 2000 Rev 1 DATA SHEET MC68160A IDT™ Enhanced Ethernet Transceiver Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MC68160A Enhanced Ethernet Transceiver

2 MOTOROLA ANALOG IC DEVICE DATA

Figure 1. 10Base-T Interface Block Diagram

20 MHz

This device contains 20,000 active transistors.

4 MOTOROLA ANALOG IC DEVICE DATA

Table 1. Pin Function Descriptiont

1 RENA O

RCLK. In the standby mode, RENA is driven to the high impedance state.

2 RX O

48 TCLK O

49 TENA I

50 RCLK O

51 CLSN O

52 TX I

be Manchester encoded. In the standby mode, TX is driven to the high impedance state. detect the line activity. Signals at ACX+/- have no effect on data path functions. detect the line activity, and a data receiver with no offset for Manchester Data reception. balanced high state voltage. by preventing crosstalk and impulse noise conditions from activating the receive function. automatically selected, the 10BASE-T outputs remain active. NOTE: The sense of the controller interface pins will change, depending on the controller selected.

Table 1. Pin Function Description (continued)

12 MFILT C Frequency Multiplier Filter Connection Point: An external resistor capacitor filter must be

16 X1 I/C

external 20 MHz CMOS compatible clock generator.

17 X2 O/C

an external CMOS Clock generator. mode, all of the controller inputs and outputs are driven to the high impedance state.

6 LOOP I

delivered following each transmission to simulate the twisted pair SQE test.

9 APORT I

circuitry associated with the unselected port.

27 TPSQEL I

28 TPFULDL I

be asserted with LOOP as a test mode is enabled that disrupts normal operation.

29 TPAPCE I

46 TPEN I/O

manually selected, the MC68160A will not produce link pulses for the TP port. with the unselected port. In the standby mode, this pin is driven to the high impedance state.

6 MOTOROLA ANALOG IC DEVICE DATA

40 TXLED O

duty cycle. In the standby mode, this output is driven to the high impedance state.

41 RXLED O

duty cycle. In the standby mode, this output is driven to the high impedance state.

42 CLLED O

duty cycle. In the standby mode, this output is driven to the high impedance state.

43 TPLIL O

is selected. In the standby mode, this output is also driven to the high impedance state.

44 TPPLR O

45 TPJABB O

the standby mode, this output is also driven to the high impedance state.

10 VDDDIV Frequency Divider Supply Pin

20 GNDSUB Substrate Ground Pin

47 GNDCTL Controller Interface Ground Pin

NOTE: Power and ground pins are not connected internally. Failure to connect externally may cause malfunction or damage to the IC.

Table 2. Controller Interface Selection NOTES: 1. Although LOOP input is not ordinarily classifed as a controller pin, it is included in this table because its sense varies according to the controller used.

  1. The Motorola controller interface contained in the MC68360 (QUICC) is compatible with the AMD 7990 (LANCE) and 79C900 (ILACC) controllers.
  2. The pin sense is shown from the perspective of the identified controller pin.
  3. Supported only by MC68160A.

Table 3. Controller Independent Mode Selection reset pulse of approximately 6.0 µs duration is generated. data reception is approximately 100 ms. Figure 2. Applications Block Diagram

8 MOTOROLA ANALOG IC DEVICE DATA

ELECTRICAL CHARACTERISTICS

Characteristic Symbol Min Max Unit Storage Temperature Range Tstg -6 5 150 °C Power Supply Voltage Range Analog Digital VDDA VDDD 7.0 7.0 V Voltage on any TTL compatible input pin with respect to Ground Voltage on TPRX, ARX, or ACX input pins with respect to Ground V - 0.5 - 0.5 VDD + 0.5 6.0 V Differential Voltage on TPRX, ARX, or ACX Input Pins VDIFF - 6.0 6.0 V NOTE: Stresses in excess of the Absolute Maximum Ratings can cause permanent damage to the device. Functional operation of the device is not implied at these or any other conditions in excess of those indicated in the operation sections of this data sheet. Exposure to Absolute Maximum Ratings conditions for extended periods can adversely affect device reliability. RECOMMENDED OPERATING CONDITIONS Characteristic Symbol Min Max Unit Power Supply Voltage Range VDD 4.75 5.25 V Power Supply Ripple (20 kHz to 100 kHz) - - 50 mV Power Supply Impulse Noise (Either Polarity) - - 100 mV Ambient Operating Temperature Range TA 0 70 °C ARX/ACX Input Differential Rise and Fall Time (see Figure 39) t260 2.0 10 ns ARX Pair Idle Time after Transmission (see Figure 39) t265 8.0 - µs ESD Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Motorola employs a Human Body Model (HBM) and a Charged Device Model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD has been adopted for the CDM, however, a standard HBM (resistance = 1500 Ω capacitance - 100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using the circuit parameters contained in this specification. ESD threshold voltage is designed to 700 V Human Body Model. DC ELECTRICAL CHARACTERISTICS (Unless otherwise noted, minimum and maximum limits apply over the recommended ambient operating temperature and power supply voltage ranges.) Characteristic Symbol Test Conditions Min Typ Max Unit POWER SUPPLY Undervoltage Shutdown Threshold - - - - 4.4 V Power Supply Current IDD - Standby Mode 145 200 5.0 mA MC68160A Enhanced Ethernet Transceiver NETCOM IDT™ Enhanced Ethernet Transceiver Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MC68160A

9MOTOROLA ANALOG IC DEVICE DATA DC ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC = 5.0 V ± 5%. Unless otherwise noted, minimum and maximum limits apply over the recommended ambient operating temperature and power supply voltage ranges for each MC68160A except where noted.) Characteristic Symbol Test Conditions Min Max Unit TTL COMPATIBLE INPUTS TTL Compatible Input Voltage Low State High State VIL(TTL) VIH(TTL) 2.0 0.8 V Input Current TTL Compatible Input Pins (Note 1) Input Current TENA TTL Compatible Input Pin: with Pull-Down Resistor IIH IIL with Pull-Down Resistor removed in Standby Mode IIH IIL IIH & IIL

0 V < VI < VDD -

±10 +200 -2 0 ±10 µA CMOS COMPATIBLE INPUTS CMOS Compatible Input Voltage Low State High State VIL(CMOS) VIH(CMOS) 3.0 1.0 V Input Current (Pin X1) IIH & IIL 0 V < VI < VDD - ±100 µA TTL/CMOS COMPATIBLE OUTPUTS TTL/CMOS Compatible Output Voltage Low State (Note 2) Low State (Note 3) VOL IOL = 4.0 mA IOL = 10 mA 0.45 0.45 V TTL/CMOS Compatible Output Voltage High State (Note 4) High State (Note 5) High State (Note 2) VOH IOH = - 500 µA IOH = - 10 mA IOH = - 4.0 mA 3.9 3.9 2.4 V Three State Output Leakage Current IOZ 0 V ≤ VOZ ≤ VDD - ±10 µA Characteristic Symbol Test Conditions Min Max Unit TWISTED PAIR RECEIVER INPUTS Input Voltage Range (DC + AC) VITP - 1.5 4.3 V Differential Input Squelch Threshold Voltage VITPSQ Note 10 270 390 mV Common Mode Bias Generator Voltage VBCMTP Note 9 1.8 3.2 V Common Mode Input Resistance RCMTP - 1000 - Ω Differential Input Resistance RDIFFTP - 2.5 - kΩ TWISTED PAIR TRANSMITTER OUTPUTS Differential Output Voltage Pre-Emphasis Level Signal Level VODFTPP VODFTPS Note 7 ±2.2 ±1.56 ±2.8 ±1.98 V Common Mode Output Voltage Range VOCMTP Note 6 0 4.0 V Common Mode Output Voltage in Standby Mode VOCMTPSB IOH = -100 µA VDD - 1.0 VDD V NOTES: 1. APORT, TPAPCE, CS0, CS1, CS2, TX, LOOP, TPFULDL, TPSQEL and TPEN (In Input Mode). 2. TCLK, RX, RCLK, RENA and CLSN. 3. TPPLR, TPLIL, TPJABB, TXLED, RXLED, CLLED and TPEN (In Output Mode). 4. TPPLR, TPLIL, CLLED, TXLED and RXLED. 5. TPJABB and TPEN (In Output Mode). 6. Measured with Test Load B1 (shown in Figure 3), applied directly to the TPTX+/- pins of the device. 7. Measured differentially with Test Load B2 (shown in Figure 4), applied directly to the TPTX+/- pins of the device. 8. Measured directly on the TPTX+/- pins of the device. 9. Measured with Test Load B3 (shown in Figure 5), applied directly to the TPRX+/- pins of the device. 10. The Common Mode Input Voltage is between 1.8 V and 3.2 V. MC68160A Enhanced Ethernet Transceiver NETCOM IDT™ Enhanced Ethernet Transceiver Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MC68160A

10 MOTOROLA ANALOG IC DEVICE DATA

DC ELECTRICAL CHARACTERISTICS (continued) (TA = 25°C, VCC = 5.0 V ± 5%. Unless otherwise noted, minimum and maximum limits apply over the recommended ambient operating temperature and power supply voltage ranges for each MC68160A except where noted.) Characteristic Symbol Test Conditions Min Max Unit TWISTED PAIR TRANSMITTER OUTPUTS Differential Output Voltage IDLE Mode Open Circuit VODFTPI VODFTPO Note 6 Note 8 ±50 5.25 mV V Differential Output Impedance TRANSMISSION Mode IDLE Mode RODFTPT RODFTPI Note 8 8.0 Ω Common Mode Output Impedance TRANSMISSION Mode IDLE Mode ROCMTPT ROCMTPI Note 8 3.0 1.0 7.0 Ω NOTES: 1. APORT, TPAPCE, CS0, CS1, CS2, TX, LOOP, TPFULDL, TPSQEL and TPEN (In Input Mode). 2. TCLK, RX, RCLK, RENA and CLSN. 3. TPPLR, TPLIL, TPJABB, TXLED, RXLED, CLLED and TPEN (In Output Mode). 4. TPPLR, TPLIL, CLLED, TXLED and RXLED. 5. TPJABB and TPEN (In Output Mode). 6. Measured with Test Load B1 (shown in Figure 3), applied directly to the TPTX+/- pins of the device. 7. Measured differentially with Test Load B2 (shown in Figure 4), applied directly to the TPTX+/- pins of the device. 8. Measured directly on the TPTX+/- pins of the device. 9. Measured with Test Load B3 (shown in Figure 5), applied directly to the TPRX+/- pins of the device. 10. The Common Mode Input Voltage is between 1.8 V and 3.2 V. DC ELECTRICAL CHARACTERISTICS (Unless otherwise noted, minimum and maximum limits apply over the recommended ambient operating temperature and power supply voltage ranges.) Characteristic Symbol Test Conditions Min Max Unit AUI RECEIVER INPUTS Input Voltage Range (DC + AC) VIA - 1.0 4.2 V Differential Mode Input Voltage Range VIDFA - ±318 ±1315 mV Differential Input Squelch Threshold Voltage VIASQ - - 275 -175 mV Common Mode Input Resistance RICMA 1.0 V < VICMA < 4.2 V 1.5 - kΩ Differential Input Resistance (ARX, ACX Inputs) RIDFA 1.0 V < VICMA < 4.2 V 318 mV < VIDMA < 1315 mV 5.0 - kΩ AUI TRANSMITTER OUTPUTS Common Mode Output Voltage IDLE Mode ACTIVE Mode STANDBY Mode VOCMIA VOCMAA VOCMSA Figure 6 IO = -100 µA 1.0 1.0 VDD - 2.0 4.2 4.2 VDD - 1.2 V Differential Output Voltage IDLE Mode ACTIVE Mode VODFIA VODFAA Figure 6 ±600 ±40 ±1315 mV Differential Output Load Current IDLE Mode IODFIA Figure 7 - ±4.0 mA Output Short Circuit Current IODSA Output Short Circuited to VDD or GND - ±150 mA MC68160A Enhanced Ethernet Transceiver NETCOM IDT™ Enhanced Ethernet Transceiver Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MC68160A

12 MOTOROLA ANALOG IC DEVICE DATA

NOTES: 1. To meet IEEE-802.3 specifications.

  1. Load on specified output is 20 pF to ground, unless otherwise noted.

Figure 8. X1 Input Voltage Levels for Timing Measurements

14 MOTOROLA ANALOG IC DEVICE DATA

Figure 12. Receive Timing (Motorola End of Frame) NOTE: Load on specified output is 20 pF to ground, unless otherwise noted. Figure 13. Transmit Timing (Intel)

16 MOTOROLA ANALOG IC DEVICE DATA

Figure 16. Receive Timing (Fujitsu Start of Frame) Figure 17. Receive Timing (Fujitsu End of Frame) NOTE: Load on specified output is 20 pF to ground, unless otherwise noted.

18 MOTOROLA ANALOG IC DEVICE DATA

NOTES: 1. Measured differentially across the output of Test Load A which is connected directly to the TPTX+/- pins of the device.

  1. Measured differentially across the output of Test Load D shown in Figure 23 which is connected directly to the TPTX+/- pins of the device.
  2. Measured across the output of Test Load C which is connected directly to the TPTX+/- pins of the device.
  3. Same as t 137 except the logic states for TENA and RENA are inverted.
  4. Measured across the output of Test Load B shown in Figure 21.
  5. Measured at the +/-90% points of the precompensation voltage feature of the waveform. (The 0% reference is 0 V differential.)
  6. Load on specified output is 20 pF to ground.

NOTE: A total of 50 Ω per driver output is required for proper series line termination. together with the internal driver output resistance. Figure 20. Test Load A Figure 21. Test Load B Figure 22. Test Load C Figure 23. Test Load D

20 MOTOROLA ANALOG IC DEVICE DATA

Figure 27. TPTX+/- Link Pulse Timing NOTE: The load attached to the specified output is a 20 pF capacitor connected to ground, unless otherwise noted. Figure 28. TPJABB Switching

22 MOTOROLA ANALOG IC DEVICE DATA

Figure 32. TPRX Receive Timing (Start of Frame) Figure 33. RENA Deassertion Delay from Last Valid Positive Transition of TPRX Pair Figure 34. TP Receive Link Integrity Switching

24 MOTOROLA ANALOG IC DEVICE DATA

NOTE: Load on specified output is a shunt 27 µH inductor and 83 Ω resistor. Figure 38. ATX Transmit Timings

  1. The squelch circuits are on at idle (with input voltage at approximately 0 V differential).
  2. If an input is in squelch, pulse is rejected if the peak differential voltage is more positive than -175 mV, regardless of pulse width.
  3. A pulse is considered valid if its peak differential voltage is more negative than -300 mV and its width, measured at -285 mV, is > 25 ns.
  4. The squelch circuits are disabled by the first valid negative differential pulse on either the AUI receive data or collision pair.
  5. If a positive differential pulse occurs on either the AUI receive data or collision pair > 175 ns, end of frame is assumed and squelch circuitry is turned on.

Figure 39. ARX/ACX Timing

Figure 40. ARX/ACX Timing separate media dependent interfaces and a SIA interface. indicator pins. All but one are open collector outputs. the received data to the controller. screened for proper sequence and pulse width requirements. controller via the SIA interface. munications controller must be synchronized to TCLK. circuit will have to be chosen for each application.

26 MOTOROLA ANALOG IC DEVICE DATA

If after approximately 40 ms after a TP or AUI transmission has begun, the EEST is still transmitting, the TPJABB pin will assert to signify a jabber condition. Also, the CLLED pin will transition high and low alternately with a 100 ms period. The transmit circuitry is, however, unaffected by the jabber condition, so the communications controller has the responsibility of monitoring and stopping transmission. When transmission is complete, the transmit circuitry will begin the end of transmit and decay to idle responses necessary to meet requirements of the 802.3 standard for the TP and AUI port. Data Reception Other than the case of being in Loop Back mode, data reception to the RX pin of the EEST is initiated by signaling at the RX+/- or AUI ARX+/- pins. If at the TP port, the data is screened for validity by checking for sequence and pulse width requirements, then passed to the decode and receive circuitry. The RENA pin asserts and the data and corresponding clock is passed to the communications controller. After the frame has been transmitted, the MC68160A detects the ending transmission and negates RENA. If at the AUI port, the data is checked for proper pulse width requirements before being passed to the decode circuitry. If the data pulses are longer than at least 20 ns, RENA gets asserted and the frame is decoded to RX with and accompanying RCLK output. Collision Collision is the occurrence of simultaneous transmit activity by two or more stations on the network. In the event of collision, the data transfer paths are unaffected. If the MC68160A is in the twisted pair mode, collision is detect by simultaneous receive and transmit activity. If in the AUI mode, collision is detected by activity on the ACX+/- pins. In either case, if collision is detected, the CLSN pin will assert to notify the communications controller. Jabber The EEST has a jabber timer to detect the jabber condition. In the event that the transmitting station continues to transmit beyond the allowable transmit time, a jabber timer (40 ms) will expire and assert the TPJABB pin to alert the communications controller of the situation. The TPJABB pin can source or sink up to 10 mA, and so, is capable of driving a status LED. In the AUI mode, the pin is driven to high impedance since the transceiver connected to the AUI port must alert the communications controller of the jabber condition. Full Duplex A feature unique to the MC68160A is the Full Duplex mode. In this mode the EEST is capable of transmitting and receiving simultaneously. Collision conditions are not announced and internal loop back is disabled. The remainder of the EEST functionality remains unchanged from the non-Full Duplex mode. Full Duplex mode is enabled by asserting the TPFULDL pin. Auto Port Selection If the APORT pin is asserted, the MC68160A will automatically select the TP or AUI port depending on the presence of valid link beats or frames at the TP RX+/- pins. If the AUI port is automatically selected by another transmitting station or by setting TPEN low, the TP transmit port of the EEST continues to transmit link beats to keep the link active. Auto Polarity Selection If the RX+ and the RX- wires happen to get reversed, the MC68160A has the ability to automatically reverse the pins internally so that the received data is valid. In addition, an open collector status pin (TPPLR) is driven low to indicate the fault. In the AUI or reset mode this pin presents a high impedance. Loop Back Mode To test the transmit and receive circuitry without disturbing the connected network, the EEST has a Loop Back mode. Loop Back mode routes transmit data and clock to the receive data and clock pins using as much of the transmit and receive circuitry as possible. This gives a test of the MC68160A Manchester encode and decode function. LOOP must not be asserted when TPFULDL pin is asserted. This causes the MC68160A to enter a test mode. This test mode is used during final test and is not intended to be entered under normal operation (see Application Notes section). MC68160A Enhanced Ethernet Transceiver NETCOM IDT™ Enhanced Ethernet Transceiver Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MC68160A

27MOTOROLA ANALOG IC DEVICE DATA APPLICATIONS INFORMATION Selection of Crystal and External Components Accuracy of frequency and stability over temperature are the main determinants of crystal choice. Specifications for a suitable crystal are tabulated below. ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Frequency ÁÁÁÁÁ ÁÁÁÁÁ

20.000 MHz

ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Mode ÁÁÁÁÁ ÁÁÁÁÁ Fundamental ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Tolerance ÁÁÁÁÁ ÁÁÁÁÁ ± 100 ppm ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Stability ÁÁÁÁÁ ÁÁÁÁÁ ± 100 ppm ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Aging ÁÁÁÁÁ ÁÁÁÁÁ ± 5 ppm/yr ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Shunt Capacitance ÁÁÁÁÁ ÁÁÁÁÁ 7.0 pF ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Load Capacitance ÁÁÁÁÁ ÁÁÁÁÁ 18-20 pF ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Series Fundamental Resistance (ESR) ÁÁÁÁÁ ÁÁÁÁÁ 25 Ω ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Drive Level ÁÁÁÁÁ ÁÁÁÁÁ 500 µW X1 X2 C5 C4 A suitable crystal is the MTRON HC49 MP-1, 20.000 MHz crystal. 20 pF for C4 and C5 have been shown to work reliably. PLL Filter Components The filter components at Pin 12 were chosen to assure adequate pull-range but with a emphasis on stability. It is not foreseeable that a design would need to change the components, but for the sake of completeness, relevant values are provided here. VCO Gain /C004324 /C0466MHz Volt • sec/C0467and, Phase Detector Gain /C0043100 /C0112/C03242 /C0466/C0109A rad/C0467and the filter impedance function is; Z(j/C0119) /C0091(j/C0119/C00411/C0324C6) j/C0119• C5 • (j/C0119/C00411/C0324C5) (for C6 /C0117/C0117C5) 10BASE-T Filter and Transformer Choice The MC68160A differential outputs are low impedance voltage sources. Therefore, external series resistors must be used in order to match the characteristic impedance of twisted pair. Since the output resistance of each leg of the transmitter is about 10 Ω, a 39 Ω resistor is used in series as shown in the applications schematic. So the impedance presented from the source to the isolation transformer is then very nearly 100 Ω. The following is a list of some 10BASE-T filter module vendors and their products. Vendor Part # FEE Fil-Mag 78Z1120B-01, 78Z1122B/D-01, 78Z1122 F-01 Valor Electronics 78Z1122 F-01 PT3877, FL1012, FL1066Valor Electronics Pulse Engineering PT3877, FL1012, FL1066 PE-65434, PE65424, PE65433gg TOKO PM01-00, PM02-00, PM05-00 AUI Transformer Choice Like the 10BASE-T outputs, the AUI differential outputs are low impedance sources and capable of meeting the IEEE 802.3 waveform requirements when a coupling transformer is used. Some AUI transformer vendors and their products are provided below. Vendor Part # Coilcraft LAX-ET304 FEE Fil-Mag 23Z90, 23Z91/ 23Z92 Valor Electronics LT6032, LT6033 Pulse Engineering PE64502, PE6103 TOKO Q30ALQ8-1AA3, Q30ALQ9-1AA3 Application Notes: Resetting the MC68160A after power up. In some applications, after initial power up, the MC68160A may not be able to transmit or receive data. This is usually caused by the LOOP and TPFULDL control lines being active at the same time. This is an illegal condition during normal operation, it places the MC68160A into the production test mode. To exit the test mode and return to normal: Set LOOP low, TPFULDL high and TPSQEL low. Then, while keeping TPSQEL low, raise LOOP after 300 ms lower TPFULDL. This will put the MC68160A into test mode but also resets the MC68160A. After 500 ms lower LOOP to get out of the test mode. TPFULDL may then be de-asserted if desired. The MC68160A is now ready for operation. A hardware implementation of this fix would be to place a pull down resistor on the TPSQEL pin. Even if test mode is entered by accident, this ensures that zero’s will be written to the test register. The hardware implementation will solve the problem if the test mode is entered because of noise on the TPSQEL pin. If the controller is toggling the MC68160A lines while it is booting up, the reset procedure must be followed. MC68160A Enhanced Ethernet Transceiver NETCOM IDT™ Enhanced Ethernet Transceiver Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MC68160A

28 MOTOROLA ANALOG IC DEVICE DATA

  1. For Suitable Crystal (X ) see applications text on previous page.1

802.3 Communication Controller

Figure 41. Typical Application Diagram

  1. Decoupling capacitors should be placed as close to supply pins as possible.

29MOTOROLA ANALOG IC DEVICE DATA FB SUFFIX PLASTIC PACKAGE CASE 848D-03 (LQFP-52) ISSUE C OUTLINE DIMENSIONS F NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER.

3 DATUM PLANE −H− IS LOCATED AT BOTTOM OF LEAD AND

IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE.

4 DATUMS −L−, −M− AND −N− TO BE DETERMINED AT DATUM

PLANE −H−.

5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING

PLANE −T−.

6 DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE −H−. 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). ÉÉÉÉ ÉÉÉÉ ÇÇÇ ÇÇÇ VIEW AA VIEW AA

2 X R R1

ROTATED 90/C0095 CLOCKWISE DIM A MIN MAX MIN MAX INCHES 10.00 BSC 0.394 BSC MILLIMETERS A1 5.00 BSC 0.197 BSC B 10.00 BSC 0.394 BSC B1 5.00 BSC 0.197 BSC C1 0.05 0.20 0.002 0.008 C2 1.30 1.50 0.051 0.059 D 0.20 0.40 0.008 0.016 E 0.45 0.030 F 0.22 0.35 0.009 0.014 G 0.65 BSC 0.75 0.018

0.026 BSC

J 0.07 0.20 0.003 0.008 K 0.50 REF 0.020 REF R1 0.08 0.20 0.003 0.008 S 12.00 BSC 0.472 BSC S1 6.00 BSC 0.236 BSC U 0.09 0.16 0.004 0.006 V 12.00 BSC 0.472 BSC V1 6.00 BSC 0.236 BSC W 0.20 REF 0.008 REF Z 1.00 REF 0.039 REF CL -X- X=L, M, N 14 26 4052 4X TIPS4X 3X VIEW Y SEATING PLANE C 0.10 (0.004) T 4X θ3 4X θ2 S0.05 (0.002) 0.25 (0.010) GAGE PLANE W K E Z SL−MM0.13 (0.005) N ST PLATING BASE METAL D J U B V A S -L- -N- -M- -H- -T- θ G θ 0 7/C0095/C0095 51 3/C0095 /C0095 /C0095 0 7/C0095/C0095 REF 12/C0095REF 13/C00955/C0095 MC68160A Enhanced Ethernet Transceiver NETCOM IDT™ Enhanced Ethernet Transceiver Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MC68160A

© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA XX-XXXX-XXXXX Corporate Headquarters Integrated Device Technology, Inc.

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#20-03 Wisma Atria Singapore 238877 +65 6 887 5505 Europe IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 For Tech Support netcom@idt.com 480-763-2056 Innovate with IDT and accelerate your future networks. Contact: www.IDT.com PART NUMBERS INSERT PRODUCT NAME AND DOCUMENT TITLE NETCOM MPC92459

900 MHz Low Voltage LVDS Clock Synthesizer NETCOM

Low Skew CMOS PLL 68060 Clock Driver NETCOM MC68160A Enhanced Ethernet Transceiver NETCOM