MC68153

MC68153 MOTOROLA | Alldatasheet

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MC68153 Bus Interrupter Module The bipolar LSI MC68153 Bus interrupter interfaces a microcomputer system bus to multiple slave devices requiring interrupt capabilities. It handles up to 4 independent sources of interrupt requests and is fully programmable. @ VERSAbus®/VMEbus® Compatible. ‘© MC68000 Compatible @ Handles 4 Independent Interrupt Sources © 8 Programmable Read/Write Registers © Programmable Interrupt Request Levels © Programmable Interrupt Vectors © Supports Interrupt Acknowledge Daisy Chain © Control Registers Contain Flag Bits ®@ Single +5.0 Volt Supply © Total Power Dissipation = 1.0 W Typical ‘© Temperature Range of 0°C to 70°C © Chip Access Time = 200 ns Typical with 16 MHz Clock © 40-Pin Dual-In-Line Packages ‘System Bus aa Interrupt LACKIN, } Acknowledge Poel fee Daisy Chain Address ce8153 H sx LSM _ JP bevie Tera [bs Tequesta Control [ty Logic & a! aaa | Buters ren EE Requests q rE] H a Coo C2] Peripheral L___.| (Slave) Interface FIGURE 1 — BLOCK DIAGRAM TERSAbus and VMEbus are trademarks of Motorola nc rs (SY MOTOROLA @= 'M68000 FAMILY MOTOROLA REFERENCE 8-1

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ABSOLUTE MAXIMUM RATINGS (Beyond which useful life may be impaired.) Supply Voltage [vec | -05t0+70 | v_| Vin BURNIN LIMITS: A maximum tn Toot tS maybe uae for ups Voage [Vout [080-55 |v _| eves nat toencand 250 nour [Oupurcurent ton Twice Rated ton | ma] [Stree Tenperaure tag | 810 +40 |e Junetion Operating Temperature DC ELECTRICAL SPECIFICATIONS (Vcc = 5.0 V +5%, Ta = 0°C to 70°C) [____Paremeter [Symbol] Min | Mex | Unk [Yow Gondios | (Wish taveripavotage | ‘vw [20 | — [|v] Low Level input Voltage [vu [| = [os [ov fp [Input Clamp Votage | Mx (| = | 18 [| Vcc = MIN iy = —18ma High Level Output Voltagel) | vou [27 [= |v _| Voc = MIN, lon = —400 uA Low Level Output Voltage Tvo | — | 04 | Vv | Vcc = MIN, io. = 80 mA Output Short Circuit Current(2) [tos | -15 | -130 [| ma_| Voc = MAX. Vout = OV [gh eve input conent tw |= | 90 | wv Ver = MAX Yn = 27 [ow evel input Crem) | 04 [ma Voc = MAX ov | [Supply Curent ce | 288 | a8 | mma | Vor = MAX Output OF Current (High) [iozw | = | 20 | uA _| Voc = MAX. Vout = 24V Output Off Current (Low) ton | = | -20 [ nA | Vcc = MAX, Vout = 0.4 ee ' Voc = 50V ! 1 9 1 65V ! 1 H 1 Hl 1 ' 1 1 1 1000 I 8 1! Go 8 i i ‘(py = pt 1 ' 1 | 1 ! { 1 1 = = 1 ag 1 1 = i Notes: 1. Not applicable to open-collactor outputs. 2. Not more than one output should be shorted at atime for longer than one second 3. CS Low to CLK High (Setup Time) of 15 ns Min must be observed. 4. IAGK Low to CLK High and TACKIN Low to CLK High (Setup Times) of 15 ns Min must be observed 5. See Table 1 for additional performance guidelines. AC TEST CIRCUIT — AC Testing of All Outputs ee M68000 FAMILY MOTOROLA REFERENCE 8-3

‘AC PERFORMANCE SPECIFICATIONS (oc = 5.0 V =5%, Ta = O°C to 70°C) [Number [——haracterisie Min [Max [Unite [Notes _]

1 RAW, A1-A3 Valid to CS Low (Setup Time) 10 - ns

2 CS Low to RW, A1-A3 Invalid (Hold Time) 5.0 = ns

3 TS Low to CLK High (Setup Time) 15 - ns 1

4 CLK High to Data Out Valid (Delay) = 55 ns 2

5 CLK High to DTACK Low (Delay) - 40 ns 2

6 DTACK Low to GS High o ns

7 GS High to DTACK High (Delay) - 36 ns 10

8 ES High to Data Out Invalid (Hold Time) ° - ns

3 GS High to Data Out High-impedance (Hold Time) - 50 ns

10 CS High to CS or [ACK Low 20 - ns

" Date In Valid to TS Low (Setup Time} 10 - ‘

2 CS Low to Data In Invalid (Hold Time) 50 - ns

13 DTACK High to Data Out High-Impedance = Fry ns 10

4 TACK Low to CLK High (Setup Time) 6 - ns 1

8 AI-A3 Valid to IACK Low (Setup Time) 10 - ns

16 TACK Low to A1-A3 Invalid (Hold Time) 5.0 - ns

7 TACKIN Low to CLK High (Setup Time) 18 - ns 8

18 CLK High to Data Out Valid (Delay) - 55 ns 3

19 CLK High to DTACK Low (Delay) - 40 ns 3

20 CLK High to INTAE Low (Delay) - 40 ns 3

2 DTACK Low to TACKIN High ° - ns 8

23 TACK Low to TACK High 0 - ns

24 TACK High to Data Out Invalid (Hold Time) 0 - ns

25 TACK High to Data Out High Impedance (Delay) - 60 ns

26 TACK High to DTACK High (Delay) - 45 ns 10

2 TACK High to INTAE High (Delay) = 35 ns

2B INTALO, INTAL1 Valid to INTAE Low (Setup Time) 10 20 CLK Per

29 INTAE High to INTALO, INTAL Invalid (Hold Time} 10 20 CLK Per

30 TACK High to IROx High (Delay) - 50 ns 7.10

31 TACK High to IACK or CS Low 20 - ns

2 CLK High to IACKOUT Low (Delay) - 40 ns 5

33 TACKIN Low to IACKOUT Low (Delay) - 30 ns 4,8

4 TACKOUT Low to IACKIN, IACK High ° = ns a |

35 JACK High to iACKOUT High (Delay) = 35 ns. |

36 TACK and CS both Low to CLK High (Setup Time) 18 - as 9

7 CLK High to TACK or GS High (Hold Time) o = ns

38 TACK or CS High to IACK and CS High (Skew) - 1.0 CLK Per 6

39 Clock Rise Time - 10 ns

40 Clock Fall Time - 10 ns

4a Clock High Time 20 - ns | | a2 Clock Low Time 20 - ns | {

43 Clock Period 40 - ns

NOTES: '. This specification only applies i the VBIM had completed all operations initiated by the previous bus cycle when CS or JACK was asserted. Following normal bus eycle, all operations are completed within 2 clock cycles after CS or IACK have been negated, it (ACK or CS is asserted prior to completion of these operations, the new cycle, and hence, DTACK is postponed if the TACK, TACKIN or CS setup time is violated, OTACK may be asserted as shown, or may be asserted one clock cycle later (ie. TACK will not be recognized until the next rising edge of the clock) 2. Assumes that 3 has been met. 3. Assumes that 14 and 17 hve both been met. 44 Assumes that 14 has been met. ((AGKOUT cannot go low prior to IACKIN going low) §. Aasumes that 14 has been met and TACKIN has been iow for at least the amount of time specified by 33, 6. 38 is the minimum skew between the last moment when both IACK and CS are asserted to when both are negated, to insure that an access cycle is not unintentionally started. 7. Assumes no other INTx input is causing THOR to be driven low. 8. In non-daisy chain systems, |ACKIN may be tied low. 8, Failure to meet this apec. causes RESET to be ignored for 1 clock period, It is then necessary to keep these signals low for 3 clock periods instead of2 10, Delay time is specitied from input signal to Open-Collector Output pulled High thru 1.0K0 resistor to +65 V. MOTOROLA 68000 FAMILY 8-4 REFERENCE

AC ELECTRICAL SPECIFICATIONS (Vcc = 5.0V +5%, Ta = 0°C to 70°C) ee Numbor(5) CLK High to Data Out Valid (Delay)(3) 1 56 GLK High to DTACK Low (Delay)(3) 2 40 ES High to DTACK High (Delay) 3 35 CLK High to Data Out Valid (Delay)(4) 4 55 CLK High to INTAE Low (Delay){4) 5 40 TACK High to Data Out High Impedance (Delay) 6 60 TACK High to DTACK High (Delay) 7 45 GS High to Data Out High (Delay) 8 45 CS High to IRQ High (Delay) 9 60 TACK High to INTAE High (Delay) 10 35 GENERAL DESCRIPTION ‘SIGNAL DESCRIPTION The MC68153 Bus Interrupter Module (BIM) is de- Throughout the data sheet, signals are presented us- signed to serve as an interrupt requester for peripheral ing the terms asserted and negated independent of devices in a microcomputer system. Up to 4 indepen- whether the signal is asserted in the high voltage or dent devices can be interfaced to the system bus by the low voltage state. Active low signals are denoted by @ MC68153. Intended for asynchronous master/slave bus ‘superscript bar. operation, the BIM is compatible with VERSAbus, VME- bus, MC8B000 device bus, and other system buses. Fig- BIDIRECTIONAL DATA BUS — D0 - D7 ure 1 shows a block diagram of a typical configuration. Pins D0 - D7 form an 8-bit bidirectional data bus to! In this example, three peripheral devices (bus slaves) from the system bus. These are active high, 3-state pins. are connected to the system data bus. Each of these D7 is the most significant bit. devices could be parallel /O, serial 1/0, or some other function. An interrupt request from any device is routed ADDRESS INPUTS — A1~ A3 to the MC68153, and the BIM handles all interface to These active high inputs serve two functions. One the system bus. It generates a bus interrupt request as function is to select one of the eight possible registers a result of the device interrupt request. When the system during a read or write cycle. Secondly, during an inter- interrupt handler or processor responds with an inter- tupt acknowledge A1 - A3 show the level of interrupt rupt acknowledge cycle, the MC68153 can answer sup- being acknowledged, and the BIM uses these to deter- plying an interrupt vector and handling all timing, mine if @ match exists with an internal level. The functional block diagram of the MC68153 is CHIP SELECT — CS shown in Figure 2. The device contains circuitry to ac- CS is an active low input used to select the BIM's cept four separate interrupt sources (INTO - INT3). In- registers for the current bus cycle. Address strobe, data terface to the system bus includes generation of bus strobe, and appropriate address bits must be included interrupt requests (IR1 ~ iRQ7), response to a bus in- in the chip select equation. terrupt acknowledge cycle (either supplying @ vector or _ passing on a daisy chain signal), and releasing the bus READ/WRITE — RW interrupt request signal at the proper time. The BIM has The R/W input is 2 signal from the system bus used flexibility provided by eight programmable read/write to determine if the current bus cycle is a read (high) or registers. Four 8-bit vector registers (VRO ~ VR3) contain write (low). status/address information and supply a byte vector in response to an interrupt acknowledge cycle for the cor- DATA TRANSFER ACKNOWLEDGE — DTACK responding interrupt source. Four other 8-bit control DTACK is an open-collector, active low output that registers (CRO - CR3) contain information that oversees signals the completion of a read, write, or interrupt ac- operation of the interrupt circuitry. The control infor- knowledge cycle. During read or interrupt acknowledge mation is programmable and includes interrupt request cycles, DTACK is asserted by the MC68153 after data level and interrupt enable and disable. Also contained has been provided on the data bus; during write cycles. in the control registers are flag-bits. These flags are it is asserted after data has been accepted from the data useful for task coordination, resource management, and bus. A pullup resistor is required to maintain DTACK interprocessor communication. high between bus cycles. eee M68000 FAMILY MOTOROLA REFERENCE 85

0-07 <> Ra? ‘ROG a3 wos fe ings a ‘Ros inaz B agi RAW — DTACK INTO INTI [xed ne IACKIN NTS iRcKOUT — NTE cux INTALO +6.0 (4) INTALT GND (4) FIGURE 3 — LOGICAL PIN ASSIGNMENT INTERRUPT ACKNOWLEDGE SIGNALS — IACK, DEVICE INTERRUPT REQUEST SIGNALS — TACKIN, (ACKOUT INTO—INT3_ ‘These three pins support the interrupt acknowledge INTO - INTS are active low inputs used to indicate to cycle. A low level on the IACK input indicates an inter- the BIM that @ device wants a bus interrupt. rupt acknowledge cycle has been initiated. This signal is conditioned externally with Address Strobe and the INTERRUPT ACKNOWLEDGE ENABLE — INTAE lower data strobe of an MC68000 type bus. After |ACK During an interrupt acknowledge cycle, this output is asserted the BIM compares the interrupt level pre- pin is asserted low to indicate that outputs INTALO and sented on address lines A1, A2, and A3 with the current INTAL1 are valid. These two outputs contain an encoded levels generated internally and determines if a match number (x) corresponding to the interrupt (INTx) being exists. Then, if input [ACKIN is asserted (driven low), acknowledged. This feature can be used to signal in- the BIM will either complete the interrupt acknowledge terrupting devices, which supply their own vector, when cycle if @ match exists or assert output [ACKOUT if no to respond to the interrupt acknowledge cycle with the match exists. vector and a DTACK signal. TACKIN and IACKOUT form part of a prioritized inter- rupt acknowledge daisy chain. The daisy chain priori- INTERRUPT ACKNOWLEDGE LEVEL — INTALO, tizes interrupters and guerantees that two or more de- INTALT vices requesting an interrupt on the same level will not These active high outputs contain an encoded num- respond to the same cycle. The requesting device (or ber corresponding to the interrupt level being acknow!- interrupter) must wait until |ACKIN is asserted and not edged. They are valid only when INTAE is asserted low. pass the signal on (assert IACKOUT) if it is to complete the interrupt acknowledge cycle. ‘clock — CLK BUS INTERRUPT REQUEST SIGNALS — iRG1 - iRO7 opeeuon opinemessiea ey clock for internat These open-collector outputs are low when asserted, indicating @ bus interrupt is requested at the corre- eset — 35, WK sponding level. An open-colecor bute is normally re: Atngugh a reat input isnot supplied, an on-board quired for sufficient drive when interfacing to a system eee CS and TACK ere. asserted bus. A pullup resistor is required to maintain IRQ ~ Gmukenepusiy, TRG7 high between interrupt requests. f MOTOROLA 68000 FAMILY

86 REFERENCE

és Sey, & CLES FS RAS s ‘ADDRESS BIT © tJ ae, ge’ € aA a Le SALE € VoTe [ol F [rc[un [ime (mcf atu] o| CONTROL AEGITENO [ro | o [+ | & [rac] xin [ine [imac 2 [ur | to | CONTROL REGISTER 1 Coby be fr [racf xin Pe fac fo [to | CONTROL REGISTER Fa [ss [oe [rac | xan | ime inact to CONTROL REGISTER 3 Cr fope pve Tvs [ve | a | %0 VECTOR REGISTER [a [oe [a | w [ve | vs | ve | vo VECTOR REGISTER | cep epa Pv Pas | ve v3 | VECTOR REGISTER La {a [iw [ve [vs [va | [vi [vo | VECTOR REGISTER 3 7 6 5 4 3 2 1 O REGISTER REGISTER BIT - NAME FIGURE 4 — MC68153 REGISTER MODEL REGISTER DESCRIPTION clearing IRE disables the interrupt request. To re- The MC68153 contains 8 programmable read’write enable the interrupt associated with this register, IRE registers. There are four control registers (CRO - CR3) must be set again by writing to the control register. that govern operation of the device. The other four aN) — Bit 4, External/Internal (X/IN) — Bit 5 of the control register FAO VR a ecto eer na cdncavele. Figure determines the response of the MC68153 during an. fill uses he eviee erate rode ige cycle. Figure interrupt acknowledge cycle. If the X/IN bit is clear illustrates the device register model. (low level) the BIM will respond with vector data and a DTACK signal, i., an internal response. if X/IN is conTnor ee rot register for each interrupt source set, the vector is not supplied and no DTACK is given re is a control r jor each it . . ‘ rout ——s by the BIM, i.e., an external devic should respond. i.e., CRO controls INTO, CR1 controls INT1, etc. The con- yay Ba) toe tha that con be a 'spon trol registers are divided into several fields: 5. Flag (F) — Bit 7 is a flag that can be used in con- least significant junction with the test and set instruction of the 1. Interrupt level (L2, Lt, 10) Tho leant significa MC68000. It can be changed without affecting chip Sit field of the register determines the level at operation. It is useful for processor-to-processor which an interrupt will be generated: communication and resource allocation. ia u to IRQ LEVEL 6. Flag Auto-Clear (FAC) — If FAC (Bit 6) is set, the Flag ° 0 0 DISABLED bit is automatically cleared during an interrupt ac- o 0 1 IRQ? knowledge cycle. 0 1 0 1RO2 ° 1 1 1RO3 VECTOR REGISTERS 1 0 0 iRaa Each interrupt input has its own associated vector 1 ° 1 1ROS register. Each register is 8 bits wide and supplies a data 1 1 oO IRO6 byte during its interrupt acknowledge cycle if the as- 1 1 1 IRQ7 sociated External/internal (X/IN) control register bit is ‘Avalue of zero in the field disables the interrupt. clear (zero). This data can be status, identification, or ‘ address information depending on system usage. The 2, Interrupt Enable (IRE) — This field (Bit 4) must be set information is programmed by the system user. {high level) to enable the bus interrupt request as- sociated with the control register. Thus, if the INTX DEVICE RESET line is asserted and IRE is cleared, no interrupt re- When the MC68153 is reset, the registers are set to a quest (IROX) will be asserted. known condition, The control registers are set to all 3, Interrupt Auto-Clear (IRAC) — If the IRAC is set (Bit zeros (low). The vector registers are set to SOF. This 3), IRE (Bit 4) is cleared during an interrupt acknow!- value is the MC68000 vector for an uninitialized interrupt edge cycle responding to this request. This action of vector.

68000 FAMILY MOTOROLA

‘SYSTEM OVERVIEW The MC68153 can be used with many system buses, 2. IACK* — signal line that indicates an interrupt ac- however, it is primarily intended for VMEbus, VERSA- knowledge cycle is occurring. bus and MC68000 applications. Figure 5 shows a system 3. IACKIN*/IACKOUT* — two signals that form part configuration similar to VMEbus. In the figure only one of a daisy chain that prior- system Data Transfer Bus (OTB) master is used. The itizes interrupters. rapa interrupt aractere provides ha eas other In sation Date Transfer Bus control signals are in- « fc r volved in the IACK bus cycle: ore (oTB maton Aces am reco’ soo 1. AS* — the Address Strobe asserted low indicates ir rOCeSSOr. acts as an inter- a valid address is on the bus. face device requesting and responding to interrupt ac- 2. DSO* — the lower Data Strobe asserted low in- knowledge cycles for up to 4 independent slaves. dicates a data transfer will occur on bus In Figure 5, functional modules are identified as in- bits D00-007. terrupters and an Interrupt Handler. An Interrupter (such 3. WRITE* — the ReadMrite is negated indicating as the MC68153) receives slave requests for an interrupt the data is to be read from the Inter and handles all interface to the system bus required to rupter. ask for and respond to interrupt requests. The Interrupt 4. A01-A03 — Address lines A01-A03 contain the Handler receives the bus interrupt requests, determines encoded priority level of the IACK when an interrupt acknowledge will occur and at which cycle. level, and finally either performs the interrupt acknow!- 5. D00-D07 — Data bus lines D00-D07 are used to edge WACK eycl or tll the DTB master to execute the pass the interrupt vector from the re- cycle. sponding Interrupter to the Interrupt The signal lines in the Priority Interrupt structure in- Handler. clude (* — indicates active low) 6. DTACK* — Data Transfer Acknowledge asserted 1. IRQ1*-IRQ7* — seven prioritized interrupt re- low signals that the Interrupter has quest lines. put the vector on the data bus. Pong rrr pag gn ' ut " I 1 ore |!1[ oresive ||! | [ore sieve] [ors save] [ors sieve] | i it u 1 H i iH i 1 im " 1 1 i H 11 [interrupter 11 [interrupter ! i in ® in 2 t 1 in (1 [/mceas3 | ! i " 1 1 it 1 \\ 1 it 1 1

3 To Next interrupter

Bus Ty ti‘(‘S us Interrupt FIGURE 5 — SIMPLE VMEbus CONFIGURATION MOTOROLA 68000 FAMILY

88 REFERENCE

q MC68153 Figure 6 shows a flow diagram of a typical interrupt Note the daisy chain operation. If the IACK level (on. request and acknowledge operation. Briefly, the se- ‘A01-A03) does not match the interrupters request level quence of events is first, an interrupter makes a request, or if no request is pending, the interrupter passes the next the Handler responds with an IACK cycle, then the IACKIN® signal on and esserts IACKOUT®. This sequen- Interrupter passes a vector to the Handler completing tial action automatically prioritizes Requesters on the the IACK cycle, and finally the Handler uses the vector ‘same level (first one in line with a request pending gets to determine additional action. Typically, an interrupt serviced) and prevents two or more interrupters from service routine is stored in software and the vector de- responding simultaneously. termines where its starting address is stored. INTERRUPTER INTERRUPTER (INTERRUPT ® ® HANDLER (Slave B Requests Interrupt) Drive IRQ4* Low Detect IR4* Low. Initiate |ACK Cycle: Place 3-bit level 4 code on AO1~A03. ‘Drive ACK* Low (causing IACK Daisy Chain to go Low.) Drive AS* to Low. Drive Write* High, Drive DSO* to Low. (Daisy Chain) Detect IACK* Low. Detect AS* Low. Check 3-bit Interrupt Acknowledge Code (Detect Match). Detect DSO* Low. Detect IACKIN® Low Place Vector Byte on Data Bus. Drive DTACK" to Low. Detect OTACK* Low. Read Vector. Release IACK Cycle. (Release AS*, A01-A03, DSO*, Write*, IACK*). Initiate Interrupt Service Sequence. FIGURE 6 — INTERRUPT REQUEST AND ACKNOWLEDGE OPERATION FLOW DIAGRAM

This discussion is a very cursory look at the bus op- tem bus in both read and write modes. The BIM has an eration. For more details including situations with mul- asynchronous bus interface, primarily designed for tiple bus masters, the user is directed to the VMEbus MC68000-like buses. The following BIM signals gener- Specification MVMEBS or VERSAbus Specification ate read and write cycles: Chip Select (C5), Read/Write M68KVBS. Also, the MC68153 can be used with other (RAW), Address Inputs (A1-A3), Data Bus (D0-D7), and buses having similar interrupt structures. Data Transfer Acknowledge (OTACK). During read and write cycles the internal registers are selected by A1, BM BUS INTERFACE A2, and A3 in compliance with the Figure 4 Truth Table. Figure 7 shows a simplified block diagram of the MC68153 interface to VERSAbus or VMEbus. Address __Figure 8 shows the device timing for a read cycle. Ri Decode and Control Logic are dependent on the appli- Wand A1-A3 are latched on the falling edge of CS and cation and must be designed to guarantee BIM ac spec- must meet specified setup and hold times. Chip access ifications. It is possible in most cases that the decode time for valid data and DTACK are dependent on the logic can be shared with the slave devices. Buffers are clock frequency as shown in the figure. provided where shown to comply with bus loading and drive specifications. It is also possible that buffers can __Figure 9 shows the device timing for a write cycle. Ri be shared with the slave bus interface. W, Ai-A3, and D0-D7 are latched on the falling edge of CS and must meet specified setup and hold times. READIWRITE OPERATION Chip access time for DTACK is dependent on the clock All eight BIM registers can be accessed from the sys frequency as shown in the figure. System Bus TROT" <{ -IRQ7* q +5.0V Data Bus _ ina? 00-po7 K |S be-87 sw aot [nos Foy) 202} bo} \\ Ext eis » SOPs kook See 2 waire-| 1 [igor we rack: rm <{} Mcee153 rs 0 BIM 3 0d _

3 A23 no Address INTO device A

‘AMO- — Decode INT) Device 8 Device AMX int interrupt (4G INTs O’vie® © (Requests Device 0 a nd "aS* tack* |] Controt |___TACK | INTAE | Te lave device SYSRESET*|___p}_ Lovie INTALO for external ITALY 5 {Interupt Ack — knowledge TACKIN wean —T | ) aero] SCL Seen SYSCLK FIGURE 7 — VMEbus/VERSAbus INTERFACE BLOCK DIAGRAM MOTOROLA 68000 FAMILY 8-10 REFERENCE

y MC68153 (0) CLK Hoy Or ~ | raat TX [roscoe vai XY | ° = ke Foy | [boa] “m {~ [eee [vans TD k@-| ae r® DTACK fo) @) seas TX [assess vane KZ ' PS zi orco —{onavaid ® (0) DTACK FIGURE 9 — WRITE CYCLE a M68000 FAMILY — REFERENCE 1A

The MC68153 accepts device interrupt requests on bit sets this response either internally (X/IN = 0) inputs INTO, INTT, INT2, and INT3. Each input is regu- or externally (X/IN = 1). lated by Bit 4 (IRE) of the associated control register {CRO controls INTO, CR1 controls INTT, etc). If IRE (In- 4. Respond externally — For the final case, IACKIN is terrupt Enable) is set and a device input is asserted, an also asserted, a match is found and the associated Interrupt Request open-collector output (RO1-IRQ7) is control register has X/IN bit set to one. The asserted. The asserted IROX output is selected by the MC68153 does not assert IACKOUT and does as- value programmed in Bits 0, 1, and 2 of the contro! sert INTAE low. INTAE signals that the requesting register (LO, L1, and L2). This 3-bit field determines the device must complete the IACK cycle (supplying a interrupt request level as set by software. vector and DTACK) and that the 2-bit code con- Two or more interrupt sources can be programmed tained on outputs INTALO and INTAL1 shows to the same request level. The corresponding IROX out- which interrupt source is being acknowledged. a wiede antes second we us ae sptse cases ate discussed In more detail in the fol- Ifthe interrupt request level is set to zero, the interrupt lowing paragraphs. is disabled because there is no corresponding IRQ out- Internal Interrupt Acknowledge put. For an internal interrupt acknowledge to occur, the following conditions must be met INTERRUPT ACKNOWLEDGE 1. One or more device interrupt inputs (INTO-INT3) The response of an interrupt Handler to a bus inter- has been asserted and corresponding control bit rupt request is an interrupt acknowledge cycle. The IRE value is one. JACK cycle is initiated in the MC68153 by receiving IACK __ low. RW, Al, A2, A3 are latched, and the interrupt level 2. TACK asserted. ‘on line A1-A3 is compared with any interrupt requests pending in the chip. Further activity can be one of four 3. A match exists between [A3, A2, Ai] and the (L2, cases: L1, LO} field of an enabled, requesting control reg- ister. If two or more devices are requesting at the 1. No further action required — This occurs if ACKIN same interrupt level, preference is_given to the is not asserted. Asserting [ACK only starts the BIM highest number requester, thatiis, INT has highest activity. If the daisy chain signal never reaches the priority and INTO has lowest. 153 (IACKIN - = voter ee responded to ome hovel ee 4. Control register bit XIN of matching interrupt will end, the chip IACK is negated, and no addi- source must be zero. tional action is required. 5. TACKIN asserted. 2. Pass on the interrupt acknowledge daisy chain — The internal interrupt acknowledge cycle timing is For this case, IACKIN input is asserted by the pre- shown in Figure 10. The 8-bit interrupt acknowledge ceding daisy chain interrupter, and [ACKOUT out- vector is presented to the data bus and DTACK is as- put is in turn asserted. The daisy chain signal is serted, Note also that INTALO and INTAL1 are valid and passed on when no interrupts are pending on a INTAE is asserted during this cycle although they would ‘matching level or when any possible interrupts are normally not be used. The cycle is terminated (data and disabled. The Interrupt Enable (IRE) bit of a control DTACK released) after IACK is negated. register can disable any interrupt requests, and in During the IACK cycle, the INTERRUPT AUTO-CLEAR turn, any possible matches. control bit (IRAC) comes into play. If the IRAC = one a for the responding interrupt source, the INTERRUPT EN- 3. Respond internally — For this case, IACKIN is as- ABLE (IRE) bit is automatically cleared during the IACK serted and a match is found. The MC68153 com- cycle, thus disabling the associated interrupt input and pletes the IACK cycle by supplying an interrupt any IROX output asserted due to this interrupt input. vector from the proper vector register followed by Before another interrupt can be requested from this a DTACK signal asserted. [ACKOUT is not asserted source, IRE must be set to one by writing to the control because the interrupt acknowledge cycle is com- register. pleted by this device. Note that IACKOUT is not asserted because this de- For the MC68153 to respond in this mode of op- vice is responding to the IACK and does not pass the eration, the EXTERNALINTERNAL control register daisy chain signal on. Also, new device interrupt re- bit (X/IN) must be zero. For each source of interrupt quests occurring on INTO-INTS after IACK is asserted request, the associated control register determines are locked out to prevent any race conditions on the the BIM response to an IACK cycle, and the X/IN daisy chain, sea MOTOROLA 'M68000 FAMILY 8-12 REFERENCE

« J\\LFV\\LY Operon _| as-ar SX Aacress vale AIO oo oro {|_| eave h +e @ —— d €3) DTACK \\ [A _ 2 ® FIGURE 10 — INTERRUPT ACKNOWLEDGE CYCLE — INTERNAL VECTOR External Interrupt Acknowledge Pass On IACK Daisy Chain For an external interrupt acknowledge, the same con- If the MC68153 has no interrupt request pending at ditions as listed above are met with one exception. Con- the same level as the interrupt acknowledge, the ACK trol register bit X/IN of matching interrupt source must daisy chain signal is passed on to the next device if be set to one. The timing is shown in Figure 11. For this TACKIN is asserted. The following conditions are thus cycle, the interrupt vector and DTACK must be supplied met: by an external device. INTAE is asserted indicating that 1, TACK asserted. INTALO and INTAL1 are val.d. The external device can 2. No match exists between [A3, A2, At] and the [L2, use these signals to enable the vector and DTACK. The L1, LO] field of an enabled, requesting contro! reg- cycle is terminated after IACK is negated. ister. 3._TACKIN is asserted. The IRAC control bit acts in the external interrupt ac- TACKOUT is asserted if these conditions are valid. This knowledge the same as described for the internal re- output drives IACKIN of the next Interrupter on the daisy sponse (see above). Also, ACKOUT is not asserted and chain, passing the signal along. Figure 12 shows the new device interrupts are disabled for reasons dis- timing for this case. TACKGUT ts negated after ACK is cussed above. negated.

(4) G2) © ror asar 7X Adaress vatis W/L @3) =a—\\_| rey acs e+e _ 6) TROX (4) ux | / Opp ©] soar TX Tmagenvme XZ @ €4) za _ A aio €) ® TACKOUT FIGURE 12 — INTERRUPT ACKNOWLEDGE CYCLE — iACKOUT MOTOROLA 68000 FAMILY 8-14 REFERENCE

CONTROL REGISTER FLAGS RESET Each control register contains a Flag bit (F) and a Flag There is no reset input, however, a chip reset is ac- Auto-Clear bit (FAC). Both bits can be read or altered tivated by asserting both CS and IACK simultaneously via a register write without affecting the interrupt op- (Figure 13). These inputs should be held low for a min- eration of the device. The Flag is useful as a status imum of two clock cycles for a full reset function. The indicator for resource management and as a semaphor control registers are reset to all zeroes and the Vector in multitasking or multiprocessor systems. Flag (F) is Registers are set to a value of $OF. This vector value is located in bit position 7 and can be used with the the uninitialized vector for the MC68000. See the MC68000 Test and Set (TAS) instruction. MC68000 Users Manual for more details on this vector. The Flag Auto-Clear (FAC) is used to manipulate the CLOCK Flag bit. If the Flag is set to one and the FAC is also one, The chip clock is required for internal operation to an interrupt acknowledge cycle to the associated inter- occur. Typical frequency is 16 MHz in VMEbus and rupt source clears the Flag bit. This feature is useful in VERSAbus applications derived from the system clock. determining the interrupt status and passing messages. Any frequency can be used, however, up to 25 MHz (Figure 14). ANN’ VL) 3 (My | FIGURE 13 — RESET re) @ “ a FIGURE 14 — CLOCK WAVEFORM TYPICAL THERMAL CHARACTERISTICS A (Junction to Ambient) Junction Temperature Package Stil Al Stil Air @ 70° Amblont T Suttx aC Tare P Suffix? _ _35°OW 137°C NOTES — {1 For reliable systom operation the maximum allowable junction temperature (T) fr plastic encapaulated packages hes been limited to + 140%. Exceeding th lit wil carte "weer-out" machanimeastorised with indusry standard eeneriy meas ag omnes eal oon 0 tach gold (au) bond wit te aluminum (Al bond pads onthe Se suroce 2. ALT) = Mime to 0 flr unto yon inereonnedt = 20 Nours

vec |" ah as RWC]? 39 a2 eq; 33 at Brack C4 37) o7 aK Cs 36 os TACKIN T] 6 351 05 Tackout C] 7 341) va made 331) v3 coc} 9 32D 02 GNp Cj 10 31 eno Vee 11 20D vee Raz C] 12 2D o1 ROS Cl 13 281) bo koa 14 272) iNTAE Ras C} 15 26 intaur RG’ C] 16 251) INTALO Ra? C17 242 INT cu) 18 ap we INTOC] 19 222 inti Go C] 20 21D) vec rere MOTOROLA 68000 FAMILY 8-16 REFERENCE