MC68150

MC68150 IDT | Alldatasheet

Document overview

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Technical content

Features

• Allows MC68/LC/EC040 or Other ‘040 Based Controllers or 68060 to Communicate With 8-Bit Memories and Any MC68XXX Peripheral
• Also Allows Other RISC Processors to Communicate With 8-Bit and 16-Bit Peripherals
• Recognizes the Port (Peripheral) Size Dynamically
• Generates Byte/Word Address to the Dynamic Port
• Generates Byte WRITE Enable Signals For 16- and 8-bit Ports
• Sends a Transfer Acknowledge Signal to the Processor When a Transfer Is Completed
• Synchronization of Data Transfer on Dynamic Port Allows Use of Any Speed Peripheral 1. Overview of Chip Operation Each access through the MC68150 is started with a chip select (CS) assertion to the MC68150 - which is generated when a PAL sees a TS signal from the ‘040 - and completed with a transfer acknowledge (TA) from the MC68150 to the MC68040. The MC68150 has two distinct buses, the MPU bus and the peripheral bus. The MPU bus connects to the processor and includes the transfer control signals (A1, A0, SIZ1, SIZ0, and R/W), the chip select (CS), the transfer acknowledge (TA) and the data bus signals (D31-D0). The peripheral bus consists of the peripheral transfer control signals (SWE, UWE, LWE, DS, PA1, PA0), and the peripheral transfer acknowledge signals (DSACK1, DSACK0 ) and the peripheral data bus (PD31-PD16). If a 32-bit peripheral bus is used, then two additional transceivers (e.g. MC74F245) are required for the lower two bytes of the data. These transceivers would be connected to the PD15-PD0 pins on the peripheral side and to the corresponding D15-D0 pins on the MPU bus. The transfer direction is controlled with the R/W signal of the processor. The transceivers are enabled only when making an access to a 32-bit port. The D15-D0 pins of the MPU bus on the MC68150 are always disabled until the port size is known, to avoid bus contention when the port is 32-bits. An access refers to the complete transaction through the MC68150. On the peripheral bus, an access is split into one, two, or four separate transfers. DYNAMIC READ/WRITE BUS SIZER FN SUFFIX PLASTIC PACKAGE CASE 779-02 91 0 /C0056 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... DATA SHEET MC68150 IDT™ 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer MC68150 JULY 30, 2009 Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc. 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer NOT RECOMMENDED FOR NEW DESIGNS EI SUFFIX Plastic Package Case 779-02 (Pb-Free Package)

Figure 1. Pinout: 68-Lead PLCC (Top View) Freescale Semiconductor, Inc.

Figure 2. MC68150 Typical System Configuration Freescale Semiconductor, Inc.

Figure 3. “FAST Bus” “SLOW Bus” Application Table 1. 68150 TRUTH TABLE (READ Mode) Freescale Semiconductor, Inc.

Table 2. 68150 TRUTH TABLE (WRITE Mode) configuration (Figure 2) illustrates communication between a 68040 and 8-, 16-, and 32-bit peripheral chips.

• Peripheral data connections are the same as for a 68030 – Connect PD31:24 for 8-bit port – Connect PD31:24 for upper byte 16-bit port – Connect PD23:16 for lower byte 16-bit port – Connect PD31:24 for upper-upper byte 32-bit port – Connect PD23:16 for upper-middle byte 32-bit port – Connect PD15:8 for lower-middle byte 32-bit port – Connect PD7:0 for lower-lower byte 32-bit port
• 32-bit ports require transceivers or latched transceivers for PD15:0 – The MC68150 only passes the upper 16 data bits on a 32-bit transfer
• 68150 does not support burst mode – One way to handle this is to connect TA of the 68150 to TBI of the 68040 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer NETCOM IDT™ 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MC68150

related, to each other. The peripheral states start with S0. Figure 4 is an example transfer with the states marked.

2.1 Access Start

are held by the MC68040 throughout the access. The transfer start is asserted around only one rising edge of the clock (BCLK). The chip select (CS) for the MC68150 is asserted while the MC68040 transfer control signals are input to the MC68150. CS recognized (DS2). If the transfer control signals change states during this set-up time, the MC68150 operation is unpredictable. held by the 68150 until CS is negated at the end of a transfer. Figure 4. MC68150 32-Bit to 8-Bit Transfer Example (READ or WRITE) Freescale Semiconductor, Inc.

2.2 Early Access Termination

on a rising edge of BCLK. The CS early negation is used when the access should be ignored, such as when a bus error occurs. For peripherals that can be read or written to twice, special care must be taken in aborting the 68150 access.

2.3 Early Release of the MPU Bus

performance at the expense of additional logic. while the MC68150 completes the access. error is coming from the MC68150. Figure 5. 32-Bit ‘040 READ from 16-Bit Peripheral With Asynchronous Termination Freescale Semiconductor, Inc.

MOTOROLA High Performance Frequency Control Products — BR1334

2.4 Access Termination

The final transfer on the peripheral side of the MC68150 occurs during DS5. The MC68150 access is normally terminated by the MC68150 asserting TA during DS6. Once the TA is asserted, TA is held asserted until at least DS8. The MC68150 negates TA asynchronously if CS is negated after DS7; an example of asynchronous termination is shown in Figure 5. An abnormal MC68150 termination occurs when the CS is negated before DS6. See early access termination for more details. For a normal access, CS is held asserted until at least DS6. TA negation is synchronous to the rising edge of DS8 if CS meets a set-up to a DS8 rising BCLK edge. Asynchronous termination is defined as any CS negation beyond the DS8 rising BCLK edge. In this case the TA occurs a delay after the CS negation, because it is asynchronous termination. During a read access, the data being presented to the MC68040 is held for at least one rising edge of BCLK (DS8). When CS is negated, the MPU data bus goes to high impedance. If the data must be held longer than a single period, then asynchronous TA negation is necessary.

2.5 MPU Bus Idle State

CS must remain high for one rising edge of BCLK between each access. This is guaranteed by the MC68040 if CS is asserted on the clock edge following TS assertion (or later) on all accesses through the MC68150. When the MPU bus is idle (between accesses), the D(31:0) are in high impedance and TA is negated. 3. PERIPHERAL BUS OPERATION The peripheral access is divided into one or more transfers. The transfers are divided into multiple states. Each state represents half a clock period. All even states are the BCLK HIGH half of the clock period. All odd states are the BCLK LOW half of the clock period. A clock edge is referenced by the state that follows the clock edge. All rising edges are referenced by even number states. All falling edges are referenced by odd number states. S0 is the first state of a peripheral access. Note that the peripheral and MPU states are distinct, though related to each other.

3.1 Initial Transfer Start

A transfer starts off the rising edge of BCLK following the CS assertion (S2). The starting address of the transfer (PA1, PA0) is asserted during S2. The MC68040 A(31:2) are routed past the MC68150, directly to the peripheral bus. Buffers can be used to minimize loading on the MC68040 address bus. If the access is a write, the peripheral data bus (PD(31:16)) is driven during S2. The starting data strobe (DS) is asserted during S3. If the access is a write, the starting write enables (SWE, UWE, and LWE) are also asserted during S3. SWE is the write enable for 8-bit peripherals. The SWE is asserted for every transfer of a write access. It indicates the data on PD(31:24) is valid and ready to be written to the 8-bit peripheral. UWE and LWE are the write enables for 16-bit peripherals. UWE indicates the data on PD(31:24) is valid and ready to be written to the 16-bit peripheral. LWE indicates the data on PD(23:16) is valid and ready to be written to the 16-bit peripheral. A 32-bit port can generate write enables from the MC68040 normally (A1, A0, SIZ1, SIZ0 and R/W). These write enables can be qualified with SWE or DS for the 32-bit peripheral. An alternative is to use the UWE and LWE in conjunction with the PA1 and PA0. If it is a 32-bit access (SIZ1 and SIZ0 = HH or LL), then apply UWE to PD(31:24), PD(15:8) and LWE to PD(23:16), PD(7:0). If it is a 16-bit access (SIZ1 and SIZ0 = HL), then apply UWE to PD(31:24) and LWE to PD(23:16).

3.2 Initial Transfer Termination

Starting with S2, the MC68150 monitors the data strobe acknowledge signals (DSACK1, DSACK0) for the access termination. Wait states are inserted into the access by maintaining DSACK1 and DSACK0 HIGH. The DSACK1 and DSACK0 are sampled on the falling edge of BCLK. DSACK1 and DSACK0 must remain valid for two successive falling edges of BCLK to be recognized. If the access is a read, the PD(31:16) must be valid a set-up before the falling edge between S4 and S5. The PD(31:16) must be held valid a hold time into S5. The DSACK1 and DSACK0 are first sampled during S2. The DSACK1 and DSACK0 are then continuously sampled each falling edge of BCLK until the entire access is completed. This means the fastest initial transfer is two clocks (starting S2 and ending S4). The size of the peripheral port is indicated by the DSACK1 and DSACK0. The port size must be indicated on the first transfer and is the port size for the remainder of the access. Once the peripheral port size is indicated on the first transfer, all subsequent transfers should be terminated with the same port size indication. If another port size is indicated on subsequent transfers of the same access, the MC68150 operation is not guaranteed nor predictable. Depending upon the conditions, the MC68150 may either Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer NETCOM IDT™ 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MC68150

DSACK0 states on subsequent transfers may or may not insert wait states into the access. (falling edges of S3 and S5). DS is negated during S5. If the access is a write, SWE, UWE and LWE are all negated during S5. PA1 and PA0 are held valid until S6. If the access is a write, PD(31:16) are held valid until S6. Table 3. DSACK1 AND DSACK0 DECODE LOGIC

3.3 Subsequent Access Termination

and LWE are asserted during S7. The DSACK1 and DSACK0 are sampled again for the subsequent transfer during S6. be held valid a hold time into S9. DS, SWE, UWE and LWE are negated during S9. an 8-bit port, read and write respectively. Both require four sequential data transfers to complete the access.

3.4 Peripheral Bus Idle State

The MC68150 enters an idle state on the peripheral bus on the rising edge of BCLK after the last transfer is terminated. are in high impedance. DSACK1 and DSACK0 are ignored. valid before DS assertion. To avoid bus contention on the peripheral bus, the R/W from the MPU can be used. falling edge. Because the DSACK signals can be changing on a falling BCLK edge, an additional wait state may be incurred. DSACK1 and DSACK0 can be negated when DS is negated. If the access is a read, PD(31:0) is valid after DSACK1 and DSACK0 are asserted and held until DS is negated. Freescale Semiconductor, Inc.

MOTOROLA High Performance Frequency Control Products — BR1334 MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) –0.3 to +7.0 V VIN DC Input Voltage (Referenced to GND) –0.5 to +7.0 V VOUT DC Output Voltage (Referenced to GND) –0.5 to VCC + 0.5 V IIN DC Input Current, Per Pin ±20 mA IOUT DC Output Sink/Source Current, Per Pin ±35 mA TSTG Storage Temperature Range –55 to +150 °C TA Operating Ambient Temperature Range –40 to +85 °C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 4.5 5.5 V VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V TA Operating Ambient Temperature Range –40 85 °C IOL /IOH Output Current, LOW/HIGH (Control Pins) (Data Pins) ±16 mA OTHER CHARACTERISTICS Symbol Parameter Conditions Ratings Unit C IN Input Capacitance VI = 0V or VCC 8.5 pF C OUT Output Capacitnace VI = 0V or VCC pF C I/O Input/Output Capacitance VI = 0V or VCC pF ILATCHUP Latchup Current >500 mA VESD Electrostatic Discharge Voltage 8,000 V PD Power Dissipation in Still Air (Calculated at Worst Case) 530 mW NOTE: Rating values are design targets. Actual performance will be noted upon completion of characterization. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer NETCOM IDT™ 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MC68150

MOTOROLAHigh Performance Frequency Control Products — BR1334 ICC versus FREQUENCY No Load (50pF Only) 25°C ICC (mA) Loaded (50pF/500Ω ) 25°C ICC (mA) 1 2 4 6 65 73 82 10 13 16 20 75 83 93 20 25 29 35 85 95 106 30 38 43 50 95 106 120 40 51 59 67 105 120 135 DC SPECIFICATIONS Symbol Characteristic Min Max Unit Condition VIH Input HIGH Voltage 2.0 VCC V VCC = 5V VIL Input LOW Voltage GND 0.8 V VCC = 5V IIN Input Leakage Current SIZ1, SIZ0, A1, A0, CS, DSACK1, DSACK0, R/W, BCLK ±20 µA VIN = 0.5V/2.4V, VCC = 5.25V IOZ Hi-Impedance (Off-State) Leakage Current D(31:0), PD(31:16) ±20 µA VIN = VIH/VIL VO = GND/VCC ΔICCT (BCLK) Additional Maximum ICC/Input BCLK Only 7.5 mA VIH = VCC –2.1V, VCC = 5.25V ΔICCT Additional Maximum ICC/Input SIZ1, SIZ0, A1, A0, CS, DSACK1, DSACK0, R/W 1.5 mA VIH = VCC –2.1V, VCC = 5.25V V Output High Voltage: For D(31:0), PD(31:16) 2.4 V IOH = –5.0mA, VCC = 4.75V VOH Output High Voltage: For DS , SWE, UWE, LWE, PA1, PA0, TA 2.4 V IOH = –16mA, VCC = 4.75V V Output Low Voltage: For D(31:0), PD(31:16) 0.5 V IOL = +5.0mA, VCC = 4.75V VOL Output Low Voltage: For DS , SWE, UWE, LWE, PA1, PA0, TA 0.5 V IOL = +16mA, VCC = 4.75V ICC Maximum Quiescent Supply Current 100 µA VCC = 5.25V Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer NETCOM IDT™ 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MC68150

(.# MC68150 MOTOROLA High Performance Frequency Control Products — BR1334 AC SPECIFICATIONS (VCC = 5.0V ±10%; TA = –40°C to +85°C; CL = 50pF; RL = 500Ω ) Spec 25MHz 33MHz 40MHzSpec Number Specification/Characteristic Min Max Min Max Min Max Unit

1 CS Asserted to BCLK Rising (Setup) 5 4 4 ns

2 BCLK Rising to CS Negated (Hold) 2 1 1 ns

3 A1, A0, SIZ1, SIZ0, R/W Valid to BCLK Falling (Setup) 8 8 8 ns

4 BCLK Rising to A1, A0, SIZ1, SIZ0, R/W Invalid (Hold) 0 0 0 ns

5 D31:0 Valid to BCLK Rising [WRITE] (Setup) 3 2 1 ns

6 BCLK Rising to D31:0 Invalid [WRITE] (Hold) 0 0 0 ns

7 BCLK Rising to PA1, PA0 Valid (tPLH , tPHL ) 2 12.5 2 10 2 9 ns

8 BCLK Rising to PA1, PA0 Invalid (tPLH , tPHL ) 2 22 2 21 2 20 ns

9 PD31:16 Valid to BLCK Falling [READ] (Setup) 2 2 2 ns

10 BCLK Falling to PD31:16 Invalid [READ] (Hold) 8 6 5.5 ns

11 DSACK1 , DSACK0 Valid to BCLK Falling (Setup) 4 2 2 ns

12 BCLK Falling to DSACK1, DSACK0 Invalid (Hold) 8 6 5 ns

13 BCLK Falling to DS, SWE, UWE, LWE (tPLH , tPHL ) 3 10 3 9 3 9 ns

14 BCLK Rising to TA (tPLH , tPHL ) 2 13 2 10 2 9 ns

15 BCLK Rising D31:16 Low Impedance [READ] (tPZL , tPZH ) 2 16 2 15 2 14 ns

16 BCLK Rising to D15:0 Low Impedance [READ] (tPZL , tPZH ) 2 16 2 15 2 14 ns

17 BCLK Rising to D31:0 Valid [READ] (tPLH , tPHL ) 0 3 0 2 0 1 ns

18a BCLK Rising to D31:16 High Impedance [READ] (tPLZ , tPHZ ) 4 18 4 16 3 14 ns 18b BCLK Rising to D15:0 High Impedance [READ] (tPLZ , tPHZ ) 4 22 4 20 3 19 ns

19 BCLK Rising to PD31:16 Valid [WRITE] (tPZL , tPZH ) 2 23 2 22 2 21 ns

20 BCLK Rising to PD31:16 [WRITE] (tPLH , tPHL ) 4 17 4 16 3 15 ns

21 BCLK Rising to PD31:16 High Impedance [WRITE] (tPLZ , tPHZ ) 3 19 3 18 3 17 ns

22 DS Asserted to SWE, UWE, LWE Asserted [WRITE] (Skew) ±0.5 ±0.5 ±0.5 ns 23 DS Negated to SWE, UWE, LWE Negated [WRITE] (Skew) ±1.0 ±1.0 ±1.0 ns

24 DSACK1 , DSACK0, Invalid to DS Negated (tPLH ) 4 4 4 ns

25 DS Negated Width 38 42 28 32 23 27 ns

26 SWE , UWE, LWE Negated Width 38 42 28 32 23 27 ns

27 CS to DSACK1, DSACK0 Valid 23 21 20 ns

28 PD31:16 Valid to DS, SWE, UWE, LWE Asserted [WRITE] 23 22 21 ns

29 SWE , LWE, UWE Negated to PD31:16 Invalid [WRITE] 27 26 25 ns

30 DS Negated to PD31:16 High Impedance [WRITE] 27 26 25 ns

31 DS Negated to PD31:16 Invalid [READ] 3 2 2 ns

32 DS , SWE, UWE, LWE Asserted Width 38 42 28 32 23 27 ns

33a CS Negated to D31:16 High Impedance [READ] (tPHZ , tPLZ ) 15 75 15 55 15 45 ns 33b CS Negated to D15:0 High Impedance [READ] (tPHZ , tPLZ ) 20 70 20 50 20 40 ns

34 PD31:16 Valid to DS Negated [READ] 8 8 8 ns

35 CS Negated to BCLK Rising (Setup) Guarantees Sync Termination 3 3 3 ns

36 BCLK Rising to CS Negated (Hold) Guarantees Async Termination 4 4 4 ns

37a TA Negation to D31:16 High Impedance [READ] (Async Termination) 11 10 9 ns 37b TA Negation to D15:0 High Impedance [READ] (Async Termination) 13 12 11 ns 38 CS Negated to TA Negated (Asynchronous Termination) 2 10 2 9 2 8.5 ns 39a CS Negated to D31:16 High Impedance [READ] (Async Termination) 2 16 2 15 2 14 ns 39b CS Negated to D15:0 High Impedance [READ] (Async Termination) 3 19 3 17 3 16 ns Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer NETCOM IDT™ 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MC68150

Figure 6. MC68150 READ/WRITE Timing (Two Transfers Shown for Clarification) Freescale Semiconductor, Inc.

Figure 7. MC68150 READ/WRITE Timing; Asynchronous Operation Only for Processors Other Than 680X0 Freescale Semiconductor, Inc.

MOTOROLAHigh Performance Frequency Control Products — BR1334 OUTLINE DIMENSIONS /C0050/C0046 /C0050 /C0050/C0046 /C0050 /C0046/C0050 /C0050/C0046/C0050 /C0046 /C0046 /C0046 /C0046 /C0050/C0046 /C0050/C0046 /C0046 /C0046 /C0046 H /C0050° /C0050/C0046 /C0050 /C0046 /C0050 /C0050/C0046/C0050 /C0050/C0046/C0050 /C0046 /C0050/C0046 /C0046 /C0046 H H /C0050/C0046/C0050 /C0050/C0046/C0050 /C0046/C0050 /C0046/C0050 /C0046/C0050 /C0046 /C0050/C0046/C0050 H /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0050 /C0046 /C0050 /C0046 /C0050 /C0046 /C0046 /C0046 /C0050 /C0046 /C0050 /C0046 /C0050 H /C0050° /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0050 H H /C0046 /C0046 /C0046 /C0046 /C0046 /C0046 /C0050 /C0046 H D -N- -L- -M- D Y BRK W V 168 X B U Z VIEW D-D /C0046 /C0046/C0050 ) !" ( # (( /C0046 /C0046 ) !" ( # (" /C0046 /C0046 ) !" ( # (" /C0046 /C0046 ) !" ( # (" H K VIEW S F /C0046 /C0046 ) !" ( # ("GC /C0046 /C0046/C0050 ) !" ( # (( VIEW S /C0046 /C0046 -T- E J /C0066 /C0046/C0050 ( /C0046 #$)( ’ )$% $ ! ( $*!’ -)( !#/C0046 /C0050/C0046 " %!#/C0046 /C0046 /C0046/C0050 %’ (/C0046 #( . /C0046" /C0050/C0046 /C0046 A /C0046 /C0046 ) !" ( # (" R /C0046 /C0046 ) !" ( # ("Z FN SUFFIX PLASTIC PACKAGE CASE 779-02 ISSUE C /C0046 ) # ) /C0046 /C0050 /C0046 /C0046 "#($#( ’ # * ’ )’"# ) ) $*)’"$() -)’"( $ "$! ) ’ *’’( ) *’’( # #)’! #. "(") ),# ) %!() $./C0046 /C0046 "#($# #$) *( ) ’)’ ) /C0046 /C0046 /C0046 ) !! #$) *( ) /C0046 /C0050 /C0046/C0046 Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc... MC68150 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer NETCOM IDT™ 32-Bit to 32/16/8-Bit Dynamic READ/WRITE Bus Sizer Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc MC68150

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