MC146805E2 NXP | Alldatasheet

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o [ *’ .,” MC146805E2 Advance Information CMOS ‘.!*$ I (HIGH PERFORMANCE SILICON e$~ 8-BIT MICROPROCESSOR UNIT The MCl@05E2 MicroprocessorUnit (MPU) belongs to the M6805 Family of Microcomputers. This 8-bitfullystaticand expandable microprocessorcontainsa CPU, on-chipRAM, 1/0,and TIMER. Itisa low-power, low-costprocessordesigned forlow-end to mid-range ap- plicationsinthe consumer, automotive, industrial,and communications markets where very low power consumption constitutes an important factor. The following are the major features of the MC146805E2 MPU: HARDWARE FEATURES

  • TypicalFullSpeed Operating Power of 35 mW @ 5 V
  • TypicalWAIT Mode Power of 5 mW
  • TypicalSTOP Mode Power of 25 pW
  • 16 Bidirectional1/0 Lines ~!,$& .,i.~:: O Internal8-BitTimer with Software Programmable 7-BitPres&i~eX:t.,,1*\\<jy,.
  • Master Reset and Power-On Reset ,. $:,$?,
  • Capable of Addressing Up to 8K Bytes of E~:$~RQlMemory‘~it:t~.● Single3- to 6-VoltSupply “*:,,.i$$,-if.s<::,~.+, .:?.‘\\\\w,,!, SOFTWARE FEATURES ,..~-’~qa;$
  • EfficientUse of Prog%,#pace
  • Versatilelnterrup$~a~ting,.~ .;:*
  • Addressin@~~~~@ with Indexed Addressing forTablesi\\,!~’
  • Efficie~~%u&tion Set
  • Memq,$~apped 1/0 This document contains information on a new product. Specifications and information herein are subject to change without notice. [M” o\\ Z SUFFIX CHIP CARRIER CASE 761 PIN ASSIGNMENTS m[ 2 LI[ 3 DS[ 4 R~[ 5 AS [ 6 PA7 [ 7 PA6 [ 8 PA5 [ 9 PA4[ 10 PA3[ 11 PA2~ 12 PA1 [ 13 PAO[ 14 A12[ 15 All[ 16 A1O[ 17 A9 [ 18 40 ]VDD 39 ]Oscl 38 ]OSC2 37 ]TIMER 36 ]P80 35 ]P81 34 ]PB2 33 ]PB3 32 ]PB4 31 ]PB5 30 ]PB6 29 ]PB7 28 ]BO 27 ]Bl 26 ]82 25 ] B3 24 ]84 23 ] B5 MOTOROLA INC., 1982 ADl~R: Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

Data Strobe (@Z) Read/Wtite ruclsInc,

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DC ELECTRICAL CHARACTERISTICS @ 3.0 V (VDD=3.O Vdc, VSS =0, TA= TL to TH, unlessotherwise noted) Charactetiatica Symbol Min Ma&*~# **t Output Voltage (1Load< 10,0 vA) vOL VDD:O,, ,, ,:1 .,”y:‘“ Total Supply Current (CL=50 pF – No dc Loads, tcYc=5 pS) ,,,,’.. ~. ,,,.,$:$+$.,’ ,+,+ *.7.. ~,. Run (VIL=O.2 V, VIH=VDD– O.2 V) IDD *::$.~,. ,,?$, Wait (TestConditions – See Note Below) Stop (TestConditions – See Note Below) IDD . >-~~t:t,,,,_}<:jX,*.,,$< 100 PA Output High Voltage (lLoad=0.25 mA) A8-A12, BO-B7, DS, AS, R/~ ~~y.,Y~., (lLoad=O.l mA) pAO-pA7, pBO-pB7 \\.:~y@~’””~ 2,7 – v Input High Voltage ~t,3~* -.,:,,,.,. TIMER, ~Q, RESET !,~>f $%>i~.),+ ,1* vlH 2,5 – v Input Low Voltage (AllInputs) ,>.~1:,,~?..~$’ vlL — 0.5 v Input Current t{,~.t;.— — RESET, IRQ, TIMER, OSCI ,rt, ..,, * Iin — *I PA Hi-Z Output Leakage ,.,$,,.,!$.,,\\kp,.,~,, PAO-PA7, PBO-PB7, BO-B7 ‘~$~1j>>a$i~?+,,,y,, ITSL – *10 PA Capacitance ~, .,:.’.,~,+1 ,<\\\\, *.. “iNOTE: Test conditionsforQuiew~~~&ent values are: Port A and B prog@m@d as inputs. vIL=O.2 V fo$:~~%~?, PBO-PB7, and BO-B7.— — vlH=vDQ–&~~~,~Or RESET, IRQ, and TIMER OSC1 in~~~,jsa $~uarewave from VSS +0,2 V to VDD – 0,2 V, OSC2 ~’h~~~.~ad (includingtester)is35 pF maximum,‘~4,,, W~~~r@e~DD isaffectedlinearlyby thiscapacitance. ;~,i.:ih,~., MOTOROLA Semiconductor Products Inc. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

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TABLE 1 – CONTROL TIMING (VSS= O, TA=TL to TH) Characteristics A), Symbol Min Typ Max Min Tvp 1/0 Port Timing – Input Setup Time (Figure3) tpVASL 5m – – 250 – Input Hold Time (Figure3) tASLpX lm – – 100 — CrystalOscillatorStartup Time (Figure5) toxov – 30 300 – ~y~y: .: –,,‘8“ 100 ms Wait Recovery Startup Time (Hgure 71 tlVASH – – 10 – ,,, \\?.$...,&,,,,,! 2 ps Stop Recovery Startup Time (CrystalOscillator)(Figure8) tlLASH – 30 3m ,.>,~1~— <l?s,!:.~.,,$15 100 ms Required InterruptRelease (Figure6) .,.,.. tDSLIH Reset Pulse Width (Figure5) “r- Timer Period (Figure7) tTLTL 1.0 – ~$li$,,*:*;>.,:1,0 – – tcyc OscillatorCycle Petiod [1/5 of tcyc) tOLOL 1000 .?:>“’*’‘“ – 200 – — ns OSCI Pulse Width High to ~ 350 ,#b* kti<.~ — 75 – – ns OSCI Pulse Width Low tOL 3gg:’’~’?i** – – 75 – — ns ,. :.., CMOS Equivalent 1 ‘estpoint1 C=50 pF, PAO-PA7, PBO-PB7 = 130 pF, A8-A12, BO-B7, DS, with VDD=5 V + 10% MOTOROLA Semiconductor Products inc. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

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  • ● Internal/External ~tTL Clock # tTH ~,’,. TCRb7 AS n n DS Unmux IntRoutine StartingAddr A8-A12 xAddress Bus h~ / IF x lF x./ x Mux BO-B7 Addr+ 1 k SP SP–11 5P–2 x SP-4 F6 F7 Address/Data PCL X PCH x A cc XG XKBus New PCti New PCL 1stOp Code IntA RO tine Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...
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o FUNCTIONAL PIN DESCRIPTION VDD AND Vss VDD and VSS providepower to the chip.VDD provides power and VSS isground. ~Q (MASKABLE INTERRUPT REQUEST) IRQ is both a level-sensitiveand edge-sensitiveinput which can be used to requestan interruptsequence. The M PU completes the currentinstructionbeforeitresponds to the request,IfIRQ islow and the interruptmask bit(1bit)in the conditioncode registerisclear,the MPU beginsan inter- ruptsequence at the end of the currentinstruction,The in- terruptcircuitrecognizesboth a “wire ORed” levelas wellas pulses on the IRQ line (see Interruptsection for more details).IRQ requiresan externalresistorto VDD for“wire OR” operation. RESET The RESET input isnot requiredforstart-upbut can be used to resetthe MPU internalstateand providean orderly softwarestart-upprocedure.Referto the Reset sectionfora detaileddescription. TIMER The TIMER inputisused forclockingthe on-chip timer, Referto Timer sectionfora detaileddescription. AS (ADDRESS STROBE) Address strobe (AS) isan output strobeused to indicate BO-B7 (ADDRESS/DATA BUS) The BO-B7 bidirectionallinesconstitutethe lower order addresses and data. These linesare multiplexed,with ad- dresspresentataddressstrobetime and data presentatdata strobetime,When inthe data mode, these linesare bidirec- tional,transferringdata to and from memory and peripheral devicesas indicatedby the R/~pin. As outputsineitherthe data or addressmodes, theselinesarecapableof drivingone standardTTL load and 130 pF, .!,. The MC146805E2 providesfortwo types o~~$~!~qtorin- puts – crystalcircuitor externalclock.T~$~$$bscillator pins are used to interfaceto a crystalCLFmIN+aS shown in$t~,.,,,,!*\\.\\~sp Figure5. Ifan externalclockisused,it~B%t@ connected to OSCI. The inputat these pinsisdiv~@{~five to form the cyclerateseen on the AS and D~:~f~.me frequency range isspecifiedby fosc.The OS~l ‘?~,,,@~stransitionsrelation- ships are provided in FigU{~~~ fot system designs using CRYSTAL – Theq[@~~@Shown inFigure5 isrecommend- ed when usinga wta.~he internaloscillatorisdesignedto interfacewit~.s~,,nAT-cut parallelresonant quartz crystal resonatorin-ttigtif$equencyrange specifiedfor fosc in the electrical~$ti~~~~~eristicstable.An externalCMOS oscillator isrecw,%:~#ed when crystalsoutsidethe specifiedranges are $~i:~eused, The crystaland components should be M$unte&as closeas possibleto the inputpins to minimize .,~d~~ut distortionand start-upstabilizationtime,:@\\..T<:i the presence of an addresson the 8-bitmultiplexedbus. The “!+w$$~::!* AS lineisused to demultiplexthe eightleastsignificantad- ‘t$~.~~$: EXTERNAL CLOCK – An externalclock should be ap- ,. ~liedto the OSCI inputwith the 0SC2 inputnot connected, dress bitsfrom the data bus, A latchcontrolledby address “~~ strobeshould captureaddresseson the negativeedge,.+Thi@$’ output iscapable of drivingone standardTTL load 4’&I130 ~L,,,:@$~ DS (DATA STROBE) This output isused to transferdata t@:~#$&& a peripheral or memory. DS occurs anytime the M~$U’@8s a data reador write.DS alsooccurswhen the ~~~ ,{b’~ka data transferto or from the MPU internalmw@.W,t%efer to Table 2 and Figure4 fortimingcharact6ri$J::$Thisoutput iscapablebf drivingone standard T~&k~&and 130 pF. DS isa con- tinuoussignalat fosc,k+5~,#n the MPU isnot inthe WAIT or STOP state.S@&’@ bus cycles are redundant reads of~:,‘$:,il~opcode bytes, <. >y<?$$~ Rl~ (READ~t&~Tt) The ~~~~u~ut isused to indicatethe directionof data trao:,f~~fo~@6thinternalmemory and 1/O registers,and ex- ,<to@&ate toa selectedperipheralwhether the M PU isgoing ‘~~k~~~d or write data on the next data strobe (R/~ I&_= processor write; R/~ high= processor read). The R/W output iscapableof drivingone standardTTL loadand 130 pF. The normal standby stateisread (high). A8-A12 (HIGH ORDER ADDRESS LINES) The A8-A12 output linesconstitutethe higherorder non- multiplexedaddresses.Each output lineiscapableof driving one standard TTL load and 130 pF. as shown in Figure10. LI (LOAD INSTRUCTION) This output isused to indicatetha~a fetchof the next op- code isin progress.LI remains low during an externalor timerinterrupt.The LIoutput isused only forcertaindebug- ging and testsystems. For normal operationsthispin isnot connected. The LIoutput iscapableof drivingtwo standard LSTTL loadsand 50 pF. This signaloverlapsdata strobe, PAO-PA7 These eightpinsconstituteinput/outputportA. Each line isindividuallyprogrammed to be eitheran input or output under software control via itsdata directionregisteras shown inFigureIi(b).An 1/0 pin isprogrammed as an out- put when the correspondingDDR bitissetto a “l”, and as an inputwhen itissetto a “O’. Inthe output mode the bits arelatchedand appear on the correspondingoutput pins.An M PU read of the port bitsprogrammed as outputs reflects the lastvaluewrittento thatlocation,When programmed as an input,the inputdata Mt(s)are not latched.An MPU read of the port bitsprogrammed as inputsreflectsthe current statusofthe correspondinginputpins.The 1/0 porttimingis shown inFigure3, See typical1/0 portcircuitryinFigure11. During a power-on resetor externalreset,alllinesare con- figuredas inputs(zeroindata directionregister).The output port registerisnot initializedby reset.The TTL compatible three-stateoutput buffersare capable of drivingone stan- dard TTL load and 50 pF. The DDR isa re~d/writeregister. M070ROLA Semiconductor ProductsInc. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

,,., ,,:,: ,. ,,. , , ,,”” ,, ,! ..,:~., ,,, ,.,’ ,,. ,,. . :,, ,, ,,. , :, ’.,,,. :,, ! .: .,-,’ .,, ., ,’,. BO-B7,, ,,, ,’, ... . “ bytes of ,rnemory(firsthalfof page zero)and iscomprised of,, the“1/0 port locations,flmer locations,and 112 bytes of RAM. The MPU can readfrom or writeto anj of,theseloca- :,, ~ ,tions.”A p~ogra,mwriteto on-chip locationsisrepeated on ,, ,, ~~ data only from the addressed on-chip location, Any read data appearing ‘on the’’inputbus. isignored. subroutine calls.At power-up, the stack pointer is set to “$O07F and it ii’decremented as data is pushed onto the stack. When data is removed from the stack, the stack .,pointarisincremented.A maximum ofW bytes of RAM is available for stack usage, Since most programs use only a.:,,, ,’ .’, ‘MEMOR~’ADDRESSING, ~.,’ ‘:},:;’, ,small part of the allotted stack locations for interruptsand/or ;, ; ,,subrouti,nestackingpurposes,’the unused bytes are usable “ The M CI%805E2 is‘capableof’addressing8192 bytes of’ forprogram data storage. ~” rn,amoryand 1/0 registers,The addresss“pace:isdi~ded into Allmemory locationsabove location$007F:arepartof the internalmemory space ‘and’ external’ memory: spacej as!” externalmemory map. In addition, ten’locations in the 1/0

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FIGURE 11 – TYPICAL PORT 1/0 CIRCUITRY I (a) Data Direction (~ Register Bit I T 1 1I I I Data Direction Register DDA7 DDA6 DDA5 DDA4 DDA3 DAI DDAO $0004 Register $0000 ! t PB7 PB6 PB5 PB4 PB3 PB2 PBI PBO TABLE 3 – l/O PIN FUNCTIONS T R/~ DDR l/O Pin Functions o 0 The 1/0 pin isin inputmode. Data iswritten intothe output data latch. Data iswrittenintothe output data latchand o 1 output to the 1/0 pin. 1 0 The stateof the 1/0 pin isread. I1 The 1/0 pin isinan output mode, The output 1 data latchisread. MOTOROLA Semiconductor Products Inc. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

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FIGURE 13 – PROGRAMMING MODEL 7 0 A 7 0 x I o Pc 12 6 0 0 00 0 0 01 cc h INZC Accumulator Index Register stack#~;$s?],$ollowed by PCH, etc. Pullingfrom the stack isin ‘The stack pointer is a 13-bit r~&~,{3~~ontaining the -ad- dress of the next free location on~he ,fack. When accessing memory, the seven most sig@%~$&lts are permanently set to 00~001. They are app~n~~d.~k the six least significant registerbitsto produce ~,,,a~ress within the range of $O07F to $0040, The stack ~fea bf&R’AM isused to store the return terrupts. Durin~%@~t&@b) or power-on reset, and during a “reset stack ~~t~.’ instruction,the stack pointer isset to itsupper li,,m~~W7F). Nested interruptsand/or subroutines may u~~,,.ti~~ts~~ (decimal) locations, beyond which the,r,! stack &oin@t’r’wraps around” and points to itsupper limit,:{th:@~y~w.$&sing the previously stored information, A ,:uB~@&*$fiecalloccupies two RAM bvtes on the stack, while .,...;,, CONDITION CODE REGISTER (CC) The condition code registerisa 5-bitregisterinwhich each bit is used to indicate the results of the instructionjust ex- ecuted. These bits can be individuallytested by a program and specificaction taken as a resultof theirstate.Each of the five bits isexplained below, HALF CARRY BIT (H) – The H bitisset to a one when a carry occurs between bits3 and 4 of the ALU duting an ADD or ADC instruction. The H bit is useful in binarv coded decimal addition subroutines. INTERRUPT MASK BIT (1)– When the I bit isset, both the external interrupt and the timer interrupt are disabled. Clearing this bitenables the above interrupts,Ifan interrupt occurs while the I bit isset, the interrupt islatched and will be processed when the I bit is next cleared. NEGATIVE BIT (N) – When set,thisbitindicates that the resultof the lastarithmetic, logical,or data manipulation was negative (bit7 in the resultisa logicalone). ZERO BIT (Z) – When set,thisbitindicates that the result of the lastarithmetic, logical,or data manipulation was zero, CARRY BIT (C) – The C bitisset when a carry or a bor- row out of the ALU occurs duting an arithmetic instruction, The C bitisalso modified during bittest,shift,.rotate,and branch types of instruction, RESETS The MC146805E2 has two reset modes: an active low ex- ternalreset pin (R ES ET) and a power-on reset function; refer to Figure 5, m MOTOROLA Semiconductor Producfs Inc. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

,:!... en orderly’s’oftware start-up proc~ external reset mode, the RESET pin must sta~:low fc mum of one tRL. ,Thl trigger to improve it: then the Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

w 07F+S P O+DDRS CLR l~Q Logic FF+Timer 7F;~Ts&ler ti Put lFFE on Address Bus FIGURE 15 – RESET AND INTERRUPT PROCESSING FLOWCHART I eSet IBit Clear w TLoad PC From: SWI: 1FFC/1 FFD ~: lFFA/1 FFB TIMER: lFF8/1 FF9 rimer Wait:lFF6/l FF71 MOTOROLA Semiconductor Products Inc. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

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FIGURE 19 – TIMER BLOCK DIAGRAM Selectedby Selectedby TCRO, # External w TCR4, TCR5 Input TInternal Clock [ Clearedby TCR3 TIMER CONTROL REGISTER (TCR) ,$’.\\JeR5 TCR4.:,. 7654 ~:,’:,. ‘ a ““’o 0*) TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCRI TCRO “’~; pin to timer ,.*’: 1 0 Inputsto timerdisabled 1 1 TIMER pin to timer 1 – Set whenever the counterdqc~~~~ to zero,or un- der program control. ‘“$:,,*\\,,/$ym,:~t:f* O – Clearedon externalrese$:lp~~er-onreset,STOP in- struction,or progra~’’w~bl “ 1 – Selectexternalclocksource. O – Selectinternalclocksource (AS). TCR4 – Externalenablebit:controlbitused to enablethe externalTIMER pin (unaffectedby RESET). 1 – Enable externalTIMER pin. O – DisableexternalTIMER pin. m MOTOROLA TCR3 – Timer PrescalerReset bit:wtitinga “l” tothisbit resetsthe prescalerto zero.A read of thislocationalways indicatesa “O” (unaffectedby RESET). TCR2, TCRI, TCRO – Prescaleraddress bits:decoded to selectone of eightoutputs of the prescaler(unaffectedby RESET). TCR2 TCR1 TCRO I Result o 0 0 + 1 0 0 1 +2 o 1 0 + 4 0 1 1 + 8 1 0 0 -16 1 0 1 +32 1 1 0 -64 1 1 i +128 INSTRUCTION SET The MPU has a set of 61 basicinstructions.They can be divided into five differenttypes: register/memory, read- modify-write,branch, bit manipulation,and control.The followingparagraphs brieflyexplaineach type. Allthe in- structionswithin a given type are presented in individual tables. Semiconductor Products Inc. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

sed to indicate“contents isreplace-dby,” and a colon indi. allthe information-necessaryto ex-,, ~the opcode. Operations :.r6aiSteror acct)mulator, and no RAM and 1/0 registers chip ROM, Direct addressing is ef- ing mode, theeffectiveaddrassof inthe”twobytesfollowingthe op- extended addressing modes are urnentsanywhere inmemory with ction.When using the Motorola ]otspecifywhether an instruction ?d addressing, The assembler nest efficientaddressing mode, (PC+2);PC+PC+3 1);Address Bus Low-(PC + 2) ;t:addressingmode, the effective is contained in the 8-bitindex isaddressingmode can access the first256 instructionsare only one byte move a pointerthrough a tableor erenced RAM or 1/0 location. )y,adding th,econtentsofthe byte ]tof the indexregister;therefore, nywhere, within the lowest 511 mple, thi,smode of addressingis thelement inan n element table. vtes.The contents of the index ntentsof (PC+I) isan le bvte “offsetindexing permits ineitherRAM or ROM, Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

INDEXED, 16-BIT OFFSET Inthe indexed,16-bitoffsetaddressingmode the effective addressisthe sum of the contentsofthe unsiged8-bitindex registerand the two unsigned bytes followingthe opcode. This addressingmode can be used ina manner similarto in- dexed 8-bitoffset,except that thisthree byte instruction allowstablesto be anywhere inmemory (e.g.,jump tablesin ROM). As with directand extended, the M6805 assembler determinesthe most efficientform of indexed offset– 8 or 16 bit.The content of the index registerisnot changed. EA=X+[(PC+ I):(PC+2)]; PC+PC+3 Address Bus High-( PC+ 1)+ K Address Bus Low+K+ (PC+2) where: K = The carryfrom the additionof X + (PC + 2) RELATIVE Relativeaddressingisused only inbranch instructions.In relativeaddressing the content of the 8-bitsigned byte followingthe opcode (theoffset)isadded to the PC ifand only ifthe branch conditionistrue,Otherwise,controlpro- ceeds tothe nextinstruction.The span of relativeaddressing is limitedto the range of – 126 to + 129 bytes from the opcode. The bitsetand clearinstructionsoccupy two bytes, one forthe opcode (includingthe bitnumber) and the sec- ond to address the byte which containsthe bitof interest. EA=(PC+I); PC~PC+2 Address Bus High YO; Address Bus Low+(PC + 1) BIT TEST AND BRANCH ‘.!$>, Bittestand branch isa combination of directad~$$$~g, bitaddressing,and relativeaddressing.The bit,@d~% and condition(setor clear)to be testedare part~f,%$<~pcode. The addressof the byte to be testedisintQ@:~~~&byte im- mediately followingthe opcode byte,<JP&$P&The signed relative8-bitoffsetisinthe thirdbyte.#~&2)~&fiNdisadded to the PC ifthe specifiedbitis set,?@:$~~@]n the specified memory location.This singlethr#~~$@ instructionallows the program to branch based3$~Jthe’~onditionof any bitin.~‘~”the first256 locationsof m~~~~$r 541+*’(R + 1) Address Bus Hig~:<~~q@8dress Bus Low~(PC+ 1) EA2= PC + 3+$~~~Q); PC~EA2 ifbranch taken; branch instructionopcode location,The Motorola assembler . f“:$~sTEM CONFIGURATIONcalculatesthe proper offsetand checks to see ifitiswithin the span of the branch. Figu~~,*~firough 25 show in general terms how the M C~468~52 bus structuremay be utilized.Specifiedinter- EA= PC+2+ (PC+ 1);PC~EA ifbranch istaken; fat~{~etailsvary with the various peripheraland memory otherwise,PC+ PC+ 2 #~&c~k emnloved. :%~t,i~$.$able11 pro~idesa detaileddescriptionof the information BIT SET/CLEAR ~t~~’!~$,presenton the bus, read/write(R/~) pin and the load in- Directaddressingand bitaddressingare combined in in- ‘“:Sstruction(Ll)pin during each cycleforeach instruction. structionswhich set and clearindividualmemory and MO Y> This informationis usefulin comoaring actualwith ex- petted resultsduringdebug of both softw~re and hardware as the control,,program is executed. The information is categorizedin groups according to addressing mode and number of cyclesper instruction. MOTOROLA Semiconductor Products Inc, Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

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  • TABLE6– BRANCH INSTRUCTIONS RelativeAddressing Mode Function Mnemonic Op # # Code Bytes Cycles Branch Always BRA 20 2 3 Branch Never BRN 21 2 3 Branch IFF Higher BHI 22 2 3 “!$,?<< skr.\\:27,, Branch IFF Lower or Same BLS 23 2 3 ,* ‘~,;:”:~.,,,?*.,,,$’’” Branch IFF CarrV Clear BCC 24 2 3 .;3>::> (Branch IFF Lower) (BLO) 25 2 3 :;~:*’&””” Branch lFF Not Equal BNE 26 2 3 ,g~,, <$ . .$, Branch IFF Equal B EQ 27 2 ~, “ y, Branch lFF Half CarrV Clear BHCC 28 2 “,k~%$>, Branch lFF Half CarrV Set BHCS 29 2 +$ci’y<;& ‘ Branch IFF Plus BPL 2A ~:w~ ‘;@ 3I t Branch lFF Minus BMI 2B I ‘::$2:Y*I 3 I ,,:$:~..{. ,..~k.;, Addressing Modes ‘*?t*,~.t.. BitSet/Clear~$% BitTest and Branch Code Bytes CVcles Code Bytes Cvcles Branch IFF Bitnis Set – – – 2.n 3 5 Branch IFF Bitn isClear qR~3:&’rh = 0...7) – — — 01+2*n 3 5 Set Bitn +,,B’%$F%n[n= O...7) 10+2*n 2. 5 — — — Clear Bitn “’” %@~R n (n= O...7),l:t~ ll+2*n 2 5 — — — ,.,:,1,{, Function Mnemonic Op # # Code Bytes Cycles TransferA to X TAX 97 1 2 TransferX to A TXA 9F 1 2 Set CarrV Bit SEC 99 1 2 ClearCarrV Bit CLC 9a 1 2 Set InterruptMask Bit SEI 9B 1 2 Clear InterruptMask Bit CLI 9A 1 2 Software Interruot Swl a3 1 10 ~Wait WAIT aF 1 2 MOTOROLA Semiconductor Products Inc. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

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TABLE 10 – MCI=5 CMOS INSTRUCTION SET OPCODE MAP Bit Manipulation Branch Read-Modify-Wtite Control BTB BSC REL DIR INH l~H 1X1 1; INH INH IMM DIR ,.>S%&T $>’F I& lx 1 IF Hi m 4 8 9 LOW B ./::..$ ml W1O ,,? 1$0 Hi ml 1 01w 0101 0110 0111 lm lml 1011 .+ !s,,$~m 1101 1170 1111 BR S ET05 BSETO 5 3 3 6 5 9 2 ... “:\\.> “ 4 5 4 BRA NEG NEG NEG NEG NEG RTI SUB SUB ‘$?* ,$S U B SUB SUB SUB o BTB BSC 2 REL 2 DIR 1 INH 1 INH 2 1X1 1 lx 1 INH 2 IMM 2 .&, ~,~~,\\+~ EXT 3 1X2 2 1X1 1 lx BRCLR05

1 BCLRO 5

‘?#&,; : cMp 4 BRN 4 3 RTS CMP CMP CMP CMP 1 0321 3 aTB 2 BSC 2 REL 1 INH 2 lhlM,.~!!a. BRSET15 EXT 3 1X2 2 1X1 I lx ml

2 BSET1

S B &;; i :$ ~Y%c SBC SBC SBC SBC 2 0310 3 BTB 2 asc REL 2 ,,J~~> DIR 3 EXT 3 1X2 2 1X1 1 lx 0310 BRCLR15 3 5 3 3 6 5 10 BCLR1 , fy;$; ~ Cpx 3 BLS COM COMA COMX COM COM Swl CPX CPX CPX s CPX 3 ml 1 3 BTa 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 1X1 1 lx 1 INH \\. 2 DIR 3 EXT 3 1X2 2 1X1 1 B R S ET25 lx 3 5 3 3 6 5 0311 ~,,$ 2 ~;$<+ 3 BSET2 BCC 5 4 LSR LSRA LSRX LSR LS R AND AND BTB 2 BS: 2 ,’,,., AND AND o AND 4 REL 2 DTR 1 INH 1 INH 2 1X1 1 lx DIR 3 EXT 3 1X2 2 1X1 1 lx Olw

5 BRCLR25

?,.>,,i, 0101 BIT BIT BIT,’,fj;>\\ BIT BTB 2 BIT BIT BSC 2 REL $. 2 MM 2 DIR 3 EXT 3 lx 1X2 2 1 B R S ET35 3 3 6 0101 5 *’EF.” 2

0 B S ET3

..” !.; 5 ROR RORA RORX ROR ROR ~~:b:,~.,,,, 0110 LDA LDA LDA LDA LDA LDA 1 1 0 8 BR SET45 BSET45 \\>lBHCC LSL LSLA LSLX LSL LSL 1032 CLC EOR EOR EOR BTB 2 EOR BSC 2 REL 2 DIR 1 2:,. ‘‘ EOR EOR 8 INH 1 INH 2 1X1 1 tx.. ~,:,.+<”? I NH 2 IMM 2 DIR 3 EXT 3 BRCLR45BTB 2 BCLR45 1X2 2 1X1 1 3 3 lx lm 6 4,. 2 3 BHCS ROL ROLA 4 3 ROLX ROL 1031 SEC ADC ADC ADC BSC 2 REL 2 DIR 1 ADC ADC ADC 9 INH 1 INH 2 1X1 1 $%, 1 INH 2 IMM 2 DIR 3 ExT 3 1X2 2 1X1 1 lx 1021 B R S ET55 BSET55 3 3 6 2 A BPL DEC DECA DECX OEC D@ 1010 CLI ORA’ ORA BTB 2 BSC 2 ORA REL 2 ORA Mm DIR 1 lxI,:t‘1 ORA ORA A INH 1 INH 2 lx 1 INH 2 IMM 2 DIR 3 EXT 3 1X2 2 1X1 1 lx 1010 B ,*~.~. BRCLR55 BCLR55 2 2 3 BMI .\\$.,,~’,::i>., 1o11 , SEI ADD aTa 2 ADO BSC 2 REL ADO ADO ADO ADD 8 ::& INH 2 IMM 2 DIR 3 EXT 3 1X2 2 \\:~\\Y.$,:$,,:! 1X1 1 B R S ET65 BSET65 lx 1o11 -. c“ 5 2 2 BMC INC 4 3 INCA INCX ;?’ (p~, llm INC RSP BTB 2 BSC 2 JMP REL 2 DIR 1 “%1 1 JMP JMP JMP JMP c o INH 1 INH :!- ,. lx 1 [NH 2 DIR 3 EXT 3 1X2 2 1X1 1 BRCLR65 BCLR65

3 TSTX$$: t:~,x&T 5

INH 1 1X1 1 lx EX; 3 JSRIX; 2 JSRIX; 1 ‘SR :; 1:1‘:> ,w: , , 1 INH 2 REL 2 DIR 3 5 3 E BR SET75 B S ET7 ~’l:;.,t,“’kc’ “ 2 2 BIL ,:<=. 1110 3 BTB 2 STOP LDX LDX BSC 2 REL LDX LOX LDX g BRCLR75 BCLR75 F BIH CLR ~g” WN; 2 CLRIX: 1 CLR 1: 1 WA’;: 1 ‘xl,: 2 ‘MM : STX::: : STC! : STX2 : STX! 1 ‘Tx : ::: CL R A@+’ 1111 3 BTB 2 BSC 2 REL 2 DIR 1 Abbreviations for Address INH Inherent A Accumulator x Index Register IMM Immediate DIR Direct EXT Extended LEGEND ‘ne.:- Opcode in Hexadecimal Opcode in Binary 1X2 Indexed, 2 Bfie (16-Bit)Offset Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NOTE: FIGURE 2 – CONNECTION TO M~OO PERIPHERALS 1 1 Address Decode Chip Select ~ rs A8-A12 )0-Q7 CMOS Non-Muxed ~o-A7 Memory s MOTOROLA Semiconductor Producfs Inc. m Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

,, ,. :,, ,. :.,.,,,’; ,,.,, ,., ”,’ ?tiGtiRE.24-’C.ONNECTION TO”sTATIC CMOS RAMS ,\\ Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

TABLE 11 – SUMMARY OF CYCLE-BY-CYCLE OPERATION Address Mode Cycles Cycle # Address Bus R/w LI Instructions Pin Pin Data Bus LSR LSL ASR NEG CLR ROL COM ROR DEC INC TST TAX CLC SEC STOP CLI SEl RSP WAIT NOP TXA RTS I Swl TI nmediate Op Code Address 1 Op Code Address + 1 1 Op Code Address + 1 1 Op Code Address 1 Op Code Address + 1 1 Op Code Address 1 Op Code Address + 1 1 Stack Pointer “1 Stack Pointer + 1 1 Stack Pointer+ 2 1 New Op Code Address 1 ,$< Op Code Address Op Code Address + 1 .@~’ Stack Pointer Stack Pointer– 1 $, ‘] 8,,*. Stack Pointar– 2 .:/,,?/!,,8o.,,. Stack Pointer– 3 Vector Address 1FFC (He~’P’’’s$:yqJ 1 Vector Address 1FFD (fi[x)’k~ 1 InterruptRoutine StaF~&~Mress 1 @ Code Next Instruction ~~levant Data #rrelevantData IrrelevantData New Op Code Op Code Op Code Next Instruction Return Address (LO Byte) Return Address (Hi Byte) Contents of Index Register Contents of Accumulator Contents of CC Register Address of Int.Routine (H1 Byte Address of Int.Routine (LO BytE InterruptRoutine FirstOpcode Op Code Op Code Next Instruction IrrelevantData IrrelevantData IrrelevantData IrrelevantData IrrelevantData IrrelevantData New Op Code Op Code Address 1 1 Op Code Op Code Address + 1 1 0 Operand Data ,.;l$~ ~!;ys” 1 Op Code Address 1 1 Op Code,,i\\.,,:. BitTest and,~,@’ch- ~ .’~:i* ,,,$:t.. 1 Op Code Address 1 1 Op Code ...t~.,’+;<:j,+;~ B R S&Y,@t:A,.

2 Op Code Address + 1 1 0 Address of Operand

5B~C:&;$ 3 Address of Operand 1 0 Operand Data 4 Op Code Address + 2,~~y“;.::T&h, 1 0 Brench Offset 5.,i.’,,,.. Op Code Address t 2 1 0 Branch Offset Relative BCC BHI BNE BEQ BCS BPL BHCC BLS 1 BIL BMC BRN BHCS 3 2 BIH BMI BMS BRA 3 BSR 6 3 Op Code Address 1 Op Code Address + 1 1 Op Code Address + 1 1 0I 1 Op Code Address 1 1 OD Code Address + 1 1 0 Op Code Address + 1 1 0 Subroutine StartingAddress 1 0 Stack Pointer o 0 Stack Pointer – 1 1010t I Op Code Branch Offset Branch Offset Op Code Branch Offset Branch Offset FirstSubroutine Op Code Return Address (LO Byte) Return Address (Hl Byte) m M070ROLA Semjconducfor Producfs Inc. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

1 o“ A~dress ‘ofOperand (HI Byte) :’ 1 0 Address of Operand (LO Byte) 1 0 Address of Operand (LO Bvte) I 1 0 Address of Subroutine (H1 Byte: 1 0 Address of Subroutine (LO Byte 1 ‘o 1st Subroutine OD Code 1 0 !Op Code Next Instruction I I 11’ 0 I Op Code Next Instruction I 1 0 Op Code Next Instruction 1’0 Op Code Next Instruction Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

TABLE 11 – SUMMARY OF CYCLE-BY-CYCLE OPERATION (CONTINUED) Address Mode Cycles Cvcle # R/~ LI Instructions Address Bus I Pin Pin Data Bus Indexed 8-Bit Offset JMP I 3 I ADC EOR CPX TST 5 LSL LSR ASR NEG CLR ROL z 6 COM ROR DEC INC JSR 6 Indexed, 16-Bit Offset Op Code Address 1 1 Op Code Address + 1 1 0 Op Code Address + 1 1 0 Op Code Address 1 1 Op Code Address + 1 1 0 Op Code Address + 1 1 0 Index Register + Offset 1 0 Op Code Address 1 1 Op Code Address + 1 1 0 Op Code Address + 1 1 Op Code Address + 1 1 ,$~,:: Index Register + Offset o \\,\\ Op Code Address 1 yi:~{l,,;$” Op Code Address t 1 1 ‘:$,pd<+~>v Op Code Address + 1 “>+?*,o Index Register + Offset ,,,t.Fti.J.,,,~~ Op Code Address :,), /<,,t<.\\$~i<;$.t:?t1 1 Op Code Address + 1 :,,:\\\\?,.,,~th” 1 0 Op Code Address + 1 ~~ ~.];,} 1 0 1 0 1 0 0 0 0 0~i, ,!,*~,s, ‘.+.,O ~$$%~ Address 1 ,~~,~bde Address + 1 1 b Code Address +2 1 ‘bpCode Address + 2 1 Op Code Address 1 Op Code Address + 1 1 Op Code Address + 2 1 Op Code Address + 2 1 Index Register + Offset 1 Op Code Address 1 Op Code Address + 1 1 Op Code Address + 2 1 Op Code Address + 2 1 Op Code Address + 2 1 Index Register + Offset o Op Code Address 1 Op Code Address + 1 1 Op Code Address + 2 1 Op Code Address + 2 1 Index Register + Offset 1 Stack Pointer o Stack Pointer – 1 0 @*et Operand Data Op Code Offset Offset Operand Data Op Code Next Instruction Op Code Offset Offset Current Operand Data Current Operand Data New ODerand Data Op Code Offset Offset Ist Subroutine Op Code Return Address LO Bvte Return Address HI Bvte Op Code Offset (H1 BVte) Offset (LO BVtel Offset (LO Byte) Op Code Offset (H1 Byte) Offset (LO BVte) Offset (LO Byte) Operand Data Op Code Offset (H1 BVte) Offset (LO BVte) Offset (LO BVte) Offsat (LO Byte) Operand Data Op Code Offset (H1 BVte) Offset (LO BVte) Offset (LO Bvtel Ist Subroutine Op Code Return Address (LO Byte) Return Address (HO BVte) I MOTOROLA Semiconductor Products Inc. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

O Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

NOTES: 1. DIMENSION~lS DATUM. ,?:::! ~(i,ti~,,, ,,.<, $~,* ,.. ., 1. POSITIONAL TOLERANCE OF LEAOS (0), a~ ‘ow;TE:’:NEAND ~ !; ‘3 i ‘i SHALL BE WITHIN 0.25 mm (O.O1OI AT MAXIMUM MATERIAL CONOITION, IN 2. OIMENSION L TO CENTER OF LEADS 3. OIMENSION B DOES NOT INCLUOE F 1.02 1.52 0.040 0.060 G 2.54 Bsc 0.100 BSC J 0.20 I Am- f :+ ‘,, , .,, ,. ; wgJF f+, pLAsTIc PAcKAGE L 15.24 BSC 0,600 BSC~’.*). M w 150 00 ,50 CASE 711-01 ..Y .,, N 0.51 I 1.02 0,0201 0.040 \\,. ( ,$$3 PLANE ‘i?i, $,.. ‘} ~~it$. ~ i. .):3,> .,4,, *;t+, ,e+,, .r> ,:,. “.:\\~\\ .~~> NOTES:~,. ,~;,.. >:;,,{ 1. DIMENSIONS A& RARE DATUMS. 2, ~lS GAUGE PLANE, P 7FG ~,$::.;[ a, 3, POSITIONAL TOLERANCE FOR

11 TERMINALS (0): 40 PLACES:

~@10.25(0,010] @l T lA@l R@ OIM MIN MAX MIN MAX 4, DIMENSIONING ANOTOLERANCING A 11.94 12,57 0,470 0.495 J C 1.60 2.OB 0.063 O.OS2 o 0,33 0,69 0.013 0,027 F 1.07 1.47 0.042 0.05S Z SUFFIX G 1.02 BSC 0,040 GSC H 0,S4 1.19 0.033 0.047 CHIP CARRIER N 1.27 1,79 0.050 0.070 CASE 761-01 R 11.94 12.57 0.470 0.495 MOTOROLA Semiconductor Products Inc. Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...

.. !,. .-, ,, ,,’ ,,, , *:*+ ,. , : ‘ ‘%;r;;lAGE ‘ “’, A PARTICULAR’ M6805” FAMILY VERSION ,, ,. .:’ ‘ ‘: {PLASTIC PACKAGE) Motorola reservesthe righttomake changes.to any products,hereinto improve ieliabilitv,functionordesign. Motorola does not assume anv Iiabilitvarising out of the applicationoruseof anv product-orcircuitdescribed herein;neitherdoesitconvevanvlicenseunder.itspatentrightsnortherightsofothers.,., ,’. ,-, .,, ,,,, ‘@” RD1-850-R2 .,, , ;,.:. ,, Freescale Sem iconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc...