MC6803

MC6801 MOTOROLA | Alldatasheet

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= SEMICONDUCTOR SS TECHNICAL DATA Mc6801 MC6803 Microcontroller/Microprocessor (MCU/MPU) The MC6801 is an 8-bit single-chip microcontroller unit (MCU) which significantly enhances the capabilities of the M6800 Family of parts. It includes an upgraded M6800 microprocessor unit (MPU) with upward-source and object-code compatibility. Execution times of key instructions have MCU can function as a monolithic microcontroller or can be expanded to a 64K byte address space. It is TTL compatible and requires one - 5-volt power supply. On-chip resources include 2048 bytes of ROM, 128 bytes of RAM, a serial communications interface (SCI), parallel | O, and a three-func- tion programmable timer. The MC6803 can be considered as an MC6801 operating in modes 2 or 3. An EPROM version of the MC6801, the MC68701 microcontroller, is available for systems develop: ment. The MC68701 is pin and code compatible with the MC6801 MC6803 and can be used to emu. late the MC6801 MC6803 The MC68701 is described in a separate Advanced Information @ 8 - 8 Multiply Instruction ® Serial Communications interface (SCI) 3 © Upward Source and Object Code Compatibility with the M6800 © 16.Bit Three-Function Programmable Timer © Single-Chip or Expanded Operation to 64K Byte Address Space © Bus Compatibility with the M6800 Family © 2048 Bytes of ROM (MC6801 Only) © 128 Bytes of RAM © 64 Bytes of RAM Retainable During Powerdown @ 29 Parallel |O and Two Handshake Control Lines @ Internal Clock Generator with Divide-by-Four Output © 40 to 85 C Temperature Range re] MOTOROLA MICROPROCESSOR DATA 3-92

FIGURE 1 — M6801 MICROCOMPUTER FAMILY BLOCK DIAGRAM egai g bE Sos ERE To] Expanded Multplexea meu Expanded Non: Multiplexed [ sraecne I? P97 Ar/D7 7/0 P20 Pe AG/O6 DS V0 ton rH von Pg tes P35 A5/D5 05 1/0 Pon KOS pal 2 pf te en Pa AS/DS Ds 1/0 3 pe ea P33 A3/03. D310 eT ae Px A202 D2 1/0 P31 ADL D1 0 P30 A/D DO_ V0 11) sc2 WW OSS TA] tree scl as 8 SB i 3 pay ais AT 1/0 P10 Pa Ak ABO pn Pas ANZ ABO. Por Pon e1 Pad ANZ Aa 0 4 ‘ Pia, pa AN a3 0 Pra Pa aio 2 1/0 PS pay ag Al 0 P16 Pao AB AD 0 jay Ty] 7 vec suraoyof rzsxe | [ en RAM {See Note! NOTE: No functioning ROM in MC6803 POWER CONSIDERATIONS The average chip-junction temperature, Ty, in °C can be obtained from: Ty=Tat(Pp* bya) O) where: Ta = Ambient Temperature, °C 8A = Package Thermal Resistance, Junction-to-Ambient, °C/W Pp = Pint*PporT Pint = !ecx Vcc, Watts — Chip Internal Power Pport = Port Power Dissipation, Watts — User Determined For most applications PpgRT<PinT and can be neglected. PpoRT may become significant if the device is configured to drive Darlington bases or sink LED loads. An approximate relationship between Pp and Ty (if PpoRt is neglected) is: Pp=K=(Ty+273°C) (2) Solving equations (1) and (2) for K gives: K=Pp+ (Ta +273°C) + byaPp? (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring Pp (at equilibrium) for a known Ta. Using this value of K, the values of Pp and Ty can be obtained by solving equations (1) and (2) iteratively for any value of Ta, eee | MOTOROLA MICROPROCESSOR DATA 3-93

5 Jas Tuer} This device contains circuitry to protect the

_______ Rating _ Symbol Nalwe __| Unit _j inputs against damage due to high static volt. Supply Voltage @3t0 -70| Vv ages or electric fede: however itis advised —_— oe 7a | that normal precautions be taken to avoid Input Voltage ~03t0 -70| V application of any voltage higher than max Operating Temperature Range Ta TL to TH c imum rated voltages to this high-impedance MmceaoT, MCEBO3 1070 Circuit. For proper operation it is recom Mcé801C, MC6803C —a0to + 85 mended the Vin and Vout be constrained to : the range Vg (Vin Vout) ~ Vcc. input Storage Temperature Range { Tstg | =88t0-150] C protection is enhanced by connecting un Used inputs to either Vpp oF Vss. THERMAL CHARACTERISTICS Characteristic Symbol] _Volue | Unit_| | Plastic 50 Cerdip A so | CONTROL TIMING (Vcc -5.0V = 5%, Vgg=0) char ot , ~ ‘Symbol C6801 MC6801-1 MC68B01 Unit i} ara roar ee erisue - i Min | Max | Min | Max | Min | Max Frequency of Operation eos | 10 | 05 | 125] os | 20 | Mie Crystal Frequency fxtat| 20 | 40 | 20 | 50 | 20 | 80 | MHe External Oscillator Frequency | 4f | 20 | 40 | 20 | 50 | 20 | 80 | MHz Crystal Oscillator Start Up Time te | — | 100 | — | 100 | — | 100, ms Processor Control Setup Time tecs_| 200, — | 170 | — | 110) —: ns DC ELECTRICAL CHARACTERISTICS (Vcc ~5.0 Vde =5%, Vgg =0. Ta~ TL to TH, unless otherwise noted) ~ _ Mc6801 \\ MC6801C 1 Characteristic ‘Symbol | Mceso3 Mc6803C | unit _ Min Max Min Max | i Input High Voltage RESET| Vin | Vss-40 Vec | Vss-40! Vcc vo Other Inputs Vss-2.0 | Vcc Vss~22 | Vec H i — Finns — Input Low Voltage Ailinputs! Vu | Vsg-03 | Vgg~0.8 | Vss-03 | Vss-08 | V Input Load Current Port 4) lin = 05 = | 98 1m __WVin=0t02.4V) Sct = 08 | 10 | Input Leakage Current _ lin | uA (Vin = 0 to 5.25 V) Nii, (ROW, RESET = 25 | = 50 : Hiz (OM State) Input Current | T | i | Win = 05 to 2.4V) Ports 1, 2,and3| ITs) —~ | w = 2 | A Output High Voltage | vou | Tv (ILoad- ~ 65 wA. Voc = Min}* Port 4, SC1 sc2| | Vgg~2.4 - Vgg~2.4 - | (WLoad= ~ 100 nA, Voc = Min) Other Outputs vgg-24 | — | Veg-24 | — Output Low Voltage Vou | iv | Wttoad=2.0 mA, Voc = Min) All outputs | = | Vss~05 | — | Vss-06 Darlington Drive Current (Vo ~ 1.5 V) Port 1| lon 1.0 40 0 | 50 | ma Internal Power Dissipation PINT =| 1200 = 1500 | mw , __ (Measured at Ta = TL in Steady-State Operation) i ! \\ i Input Capacitance Port3,Port4,SC1/ Cin | = — | 12.8, = 125 | pF Win 0. TA 25 C. fo = 1.0 MH) Other Inputs to = | tb Voc Standby Powerdown| Vspp | 4.0 5.25 ao | 525.) V _ Powerup| Vse. 475 | 5.25 475 525 | Standby Current Powerdown| ISBB = [eo [= a0 | mA YY *Negotiable to ~ 100 yA (for further information contact the factory) MOTOROLA MICROPROCESSOR DATA 3-94

BUS TIMING (See Notes 1 and 2) ~ if ~~ Mceeoi | Mcegoi-1 | Mc68B07 Noone Characteristics Symbol | _MC6803 MC6803-1_| MC68B03_ Unit lumber _ 7 | [Min | Mex [Min | Max] Min | Max 1 _[€yele Time 7 [eye | 10 [20 [os [20 [os | 20s ns 2 [Pulse Width, € Low PWe,_| 430 | 1000 | 360 | 1000 | 210 | 1000, ns [Pulse Width, Etow ‘3 [Pulse Width, E High PWen | 460 | 1000] 360] 1000 | 220 | 1000. ns 4 [Clock Rise and Fall Time tht = [20 ns

9 Address Hold Time TAH 20 20 | 10 a ns

12 [Non-Muxed Address Valid Time 10 &* tav_| 200 150 70 ns 17__|Read Data Setup Time - | tosn | 80 | — | 70 | — , 40 | — 7 ns [18 [Read Data Hold Time _—_ [toe [10 | [0 0 [ns [__19 [Write Data Delay Time a | toow =| 228 | — | 200120 ns 21 [Write Data Hold Time —Ptonw , 20 j= a0 [0 [ns 24 [Muxed Address Valid Time to AS Fall™ tasL___60 50 20 | ~~ ns [25 | Muxed Address Hold Time tan, | 20 | 20 | 10 | = ns [26 [Delay time, E to AS Rise" rr a ns 27__ [Pulse Width, AS High PWasn| 220 1170 10) — as 28 [Delay Time, AS to E Rise” [sen | 90 | =) 70 [fas f= ns 29 [Usable Access Time* tacc_| 695 | — | aes | — 1 270; — . ns 3 “At specified cycle time **tasp parameters listed assume external TTL clock drive with 50° ~ 5% duty cycle. Devices driven by an external TTL clock with 80%” 1°e duty eycle or which use a crystal have the following tag specifications: 100 nanoseconds minimum (1.0 MHz devices) 80 nanoseconds minimum (1.25 MHz device}, 50 nanoseconds minimum (2.0 MHz devices}. FIGURE 6 — BUS TIMING . > i — Senos _@) © ws (0) sm) ‘Non wuscat | OXRKXXX TKXX Ko - pod S Nowe -o-| Whoo XO} {TR © | © of | Fowl. Address N_ | Strobe (AS! NY ‘ NOTES. © 1 Voltage levels shown are Vi 50.5 V, V4224 V, unless otherwise specitied 2. Measurement points shown, are 08 V and 2.0 V. unless otherwise specified. 3. Usable access time is computed by 12+3-17+4 4. Memory devices should be enabled only duning € high to avoid port 3 bus contention MOTOROLA MICROPROCESSOR DATA 3-96

FIGURE 7 — CMOS LOAD FIGURE 8 — TIMING TEST LOAD PORTS 1, 2, 3, 4 Voc aL 18Ko Test Pomnt wamo61s0 Test Point ‘or Equivalent cage 30 oF Mnto7000 Tt or Equivalent C= 90 pF for P30-P37, PA40-PA7, E, SCI. SC2 = 30 pF for P10-P17, P20-P24 A= 37 KO for PAO-PA7, SCI. SC2 224 ka for P10-P17, P20-P24 24 KO for P30-P97. INTRODUCTION The MC6801 is an 8-bit monolithic microcomputer which The term “port,” by itself, refers to all of the hardware ‘can be configured to function in a wide variety of applica- associated with the port. When the port is used as a “data tions. The facility which provides this extraordinary flexibility port” or “I/O port,” itis controlled by the port data direction is its ability to be hardware programmed into eight different fegister and the programmer has direct access to the port ‘operating modes. The operating mode controls the con: pins using the port data register. Port pins are labeled as Pi) figuration of 18 of the 40 MCU pins, available on-chip where i identifies one of four ports and | indicates the par- resources, memory map, location (internal or external) of in- ticular bit. terrupt vectors, and type of external bus. The configuration The microprocessor unit (MPU) is an enhanced MC6800 of the remaining 22 pins is not dependent on the operating MPU with additional capabilities and greater throughout. Itis, mode. upward source and object code compatible with the Twenty-nine pins are organized as three 8-bit ports and MC6800. The programming model is depicted in Figure 9, ‘one 5-bit port. Each port consists of at least a data register where accumulator D is a concatenation of accumulators A and a write-only data direction register. The data direction and B. A list of new operations added to the M6800 instruc register is used to define whether corresponding bits in the tion set are shown in Table 1 data register are configured as an input (clear) or output The MC6803 can be considered an MC6801 that operates (set) in Modes 2 and 3 only. MOTOROLA MICROPROCESSOR DATA 3-97

? A of? 8 oI 8-Bit Accumulators A and B i o 9) CD TD PTET [e] constion cove register sccm

3 Halt Carry (From Bit 3)

The MC6801 provides eight different operating modes (0 expanded multiplexed modes. Table 2 summarizes the char through 7) and the MC6803 provides two operating modes (2 acteristics of the operating modes. and 3). The operating modes are hardware selectable and determine the device memory map, the configuration of port 3, port 4, SC1, SC2, and the physical location of the inter. MC6801 Single-Chip Modes (4, 7) rupt vectors, In the single-chip mode, the four MCU ports are con- figured as parallel input/output data ports, as shown in FUNDAMENTAL MODES Figure 10. The MCU functions as a monolithic microcom- The eight operating modes can be grouped into three fun- puter in these two modes without external address or data damental modes which refer to the type of bus it supports: buses. A maximum of 29 I/O lines and two port 3 control single chip, expanded non-multiplexed, and expanded lines are provided. Peripherals or another MCU can be inter: multiplexed. Single-chip modes include 4 and 7, expanded faced to port 3 in a loosely coupled dual processor configura- non-multiplexed mode is 5, and the remaining five modes are tion, as shown in Figure 11 MOTOROLA MICROPROCESSOR DATA 3-98

In single-chip test mode (4), the RAM responds to $XX80 bidirectional data bus and port 4 is configured initially as an through $XXFF and the ROM is removed from the internal input data port. Any combination of the eight least-signif address map. A test program must first be loaded into the cant address lines may be obtained by writing to the port 4 RAM using modes 0, 1, 2, or 6. If the MCU is reset and then data direction register. Stated alternatwely. any combination programmed into mode 4, execution will begin at ‘of AO to A7 may be provided while retaining the remainder as SXXFE:XXFF. Mode 5 can be irreversibly entered from mode input data lines. Internal pullup resistors pull the port 4 lines 4 without asserting RESET by setting bit 5 of the port 2 data high until the port is configured register. This mode is used primarily to test ports 3 and 4 in Figure 12 illustrates a typical system configuration in the the single-chip and non-multiplexed modes expanded non-multiplexed mode. The MCU interfaces MC6801 Expanded Non-Muttiplexed Mode (5) directly with M6800 Family parts and can access 256 bytes of ‘A modest amount of external memory space is provided in external address space at $100 through SIF. IOS provides the expanded non-multiplexed mode while significant on an address decode of external memory ($100-$1FF! and can chip resources are retained. Port 3 functions as an 8-bit be used as a memory-page select or chip-select line TABLE 2 — SUMMARY OF MC8801/03 OPERATING MODES [Common to all Modes Reserved Register Area Port 1 Port 2 Programmable Timer Serial Communications Interface [Single Chip Mode 7 128 bytes of RAM; 2088 bytes of ROM Port 3s a paraliel 1/0 port with two contro} lines Port 4 is a paraliet|/0 port SC1 is Input Strobe 3 (/S3)_ SC2 is Ourput Stiobe 3 (OS3) Expanded Non: Muttiplexed Mode 5 128 bytes of RAM: 2048 bytes of ROM 256 bytes of external memory space Port 3 is an &-bit data bus Pon 4 is an input port/address bus SC1 is Input/Output Select ((05) SC2 is Read/Write (8/W) Expanded Multiplexed Modes 1, 2, 3, 6° Four memory space options (G4K address space! (1) No internal RAM or ROM (Mode 3) (2) Internal RAM, no ROM (Mode 2) (3) internal RAM and ROM (Mode 1) (4) Internal RAM, ROM with partial address bus (Mode 61 Port 3 is 8 multiplexed address/ data bus Port 4 is an address bus {inputs/address in Mode 6) SCI is Address Strobe (AS) SC2 is Read/Write (R/W) Test Modes 0 ond 4 Expanded Multiplexed Test Mode 0 May be used to test RAM and ROM Single Chip and Non-Multiplexed Test Mode 4 (1) May be changed to Mode 8 without going through Reset (2) May be used to test Ports 3 and 4 as 1/0 ports * The MCBBO3 operates only in modes 2 and 3. ee MOTOROLA MICROPROCESSOR DATA 3-99

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Expanded-Multiplex Modes (0, 1, 2, 3, 6) PROGRAMMING THE MODE A 64K byte memory space is provided in the ex The operating mode is determined at RESET by the panded-multiplex modes. In each of the expanded-mul- levels asserted on P22, P21, and P20. These levels are tiplexed modes port 3 functions as a time multiplexed latched into PC2, PC1, and PCO of the program control addressidata bus with address valid on the negative register on the positive edge of RESET. The operating edge of address strobe (AS), and data valid while E is mode may be read from the port 2 data register as high. In modes 0 to 3, port 4 provides address lines AB shown below, and programming levels and timing must to A15. In mode 6, however, port 4 initially is configured be met as shown in Figure 15. A brief outline of the at RESET as an input data port. The port 4 data direction operating modes is shown in Table 3. Note that if diodes register can then be changed to provide any combi are used to program the mode, the diode forward volt nation of address lines, A8 to A15. Stated alternatively, age drop must not exceed the VMpDD minimum. any subset of A8 to A15 can be provided while retaining the remaining port 4 lines as input data lines. Internal PORT 2 DATA REGISTER pullup resistors pull the port 4 lines high until software configures the port In mode 0, the reset vector is external for the first two te 5 4 3 2 1 0 E cycles after the positive edge of RESET, and internal toy ec sone buses are connected so there must be no memory map overlap in order to avoid potential bus conflicts. Mode Ois used primarily to verify the ROM pattern and mon. Circuitry to provide the programming levels is de itor the internal data bus with the automated test equip: pendent primarily on the normal system usage of the ment. three pins. If configured as outputs, the circuit shown Only the MC6801 can operate in each of the ex in Figure 16 may be used; otherwise, three-state buffers panded-multiplexed modes. The MC6803 operates only can be used to provide isolation while programming in modes 2 and 3 the mode. Figure 13 depicts a typical configuration for the ex panded-multiplexed modes. Address strobe can be used to control a transparent D-type latch to capture ad: dresses A0-A7, as shown in Figure 14. This allows port 3 to function as a data bus when E is high. TABLE 3 — MODE SELECTION SUMMARY pa | p21 | P20 Taterupt | Bus Operating pc2_| pci _| Peco RAM | Vectors | Mode Mode 7 7 H H 1 1 p Single Chip 6 4 H L 1 ' MUX'5. 6! | Multplexed Partial Decoge 5 H L H 1 1 NMUX(5.6)] Non-Mulnplexed Partial Decode

4 H ‘ fa 12 ' i Single-Chip Test

3 L H H € e muxi4) | Multiplexed No RAM or ROW

2 L H U e e mux's! | Multiplexed RAM 1 L L H i € Muxia! | Muluplexes RAM and ROM ° ‘ L L 1 13) mux'4) | Multiplexed Test Legend NOTES, T= Internal TH) intemal RAM is addressed at $XXB0 € — External (2) Internai ROM 1s disabled MUX — Multiplexed (3) RESET vector 1s external for two cycies after RESET goes high NMUX — Non-Multiplexed (4) Addresses associated with ports 3 and 4 are considered external in modes 0. L = Logie Zero 1,2, and 3 H — Logic One (5) Addresses associated with port 3 are considered external in modes 5 and 6 (6) Port 4 default 1s user data input. address output 15 optional by writing to port 4 data direction register ‘The MC6803 operates only in modes 2 and 3 MOTOROLA MICROPROCESSOR DATA 3-101

mH __ Port 1 Mc6803 Port 3 8 Lines B/W 5 1/0 Lines Port 4 Serial 1/0 8 Lines 16-Bit Timer Address Bus Yss Vee XTAL o Pot3 8 8 Data Bus Vee Sam ers Bea | | toe a eee 00 A Port? E Vss a amr Qy cH Address/Data Ty s7atsa73 Address Ag-A7 aannn (Typical) Saeeee) Saeeene Og Og MOTOROLA MICROPROCESSOR DATA 3-102

FIGURE 17 — MCEB01/0 MEMORY MAPS (Sheet 1 of 3 cao mcosor Multiplexed Test Mode seoee Multiplexed! RAM and ROM a0 Internal Registers cooootti s001F Wh} ternal Registers External Memory Space soone 4 Z ,, internal RAM SOOFF ‘SO0FF Internal ROM Yj oe Yj seer GY sreret2l ZA} rosernat ntersupt vectors!2!| gree +1 ctrnalinterruot Vectors rere nores 1) Excludes the folowing adcresses which may be | notes used externally: $04, $05, $06. $07, and SOF. 1) Excludes the following addresses which may be 2) Addresses SFFFE and SFFFF are considered to externally 504 S00 46 S07 one Soe 2xtgnal accessed within two eyces atter'« | 2) jneinel ROM addiocoee S460 te Sherr oe not times 3) Aftor two MPU cycles, there must be no over lapping of internal and external memory spaces to avoid driving the date bus with more than one 4) This mode isthe only mode which may be used to examine the mterrupt vectors m internal ROM Using an external RESET vector MOTOROLA MICROPROCESSOR DATA 3-104

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MC6801/03 INTERRUPTS between them to prevent supplying power to Vcc during powerdown operation "Vee standby should be tied to The M6801 Family supports two types of interrupt re: ground in mode 3. quests: maskoble and non-masksble. A'nion-maskable inter rupt (NMI) is always recognized and acted upon at the com: controlled by the condition code register | bit and by in- TABLE 4 — INTERNAL REGISTER AREA Gividual enable bits. The | bit controls ll maskable inter rupts. Of the maskable interrupts, there are two types: [ROT Sort SS and IRQ2. The programmable timer and senal cormmunica a ec & in Figure 1. External devices (and 1S3) use IRO7. An IRO1 in- Port 2 Data Register 03 {All IRQ2 interrupts use hardware prioritized vectors. The Cee en Foe or tion. All interrupt vector locations are shown in Table 5. Timer Control and ‘Status Regester 38 The interrupt flowchart is depicted in Figure 18 and is Counter thigh Byte) ® oe common to every interrupt excluding reset. During interrupt Counter (Low Sytel on servicing the program counter, index register, A accumu Output Compare Register ‘High Byte 0B lator, 8 accumulator, and condition code register are pushed Surpat Compare Regater Low Bie = to the stack. The | bit is set to inhibit maskable interrupts and Input Capture Hegister High siytel bo @ vector is fetched corresponding to the current highest put Capture Regster ‘Low Byte! oe priority interrupt. The vector is transferred to the program Port 3 Control and Stotus Register ore RESET timing are illustrated in Figures 19 and 20 Transnmt/Recerve Control and Status Register n FUNCTIONAL PIN DESCRIPTIONS RAN Control Register = Vcc AND Vss * External addresses - modes C. 1, 2, 3.5, and 6, carrot be 32. Voc and Vsg provide power to a large portion of the cessed in mode 5 ino {08 MCU. The power supply should provide +5 volts (+5%) to oo cutest aoeosoet ns moows 0.12 ana? dissipation (including Vcc standby), will not exceed Pp miliwatts Vcc STANDBY TABLE 5 — MCU INTERRUPT VECTOR LOCATIONS. through $BF) of the RAM and the STBY PWR and RAME [mse [ise [interrupt state, In the powerup state, the power supply should provide +5 volts (+5%) and must reach Vsp volts before RESET reaches 4.0 volts. During powerdown, Vcc standby must re- STBY PWR bit While in powerdown operation, the standby current will not exceed |: — wertiow! itis typical to power bsth VCC and VCC standby from the same source during normal operation. 4 diode must be used TRO? Interrupt eee] MOTOROLA MICROPROCESSOR DATA 3-107

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XTAL AND EXTAL SC1 and SC2 In Single-Chip Mode These two input pins interface either a crystal or TTL In single-chip mode, SC1 and SC2 are configured as an compatible clock to the MCU internal clock generator. input and output, respectively, and both function as port 3 Divide-by-four circuitry is included which allows use of control lines. SC1 functions as IS3 and can be used to indr- the inexpensive 3.58 MHz or 4.4336 MHz Color Burst TV cate that port 3 input data is ready or output data has been crystals. A 20 pF capacitor should be tied from each accepted. Three options associated with IS3 are controlled crystal pin to ground to ensure reliable startup and op- by port 3 control and status register and are discussed in the eration. Alternatively, EXTAL may be driven by an ex- PORT 3 (P30-P37). If unused, 1S3 can remain unconnected ternal TTL-compatible clock at 4fo with a duty cycle of SC2 is configured as OS3 and can be used to strobe out 50% ( + 5%) with XTAL connected to ground put data or acknowledge input data It is controlled by out: The internal oscillator is designed to interface with an AT- put strobe select (OSS) in the port 3 control and status cut quartz crystal resonator operated in parallel resonance register. The strobe is generated by a read (OSS = 0) or write mode in the frequency range specified for fx TAL. The {OSS = 1) to the port 3 data register. O53 timing 1s shown in crystal should be mounted as close as possible to the input Figure 4 pins to minimize output distortion and startup stabilization time.* The MCU is compatible with most commercially ‘SC1 and SC2 In Expanded Non-Multiplexed Mode available crystals. Nominal crystal parameters are shown in In the expanded non-muitiplexed mode, both SC1 and Figure 21 SC2 are configured as outputs. SC1 functions as input/ out a put select (TOS) and is asserted only when $0100 through RESET S01FF is sensed on the internal address bus. This input is used to reset the internal state of the device SC2 is configured as read/write and 1s used to control the and provide an orderly startup procedure. During powerup. direction of data bus transfers. An MPU read is enabled RESET must be held below 0.8 volts: (1) at least tRc after when read/write and € are high Vc reaches 4.75 volts in order to provide sufficient time tor thé clock generator to stabilize, and (2) until Vcc standby SC1 and SC2 In Expanded-Multiplexed Mode reaches 4.75 volts. RESET must be held iow at least three E In the expanded-multiplexed mode, both SC1 and SC2 are cycles if asserted during powerup operation configured as outputs. SC1 functions as address strobe and can be used to demultiplex the eight least-significant ad E (ENABLE) dresses and the data bus. A latch controlled by address This is an output clock used primarily for bus synchroniza strobe captures address on the negative edge, as shown in tion. It is TTL compatible and is the slightly skewed divide Figure 14 by-four result of the device input clock frequency. it will ‘SCZ is configured as read/write and is used to contro! the drive one Schottky TTL load and 90 pF, and all data given in direction of data bus transfers. An MPU read 1s enabled cycles is referenced to this clock unless otherwise noted when read/write and E are high NON-MASKABLE INTERRUPT (NMI) PORT 1 (P10-P17) ‘An NMI negative edge requests an MCU interrupt se- Port 1 is a mode independent 8 bit I/O port wath each line quence, but the current instruction will be completed before an input or output as defined by the port 1 data direction it responds to the request. The MCU will then begin an inter register. The TTL compatible three-state output buffers can Tupt Sequence. Finally, a vector is fetched from SFFFC and drive one Schottky TTL load and 30 pF, Darlington tran SFFFD, transferred to the program counter and instruction sistors, or CMOS devices using external pullup resistors. It is execution is resumed. NMI typically requires a 33 k@ configured as a data input port by RESET. Unused lines can (nominal) resistor to Vcc. There is no internal NMI pullup remain unconnected resistor. NMI must be held low for at least one E cycle to be recognized under all conditions. PORT 2 (P20-P24) MASKABLE INTERRUPT REQUEST 1 (JRO?) PORT 2 DATA REGISTER TRO? is a (evel-sensitive input which can be used to re- ‘quest an interrupt sequence. The MPU will complete the cur 7 6 6 4 32 4 0 rent instruction before it responds to the request. If the inter MCU will begin an interrupt sequence. A vector is fetched from $FFF8 and $FFF9, transferred to the program counter, Port 2 is a mode-independent, 5-bit, multi-purpose 1/0 and instruction execution is resumed. port. The voltage levels present on P20, P21, and P22 on the TRO? typically requires an external 3.3 k@ (nominal) rising edge of RESET determine the operating mode of the resistor to VCC for wire-OR applications. IROT has no inter: MCU. The entire port is then configured as a data input port nal pullup resistor. The port 2 lines can be selectively configured as data output lines by setting the appropriate bits in the port 2 data direc. STROBE CONTROL 1 AND 2 (SC1 AND SC2) tion register. The port 2 data register is used to move data The function of SC1 and SC2 depends on the operating through the port. However, if P21 is configured as an out mode. SC1 is configured as an output in all modes except put, it will be tied to the timer output compare function and single-chip mode, whereas SC2 is always an output. SC1 cannot be used to provide output from the port 2 data and SC2 can drive one Schottky load and 90 pF register. «Devices made with masks subsequent to MSG, MD, and T5P incorporate an advanced clock with improved startup charactenstics, ry MOTOROLA MICROPROCESSOR DATA 3-110

FIGURE 21 — M6201 FAMILY OSCILLATOR CHARACTERISTICS (2) Nominal Recommended Crystal Parameters, Nominal Crystal Parameters* As on 500 30-50 0 30-50 @ 20-40 @ os 35 pF 65 pF 46 pF 46 pF 46 pF cr 0.015 pF 0.025 pF ©} 001.002 pF | 001.002 pF | 001-002 oF NOTE: These are representative AT-cut crystal parameters only. Crystals of other types of cut may also be used 2 3 2 $$] es 3 co RS C= 20 pF (typical) Co Equivalent Cireut NoTE TTL-compatibie oscillators may be obtained from Motorola Component Products ‘Attn: Data Clock Sales 2853 N. Edgington St Franklin Park, IL 60131 Tel: 312-481-1000 Telex: 433-0067 (b) Oscillator Stabilization Time (tac) a75V Vee ee RESET | a oav ‘RC Oscillator Stabilization Time, tac MOTOROLA MICROPROCESSOR DATA 3-111

Port 2 can also be used to provide an interface for the Port 3 In Expanded Non-Multiplexed Mode serial communications interface and the timer input edge Port 3 is configured as a bidirectional data bus (07-00) in function. These configurations are described in PROGRAM- the expanded non-multiplexed mode. The direction of data reer isene and SERIAL COMMUNICATIONS INTER: transfers is controlled by read/write {SC2) Data 15 clocked . by € (enable! The port 2 high-impedance TTL-compatible output buffers are capable of driving one Schottky TTL load and 30 pF, or Port 3 In Expanded-Multipiexed Mode levices using external pullup resistors Port 3s configured as a time multiplexed address (AO: A7) 3 \\d data bus (07-00) in the expanded-multiplexed modes PORT 3 (P30-P37) on Port 2 con be vontiguted as an 1/0 port, a bidvect where address strobe (AS! can be used to demuttiplex the "3 can be configured as an I/O port, a bidirectiona two buses. Port 315 held in a high-impedance state between B-tit deta bus, ofa multohexed addresa/ cate bus depending valid. address and data to prevent bus conficts impedance output buffers can drive one Schottky TTL load PORT 4 (P40-P47) nd 90 pF. Unused lines can remain unconnected 279 0 pI Sed lines can rema Port 4 is configured as an 8-bit | O port, as address out Port 3 In Single-Chip Mod puts, or as data inputs depending on the operating mode ° ° na % x oO, am th 7 : Port 4 can drive one Schottky TTL load and 90 pF and is the ort 3 is an & bi Port in the single-chip mode, with nly pert with internal pullup resistors. Unused ine nn each line configured by the port 3 data direction register ee erscenected este! seginescan'e There are also two lines, IS3 and OS3, which can be used to controi port 3 data transfers Port 4 In Single-Chip Mode Three port 3 options are controlled by the port 3 control and status register and are available only in single-chip In single-chip mode, port 4 functions as an B-bit | O port 3 mode’ (1) port 3 input data can be latched using 183 as a with each line configured by the port 4 data direction control signal, (2) O53 can be generated by either an MPU register lnternal pellup resistors allow the port to directly food of welts to the port date vegister, and i an IGN in interface with CMOS at volt levels. External pullup resistors terrupt can be enabled by an [S3 negative edge Port 3 latch fo more than S volts, however, cannot be used timing is shown in Figure 5 9 3 Port 4 In Expanded Non-Multiplexed Mode Port 4 is configured from reset as an 8-bit put port PORT 3 CONTROL AND STATUS REGISTER where the port 4 data direction register can be written to pro 7 6 6 4 3 2 1 0 vide any or all of eight address lines, AO to A7. internal s pullup resistors pull the lines high until the port 4 data direc: is3 finan] x Joss|taen} x | x | x | sooor tion register 1s configured Fisg [enabie| lenabi Port 4 In Expanded-Multiplexed Mode Bit 0-2 Not used In all expanded-multiplexed modes except mode 6, port 4 ain 3 LATCH ENABLE. This bit controls the functions as half of the address bus and provides AB to A15 input lateh for port3. I set, input data in mode 6, the port is configured from reset as an 8-bit islatched by an 183 negative edge. The parallel input port, where the port 4 data direction register latch is transparent after a read of the can be written to provide any or all of upper address lines AB port 3 data register, LATCH ENABLE to AIS. Internat pullup resistors pull the lines high unti the fe cleared dunng reset port 4 data direction register 1s configured, where bit 0 con Bia OSS (Output Strobe Select) This bit ols AB determines whether OS3 will be RESIDENT MEMORY generated by 21686 or wnte of the port The MC6801 provides 2048 bytes of on-chip ROM and 128 ata register. When clear, the tobe bytes of on-chip RAM generates by a write, OSS is cleared pin and is maintainable during Vcc powerdown, This stand. 1g reset by portion of the RAM consists of 64 bytes located from $80 ans Not used through $8F Bit 6 1S31RQ1 ENABLE. When set. an ROT Power must be supplied to VCC standby if the internal interrupt will be enabled whenever 1S3 RAM is to be used regardless of whether standby power FLAG is set; when clear, the interrupt operation is anticipated is inhibited. This bit 1s cleared during The RAM is controlled by the RAM contro! register reset Bit 7 1S3 FLAG. This read-only status bit 1s RAM CONTROL REGISTER ($14) set by an IS3 negate edge. It 1s The RAM control register includes two bits which can be cleared by a read of the port 3 contro! used to contro! RAM accesses and determine the adequacy and status register (with IS3 FLAG set! of the standby power source during powerdown operation followed by a read or write to the port It is intended that RAME be cleared and STBY PWR be set 3 data register or during reset as part of a powerdown procedure. MOTOROLA MICROPROCESSOR DATA 3-112

RAM CONTROL REGISTER standby RAM is not valid. This bit can 7 6 5 4 3 2 1 0 be set only by software and is not af- fected during reset stey|rame| x | x | x | x [x | x ected during rese! PWR PROGRAMMABLE TIMER Bit 0-5 Not used. Bit 6 RAME RAM Enable. This read/write bit can The programmabie timer can be used to perform input be used to remove the entire RAM waveform measurements while independently generating an from the internal memory map. RAME output waveform. Pulse widths can vary from several micro: is set (enabled) during reset provided seconds to many seconds. A block diagram of the timer is standby power is available on the posi shown in Figure 22 tive edge of RESET. if RAME is clear, any access to a RAM address is exter COUNTER (09:08) nal. If RAME is set and not in moce 3. The key timer element 1s 2 16-bit free-running counter the RAM is included in the internal which is incremented by € (enable). Its cleared during reset map and is read-only with one exception’ a write to the counter Bit7 STBY PWR = Standby Power. This bit is a 1$08) will preset it to $FFF8 This feature, intended ‘or read/write status bit which, when testing, can disturb serial operations because the counter ‘once set, remains set as long as Voc provides the SCI internal bit rate clock TOF 1s set whenever standby remains above Vsgp (mini the counter contains all ones mum. As long as this bit is set follow ing a period of standby operation, the OUTPUT COMPARE REGISTER ($0B:0C) standby power supply has adequately The output compare register is a 16-bit read. wnite register preserved the data in the standby sed to control an output waveform or provide an arbitrary RAM. If this bit is cleared during a timeout flag_ It is compared with the free-running counter on period of standby operation, it ind each E cycle. When a match occurs, OCF is set and OLVL Is cates that Vcc standby had fallen to a clocked to an output level register If port 2, bit 1, 1s con level sufficiently below Vsag (mini figured as an output, OLVL will appear at P21 and the output mum) to suspect that data in the compare register and OLVL can then be changed for the next FIGURE 22 — BLOCK DIAGRAM OF PROGRAMMABLE TIMER, ice NACBBO17 MC6BOS internal Bus 708-0 308.08 500 0€ ourpur Compare | [ Free Running | | Input Capture Fiegster 16-8 Counter Register ea eSies o re — Register 3 "2 “UOOU ve wy ‘es c-b- Output Compare Pulse ! Outout input Level Edge Bn} Bo Pon 2 Pon 2 MOTOROLA MICROPROCESSOR DATA 3-113

‘compare. The function is inhibited for one cycle after a write Bit 8 TOF Timer Overflow Flag. TOF is set when to its high byte (SOB) to ensure a valid compare. The output the counter contains all ones. It is compare register is set to SFFFF at RESET cleared by reading the TCSR (with TOF set) then reading the counter high INPUT CAPTURE REGISTER (60D:0€) byte (308), or during reset The input capture register is a 16-bit read-only register ait 6 OCF Output Compare Flag. OCF is set used to store the free-running counter when a "proper" in- when the output compare register ut transition occurs as defined by IEDG. Port 2, bit 0 should matches the free-running counter. Its be configured as an input, but the edge detect circuit always Cleared by reading the TCSR (with senses P20 even when configured as an output. An input OCF set) and then writing to the out capture can occur independently of ICF: the register always put compare register (S0B or SOC), or Contains the most current value. Counter transfer is in Guring reset hibited, however, between accesses of a double byte MPU ait 7 ICE Input Capture Flag ICF 1s set ton read. The input pulse width must be at least two cycles to dicate a proper level transition, it 1s ensure an input capture under all conditions Cleared by reading the TCSR Wwith ICF set) and then the input capture register TIMER CONTROL AND STATUS REGISTER (808) high byte (SOD), or during reset The timer control and status register (TCSRI is an 8-bit register of which all bits are readable, while only bits 0-4 can be written. The three most-significant bits provide the timer SERIAL COMMUNICATIONS INTERFACE (SCI) status and indicate if © 2 proper level transition has been detected, A tull-duplex asynchronous serial communications inter @ a match has occurred between the free-running face (SCI is provided with two data formats and a variety of 3 Counter and the output compare register. and rates. The SCI transmitter and receiver are functionally in- dependent, but use the same data format and bit rate, Serial © the free-running counter has overtlowed cach ot the three boone cok ae eS Oe data formats include standard mark/space (NAZI and Bi to oft rh mee sven Soe ooetle bit *. rene phase and both provide one start bit, eight data bits, and one and is controlled by an individual enable bit in the TCSR stop bit. “Baud” and “bit rate” are used synonymously in the following description TIMER CONTROL AND STATUS REGISTER (TCSR) © folowing aescnes 7 6 5 4 3 2 7 WAKE-UP FEATURE $0008 In a typical serial loop multi-processor configuration, the software protocol will usually identify the addres. see(s) at the beginning of the message. In order to per- Bit 0 OLVL Output Level. OLVL is clocked to the mit uninterested MPU’s to ignore the remainder of the output level register by @ successful message, a wake-up feature is included whereby all fur- output compare and will appear at P21 ther SCI receiver flag (and interrupt) processing can be if bit 1 of the port 2 data direction inhibited until its data line goes idle. An SCI receiver is register is set. itis cleared during reset re-enabled by an idle string of eleven consecutive ones Bit 1 €IDG Input Edge. IEDG is cleared during or during reset. Software must provide for the required reset and controls which level trenet idle string between consecutive messages and prevent tion will trigger a counter transfer to it within messages. the input capture register PROGRAMMABLE OPTIONS IEDG=0 Transfer on a negatwve-edge The following features of the SCI are programmable: =| Transfer on 2 positive-edge © format: standard mark/space (NRZ) or Bi-phase Bit 2 ETO! Enable Timer_Overfiow Interrupt © clack. entemal or internat bit vate clock When set, an iRO2 interrupt is enabled © clo for a timer overtiow: when clesr, the © Baud: one of four per E clock frequency, or external interrupt is mhibited. It is cleared dur clock (x8 desired baud) ing reset © wake-up feature: enabled or disabled Bit 3 EOC! Enable Output_Compare Interrupt © interrupt requests. enabled individually for transmitter When set, an {FOZ interrupt is enabled and receiver for an output compare, when clear, © clock output internal bit rate clock enabled or disabled the interrupt is inhibited, It is cleared to P22 during reset Bit 4 E:CI Enable input Capture Interrupt. When SERIAL COMMUNICATIONS REGISTERS set, an IRQ interrupt is enabled for an The serial communications interface includes four ad- input capture, when clear, the inter dressable registers as depicted in Figure 23. It is controlled rupt is inhibited. It 1s cleared during by the rate and mode contol register and the transmit/ reset recewve control and status register. Data is transmitted and MOTOROLA MICROPROCESSOR DATA 3-114

received utilizing @ write-only transmit register and a read time and rates for three selected MCU only receive register. The shift registers are not accessible to frequencies Software. Bit 3:Bit 2 €C1:CCO Clock Control and Format Select. These two bits control the for- Rate and Mode Control Registers (RMCR) ($10) mat and select the serial clock source The rate and mode control register controls the SCI bit ICC1 is set, the DOR value for P22 is rate, format, clock source, and under certain conditions, the forced to the complement af CCO and configuration of P22. The register consists of four write-only cannot be altered until CC1 is cleared bits which are cleared during reset. The two least-significant If CC1 is cleared after having been set. bits control the bit rate of the internal clock and the remain its DOR value is unchanged. Table 7 ing two bits control the format and clock source defines the formats, clock source, and use of P22 RATE AND MODE CONTROL REGISTER (RMCR) 7 6 5 4 3 2 1 90 Hoth Ct and COD are set an extemal FTL-compantte Sco clock must be connected to P22 at eight times (BX) the 50% (+ 10%). ff CC1:CCO= 10, the internal bit rate clock 1s Bit 1:Bit 0 SS1:SS0 Speed Select. These two provided at P22 regardless of the values for TE or RE bits select the baud rate when using the internal clock. Four rates may be NOTE: The source of SCI internal bit rate clock is the timer selected which are a function of the free-running counter. An MPU write to the counter MCU input frequency. Table 6 lists bit can disturb serial operations. FIGURE 23 — SCI REGISTERS Bi? Rate and Mode Control Register Bit Transmiv/ Receive Control and Status Regste Receive Data Register [LTTit{ [Tt tJ» Port 2 Not Addressable) Fx " Clock 10 Bit Rate Bit Generator —e Not Addressable in 2 | Bit 2 LT TT] |] Tt | Transmit Data Registe MOTOROLA MICROPROCESSOR DATA 3-115

Transmit/Receive Control And Status Register RDRF and/or ORFE is set, when clear. (TRCSR) ($11) the interrupt is inhibited. RIE is cleared The transmit/receive contro! and status register controls during reset. eae neon, rd ogg nag Ens TORE dividual interrupts and monitors the status of serial opera- is set when the transmit data register is tions. All eight bits are readable while bits 0 to 4 are also transferred to the output senal shift tosh oat setae or ectten ommarely sean eceve CONTROL ano STATUS ca Re ORE REGISTER (TRCSR) register, Additional data will be ogg ROSTER THESH re ee a fowereon ne Lae [re [ie [wo] oe Bit 6 ORFE Overrun Framing Error if set, ORFE in: oraantomon oy fat OE 9 solu owwap anita ona whens oon an ese, eeu op ie ine. ens we nar tae ome 2 wpa rene oc rae ee ts Srey even gnc ai eae set if the line is idle. boundaries of the bit stream are not ; ead Sack ase cite te na pa 938 ron in rt Seebeeepce Stn om remain set if TE is subsequently RDAF ts set, then an overrun has oc: 3 Cleared. When TE is changed from curred; otherwise a framing error has clear to set, the transmitter 1s con been detected. Data is not transferred sto, 8 motes aie os se es een oe mtn ey nan cleared during reset a framing error 1s transterred to the ee nes oar ays ate! an TROD interrupt is enabled when quent data transfer blocked until the seat ra goon oe nna et Tones cone, gen ee ae eae come REE Jerome mira cane "ee week reer Eni hyo a 7 oy Se eae a Tg platelet ser Sn fea FOR, sures cates ae An Scrat am wat during reset register It is cleared by reading the siete tent eat an FES Set" ee an IRQ2 interrupt is enabled when receive data register, or during reset sno sco rsa nave sores [Mo | 24876 Wie] a0 Maz “area wre [erage MH 2288 MHz | Pt HRSE Ease, |S 77°] 28 | mses | cases | ermes i | nm | Siaceeets | sprees, | siweaoees [2 | cst | iets | erent | ae Ee {an ~ omar Ano ae ume CONOL cP as eae Parle eos of me fir moe feet] oe sc=SrTSh wan ba oan we mn a Gn MOTOROLA MICROPROCESSOR DATA 3-116

SERIAL OPERATIONS ‘executable instruction is sufficient to identify the instruction The SCI ts initialized by writing control bytes first to the and the addressing mode. The hexadecimal equivalents of rate and mode control register and then to the transmit/ the binary codes, which result from the translation of the 82 receive control and status register. When TE is set, the out: instructions in all valid modes of addressing, are shown in put of the transmit serial shift register is connected to P24 Table 8. There are 220 valid machine codes, 34 unassigned and serial output is initiated by transmitting a 9-bit preamble codes, and 2 codes reserved for test purposes of ones. At this point one of two situations exist. 1) if the transmit PROGRAMMING MODEL data register is empty (TDRE=1), a continuous string of A programming model for the MC6801/03 is shown in ones will be sent indicating an idle line, or 2) if a byte has Figure 10. Accumulator A can be concatenated with ac been written to the transmit-data register (TORE =O), it will cumulator B and jointly referred to as accumulator D where be transferred to the output serial shift register (synchroniz. Ais the most-significant byte. Any operation which modifies ed with the bit rate clock), TORE will be set, and transmis, the double accumulator wil also modify accumulator A sion will begin and/or B. Other registers are defined as follows The start bit (0), eight data bits (beginning with bit 0) and a Program Counter — The program counter is a 16-bit stop bit (1), will be transmitted. If TORE is still set when the register which always points to the next instruction next byte transfer should oxcur, ones wid be sent uni more Stack Pointer — The stack pointer is a 16-bit register ala & provided. In Biphase format, the output toggles @ which contains the address of the next available location in a the start of each bit and at half pit time when 9 one 's sent pushdown/pullup (LIFO) queue. The stack resides in ran leceive operation is controlled by RE which configures PZ dom access memory at a location defined by the program as an input and enables the receiver. SC! data formats are i oe lustrated in Figure 24. i Index Register — The index register is a 16-bit register INSTRUCTION SET which can be used to store data or provide an address for the indexed mode of addressing The MC6801/03 is upward source and object code com Accumulators — The MPU contains two 8:bit accumu patible with the MC6800. Execution times of key instructions lators, A and B, which are used to store operands and results have been reduced and several new instructions have been from the arithmetic logic unit (ALU). They can also be con added, including a hardware multiply. A list of new opera catenated and referrad to as the D (double) accumulator tions added to the MC6800 instruction set is shown in Table Condition Code Registers - The condition code register 1 indicates the results of an instruction and includes the In addition, two new special opcodes, 4E and SE, are pro following five condition bits. negative (NI, zer9 (2), overtiow vided for test purposes These opcodes force the program (V}, carey/ borrow from MSB iC). and halt carry from bit 3 counter to increment like a 16-bit counter, causing address, (H) These bits are testable by the conditional branch in. lines used in the expanded modes to increment unti! the structions Bit 4 1s the interrupt mask «| bit) and inhibits ait device is reset. These opcodes have no mnemonics. maskable interrupts when set. The two unused oits, 86 and The coding of the first (or only) byte corresponding to an 87, are read as ones FIGURE 24 — SCI DATA FORMATS Output Clock NRZ : Format : Br Phase Format , Br BG, ide Ste gg gg SIP Data 01001101 ($40) MOTOROLA MICROPROCESSOR DATA 3-117

ADDRESSING MODES Extended Addressing — The second and third bytes of the instruction contain the absolute address of the Six addressing modes can be used to reference mem- operand. These are three byte instructions. ory. Asummary of addressing modes for all instructions Indexed Addressing — The unsigned offset contained is present in Tables 9 through 12, where execution times in the second byte of the instruction is added with carry are provided in E cycles. Instruction execution times are to the index register and used to reference memory summarized in Table 13. With an input frequency of 4 without changing the index register. These are two byte Mbz, E cycles are equivalent to microseconds. A cycle: instructions. by-cycle description of bus activity for each instruction Inherent Addressing — The operand(s) are registers is provided in Table 14 and a description of selected and no memory reference is required. These are single instructions is shown in Figure 25. byte instructions. Immediate Addressing — The operand or “immediate Relative Addressing — Relative addressing is used byte(s)" is contained in the following byte(s) of the in ‘only for branch instructions. If the branch condition is struction where the number of bytes matches the size true, the program counter is overwritten with the sum of the register. These are two or three byte instructions. of a signed single byte displacement in the second byte Direct Addressing — The least-significant byte of the of the instruction and the current program counter. This operand address is contained in the second byte of the provides a branch range of | 126 to - 129 bytes from instruction and the most-significant byte is assumed to the first byte of the instruction. These are two byte in be $00. Direct addressing allows the user to access $00 structions. through $FF using two byte instructions and execution time is reduced by eliminating the additional memory access. In most applications, the 256-byte area is re- served for frequently referenced data TABLE 8 — CPU INSTRUCTION MAP

2 Bis sa |r saa 21 [sa 00a 2 ]ar sts etno § 3 ]e2 a00e 63

eve 32 }sc Nee ro sua om 3 2 ]ca snow 2 2 |e cone 43 NOTES 1 Adressing Moses INHER Ionerent INDXDsindexed_MMED mimmmecate ReLefelsive.EXTNDmextended OIF Direct MOTOROLA MICROPROCESSOR DATA 3-118

TABLES — INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS [ ier | cone | mace Ssdacnc oo Lee! a SEES Ponte pene fool #6] [F[oo]-[ a] oal-[F Ton] [4] aimee Spoaten [ati tt eztv] [Tors rome Rognie——f crx ocfefafe|s} tate sfactefa] |] power Teel TTT IT] [Deserentinaecteone Tort | fT ttt Ppp yt feb poe [| [Deseren sick Pone Pes TTT PPT pp pee] [Treement nee Rapier we OE fof ee | [Tacrement Stack Pomer | NST TTT TT TT TT aifstifiseerse TT Te Te] [icsdiners egal a peete a fets fa fepsy PT eam [isos suck Ponte Tos ea adae [a fo aefs] afeetefa[ |p [usr =n fete te | [Sere noortenste Pore Pt fore aferts tapes pp Poe | [Sie Sea Pani Ps reaper apertets| | fa fT | [oer Rep seo Peme Pos OT sper [Sic P= noes Reon PST pe] a TO cc od eee Pee PTT TPP es serces PEP EE y) Par Le= Leeieiis| = ae Merry Operations Expression cee CE or a SD CC [ere spear ety Tt eee [roca os] [aor] [ote late falefs pT enwecee TT] = eee ete pee [rove eel afoef> Peele} pele fs | [fees [faba rosea ates] Plate tetep py [too TT ro fawoatee(etetee [fo Taedey 2 feefe te [ae TT EN 9 ND DC SA Ta Rane pe re rabere bate = etry lascat TT PT ee GO 40 - GE a CUCHEMLLSEA [Samer boone se COO CEE eT] ‘Shift Right, Arthmenc: [ase TTT TT fee te fey TT = CRCHERERESER peers Bec ee Cinttno-8 et A rere] ae SZ 63 sn NC tt fare fod etoet le teb tele p tp ee [como Rename Tee? PT PP) Py Pee Cie Pee Cr epee ee am Compare SS CA ED ES ES CO eC re RRB eee ee Ta Comoran So a CS DC 7 nO [ewes DOE TCs] a MOTOROLA MICROPROCESSOR DATA 3-119

TABLE 10 — ACCUMULATOR AND MEMORY INSTRUCTIONS (Sheet 2 of 2) Condon Codes Ces: Heleteleis| — Mae Memory Operations [on] -] #] 1m T=] Expression [BecinAgua a Poa PT PT foal af Toa onan sumac fe Pe] TTT 1] Decrement i A A dd pec teal aa

2 Od HE |

Exchse OR [eonalasl 2] 2[ sa] st apaal af oteatatst TP taem—a tft taf] pees SEE HEsr SER EERE ess; ERA Treen a NN brea bee tana | weal TT Or pscfa fee | oad Recent [Loaalasl =[o[ [a] 2 [aol afespeta] TP wa eonNoR [eoaslosf [fool 3 2feel a] af rela [at |_| Iw=e SEES Lond Doobie [woo fecf sf sfod-«fatectstafrcfs psf [Iwao ff] tt Tat] Toca Sat Lat Ree eter = EEontit peal PT telat 9 oto — EE Re eta YF meet Se reOritirey Sh Rant Lope! One = [fetal ir : pseat TP eet) e-CO-8 Eee SO & Prat beset ee [ese Pw profil fa TT 7s Comeioment Wega! Puc TTT pele to potetst TT Yow=m Tre] fecal TT teeta Jooraa TT] feesel TTT Cy feel foo 8 eT] [Ne Sbernon nor Py fore p feos re PY inchave OF foraafeal 2[aloat sy faalaoleafatay TT Jasw—a Te Tt Tat] pee GSE Ess bree ste} ss $a Puan Data fesmal PT ts fase TY] SY Put Data 9 Yr TE a DY Rovate Lett feo t TT TT | Tele fepefesy CT | — feTetrittttT] fowl Te @ 4-8 eet frost TT fete] e EET Rotate Ran Leon TTT tetetepefetay Try = aCHEREAEIER| feos TP er! &- OE er a eee CCHRSES EAE | Svewect Aecomiatr TE swa Tt tofah noma si] Subtract wath Cary peste br Ces tent ee et Hee Ss [secefcrl af a foals afefetatrefe[at TT Tecmo ETT] Store Accumuitors SZ A 8 jsrael TT fos tatetstatete fst TT fame fe Pett tt ate {sro [ [fools 2 feols {afrols fs{ [| Jo—mme te fe tt aT] Sober [susaleofe [feof s [2 [aol « [> feofe st TP [awa] fe PTT] tsusefcol2[ fools afeofs]atrofe fat TT Jew—s fe rte | [Swoussi Doutie fsueofasf«fafea[s (2 fasfe [2fasfefat [| Jo-wmnr=o Jt rr] Transter Accunator Be ple ae tte nr Tost Ze 6 Wins Fee EEE EP ee peepee fisral TP TT PT poole Ti Jao [TT Tafa bse TET TTT TTT TT bop feo fdr] MOTOROLA MICROPROCESSOR DATA 3-120

TABLE 11 — JUMP AND BRANCH INSTRUCTIONS Celene lela Inherent [sTs}3T2q To] [Ol -[ #[ Oe] -T# [oo] -] # [oo] -T foo] -T #] Brench Test PAT TNT z{vTc} cc CL DY [anche ee Oe OO rere [rarer con Gew Pee tab Perr yee EE [prerchitewrysea pes Py sbre C e fee [Bronckit ze eee BP PI [Bonet e200 eee eb eves | [Bioncnitsze0 peer Pte PCP ee [Branchwrigner fem] || jatstet fT] Pi] yt lero yey Te) [BroncnitranerorSone Pers PT tate fee a A a A [Bron rtowe orSene pas Pep Ppp fers ee TDD HD [Bron Not Eamras —Penet Teste ee [Bionc rovetew cer Pave PT tephetp P| pee Te) [Bron roverow ser fae Pt apt Cp Ppt bE EE [erononirus ent tt ete py fee [eranch To Somasinw Pose PT feoferet TTT rt | occa] 3 a Oa ec [ure To Someuine ——_——Fose ols} a] fool Pe mofo st TT] ooo [Ro Opener wor PE eee) [rein From omaat TT pepo REM ENE EN EA [Retin rom Subrumme PAST EET TPT LT fp ms Jee seem onetorsione fe fe fo To fe fe [Sativa inert owe PT el EEE EE [wor Forint war OEE Tee EE ETE EI TABLE 12 — CONDITION CODE REGISTER MANIPULATION INSTRUCTIONS | eneanr | Inherent [sTaTsT2Tifo [rane [ Op | —[ F | Bootean operation [ATI Tw Tz {vc a SR [Gear iverapt Mask a oe eo) [ciear Overiow cv owe [ov a] [set Ceny sec fo ec I [Serinvemaptwak se for ff ST) [Set Overton stv fos fo Pa | [acoumslaor ACR SSS te fw fe coe [Get Acoumomiora SS tea for fe ccm ] LEGEND CONDITION CODE SYMBOLS + Boolean Inclusive OR T Aftected we Complement ot MOTOROLA MICROPROCESSOR DATA 3-121

TABLE 19 ~ INSTRUCTION EXECUTION TIMES IN E CYCLES ma [el ele wx ° ° fe ax |e] el} s Swe | 8 3 | acc | 2] 3] & ise | 8 sls ao | 2 | 3] & ton | 8 a4 sooo | | s | sé wo | 3 5 | 5 ao | 2] 3] 8 tes | 3 ss ASB : : cst 5 ASR $ : ‘sto a eee : 3 tsp 2 acs : 3 sro 5 eco : 3 wut fa ce : 3 wes 2 act : 3 oP 2 oi 3 ona 3 ans 3 rn | 3 ar 3 rox | 8 ae 5 mo | 8 ato 3 rox | 8 ais 3 moo | 8 aur 3 non | 8 aM 3 mn os 15 ene 3 as | 8 | 8 : ore 3 sa | 3 | 8 > aha 3 sec || 2 | 3 : ann 3 se | S| e 3 ash é se of 2 ave F sv | 3 2 vs : Ta sta] > cea : t] sto | 8 : ce : 2) 3 ss | 8 : cu : a] 3 sx | 8 : ctr 3 p] 8 sue | 3 : ey : 2] 8 sua | : ce ‘ o| 3 sm |e mH com a a8 7 crx sis jefe tar i Baa ele je}? ea 2 bee efs [es |: Tea 2 es cfs fe]: st 2 oex e}e je]: Sx 3 fon s[f dele mS 3 ine e|e jefe wa 3 INS ele le|$ I F557 3-122

SUMMARY OF CYCLE-BY-CYCLE OPERATION Table 14 provides a detailed description of the information per instruction. In general, instructions with the same ad- present on the address bus, data bus, and the read/write dressing mode and number of cycles execute in the same (R/W) line during each cycle of each instruction manner. Exceptions are indicated in the table The information is useful in comparing actual with ex. Note that during MPU reads of internal locations, the pected results during debug of both software and hardware resultant value will not appear on the external data bus ex- a the program is executed. The information is categorized in cept in mode 0. “High order” byte refers to the most- groups according to addressing mode and number of cycles significant byte of a 16-bit value TABLE 14 — CYCLE-BY-CYCLE OPERATION (Sheet 1 of 5) ‘Address Mode end Cycle RW) Instructions ’ Address Bus Line IMMEDIATE ‘ADC FOR Z [1 [Oncode Aadiess 1 Opcede ADD LOA 2 | Opcode Address +1 1 | Operand Data ‘AND ORA BIT sBc MP SUB LOS 3 | 1 Opcode Adaress 1 | Opcode Lox 2 | Opcode Address + 1 + | Operand Data (High Order Byte! Loo 3. | Opcode Address-+2 1_ | Operand Data ‘Low Order Byte) 3 CPX T | Opcode Aaaress T | Opeode suBD 2 | Opcode Address +1 1 | Operand Data (High Order Byte ADDD 3 | Opcode Address +2 + | Operand Data (Low Order Byte) 4 | Address Bus FFFF 1 | Low Byte of Restart Vector DIRECT ADC EOR 3 | 1 | Opcode Address Opcode ADD LA 2 | Opcode Address +1 Address of Operand AND ORA 3. | Address of Operand Operand Data BIT SBC cup SUB STA 3 [1 [Opcode Address 1] Opeoe 2 | Opcode Address +1 1 | Destination Address 3__| Destination Address. ©_| Data trom Accumulator TS T_[Opcode Address Opeode Lox 2 | Opcode Address +1 Address of Operand LoD 3. | Address of Operand Operand Data (High Order Byte 4_| operand Address+ 1 Operand Data (Low Order Byte) STs 1 | Opcode Address T | Opeode sTx 2. | Opcode Address +1 1 | Address of Operand sTD 3. | Address of Operand © | Register Data (High Order Byte) 4 _| Address of Operand +1 0_| Register Data (Low Order Byte) Px & | 1 | Opcode Adaress Opcode SUBD 2. | Opcode Address +1 Address of Operand ‘DOD 3. | Operand Address Operand Data (High Order Byte) 4 | Operand Address+1 Operand Data (Low Order Byte! 5_| Address Bus FFFF Low Byte of Restart Vector ISA 5 |? |Opcode Address 1 | Opcode 2 | Opcode Address +1 1 | irrelevant Data 3. | Subroutine Address 1 | First Subroutine Opcode 4 | Stack Pointer 0 | Retun Address (Low Order Byte? 8_| Stack Pomter-1 0 | Return Address (High Order Byte! MOTOROLA MICROPROCESSOR DATA 3-123

Address Mode and RW] MOTOROLA MICROPROCESSOR DATA 3-124

TABLE 14 — CYCLE-BY-CYCLE OPERATION (Sheet 3 of 5) ‘Address Mode and Cycle RW Instructions xycles| Address Bus Line INDEXED. IMP 1 ]Opcode Address: ‘Opcode| 2 | Opcode Address + 1 Oftser 3 | Address Bus FFFF Low Byte of Restart Vector ADC EOR T | Opcode Address Opcode ADD LDA 2 | Opcode Address +1 Offset AND ORA 3 | Adaress Bus FFFF Low Byte of Restart Vector BIT SBC 4 | Index Register Plus Ottset Operand Data CMP. SUB STA 1 | Opcode Address 1 | Opcode 2 | Opcode Address +1 1 | Offser 3 | Address Bus FFF 1 | Low Byte of Restart Vector 4_| Index Register Pius Offset 0 | Operand Data ToS 1 | Opcode Address 1 | Oncode Lox 2 | Opcode Address +1 1 | oftset Loo 3. | Address Bus FFF 1 | Cow Byte of Restart Vector 4 | index Register Plus Offset + | Operand Data (High Order Byter 5 | index Register Plus Ottset+1 | 1 | Operand Data ‘Low Order Bytel STS 1 | Opcode Address 1 | Opcode SIX 2 | Opcode Address + 1 1 | Oftser STD 3 | Address Bus FFF 1 | Low Byte of Restart Vector 4 | Index Register Plus Ottset 0} Operand Data (High Order Byte! 5 | index Register Plus Oftset+ 1 | 0 | Operand Data ‘Low Order Bytel ASL isR T | Opcode Address T | Opcode ASR NEG 2 | Opcode Address +1 1 | ofser CLR ROL 3. | Address Bus FFFF 1 | Cow Byte of Restart Vector coM ROR 4 | Index Register Plus Offset + | Current Operang Data DEC TsT* 5 | Address Bus FFF 1 | Low Byte of Restart Vecto: INC. 6 _| index Register Plus Otfset 0_| New Operand Data CPX 1 | Opcode Address 1 [Oncode suBD 2 | Opcode Address +1 1 | ottser ADDD 3 | Address Bus FFF 1 | Low Byte of Restart Vector 4 | Index Register+ Offset 1 | Operand Data (High Order Syte! 5 | index Ragister + Offset +1 1 | Operand Data iLow Order Byte! 6_| Address Bus FFFF Low Byte of Restart Vector TSR 1] Opcode Address T_| Opcode 2 | Opcode Address +1 1 | Oftser 3. | Address Bus FFFF 1 | Low Byte of Restart Vector 4 | index Register + Otfset 1 | First Subroutine Opcoae 5. | Stack Pomnter © | Return Address (Low Order Byte 6 _| Stack Pointer— 1 0 | Return Adaress (High Order Byte) *TST does not pertorm the write cycle during the sixth cycle. The sixth cycle 1S another address bus= SFFFF MOTOROLA MICROPROCESSOR DATA 3-125

TABLE 14 — CYCLE-BY-CYCLE OPERATION (Sheet 4 of 5) ‘Address Mode and Cycle] RW Instructions lcyctes| Address Bus Line INHERENT ABA DAA SEC] 2 | 1 | Opcode Address Dpcode ASL GEC SEI 2 | Opcode Address +1 Opcode of Next Instruction ASR INC SEV CBA sR Taal cL NEG Tap cu oP Tal CLR ROL TPA clv ROR TST COM SBA BX 3 | 1 | Opcode Address Dacode 2 | Opcode Address +1 Irrelevant Data 3_| Address Bus FFF Low Byte of Restart Vector ASLO 1 [Opcode Aagress Opcode UsRO 2. | Opcode Addtess +1 irrelevant Data 3_ | Address Bus FFF Low Byte of Restart Vector DES 3] 1 | Opcode Address ‘Opcoae INS 2 | Opcode Address +1 Opcode of Next instruction 3__| Previous Stack Pointer Contents relevant Data TNX 3 | 1 | Opcode Adaress Oocode vex 2 | Opcode Address +1 Opcode of Next Instruction 3 | Address Bus FFF Low Byte of Restart Vector PSHA 3 | 1 | Opcode adress Opcode PSHB 2. | Opcode Address +1 Opcoae of Next tastruction 3_| Stack Pointer Accumulator Data Tx 3 [1 [Opcode Adaress Opcode 2 | Opcode Address + 1 Opcode of Next Instruction 3_| Stack Porter Irrelevant Data 1S 3] 1 | Opcode Address ‘Opeode 2 | Opcode Address + 1 Opcode of Next Instruction 3. | Address Bus FFF Low Byte of Restart Vector PULA 1] Opcode Adaress 7} Opcode pute 2 | Opcode Address +! 1 | Opcode of Next Instruction 3. | Stack Pointer 1 | irretevant Oata 4_| Stack Pointer+1 1__| Operand Data trom Stack PanK 1] Opcode Aaaress 1 | Opcode 2 | Opcode Address +1 1 | \\erelevant ata 3. | Stack Pointer 0 | Index Register (Low Order Byte) 4_| Stack Pointer~ 1 0_| Index Register (High Order Bytel PUIX S| 1 [Opcode Aaaress 1 | Opeode 2. | Opcode Address +1 + | iretevant Data 3 | Stack Pointer 1 | inelevant Oata 4 | Stack Pointers 1 1 | index Register (High Order Byte) 5 _| Stack Pointer +2 1_| Index Register (Low Order Byte) RTS 3 | 1 | opcode Address Opcode 2 | Oncode Agaress +1 lueeievant Data 3 | Stack Pointer lrretevant Data 4 | Stack Pointer 1 Address of Next Instruction (High Order Byte! 5_| Stack Pointer +2 Adress of Next Instruction (Low Order Byte) War 1 | Opcode Aadress T | Opcoae 2 | Ovcode Adaress +1 1 | Opcode ot Next Instruction 3. | Stack Pointer © | Retumn Address ‘Low Order Byte! 4 | Stack Pointer - 1 0 | Retin Address (righ Order Byte! 5 | Stack Pointer ~2 0 | index Register (Low Order Byte! 6 | Stack Pointe: ~ 3 0 | index Register (High Order Bvte 7 | Stack Pointer ~ 4 0 | Contents of Accumulator & 8 | Stack Pointer © | Contents of Accumwtator 8 2 | Stack Pointer—6 0 | Contents of Conciton Code Register MOTOROLA MICROPROCESSOR DATA 3-126

‘Address Mode and ‘Cycte| RW) a Laie a — = as, ae 2 |e ee eve 1 [see tr om tie tr tr on : | senses tS fo : is te tS fo 1 |e bast sb So a | Moe bast bo ne Aes bt ot = 2 ie ae 2 | Opcode Address +1 1 Irrelevant Data 2 | | a 2 | tere iL ters | Sr ra conn : |= tone | Sa one ot ¢ | rns : | Seiten Aten 2 | tone | ere ar g | icant {| eina torso ae 3 [serene | Ratn Roomba = offs e? | 3 1 ee 1 | ee ieee 2 |e 2 | set oe ote : | fone s |S At 3 | rones @ | eo oa é |e one s | ie toa on Sa 2 seen : | Siew ge one 2 | aca ae 3 [sense | ema fires, |! iti mon ou i [se ieentra | | Reese on oe BCC BHT BNE BLO 3 1 Opcode Address’ Opcode —— ee ca ses a om be] ” |: [Si een CO vc co Bo set Be me — _ See, To : |S Sen Sa ac 2 er | | | eekstiome t | Sesion crow ina : Se wr Ses ie Dr MOTOROLA MICROPROCESSOR DATA 3-127

$ 27 az g/8 al elelsteRelelel of (Sletsteelell sla]s 3) eleleleyeiZ/Z) 2] jsteleysieilz| {2 )els Slalalelel= l= sjeyslelel=l=| sle]2/2 Sy] ale EE 3°] 5) BUPPTS TTR Hass gsse5 a ~ BEERRSS geeeae6 —— o oo "i g|< € § el. 8 ag az of el <

2 EB A § a 8

2 & = = 3 2 é 2 = = e Fi al ES | | z f & a ale a Ele a e l= a Bees 8 aT 7S was F 4 4 i <> A _ i ee — 2 §l= elf slel-lel slelelale glels BEE cle) l2Z/2 giglel2| elelelelz €lg}z sla FEE Sy") ae S/5/-/3) Sie |z/c)s) a} ]= ale ciig 2 ° ° 3 z gage? ee ee ee es MOTOROLA MICROPROCESSOR DATA 3-128

ORDERING INFORMATION

The following information is required when ordering Verification Media ‘a custom MCU. The information may be transmitted to All original pattern media, EPROMSs or floppy disks, Motorola using the following media: are filed for contractual purposes and are not returned. MDOS, disk file ‘A computer listing of the ROM code will be generated PC-DOS disk fite (360K) and returned along with a listing verification form. The EPROM(s) 2516, 2716, MC68701 listing should be thoroughly checked and the verifica- To initiate a ROM pattern for the MCU, it is necessary tion form completed, signed, and returned to Motorola to first contact the local field service office, sales person, ‘The signed verification form constitutes the contractual or a Motorola representative. agreement for the creation of the customer mask. To aid in the verification process, Motorola will program FLEXIBLE DISKS customer supplied blank EPROM(s} or DOS disks from Several types of flexible disks (MDOS™ or PC-DOS the data file used to create the custom mask. disk file) may be submitted for pattern generation. They should be programmed with the customer's program, ROM Verification Units (RVUs) using positive logic sense for address and data. The Ten MCUs containing the customer's ROM pattern diskette should be clearly labeled with the customer's will be sent for program verification. These units will name, date, project or product name, and the filename have been made using the custom mask, but are for the containing the pattern. ‘ purpose of ROM verification only. For expediency, the In addition to the program pattern, a file containing MCUs are unmarked, packaged in ceramic, and tested the program source code listing can be included. This with five volts at room temperature. These RVUs are data will be kept confidential and used to expedite the free with the minimum order quantity, but are not pro. process in case of any difficulty with the pattern file. duction parts. These RVUs are not guaranteed by Mo- torol lity Assuran MDOS Disk File ‘orola Quality Assurance 3 MDOS is Motorola's Disk Operating System available Ordering Information on the EXORciser* development system. The disk me- The following table provides generic information per- dia submitted must be a single-sided, single-density, 8- taining to the package type and temperature for the inch MDOS compatible floppy diskette. The diskette must MC6801/MC6803. This MCU device is available only in contain the minimum set of MOOS system files in ad- the 40-pin dual-in-line (DIP) package in the Cerdip and dition to the pattern file. Plastic packages The .LO output of the M6801 cross assembler should be furnished. In addition, the file must be produced DOS a trademark of Motorola inc. using the ROLLOUT command, so that it contains the MS-DOS ig a trademark of Microsoft, Inc. absolute image of the M6801 memory. It is necessary EXORciser is a registered trademark of Motorola Inc. to include the entire memory image of both program IBM is a registered trademark of International Business and data space. All unused bytes, including those in the Machines Corporation, user space, must be set in logic zero. PC-DOS Disk File GENERIC INFORMATION PC-DOS is the BM" Personal Computer Disk Oper- _ ating System. Disk media submitted must be standard Frequency | Temperature Cerdip Package | Plastic Package | density (360K), double-sided 5-1/4 inch compatible floppy (MHz) "| (Degrees C) | _(S Suffix) AP Suffix) diskette. The diskette must contain the object file code 10 | oto70 McBs0181 Mceso1rT in Motorola's S-record format. The S-record format is | to 40 to -85| Mcé801cs1 | MC6B01CP1 a character-based object file format generated by M6801 125 01070 Mces01s1.1 | MCeao1P1.1 cross assemblers and linkers on IBM PC style machines. | 125 40 to 35] Mcego1cs-1 | Mcés01cP-1 | 20 01070 | MCeBBOIS1 | MCésBOIPI EPROMS +0 0t0 70 Mces03s_ | | MC6803P A single 2K EPROM is necessary to contain the entire j LS | 40 to a5) Mceaoscs | Mcseuse. MC6801 program. The EPROM is programmed with the | 128 | —a0'to -85| MCBB03CS-1 | MCBBO3CP.1 customer program using positive logic sense for ad: 20 01070 MC68B035. | _MC68B03P dress and data. All unused bytes, including the user's a space, must be set to zero. If the MC6801 MCU ROM pattern is submitted on a single 2516 or 2716 type EPROM, memory map ad- dressing is one-for-one. The data space ROM runs from EPROM address $000 to $7FF. If an MC68701 is used, the ROM map runs from $F800 to SFFFF For shipment to Motoro!a, EPROMSs should be placed in a conductive IC carrier and packed securely. Styro foam is not acceptable for shipment eee eee eee e eee eee eee MOTOROLA MICROPROCESSOR DATA 3-129

TRO Gs 36f] P31 RESET G6 36 ps2 vote shes P1720 2p Yeo MOTOROLA MICROPROCESSOR DATA 3-130