MC6802CP

MC6802 MOTOROLA | Alldatasheet

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= SEMICONDUCTOR SE TECHNICAL DATA Mc6a02 Microprocessor With Clock and Optional RAM The MC6802 is a monolithic 8-bit microprocessor that contains all the registers and accumulators of the present MC6800 plus an interna! clock oscillator and driver on the same chip. In addition, the MC6802 has 128 bytes of on-board RAM located at hex addresses $0000 to $007F. The first 32 bytes of RAM, at hex addresses $0000 to $001F, may be retained in a low power mode by utilizing VCC standby; thus, facilitating memory retention during a power-down situation. The MC6802 is completely software compatible with the MC6800 as well as the entire M6800 family of parts. Hence, the MC6802 is expandable to 64K words. @ = On-Chip Clock Circuit © 1288 Bit On-Chip RAM @ 32 Bytes of RAM are Retainable © Software-Compatible with the MC6800 © Expandable to 64K Words © Standard TTL-Compatible Inputs and Outputs © BBit Word Size 16-Bit Memory Addressing © Interrupt Capability TYPICAL MICROCOMPUTER Voc Veo Voc vec § s e § Counter/ | Mcse4s Z TO — ‘This block diagram shows a typical cost ef ‘RESET cso vMaA FATT 7 center of the microcomputer system and is 2k Bytes ROM eo RE a ROM combination chip. It is not intended AD-AI0, S cre : Contrt f =} 2F2 C8 Kame dawns xtac MOTOROLA MICROPROCESSOR DATA 3-256

[Supp Vonage —SS—*d (Mc «| =0 10 +76] Vv | err eae: owover tis advised Supply Voltage Nec _|-0.3t0 +7.0| V ages or electric fields; however, itis advised that normal precautions be taken to avoid ‘Operating Temperature Range Ta ry application of any voltage higher than max- ‘Mc6802, MC6S0A02, MCG80B02 Oto +70 imum rated voltages to this high-impedance MC8802C, MC680A02C i 40 to +85 circuit. Reliability of operation is enhanced it aeite patton. eatervee orvecl Storage Temperature Range Tstq_|-85 to +150] °C voltage level (0.g., either Vsg or Vcc) THERMAL CHARACTERISTICS [characte Symbol Value [Unit | ‘Average Thermal Resistance (Junction to Ambient) Plastic Onn 100 |rcw POWER CONSIDERATIONS. The average chip-junction temperature, Ty, in °C can be obtained from. 3 Ty=Tat (Ppa) a where: Ta = Ambient Temperature, °C Ja = Package Thermal Resistance, Junction-to-Ambient, “C'W Po = Pint*Prort . Pint = !ccxVcc, Watts — Chip Internal Power Pport = Port Power Dissipation, Watts — User Determined For most applications Ppot<PinT and can be neglected. PrORT may become significant if the device is configured to drive Darlington bases or sink LED loads. ‘An approximate relationship between Pp and Ty (if PpoRT is neglected) is: Pp=K= (Ty +273°C) (2) Solving equations (1) and (2) for K gives: K=Po + (Tq + 273°C) + 8Ja-PD? (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring Pp (at equilibrium) for a known Ta. Using this value of K, the values of Pp and Ty can be obtained by solving equations (1) and (2) iteratively for any value of Ta MOTOROLA MICROPROCESSOR DATA 3-257

DC ELECTRICAL CHARACTERISTICS (Vpp = +5.0 Vdc + 0.5%, Vgg =0, Ta=0 to 70°C, unless otherwise noted) Characteristic [| Symboi [min [typ [Mex | unit | input High Voltage Logie, EXTAL Veg +20 Veco | ¥ Reset Vest4o vee Input Low Vohage Toole EXTAL RESET Vss-03] = |Veg+08 input Leakage Current (Vin =0 to 6.25 V, Vpp=mex) Logie! tin [= [10 [2s | na | ‘Output High Voltage VoH v (Load = ~208 vA, Voc=min) _ 00.07 * Veg +24 (ied = — 145 WA, Vec= min) AO-A15, RAW, VMA, E Vegt24 (Coad = — 100 WA, Vee = min) BA veg+24 Output Low Voltage (ILoad= 1.6 mA, Vec= min) [vor [=| = [vssroal | Internal Power Dissipation (Measured at Ta=0°C) Pr | — | ovo | 10 | w | Vop Standby Power Down| Vsep v PowerUp| Vee Standby Current 1588 [=| ao | ma | Capacitance # 0-07) Cin Win"0, TA~25°C, f= 1.0 MHz) Logic inputs, EXTAL AO-A1S, RW. VMA| —_Cout “In power-down mode, maximum power dissipation is less than 42 mW. 3 #Capacitances are periodically sampled rather than 100% tested. CONTROL TIMING (Vcc-50V =5%, Vsg=0, TA=TL to TH). unless otherwise noted) — a Frequency of Operation | ft [or | v0 [or | is [on | 20 [mee | Crystal Frequency txrar | 10 [40 [10 [60 | 10 [a0 | mee | External Oscillator Frequency [ato | oa | 40 | 04 | 60 | 04 | a0 | Mix | Crystal Oscillator Start Up Time: [we | woo | — [100 [= | too | — [ms | Processor Controls (HALT, MR, RE, RESET, ING NAM) Processor Control Setup Time tres Processor Control Rise and Fall Time eee (Does Not Apply to RESET) tet MOTOROLA MICROPROCESSOR DATA 3-258

BUS TIMING CHARACTERISTICS =| eee eel Symbot Unit Nu [Min [Max | Min [ Max | Min | Max | [1 |eveetime eye | 10 [| 10 [Loser | v0 | 08 | 10 | os |__2 [Pulse width & Low | Pwer | 450 | s000 | "280 | s000 | 210 | 5000 | ns [3 [Pulse width, € Hiah | Pwen | 450 | 9500 |” 280 | 9700 | 220 | 700 | ns | | 4 [Clock Rise and Fall Time [inte | — [as [= | as | — [2s J os | 9 [Address Hold Timer [wu | 20 | — | 2 | — | 2 | = [ns Non-Muxed Address Valid Time toE (see Note 4) | tavi | 160 | — so | — | as |__17__ [Read Data Setup Time i [16 | Read Data Hold Time tna | 10 | — | io | — [to | = | ns [19 [Write Data Delay Time woow | — | 225 | — | v0 | — | 160 | ns [21 [Write Data Hold Time* Ttonw | 30 | — | 20 | — [20 | — | ns | {__29 [Usable Access Time (soe Note 4) [race [sas [ = [335 | — | 238 | — [ns Address and data hold times are periodically tested rather than 100% tested ~ Se © BV, Address ASA SV oases 000000: [XX >_> | i © i rE © -O-> ++ ead Data MPU Reas Data Non Nunes Wate Dato Ot NOTES: 1. Voltage levels shown aro Vi<0.4 V, Vi1>2.4 V, unless otherwise specified. 2; Measurement points shown are 0.8 V and 20 V, unless otherwise noted. 3: Usable access time is computed by: 12 3=4~17 3 Itrograme are not executed fromm on-board RAM, TAV1 applies. If programs are to be stored and executed from on-board RAM TAV2 applies. For normal date storage in the on-board RAM, this extended delay does not apply. Programs cannot be Sxecuted frorm on-board RAM when using A and B parts (MC6BA02, MCSBB02), On-board RAM can be used for data storage with all parts 5. Rilelecthical and control characteristics are referenced from: T =0°C minimum and TH = 70°C maximum: MOTOROLA MICROPROCESSOR DATA 3-259

Mcé6802 GURE® — BUS THING TEST LOAD arias eter S007, € vnapre00 = 16.5 k® for AO-Al5, B/W, and VMA or Equiv. GURE 4 — TYPICAL DATA BUS OUTPUT DELAY FGURE 5 — TYPICAL READ/WAITE, vida AND venue CAACITI Lon ADDRESS OUTPUT DLLAY wenn CAPAEITNE LOADING [rae reo e ft = 300 [ Pye 2 an ft _ 3 ea steer 4 ao Ze z i ees oa soeseeeon of FIGURE 6 — EXPANDED BLOCK DIAGRAM 1 [cannes FE RAM Erabie (Tor ‘Non-Maskable Interrupt (Sit eck Counter 4 Counter extat contro Read/Wote (RW) a H i a a a a MOTOROLA MICROPROCESSOR DATA 3-260

FIGURE 8 — SAVING THE STATUS OF THE MICROPROCESSOR IN THE STACK 1 ‘ 1! a mot | met | SP = Stack Pointer o-7[ fe —— se EC = Condition Cones (Alto called the Processor Status Byte! m-e[ cc | Acca Accumulator & m-s[acce | IKH = index Register, Higher Order 8 Bits m-4{ acca | IXU= Index Register, Lower Order 8 Bits m3 PCL - Program Counter, Lower Order 8 Bits m2 ™ 3] at map ren | E ™ sr Pree | mea a] ome? EH 1 1 l ' 1 1 : 1 1 ' eatore ater

3 MPU SIGNAL DESCRIPTION

Proper operation of the MPU requires that certain contro! tion, bus available will be at a high state, valid memory ad- and timing signals be provided to accomplish specific tunc- dress will be at @ low state. The address bus will display the tions and that other signal lines be monitored to determine address of the next instruction. the state of the processor. These control and timing signals To ensure single instruction operation, transition of are similar to those of the MC6800 except that TSC, DBE, the HALT line must occur tpcs before the rising edge 1, 42 input, and two unused pins have been eliminated, of E and the HALT line must go high for one clock cycle. and the following signal and timing lines have been added HALT should be tied high if not used. This is good RAM Enable (RE) engineering design practice in general and necessary to en- Crystal Connections EXTAL and XTAL ‘sure proper operation of the part. Memory Ready (MR) _ Vc Standby READ/WRITE (R/W) Enable 62 Output (E) This TTL-compatibie output signals the peripherals and The following is a summary of the MPU signals memory devices whether the MPU is in a read (high) or write (low) state. The normal standby state of this signal is read ADDRESS BUS (A0-A15) (high). When the processor is halted, it will be in the read Sixteen pins are used for the address bus. The outputs are state. This output is capable of driving one standard TTL capable of driving one standard TTL load and 90 pF. These load and 90 pF lines do not have three-state capability. VALID MEMORY ADDRESS (VMA) DATA BUS (00-07) This output indicates to peripheral devices that there is @ Eight pins are used for the data bus. It is bidirectionel, valid address on the address bus. In normal operation, this transferring data to and from the memory and peripheral signal should be utilized for enabling peripheral interfaces devices. !t also has three-state output buffers capable of ‘Such as the PIA and ACIA. This signal is not three-state. One driving one standard TTL load and 130 pF standard TTL load and 90 pF may be directly driven by this Data bus will be in the output mode when the internal active high signal. RAM is accessed and RE will be high. This prohibits external data entering the MPU. It should be noted that the internal BUS AVAILABLE (BA) — The bus available signal will nor- RAM is fully decoded from $0000 to $007F. External RAM at mally be in the low state: when activated, it will go to the ‘$0000 to $007F must be disabled when internal RAM is ac- high state indicating that the microprocessor has stopped cessed. and that the address bus is available (but not in a three-state condition). This will occur if the HALT line is in the low state HAUT or the processor is in the WAIT state as a result of the execu: When this input is in the low state, all activity in the tion of a WAIT instruction. At such time, all three-state out: machine will be halted. This input is level sensitive. In the ut drivers will go to their off-state and other outputs to their FAUT mode, the machine will stop at the end of an instruc normally inactive level. The processor is removed from the MOTOROLA MICROPROCESSOR DATA 3-262

WAIT state by the occurrence of a maskable (mask bit |= 0) tion of a routine to initialize the processor from its reset con. or nonmaskable interrupt. This output is capable of driving dition. All the higher order address ines will be forced high ‘one standard TTL load and 30 pF. For the restart, the last two ($FFFE, $FFFF) locations in __ memory will be used to load the program that is addressed INTERRUPT REQUEST (IRQ) by the program counter. During the restart routine, the inter- ‘A low level on this input requests that an interrupt se- rupt mask bit is set and must be reset before the MPU can be quence be generated within the machine. The processor will interrupted by RO. Power-up and reset timing and power. wait untit it completes the current instruction that is being down sequences are shown in Figutes 9 and 10, respectively excuted before it recognizes the request. At that time, if the RESET, when brought low, must be held low at least three. interrupt mask bit m the condition code register is not set clock cycles. This allows adequate time to respond internally the machine will begin an interrupt sequence. The index to the reset. This is independent of the trc power-up reset register. program counter. accumulators, and condition that is required code register are stored away on the stack. Next the MPU When RESET 1s released it must go through the low-to will respond to the interrupt request by setting the interrupt high threshold without bouncing, oscillating, or otherwise mask bit high so that no further interrupts may ocour. At the causing an erroneous reset {less than three clock cycies) end of the cycle, a 16-bit vectoring address which is located This may cause improper MPU operation until the next valid in-memory locations $FFFB and SFFF9 is loaded which reset causes the MPU to branch to an interrupt routine in memory ‘The FATT line must be in the high state for interrupts 10 NON-MASKABLE INTERRUPT (NMI) be serviced. Interrupts willbe latched internally while HALT 'A low-going edge on this input requests that a non is tow maskable interrupt sequence be generated within the pro A nominal 3 kf pullup resstor to Vcc should be used for Gessor. As with the interrupt request signal, the processor wire-OR and optimum control of interrupts. IAG may be tied wil complete the current instruction that is being executed the condition code register has no effect on NMI RESET “The index register. program counter, accumulators, ang This input is used to reset and start the MPU from 2 condition code registers are stored away on the stack. At the power-down condition, resulting from a power failure or an tend of the cycle, 3 16-bit vectoring address which is located Initial start-up of the processor When this ine 1s low, the in. memory locations $FFFC and $FFFD is loaded causing the MPU is inactive and the information in the registers will be MPU to branch to an interrupt service routine in memory lost. if 8 high level is detected on the input, this will signa’ ‘A nominal 3 kX pullup resistor to VCC should be used for the MPU to begin the restart sequence, This wilt start execu wire-OR and optimum control of interrupts. NMi may be tied FIGURE 9 — POWER-UP AND RESET TIMING 475V Veco ‘ SLL LLL RESET Vi Opts 1 \\See Note Below) he RESET a ee Opto 2 'See F-gute 10 tor Power-down Conaition! eer Pct NOTE. if option 1 is choson, AESET and RE pins can be ted together MOTOROLA MICROPROCESSOR DATA 3-263

directly to Vcc if not used FIGURE 10 — POWER-DOWN SEQUENCE Inputs TRO and NMi are hardware interrupt lines that are @ low E following the completion of an instruction. ee INTERRUPT VECTORS os [ms is | ia Vin Cyel Machine No No No oo —- No, MOTOROLA MICROPROCESSOR DATA 3-264

MCcé6802 FIGURE 12 — CRYSTAL SPECIFICATIONS ee a | 8 ee da [a wre | a09F [200 | cure vt 7 ~ ~ Crystal Loading ra WN Pa [(—[awme [some [comme [aoa] [a[ a [a | wa [aoa] [ext asp “ear oor [oF | [apse [sax Pm Pe] 20 mm max G™rcley B) OHO 87 2 GZ HU al E Signal is Wired Apart from 38 Pin e ; x“ and 39 Pin a MOTOROLA MICROPROCESSOR DATA 3-265

RAM ENABLE {RE} MPU INSTRUCTION SET . A TTL-compatible RAM enable input controls the on- - : - ; chip RAM of the MC6802, When placed in the high state, Tha instruction set has 72 different instructions. Included the on-chip memory is anabled to respond a figh MPU are binary and decimal arithmetic, logical, shift, rotate, load, controls, in the low state, RAM is disabled. This pin may Sloe, Conditional of unconditional branch, interrupt and also be utilized to disable reading and ‘writing the on- stack manipulation instructions (Tables 2 through 6}. The in- chip RAM during a powerdown ion. RAM Enable Struction sar if the same as that for the MCBBOO. must be low three cycles before Vcc goes below 4.75 Vv curing powerdown, RE should be tied to the correct high or low state if not used. MPU A ESSING M EXTAL AND XTAL v ODES These inputs are used for the intemal oscillator that may - There are seven address modes that can be used by 8 pro- be crystal controlled. These connections ar for a parallel gearnmer, with tha addressing mode a function af both the resonant fundamental crystal Isee Figure 12). (AT-cur.) A type of instruction and the coding within the inatrction. & divide-by-four circuit has been added so a 4 MHz crystal may summary of the addressing modes for a particular instruchon be used in lieu of a 1 MHz crystal for a more cost-effective ‘can be found » Table 7 along with the assocwied instruction system. An example of the crystal circu layout i shown in @mecution time that is gwen in machine cycles. With a bus Figures 13. Pin 39 may be driven extemally by a TTL input frequency of 1 MHz, thesa times would be microseconds. signal four times the required E clock frequency. Pin 34 is to be grounded. ‘ sirsctl ACCUMULATOR [ACCX) ADDRESSING An network is not directly usable as a frequency In accumulator only addressing, sither accumulator A oF source on ping 3and 39. An AIC network type TTL or CMOS accumulat T meprueti oscillator will work well as long 43 the TTL or CMOS output Nor B ts specified. These are one byte instructions. 3 drives the on-chip oscifistor. IMMEDIATE ADDRESSING thesvane orks are not mended tc be used in place of In immediate addressing, the operand is contained in the 7 second f the instruction except LOS and LOX which fan external clock is used, it may not be halted for eve the aperand i ihe second and third byeas af ine in Ub ha aah ctl fe ba i struction. The MPU addresses this location when it ferchas ra e internat RAM. and requires the external clock to the immediate instruction for execution. These are iwe- or in aon. thres-byte instructions. MEMORY READY (MR} DIRECT ADDRESSING. MR is a TTL-compatible input signal comtrofling the stret- in direct addressing, the address of the operand is contain- ching of E. Use of MR requires syechronization with tha 4xf, ed in the second byte of the instruction. Direct addressing sagnal, as shown in Figure 14. When MIR ip pigh, E wall be in allows the user to directly addiness the lowest 256 bytes in the normal operation. When MIR is low, E will be stretched in- machine, Le. locations zero through 256. Enhanced axecu- tegral numbers of half penods, thus allowing interface to thon times are achiewsd by Storing data in these locations, tn slew mamoareas. Memory Aeady timing is shove in Figure 15. most configurations, it should be 4 random-access memory. MA should be tied high (connected directly to Vioc! it not These are Teor byte instructors. used. This is necessary to ensure proper operation of ihe part A maximum stretch is teye. EXTENDED ADDRESSING In extended addressing, the ackires contained i the 5e- ENABLE (E) cond byte of the instruction is used as the higher aight bits of This pin supplies the clock forthe MPU and the rest of the the address of the operand, The third byte of tha instruction system, This & a singl+phase, TTL-compatitia clock. This ip used as the lower eight bits of the address for the operand. lock may be conditioned by a memory read signal. This This is an absolute address in memory. These are three-byte equivalent to é2 on the MCBSO0. This outpu: & capable of instructions. ‘driving one standard TTL toed and 130 pF. INDEXED ADDRESSING Voc STANDBY In indewed addressing, the address contained in the se- This pin supplies the dc voltage to the first 32 bytes. ‘cond byte of the instruction is added to the index registers of RAM as wall as the RAM Enable (RE} control logic. lowest sight bits in the MPL. The carry is then added to the Thus, retention of data in this portion of the RAM on a higher order eight bits of the index register. This result is power-up, power-down, or standby condition is guar- then used to address momory. The modified address is held anteed. Maximum current drain at ¥Vgp maximum is in @ temporary address register so there i8 no change ta the 'SaB- index ragisier. These are two-byte instrections. MOTOROLA MICROPROCESSOR DATA 3-267

IMPLIED ADDRESSING byte of the instruction is added to the program counter's In the iniplied addressing mode, the inatrectian gives the lowest aight bits plus two. The carry or borrow is then added address (1.€., Stack painter, index regisner, etc.}. These are to the hagh eight bits, This albows the user to address data oné-byte instructions. within arange of ~ 126to + 129 bytes of the present instruc: tion, These ane twoebyie insinwctions, RELATIVE ADDRESSING In relative addressing, the address cortained in the second TABLE 2 — MICROPROCESSOR INSTRUCTION SET -- ALPHABETIC SEQUENCE ABA Add Accurnutators: cn ‘Gear Pu Pull ata ADC Aad with Garry CL Glaar Cheertion ROL Pca ADD Aad CMP = Compare ate vet AND Logical And com Ga ROR Rotate Paght ASL Anihmetic Shit Left CPX Compare Index Register ATL Return from Wterrut ‘ASA ‘Anthmetc Snet Fight AA chu ATS Feetymn from Sigbecutene cc Branch # Camry Clear DEC Gecumat Aa SBA Subtract Accurulaiors BCS Branch if Carry Set DES —Decrament Stack Pomwor «= Sec Sulsiract wom Carry BEQ Branch # Equal to Zero DEX Decrement index Regier «SEC S81 Carry BGE — Branch # Greater or Equal Zero SEI Set interrupt Mash Bat Branch # Greater thar 2 FOR = Exchsive OR SEV Set Overflow BH Branch # Higher INC: Increnren STA Store Accumwlatce BIT Bil Test 1S ——sIncromnent Stack Pointer STS Stone Stack Register BLE Branch # Loss or Equal INX —rcrement index Fingstor = “SX = ‘Siore inclex legistor LS Branch d Lower or Same SUB Subtact ELT Grarcha Lees fan cero 4MP hampe SWI Sodtware internupt BM Branch # Minus JER amp to Suorouting TAB Transler Accumulators BNE Branch # Not Equal to Zero LOA Load Accurmulator TAP Transtar Accummlabors io Condvion Code Flag. BPL Branch # Plus: Los Load Stack Ponber TRA Tranater Accumulators. BRA Branch Always Lox Load Indien Flegeatar TPA Transfer Condition Code Peg to Accumulator BSA Branch io Subroumne LSA Logical Shi Flight TST Teal evC Branch # Overfiow Clear NEG Megate TSX Transter Stack Pointer to Inchax Plegister avs Branch # Overflow Sat NOP Ne Ch TS Tranter index Fliegeter to Stack Panter CBA = Compare Accumutators, WAI Wai for Interrupt cic Clea Cary OPA inclusive OF Accumulator cu ‘Clear internapt Mask PSH Push Data MOTOROLA MICROPROCESSOR DATA 2-268

TABLE 3 — ACCUMULATOR AND MEMORY INSTRUCTIONS ASOMERAG ORES SPSL Ean GAT MSTICGPARTION Comb COBE eee [wean J ainect | wits [eaves [ mmuue | ‘1mm spire to fefa]a[apoTe] orenanans wacwoun [er - -[er - =[ee ~ =]ar -_ [or | ri semen OOH EG ata wore [oe 2 2/t i van afar e 3 awa TePELELe aDba mor ff/oB Ss t/t & PP eR # cow -E ayeyrpryp tee Add Arent ana wav [almen sfelefe| sys ag art Coy acca [mg afm a aja es alae a Perrrars ifele|e[e|e er er ame 8 tfa}syelele me anna fw oz afm 3 gars la ao owes ele |s|s]a)= ance foe aloe a rire s Pl ee ao wt slab |-|ale Ba tee ia faz cho a glass Flas a 3 aw left |s]a]e ot oP Thos a epee a pes ak ee whet: [:jale tun cue oi oghwor os nee alela}ay ala cin wor td mee sleln|sl aha cure worm ofa}n]s| eh tance rr er ee aw ele}: |i} s] | twee [ce 2 tfor ot afi ko apm ad aw ede] 3] Cagle tej cm wattle wyerspipids Cores TS com aooalae a aw afele| sels taan aaa |mee efe]=petals coat | hoaofa@a fel |:]ajs anew 7 nts. loor afm a ow fa}: ]: EoD omepnt neca i [wor orleans f=]: | Hee wEGe beoorpor)aon@ weleb: |: HED etm Achat naa 1871 b Cpewnne aay ae of mcm Croctey [ote]: | 2] ate HOD Feet bauer pee woe ghana acer’ ole]: |: pe nete | lee pot lene ale): |! foe Eaciaur OF copa Cs ee en age a efelt) idee eoke ca tjom ft BPE Spe a ‘aaw a elelc) iia le agemes RE wotoalm ea Meroe ele le|: fay nc fac ou lactce afelships| ick i rr re syey- [fae Load Amber cry my orfw os Flop & a]me 4 oF jue eyeysjcpaie inas [ce 2 zion a tle 5 alee a 8 fw elelitslale) hwo naga [ae 2 T)aa a tl] ak a Tua fF [aew ow vets tefeys| han baa roa | wo fe gt vse |efstalel sls rea | ren es oe eleel na Dace Pula | | Pn a ed [sles “fale fue | oan | sre ae niger islzle|stel* fause ta nat fe elm ea FY — air Areal mo.a | wt +} S- eee ale) s( Hos mae | er) ae) fBW Haute te ADR ee ee 4) — | fe: fone | | «oy |sh SSS RS isfel:: A Perry | | | eroijel & om =e ARE : anus 4 Pare eee er ee BE ar pra eee singe sineninn ' wea alee a | | - wale: aa 1 i [aoe ) | apoeimp g ahelry: aks wate! ow mE ale |2) ag: Deh mast Li rey | la 1 2] ej ” _ alelal sf: tina Jaa flat gecumop-9 lela’: fea: in | fwd bia fa alma, fa: faise Aceur saa Jar a glare cle 8 Ja alesls|ale ara toa cher boars re afe|s/cinle some sina mand iit ies 3 te syed ity! hae cea zjee 1. tp 8 RlFa a bee a@ejelrp spc: Satin wth Cees mee [or ioaf a afar s glares a tos bela] es) 2i seca [ocr ro 2]or eo a)tr ez) re 4 ak Je ce elels yc]: Tease bara Tak wala atel:|ia]= Tew tee Mea rat ib + Fle & FE j ¥-oo wlelc} tape rata | mor oy | ace sal] sia) e bel [abel Tej nore. coaniTeen coor seMNOLE (GF pean Gee snvets mat cares ethene a ~ Remtar af MPU Dye El Bettas Energie OF Mart patty tae = fons of Frege Bar Bo commence oo P tegtsat ae

2 Ramee Rat = Testi brs ere

~ nee, Mira. 2 Bs de, elles 2 nee asa Booty tes 4 Goertge, J ccaneimnaes Mp Eevterich meaty san gacted i be Suck Pate CE canmptra ee? fet Alea Fieve. Atgotwsteeatdarneg may often isa th cman Ha ARLIED aaa 5 Sritient [Tew and wer Far hes rhe MOTOROLA MICROPROCESSOR DATA 3-269

TABLE 4 — INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS COND. COOF ARG. [ wmweo Toomer | | _extwe | minuen | [s[a]s[e[s To ronren osenarions sawewonec | 0” [| =[e#]~| =[or]~]=[0r]~|=| or] ~ = | sooveanammrmmeric oneravion [| 1 |z/¥ 1c | CCarmgace lags: fg ex | aE efalfacte|afects | o Fe My TS ee ‘Dectarmest badien Fy nex amped E-rk jesie]ele Decrammasa Stack Prat oes i ulala 1 -aP |a'eelelele increment iecien Ra ne H | miale Keak lee eles Inceernaen Brack Par ms i mypele ah -aF ie eee ss aad index fog, Wk | ue apryeelelaleys jal Pern Oe i* bt als ‘aad Sick Free ws | tt alalee|e)afaels)a] | MSP cM ESP je 2 fale Sows inde Brg atx slafee|ririeejela) 7 | Ka My IMs te 2 edls ele Seo Sack Pein sts s|efarlriziarj6| | | Py “Md, SPy aM = eed: ale ied Beg. Stack Par 145 : jit ster | Kode aia etalece Suck Fie -tnas ha vax | i i wiaya ait ok sie esiee TABLE 5 — JUMP AND BRANCH INSTRUCTIONS ‘COND. CODE REG. wearive | wore | cxtee | merveo | [»[afajafifel «_orenaTions wutwome Tar’ ]=tor]=[=tarl=t=ler[=[=] anancwvesr [wf wz Tw fe] Brae’ Alea +na, mia Mane + ellelel= reser IF Gaon Chew ne tn sl ejap alate Grarea IF Carty Sat as | wa | cel eiele}eleta Brana It» Zeve a9 gla 1 | ore eoelalel ele france 1h Zee aGE jmela | ] a@v-t oe elelelele Brant It Zero aGr mia i | zeinOv-d es elepelele france if Higher Bee aia | | | pete wwe alee Beech S00 aur wie i | genre es ejejele ‘| teach If Lower Oe Saree BLE ni l tezet aieterelele Tench i Zora mur | mle | | nawer slalejpale | fegach Miran ae mle i i wee s)fispeiee Baaech Ht Wen gual Zara art aa} e ' , 0 zen slelele 3|5| Brareh tl Ove Cieur Bye la fo vee ape elelele Sranah t Dvaetipw fat te nla | ved er elelalele Broveh it Plas aL gala wee elelelelele frangh To Subeestien BSA ap} a | . 2/2] ajele jure aur te] atalvel a) 3 4 See Speci Dorrie el elalelels dung Ta Subiouttee 18 ap] #) 2/aoj 9] a (Figure 18 . eytje ale Ma Dpetrtion wor onlzrje Advarues Prog Com Only wl elelelale Raion Fron binetrapt aT mpi] — # —_ Aven From Sebeewtine | ats als fal | epepepsyele Setters tauaerupe wi a liala ‘ben Spec Opie ala el alee (pe Fo roerage Lat aef ads] Fguee a #|@ ef ele MOTOROLA MICROPROCESSOR DATA 3-270

FIGURE 16 — SPECIAL OPERATIONS SPECIAL OPERATIONS 265A, JUMP TO EUBROUTING: 1 _Main Progrien, FJ ‘Stack 1 __tearevone s [aoe] a ce Oe | moun | eet c> w-1 Leia _| cd ned [Ret ain ira] a “R= BB Urpgeed Yatue [m2] gy and Let Dh Form ed ey Man hopan oe Suck tt Subravtine © (ao A -erf 3 [ase too] a+) [Se Suer Aaa | sei [lasake | _ EXTAD fF 1 [ites aan] — > fa 1a Fenmnd ram By RL ed [Mean Main bau J 1 Stack Posner Atte: Eurcenere BSA, BRANCH TO SLBA GUTINE Main Png 4 Stack ep Suarunne fe err as ordre [habe ine] nv? [anerme aos | @ Crone _] JM, JUMP PE Mas Progan ey Man Fagen ATS, RETURN FROM SUBROUTINE PE Sabreutine: Pa Sart BE en Progra, rf cerca | Fs P= = weet - SPE AT RETIN POM INTERRUPT. elena Pager 2 sect ote Pagen Ss Cs + [pews tans tra] seer [aoe | weet [ane | at-t [een ian oe ses re TABLE 6 — CONDITION CODE REGISTER MANIPULATION INSTRUCTIONS. COM CODE Pac. [eerie pada ortnarions: wnenonee [or] | =| someaworemation{ ae 1 om 2 ive | Cite Carry TLE mw ac ee 8 Fe oe Qian Wrierrugt Maik cu Lg ow =e) R #8 2 2 ‘Dirge treet coe | me Bee elie ee ke fat Cathy SEC we tee oe # # 8 5 Ber Irveerape Pape bt a] cil Te ef: 8 oo ® ‘Sat Dat cre SEW = tw ee 8 @ig ® acelir A CCA rap a6 A ECR i- CCA Ace LiL ar COR +a ele oe alae COMDNTOON CODE REGISTER MOTUS: olbe oet ot tent atrue ane cleared arherence 1 ev) Test Amat» 80000800" 2 ABM Tent Spe ber ef ont pgatart (5) byte = 17 : ech Tet Reoen # SOOO? a [Ba Vb Ten 2s ceenpterrant certian fra dubnacnen ot MG tere Bar het Decvenad watt af esost pepeetcara ACEI Chatactes greater Tha fore™ ee) Tent evel rea Peay pera 1B ER Te Chet claaeed of pteveburtly a1! 10 1AM) Load Cowen Code Amgeriee trom Siete chet Seeca! Operas one a We Wl Tet Gperend = 10000000 eon tn tepcunen? 1 Tir th Sec ayhen enterrape cccues I prewiterty Mel. a Aces Makai Ly HBe Vi Tear Opersed G10 PTET gre tewercaben® Vevteren pri ou rarcja rid 1G eet Pee det Se & WB) Tepe Set equal derail of BGA whe a han aoe Zz oh Sei acterdeng ta the carapers of Acceruiatar & MOTOROLA MICROPROCESSOR DATA 3-271

TABLE 7 = INSTRUCTION ADDRESSING MODES AND ASSOCIATED EXECLITION TIMES. (Times in Machina Cyete) " : H BoGedrai Soa .dae 2E9PiGEG: 2EEERR GG S¢ Faget Fe &<iacskcs:eE& ABA * 8 & 2 oe 2 oe nC 2 8 8 BT # anc a 8 2 9 4 5 #8 «© NS ss 8 & & & ADD = *# 2 3 4 & ww « 1 ee 8 e ee & AND ok ow 62 3 4 5 ow @ IMF ss # 3 4 ie ask zt 8s # 6 Fo 8 & Jen ee 2 8 Boe ASA 2 os 8 6 TF we @ LOA » # #£ 3 4 5 @ acc se ee 8 oe ea Los s 3 4 5 6 # acs 8 8 ee ea Lox * 2 4 5 6 # BEA er ee er ee | LSR Boe » 6 T «® BoE NEG 2 8 # 6 To # 8GT se ee ew ew NOP e 8 e e # 2 BHI ee ee ee | OFA os «# # 3 4 & @ BT s *® 2 3 4 5 wm PSH se 8 ee me 8 es se ew oe a Pu ee ee ee BLS ee ee ew a ROL z= e* # 6 TF «# aT ee ee ee ROA Poe « 6 T @ BMI * 2 8 8 ew we 4 RTI 2 8 2 2 0 BNE se 8 8 ew ew 4 ATS 8 © © &# 6 BPL ee ee ee | SBA se 2 es 2 ew 2 BAA Cr sac e «© 2 3 4 & @ BSR 8 8 8 8 oe sec es e 8 8 FE avc 8 es ew ee a SEI © © © # 2 avs = es es es ew 4 SEW = 8 8s es we 2 CBA * 8 © # #© 2 & STA 1 6 6 4 5 6 ow cc se 8 © © 2 © STs es 8 &§ B&B T cu * 8 & © © Boe STx * 6 8 6 Tow LA Foe e# &€ Fw sug woe FoF 4 Sw LW se e 8 e Fe Swi ee 8 ew cMP = 6 2 3 4 Sf ww TAB = 2 8 es 8 2 SoM Poe 6 6 7 w « TAP * 8 # ew 2 oaa es es es we 2 TRA se 8 e 0 2 DEC 2 8 © &€ Fo mw oe TST 2 8 = &€ Fo w oES = 8 © e 8 4 oe TSK 8 ee oe 4 DEX ee ee oe 4 Tse o # © 2 we af —oR oe 2 9 4 5 w «8 WAL © © ee FH NOTE — fenerrugt rime rs 12 eyeles trom the endl of The ETUCDON Heng EXeCUteN, except tolkowng SWAL inntruciee Then itis d cycles MOTOROLA MICROPROCESSOR DATA S272

SUMMARY OF CYCLE-BY-CYCLE OPERATION 7 Table & provides a detailed description of the infomation as ihe control program Ss executed, The information 1 present on the achdness bus, data bus, valid memery address categorized in groups according to addressing modes and ling IVMAL, and the read/write line (RW) during each cycte number of cycles per instruction. iin general, instructions for @och instruction with the same addressing mode and number of cyches ex- This information i¢ useful in comparing actual with ex- cute in the same manner, exceptions are indecated in the pected results during debug of both software and hardware tabbe.) TABLE & — OPERATIONS SUMMARY [asstamat, Jove |URE] nema Lone and Instructions IMMEDIATE AGC EOR ‘Op Code Address Op Coos ONG GRA Op Code Addr +4 Operand Date BIT Sec cMF SUB CPx Op Cade Addrass Op Code tox Op Code Addons + 1 Gparand Data (High Order Byte) Op Coe Address + 2 ‘Operend Data {Love Oraer Byte! CHRECT 3 abc EOR ‘Op Code Addrets ‘Op Code SIT Sec Acdrost of Operand ‘Operand Dara CMP SUB cP Op Coe Address 1 | Op cone Lbs Op Gage Aaaeate +1 1 | Adsrens of Gowran Address of Opersnd 1) 1 | Qpeand Data High Crete Gyre ‘Operand Address +17 1] Operant Data (Lees Ovelar Byte ‘Op Code Address H Op Cone Dp Code Address © 1 | 4 | Gastination actetross Duttination Address 1 | teeetevant Oats IMete 1 Destination Address 0 | Data teat Accumulator

1 Op Conde Adctrass 1 Op Code

2 Op Cage Address + 1 1 | Adare of Onerand

3 Ackires of Oper + frrelewsnd Data (Mote 1) |

‘ Address of Operand o Fragister Data {High Order Bytel

5 Addret of Operane + 1 6 | Rogier Gata [Low Crider Byrah

‘Dp Code Address © 1 Otter Index Fegister Irrelevant Cate (Nowe 1 Index Ragister Plus Offset (vie Carryt Incatevant Gata (Note 1) ADC EOR Op Code Adtirets ‘Op Code aoe ee Op Coe Address +1 Offset BIT sec Index Plegister Ieralevant Gata (Mote 1 cMP Sue Index Flagister Plus Offent (uefa Carry! lerelevent Gata [Nowe 13 Index Plegirter Plus Offser Oparand Data CPx Op Code Adairess Op Code te Op Code Adciwss + 1 Ottsat Indian Aegister leralavent Dara (Mote 11 Index Fregirter Plus Ottset (w/o Carry) irrelevant Gate (Note th Indien Register Pius Coffea ‘OCperend Data (High Order Byte! Index Flegicter Plus Offset +1 Operand Data iLow Order Bytel a MOTOROLA MICROPROCESSOR DATA 3-273

TABLE 8 — OPERATIONS SUMMARY (CONTINUED) - [_astematts lov] e*lis [samme IB] and inetructaors : INDE XED (Contineed) Op Code Addiness Op Code Op Goch Acidress + 1 ‘Otter tedden Flegiana lereleusar Qate (Nowe Th Indes Plagister Pius Of teat Iwi Corry leretevent Date (Note 1) Indes Flegiaver Plus Ottsat Irrelevant Gane (Note 1 Inciox Foegister Pius Ofdyat ‘Operand Gata aS LSA v | 7 | Gptode addres Op Code asa NEG 2 | 1 | Op Come Address «1 Ofteet cOoM ROR ? a o index Feegisear ferolevent Date (Note 1) nee aT 4 | 0 | tnctex Plegister Plus Otter trio Carre Weeigvant Data (Note 1) 5 | 1 | trdes Feegiaer Plus OHset Cumen Operend Data 6 | 0 | tncex Regignr Plus tise Herelevant Gata (Note 1) T ae. lex Register Plus O4 feet New Cperand Data (Note 3! Note STE 1 ‘Op Code Address: Dp Code six 2 Op Code Address +1 ‘Ofteat 3 7 a Indes Feepisrer Irrelevant Date (Note 1 4 Indios Feygivter Plus Otises two Carey! Irralecant Gate (Nowe 1b

8 Indax Feogisrer Plus Ofised Irrelevant Gate INote 1

6 index Phogieter Plat Otter Opersnd Date [High Order Byted ? Index Fiegisser Plus Offset + 7 ‘Opersnd Cate [Low Order Bytel JS 1 1 Op Coce Antdrens ‘Op Code 2 | 01 | opcode address +1 ‘Ofset 3 | 0 | index Feyister Iereleunnt Date (Note tf 4) 1 | Stack Pointer Rasturn Actress (Law Order Bytat 5 | 1 | Stack Pointer — 1 Peetuen Address [High Greer Byach 6} 0 | Stack Pointer — 7 Mrelevane Oata [Note 1) 7 | | indos Feepister Irretecant Gate Ite 1) & | 0 | index Regisnor Plus Ottser fala Carry! Inraterant Data INow 17 EXTENDED Op Code Andress Op Code ‘Op Code Address +1 dame Address [High Geder By tel ‘Op Code Address #2 Jump Adeiress [Low Oroer Byteh ADC EOR Op Code Address Op Code ano baa Op Code Address + 1 Address of Qperand (High Crder Bytel BIT sac Op Code Addruts + 2 Addren of Opgrand {Low Order Gytel MP SUB Agdeess of Oparand Operand Dara crx Op Code Achdrana Op Code tox Op Code Address +1 Address of Gperand {High Order Bytel Op Code Addran+ 7 Address of Operand (Low Order Sytal Address of Operand ‘Operand Data iHigh Cedar Byte Addrect of Cperand + 1 Operand Data (Low Onder Bytel Op Code Address ‘Op Code Oo Code Address + 1 Destinetion Address (High Order Syreb Op Code Address +2 Destination Adteiress [Low Order Bytal ‘Oparand Destination Agden trrelmeant Gata (Note 1h ‘Operand Destination Ackcness Bata from Acciemularar ASL LSA 1 ‘Op Conte Actress Op Cade age NEG + | Op Gone medrese + 1 Ackiress of Operand (High Order Byte OM ROR 1 ‘Op Code Address + 2 Addn of Openend (Leer Onder By tel gec Tet 1 | Adaress of Operand Current Operand Gata o Adciness of Operand Arvetevart Data (Nove 1) od addres of Operend New Operand Gate (Note 3} thiore Ei a MOTOROLA MICROPROCESSOR DATA 3-274

Mcés02 TABLE & — OPERATIONS SUMMARY (CONTINUED! erantttte Jeon [F*]iiE] aan ET om aed Instructions Lie EXTENDED (Contineed? ‘Op Code Address Op Cade ‘Oe Code Address + 1 Addresc of Operand ‘High Order Byte! ‘Op Code Addrass + 2 Address of Operand (Low Order Bytel Addrats of Operand terelevent Date [Note 1} aatdross of Operand ‘Operand Qua [High Order Bytel Addiree. of Operand + 4 ‘Cparand Dane [Low Creer Byrat PR 1 ‘Op Code Address 1 ‘Op Code

2 Op Code Agdewas +1 1 | Addrew of Subroutine (High Order Bytel

3 Op Code Ankiness + 2 1 Address of Sutrouting (Low Order Byted

4 Subroutine Starting Address 1 | Op Code of News Instruction

5 ‘Steck Pointer o Return Addrer (Low Order Bytel

6 Suaek Pointer — 1 D | Retain Address High Order Bytel

7 Stack Pointer — 2 1 | irrelevant Date IMoue 1

a Op Code Addresi + 2 1] trratevant Dara clove 11 a Op Code Adcress + 2 1 | Address of Susroutine |Low Order Gynel INHERENT AGA DAA SEC Op Code Address: ‘Op Coda 3 fen Whe Seu Op Code Address + 1 Op Code of Next Instrection CBA LSR TAB cLO NEG TAF cli NOP TEA CLA ROL TPA Lv AOR TST cOM Sha BES ‘Op Code Addrans Op Cone aex Op Code Address + 1 Op Code af ext Inviruction 1x. Previous Register Contents Wrretevant Dara (Note 11 New Aegater Contents irrelevant Date (Neve 1) Op Code address Op Code Op Cade Addrans +1 Op Code af Ment Insiruction Stack Pointer Accumulator Date Stack Pointy — 1 Accumulator Data PuL On Code Address Op Code Op Code Aaress +1 Op Cone of Pens Insruction Steck Pointer Irrelevant Date (Note 1] Stack Poinues + 1 Operand Data from Stuck Op Code Agdrent Op Code ‘Op Code Address + 1 Op Code of Mast inatiructian Stack Puinwer Ireatevant Bete INote 1 Mew Index Plegisser Ievetevant Data Note 1 ‘Op Code Addr ‘Oe Code ‘Op Code Address +1 Op Code of Next trstruction Index Fegister trrelavent Date New Stack Pointer Irrelevant Data Op Code Address ‘Op Code Op Code Addregs + 1 irrelevant Data (Note 2) ‘Stack Pointer Hrrelevant Data (More 1) Stack Pointer + 1 Address of Neck Instruction (High ‘Order Bytal Stack Pointer + 2 Addrmts of Next instruction (Low Order Byte! a MOTOROLA MICROPROCESSOR DATA 3-275

TABLE & — OPERATIONS SUMMARY (CONCLUDED) [tstrmtite, [ovum | S*|ies] nae [| ore and etruttions Crm | # INHERENT (Continued!

1 Gp Code Address T [Op God

2 Op Cone Addrets +1 1] Op Code of Newt Iranruetion

3 Stack Pointer 0 | Return Address (Low Order Byte)

4 Stack Pointer = 1 O | Retuen Adciens (High Order Byte

5 Stack Pointer — Z 1D | tnciax Register |Low Order Bytel

6 Stuck Pointer — 3 0 | Indies Fagister (High Crear Byte!

7 Stack Pointe: — 4 0 | Contents of Accumutstor A

a Stack Pointer - & 0 | Contents of Accumulator & EI Stack Pointer — 6 1_| Contents of Cond. Code Ragisnar ATI 1 Op Code Ackiner 1 [Op Code

2 Op Code Address +1 1 | irretevart Guta (Nowe 2)

3 Stack Pointer 1 | teraievest Gata (Note 1)

4 Srack Pointer #4 1 | Contents of Cond. Code Register trom Stack

5 Stack Pointer #2 1 | Contents of Accumulator @ from Stack

6 Stack Pointar +3 1 | Contents of Accumulator A trom Stack

7 Stack Pointer +4 + | Index Fleginer trom Stack (Migh Order

Byte! B Stack Pointer + 5 1 | inden Regier trem Steck [Low Order Bytet EI Stack Pointer +6 1 | Next ingtruction Address trom Stack {High Order Bytal oT] Stack Pointer + 7 1 | Mext dratrustion Ackirest from Stack {Low Order Bytel

1 Op Code Addrert 1 | Op Code

2 ‘Op Code Address * 1 1 | Ireetevarnt Oat (Note 1h ET Stack Pointer 0 | Return Address (Low Order Byrel 4 Stack Pointer — t 0 | Return Addoete (High Drier Byte! & Stack Pointar — 2 @ | lncen Register (Low Cedar Byte)

5 Stack Pointer — 3 D | todas Feginter (Hogh Order Byted

? Beeck Poincar — 4 | Contents of Accumulator

8 Stack Pointer — 5 f | Contents of Accumulator B

a ‘Stack Pointer — 6 | Contents of Gand. Code Megirter 10 ‘Stack Pointer — 7 1 | Ireetervant Gata (Nate Th W Vector Address FFFA IHex) 1 aires af Subroutine (IMigh Order te

12 Mector Addrecs FF FE [Han] * | atcrass ot Subroutine (Low Order

ecc BHt BNE Op Code Address Op Code Bce BLE ae Op Code Addran +t ranch Offer BGE BLT ave Op Come Addrase * 2 feretevant Date INote 1h ocr Bm Bvs Branch Addrass Irewlavant Data (Nowe 1h 1 1 [On Code Adcrece Op Come 2 | + | Op Code Adaress +1 Branch Offset

3 O | Reture Address of Main Progam Irrehevart Gate (Note 17

4) 1 [Stack Pointer Return Address (Low Crder Bytel 5 | 1 | Stack Pointer —1 ‘Aeturn Address (High Order Byte

6 O | Stack Poinser — 2 ieretevent Data [Note 1)

7) | 0 | Fetus Adaress of Main Program leretevent Data (Not 1 & | oo | Sutmensting Address INotw 41 teratevent Date (Note 1 NOTES: 1H deviog which & addressed during the cycle uae WMA, Ihen sho Catia Bus avi go to the high-impedance thres-siate condiban, Depending on bus capacitance, daa from the previous. cycle may be mained on the Data Bus. 2. Data ib ignored by the MPL 3 for TST, VMA=0 and Operand data does not change 4.5 Byte of Address Bus MS Gyro of address of BSR insiruction and LS Byte of Address Bus=LS Byte of Sub-Aoutine Address nee) MOTOROLA MICROPROCESSOR DATA 3-276

MECHANICAL DATA AND ORDERING INFORMATION .

ORDERING INFORMATION

P Sut 10 40°C to +86"C | MOSROZCP 1s Cow MceBaozP 1 ~a0°C tn +850 | | MCBBADZCP

20 WC to TC Mceapo2P

$ Suffix 1.0 —artio +eSC | | MCEBOZCS

1.6 OC to 7S MCEBADZS

16 arc to + BSC MCE6BAOZCS.

20 OC to 70°C MCEBBOZS:

Ves Jie 40) RESET <) HALT Q2 39 exTaL mR G3 aa TAL ira ga ape MA 05 36) RE AM ge 35 0 Vor Standby BA]? 340 Rv Veo Le a3 pe ao qo 320 oF Al dio 310 02 az gu 30 ff pa Ag iz za 0 ba Ad [13 287] Os AB 14 270 pe Ag 15 260 oF AT 16 76H ats Ag Qi7 240 at 4g (18 23 ai aid qis 220 Ai All Qiao 2170 veg. MOTOROLA MICROPROCESSOR DATA 3-277