MC68010

MC68010 MOTOROLA | Alldatasheet

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= SEMICONDUQON — EEE TECHNICAL DATA MC68010 Technical Summary 16-/32-Bit Virtual Memory Microprocessor This document contains an MC68010 summary and a detailed set of para- metrics. For detailed information on the MC68010, refer to the M68000UM/AD, M68000 8-/16-/32-Bit Microprocessor User's Manual. The MC68010 is a member of the M68000 Family of advanced microprocessors. Utilizing VLSI technology, the MC68010 is a fully implemented 16-bit micro- processor with 32-bit registers, a rich basic instruction set, and versatile ad- dressing modes. The following resources are available to the MC68010 user: © 17 32-Bit Data and Address Registers @ 16-Mbyte Direct Addressing Range @ Virtual Memory/Machine Support @ 57 Powerful Instruction Types @ High-Performance Looping Instructions ®@ Operations on Five Main Data Types @ Memory-Mapped 1/0 @ 14 Addressing Modes This document contains information on a new product. Specifications and information herein are subject to change without notice. 3-136 M68000 FAMILY REFERENCE MANUAL MOTOROLA

The MC68010 is fully user object-code compatible with the earlier members of the M68000 Family and has added features of virtual memory support and enhanced instruction execution timing. The MC68010 is pin-for-pin compatible with the MC68000. The MC68010 possesses an asynchronous bus structure with a 24-bit address bus and a 16-bit data bus. As shown in the user and supervisor programming models (see Figures 1 and 2), the MC68010 offers 17, 32-bit, general-purpose registers, a 32-bit program counter, a 16-bit status register, a 32-bit vector base register, and two 3-bit alternate function code registers. The first eight registers (DO-D7) are used as data registers for byte (8-bit), word (16-bit), and long-word (32-bit) operations. The second set of seven registers (A0-A6) and the stack pointers (SSP and USP) may be used as software stack pointers and base address registers. In addition, the address registers may be used for word and long-word Operations. All 17 registers may be used as index registers. MOTOROLA 68000 FAMILY REFERENCE MANUAL 3-137

in a trace (T) mode and in a supervisor (S) or user state. Figure 3. Status Register word data, etc., are provided in the instruction set.

Most instructions can use any of the 14 addressing modes listed in Table 1. counter relative mode can also be modified via indexing and offsetting. Table 1. Addressing Modes

ulations and extended arithmetic operations. Table 2. Instruction Set Summary

Table 3. Variations of Instruction Types

3 ANDI to SR AND Immediate to Status Register

VIRTUAL MEMORY/MACHINE CONCEPTS In most systems using the MC68010 as the central Processor, only a fraction of the 16-Mbyte addressing space will actually contain physical memory. How- ever, by using virtual memory techniques, the system can be made to appear to the user to have 16-Mbytes of physical memory available. These techniques have been used for several years in large mainframe computers and more recently in minicomputers and now, with the MC68010, can be fully supported in microprocessor-based systems. In a virtual memory system, a user program can be written as though it has a large amount of memory available to it when only a small amount of memory is physically present in the system. In a similar fashion, a system can be de- signed which allows user programs to access other types of devices that are not physically present in the system. With proper software emulation, a physical system can be made to appear to a user program as any other computer system, and the program may be given full access to all resources of that emulated system. Such an emulated system is called a virtual machine. The MC68010 supports these modes through its instruction continuation mech- anism. When an address error or bus error is encountered, the MC68010 will place its internal state on the supervisor stack. The appropriate exception han- dler is erased and, upon completion, causes the MC68010 to reload its internal state and resume execution. Loop mode takes advantage of the fact that the MC68010 can contain three elements of the instruction stream internally. When these elements are 1) a loopable instruction, 2) the DBcc instruction, and 3) a branch displacement to the loopable instruction, the MC68010 will enter the loop mode in which no instruction accesses are made; only data accesses are performed. This allows extremely fast data transfers as well as providing the bus access made by the MC68010. MOTOROLA M68000 FAMILY REFERENCE MANUAL 3-143

described in the following paragraphs. Figure 4. Functional Signal Groups can transmit and accept data in either word or byte length.

This signal indicates a valid address on the address bus. These signals control the flow of data on the data bus, as listed in Table 4. R/W is low, the processor will write to the data bus as shown in Table 4. Table 4. Data Strobe Control of Data Bus

1 No Valid Data | Valid Data Bits

may not appear on future devices.

Bus request, bus grant, and bus grant acknowledge form a bus arbitration circuit to determine which device will be the bus master. Bus Request (BR) This input is wire-ORed with all other devices that could be bus masters. This input indicates to the processor that some other device desires to become the bus master. Bus Grant (BG) This output indicates to all other potential bus master devices that the processor will release bus control at the end of the current bus cycle. Bus Grant Acknowledge (BGACK) This input indicates that some other device has become the bus master. This signa! should not be asserted until the following four conditions are met: 1. A bus grant has been received. 2. Address strobe is inactive, which indicates that the microprocessor is not using the bus. 3. Data transfer acknowledge is inactive, which indicates that neither mem- ory nor peripherals are using the bus. 4. Bus grant acknowledge is inactive, which indicates that no other device is still claiming bus mastership. INTERRUPT CONTROL (IPLO, IPL1, IPL2) These pins indicate the encoded priority level of the device requesting an interrupt. Level 7 is the highest priority; level 0 indicates that no interrupts are requested. Level 7 cannot be masked. The least significant bit is IPLO and the most significant bit is |PL2. These lines must remain stable until the processor signals interrupt acknowledge (FCO-FC2 are all high, A16-A19 are all high) to ensure that the interrupt is recognized. 3-146 M68000 FAMILY REFERENCE MANUAL MOTOROLA

The three system control inputs are used to reset or halt the processor and to indicate to the processor that bus errors have occurred. Bus Error (BERR) This input informs the processor that there is a problem with the cycle currently being executed. Problems may be a result of: 1. Nonresponding devices 2. Interrupt vector number acquisition failure 3. Illegal access request as determined by a memory management unit 4. Other application-dependent errors The bus error signal interacts with the halt signal to determine if the current bus cycle should be re-executed or if exception processing should be per- formed. Reset (RESET) This bidirectional signal resets (starts a system initialization sequence) the Processor in response to an external reset signal. An internally generated reset (result of a RESET instruction) causes all external devices to be reset, and the internal state of the processor is not affected. A total system reset (processor and external devices) is the result of external HALT and RESET signals applied simultaneously. Halt (HALT) When this bidirectional signal is driven by an external device, it causes the processor to stop at the completion of the current bus cycle. When the processor is halted using this input, all control signals are inactive, and all three-state lines are put in their high-impedance state. When the processor stops executing instructions, such as in a double bus fault condition, the HALT line is driven by the processor to indicate to external devices that the processor has stopped. M6800 PERIPHERAL CONTROL These control signals are used to interface synchronous M6800 peripheral de- vices with the asynchronous MC68010. MOTOROLA M68000 FAMILY REFERENCE MANUAL 3-147

state of the bus on the MPU. the processor should use automatic vectoring for an interrupt. Table 5. Function Code Outputs 4 are reserved for future use by Motorola.

minimum and maximum pulse-width times. Table 6 is a summary of all the signals discussed in the previous paragraphs. Table 6. Signal Summary

Transfer of data between devices involves the following leads: 1. Address bus A1-A23 2. Data bus DO-D15 3. Control signals The address and data buses are separate parallel buses used to transfer data using an asynchronous bus structure. In all cycles, the bus master assumes responsibility for deskewing all signals it issues at both the start and end of a cycle. In addition, the bus master is responsible for deskewing the acknowledge and data signals from the slave device. The following paragraphs explain the read, write, and read-modify-write cycles. The indivisible read-modify-write cycle is the method used by the MC68010 for interlocked multiprocessor communications. READ CYCLE During a read cycle, the processor receives data from the memory or a pe- ripheral device. The processor reads bytes of data in all cases. If the instruction specifies a word (or double word) operation, the processor reads both upper and lower bytes simultaneously by asserting both upper and lower data strobes. When the instruction specifies byte operation, the processor uses an internal AO bit to determine which byte to read and then issues the data strobe required for that byte. For byte operations, when AO equals zero, the upper data strobe is issued. When AO equals one, the lower data strobe is issued. When the data is received, the processor correctly positions it internally. lf DTACK, BERR, or VPA is not asserted for the required setup time before the falling edge of state 4, a wait cycle will be inserted in the bus cycle, and DTACK will be sampled again on the falling edge of each wait cycle. The MC68010 will continue to insert wait cycles until DTACK, BERR, or VPA is recognized. WRITE CYCLE During a write cycle, the processor sends data to either the memory or a peripheral device. The processor writes bytes of data in all cases. If the instruc- tion specifies a word operation, the processor writes both bytes. When the instruction specifies a byte operation, the processor uses an internal AO bit to determine which byte to write and then issues the data strobe required for that byte. For byte operations, when AO equals zero, the upper data strobe is issued. When AO equals one, the lower data strobe is issued. If DTACK, BERR, or VPA is not asserted for the required setup time before the falling edge of state 4, a 3-150 M68000 FAMILY REFERENCE MANUAL. MOTOROLA

wait cycle will be inserted in the bus cycle, and DTACK will be sampled again on the falling edge of each wait cycle. The MC68010 will continue to insert wait cycles until DTACK, BERR, or VPA is recognized. READ-MODIFY-WRITE CYCLE The read-modify-write cycle performs a read, modifies the data in the arithmetic logic unit, and writes the data back to the same address. In the MC68010, this cycle is indivisible in that the address strobe is asserted throughout the entire cycle. The test and set (TAS) instruction uses this cycle to provide meaningful communication between processors in a multiple processor environment. TAS is the only instruction that uses the read-modify-write cycles; since TAS only Operates on bytes, all read-modify-write cycles are byte Operations. CPU SPACE CYCLE During a CPU space cycle, the MC68010 reads a peripheral-device vector num- ber or indicates a breakpoint instruction. If the cycle is to read a vector number, itis referred to as an interrupt acknowledge cycle. A CPU space cycle is indicated when the function codes are all high. The address bus then defines what type of CPU space cycle is being executed. The MC68010 defines two types of CPU space cycles, the interrupt acknowledge cycle and the breakpoint cycle. The interrupt acknowledge cycle on an M68000 Family compatible processor is defined as a CPU space cycle with the most significant address lines high; on the MC68010, this cycle means that A4d-A23 will be high. The level of the interrupt being acknowledged is encoded on address lines A1—A3. An interrupt acknowledge cycle is terminated in the same manner as a normal read cycle. The processor expects a peripheral device to respond to an interrupt ac- knowledge cycle with a vector number that will be used to transfer control to an interrupt handler routine. The breakpoint read cycle is executed by the MC68010 in response to a break- point illegal instruction. A breakpoint cycle on the MC68010 is defined as a CPU space cycle with all of the address lines low. The processor does not accept or send any data during this cycle. The breakpoint cycle may be terminated by DTACK, BERR, or VPA. PROCESSING STATES The MC68010 is always in one of three processing states: normal, exception, or halted. MOTOROLA M68000 FAMILY REFERENCE MANUAL 3-151

The normal processing state is that associated with instruction execution; the memory references are to fetch instructions and operands and to store results. A special case of the normal state is the stopped state which the processor enters when a stop instruction is executed. In this state, no further references are made. EXCEPTION PROCESSING The exception processing state is associated with interrupts, trap instructions, tracing, and other exception conditions. The exception may be internally gen- erated by an instruction or by an unusual condition arising during the execution of an instruction. Externally, exception processing can be forced by an interrupt, a bus error, or a reset. Exception processing is designed to provide an efficient context switch so that the processor may handle unusual conditions. HALTED PROCESSING The halted processing state is an indication of catastrophic hardware failure. For example, if, during the exception processing of a bus error, another bus error occurs, the processor assumes that the system is unusable and halts. Only an external reset can restart a halted processor. Note that a processor in the stopped state is not in the halted state, nor vice versa. INTERFACE WITH M6800 PERIPHERALS Motorola's extensive line of M6800 peripherals are directly compatible with the MC68010. Some devices that are particularly useful are as follows: MC6821 Peripheral Interface Adapter MC6840 Programmable Timer Module MC6843_ Floppy Disk Controller MC6845_ CRT Controller MC6850 Asynchronous Communications Interface Adapter MC6854_ Advanced Data Link Controller To interface the synchronous M6800 peripherals with the asynchronous MC68010, the processor modifies its bus cycle to meet the M6800 cycle re- quirements whenever an M6800 device address is detected. This modification is possible since both processors use memory-mapped 1/0. 3-152 M68000 FAMILY REFERENCE MANUAL MOTOROLA

Operating Temperature Range TA TL to TH Cc application of voltages higher MC68010 Oto 70 than maximum-rated volt- Mc68010C 40 to 85 ages to these high-imped- Em ance circuits. Tying unused 3 logic voltage level (e.g., either GND or Vcc) enhances reli- ability of operation. THERMAL CHARACTERISTICS |___Characterstic___[ Symbat vaiue | Symbot | Vatue [Rating | Thermal Resistance (Still Air)| 6a, Jc “CW Ceramic, Type L/LC 30 15* Ceramic, Type R/RC 33 15 Plastic, Type P 30 15% Plastic, Type FN 45 25* *Estimated POWER CONSIDERATIONS The average die-junction temperature Ty in °C can be obtained from: TJ=TA+(Pp + 6ya) (1) where: Ta =Ambient Temperature, °C ®jA =Package Thermal Resistance, Junction-to-Ambient, °C/W Pp -=PINT+PV/O PINT =!cc Vcc, Watts — Chip Internal Power Pyo =Power Dissipation on Input and Output Pins — User Determined For most applications P)/Q<P|NT and can be neglected. An appropriate relationship between Pp and Ty (if Plo is neglected) is: Pp=KATJ +273 °C) (2) Solving equations (1) and (2) for K gives: K=Pp + (Ta + 273°C) + 0JA*PD2 (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring Pp (at thermal equilibrium) for a known Ta. Using this value of K, the values of Pp and Ty can be obtained by solving equations (1) and (2) iteratively for any value of Ta. MOTOROLA M68000 FAMILY REFERENCE MANUAL 3-153

The curve shown in Figure 5 provides the graphic solution to these equations for the specified power dissipation of 1.5 watts over the ambient temperature range of —55 °C to +125 °C using a maximum 6JA of 45 °C/W. Ambient tem- perature is that of the still air surrounding the device. Lower values of 6jA cause the curve to shift downward slightly; for instance, for 8JA of 40 °/W, the curve is just below 1.4 watts at 25 °C. The total thermal resistance of a package (6JA) can be separated into two components, 8JC and 8CA, representing the barrier to heat flow from the semi- conductor junction to the package (case) surface (6JC) and from the case to the outside ambient air 6CA). These terms are related by the equation: ®JA=8JC+9CA (4) €JC is device related and cannot be influenced by the user. However, @CA is user dependent and can be minimized by heat sinks, ambient air cooling, ther- mal convection, and other thermal management techniques. Thus, good ther- mal management on the part of the user can significantly reduce 8CA so that 8JA approximately equals 6JC. Substitution of 6JC for @JA in equation 1 results in a lower semiconductor junction temperature. Table 7 summarizes maximum power dissipation and average junction tem- perature for the curve drawn in Figure 5, using the minimum and maximum values of ambient temperature for different packages and substituting @JC for 8JA (assuming good thermal management). Table 8 provides the maximum power dissipation and average junction temperature for the MC68010 assuming that no thermal management is applied (i.e., still air). NOTE Since the power dissipation curve shown in Figure 5 is negatively sloped, power dissipation declines as ambient temperature increases. Therefore, maximum power dissipation occurs at the lowest rated am- bient temperature where power dissipation is lowest. Values for thermal resistance presented in this manual, unless esti- mated, were derived using the procedure described in Motorola Re- liability Report 7843, Thermal Resistance Measurement Method for MC68XXX Microcomponent Devices, and are provided for design pur- poses only. Thermal measurements are complex and dependent on procedure and setup. User-derived values for thermal resistance may differ. 3-154 M68000 FAMILY REFERENCE MANUAL MOTOROLA

AMBIENT TEMPERATURE (Tq), °C. Figure 5. Power Dissipation (PD vs Ambient Temperature (Ta) Table 7. Power Dissipation and Junction Temperature vs Table 8. Power Dissipation and Junction Temperature vs

AC ELECTRICAL SPECIFICATIONS DEFINITIONS The AC specifications presented consist of output delays, input setup and hold times, and signal skew times. All signals are specified relative to an appropriate edge of the clock and possibly to one or more other signals. The measurement of the AC specifications is defined by the waveforms shown in Figure 6. To test the parameters guaranteed by Motorola, inputs must be driven to the voltage levels specified in this figure. Outputs are specified with minimum and/or maximum limits, as appropriate, and are measured as shown in Figure 6. Inputs are specified with minimum setup and hold times, and are measured as shown. Finally, the measurement for signal-to-signal specifica- tions is also shown. Note that the testing levels used to verify conformance to the AC specifications does not affect the guaranteed DC operation of the device as specified in the DC electrical characteristics. 3-156 M68000 FAMILY REFERENCE MANUAL MOTOROLA

20 VAUD 20V {/, ~< tou

1. This output timing is applicable to all parameters specified relative to the rising edge of the clock.
2. This output timing is applicable to all parameters specilied relative to the falling edge of the clock
3. This input timing is applicable to all parameters specified relative to the rising edge of the clock
4. This input timing is applicable to all parameters specitied relative to the falling edge of the clock.
5. This timing is applicable to all parameters specified relative to the assertion/negation of another signal

A. Maximum output delay specification. B. Minimum output hold time. C. Minimum input setup time specification. D. Minimum input hold time specification. E. Signal valid to signal valid specification (maximum or minimum). Figure 6. Drive Levels and Test Points for AC Specifications

*With external pullup resistor of 1.1 (L. **Capacitance is periodically sampled rather than 100% tested. MC68010 and are valid only for product bearing date codes of 8827 and later. Figure 7. Clock input Timing Diagram

AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES (Vec =5.0 Vdc +5%; GND=0 Vdc; Ta=TL to TH; see Figures 8 and 9} iti |_emrier [tomer [ 125 aie | pm | eee ri a ff a [e |icatowwnawenveis ite | -| ef -| »f-| [| Panza meaner fowl [T= Pel | (Maximum) [2 [ea won onacrens Femaistinmen’ aan! of] of] al—[~ | [Te JooaninoAS.OSamone tems | | of af wp a] wl] w | cn Asserted (Write} dO a a (Write) [2 [carton was tenance sida f=] @[-] @]-] op | [ is? 5. OS neguestoaaorss Feivaia | sna] | —| | -| »]— [ow | [2 [aS tone DS Reaa) wie Assoned [eg [ a0 | = [os | = [eo [|_| [io [oSwamassereswen tos pw | | —| [fw | [i [rs bSwmnegaes sp | — foe | — Pe | fo | [15 fovsk ono con assign inpacinws | woner [—- | © | — | | wpm | [7 PS OS negaessonwinais sm | | w[- |») — [ow | [et loca tenon tonnes Pew | o| @| of «| 0] w[ | [20 Joost omonituow were irom | of =f ef «| of oe | [one Of Asserea on Wvaiawesd [sw | — | wf —- | 0] — | | ve | [2m paces vaistoniiowwed wm | @|—] af[—[ o|—] | | 214? fre vaidtonWtow ite [weve [oo | — | oo [= [oo [= [oe | | 222 [RiiLow io BS assened wie) | muse | oo | — [oo [ = [ao | = [ve | [2s [ocatowodasouveawe _[raoot-| @f-| »[-| =| m | [2 [is oS neges wos oninaiawne [sor | - | wf - | a] — [| [2 [owen vate cost ow Seip tne twa | wa |v] —[ wf — | w[— [os] | 27A% [tate BERR Assertedio Cocktow ‘Soup Time) [ween | as | — [as | — [os | [oe | a (Asynchronous Hold) i (Hold Time on Read) [aa 5.05 nego ovainen moses —[omaz | — [wr [wo] — [of | [30 FS. 0S neoweao BER ewes [suse 0 | |] @|— | | | 212-5 [DTACK Assorted to Datatn Vala Setup Timed | eomumi[ — | so | — [os [= [so [os | |_22_[RACT and RESET input Transiton Time | tater [0 | 200 [0 [ 200 [0 [ 200 | ns_| [22 [occkigh oat assened Pec | — |e | | oo [= [ao fe | [24 [otoceHignio@nevated tcc [ — [oe | — [so | — [of os | [as BasenesoaGasenea one vs a= [vs [3s [ve as [om | MOTOROLA M68000 FAMILY REFERENCE MANUAL 3-159

(Continued) characteristic |_smrer | tomies | 125 wie | 37A8 |BGACK Asserted to BR Negated tGacrH} 20] 1.5 | 20] 15 | 20] 15 Clks Ciks Clks 38 |BG Asserted to Control, Address, Data Bus High tGLz 70 Impedance (AS Negated) 45. |E Low to Control, Address Bus Invalid teLcal | 30 10 10 ns (Address Hold Time} [sie wih tow [ex _[m[— [oo [ — [ao] — | oe | “These specifications represent an improvement over previously published specifications for the 8-, 10-, and 12.5-MHz MC68010 and are valid only for product bearing date codes of 8827 and jater. NOTES 1, For a loading capacitance of less than or equal to 50 pF, subtract 5 ns from the value given in the maximum columns. 2. Actual value depends on clock period 3. In the absence of DTACK, BERR is an asynchronous input using the asynchronous input setup time (#47) 4. For power-up, the MC68010 must be held in the RESET state for 100 ms to allow stabilization of on-chip circuitry. After the system is powered up, #56 refers to the minimum pulse width required to reset the processor 5. If the asynchronous input setup time (#47) requirement is satisfied for DTACK, the DTACK asserted to data setup time (#31) and DTACK asserted to BERR asserted setup time (#48) requirements can be ignored. The data must only satisfy the data-in to clock iow setup time (#27) for the following clock cycle, and BERR must only satisfy the late BERR asserted to clock-low setup time (#27A) for the following clock cycle 6. When AS and R W are equally loaded (= 20%), subtract 5 ns from the values given in these columns. 7. The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before asserting BGACK. 8 The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be reasserted. _— 9. The falling edge of Sé6 triggers both the negation of the strobes (AS and xDS) and the falling edge of E. Either of these events can occur first, depending upon the loading on each signal. Specification #49 indicates the absolute maximum skew that will occur between the rising edge of the strobes and the falling edge of E 3-160 M68000 FAMILY REFERENCE MANUAL MOTOROLA

1. Setup time for the asynchronous inputs IPL2-IPLO and VPA (#47) guarantees their recognition at the

nex! falling edge of the clock.

1. BR need fall at this time only to ensure being recognized at the end of the bus cycle.
2. Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V,

range such that the rise or fallis linear between 0.8 V and 2.0 V. Figure 8. Read Cycle Timing Diagram

1. Timing measurements are referenced to and from a low voliage of 0.8 V and a high voltage of 2.0 V,

range such that the rise or fall is linear between 0.8 V and 2.0 V.

1. Because of loading variations, R/W may be valid after AS even though both are initialed by the rising edge

Figure 9. Write Cycle Timing Diagram

AC ELECTRICAL SPECIFICATIONS — PERIPHERAL CYCLES TO M6800 (Vee =5.0 Vde= 5%; GND =0 Vdc; Ta=TL to TH, see Figures 10 and 11) [12° |clock Low to AS, DS Negeted wasn | — | 2 | = [so [= [a0 [ns | [187 [Clock High to RW High (Read) cus [0 | ss [0 [as [0 | a0 [ns | | 20" [clock High to AW Low (write wont [| of ss [of as | o[ 40 [ns | | 23 [Clock Low to Data-Out Valid (Write) tco | — | 2 | — [50 [ — | 50 | ns | Data-In Valid to Clock Low (Setup Time of Read) tice [of ~ [wo] — | wl — Jos | AS, DS Negated to Data-in Invalid tSHDII ns (Hold Time on Read) } 45 |E Low to Control, Address Bus Invalid tercar | 30 10 ns (Address Hold Time) Asynchronous Input Setup Time | ws [0 | — To [= To [= Tas | [_ 49? |S, 0S, Negated to E Low tsuer_| 70] 70 | -s5[ ss [ -as [45 | ns | [eee win i [een [— [oe | — Pao ee [a [rm [—0 [ oo E Low to Data-Out Invalid teroor | 20 | — | [J is] = [is | *These specifications represent an improvement over previously published specifications for the 8-, 10-, and 12.5-MHz MC68010 and are valid only for product bearing date codes of 8827 and later. NOTES: 1, For a loading capacitance of less than or equal to 50 pF, subtract 5 ns from the value given in the maximum columns. 2. The falling edge of S6 triggers both the negation of the strobes (AS and xDS) and the falling edge of E. Either of these events can occur first, depending upon the loading on each signal. Specification #49 indicates the absolute maximum skew that will occur between the rising edge of the strobes and the falling edge of E. MOTOROLA M68000 FAMILY REFERENCE MANUAL 3-163

Figure 10. MC68010 to M6800 Peripheral Timing Diagram (Best Case)

iS) y S Cth @RGLY 3 pyy A oo) em 6 eae A] 2 2 A A 8 4 A g 3 ® * @ & ao = S iS) a o 3 = > & ATA $ 6S : K t _3 > $ : g § 3 8 > 2 2€ : 2) i 2 = 6 = ; 2 ¢ : < - . BOE 2 - = g 2 = q s o . i 8 = 3 = = 8 °o S : 2 8 * 5 ¢ 8B, va 3 ic ey Gy" } § ° a 8 é 8 ze & & 5 3 MOTOROLA M68000 FAMILY REFERENCE MANUAL 3-165

AC ELECTRICAL SPECIFICATIONS — BUS ARBITRATION (Vcc =5.0 Vde + 5%; GND=0 Vde; Ta=TL to TH; see Figures 12-15) fmm | owmene [mn tt te 7 [Clock High to Address, Data Bus High tcHADZ 70 Impedance (Maximum) [16 _[Ciock High to Control Bus High Impedance toucz | — | eo | — | ro | — | 0 [os | Clock High to 8G Assented ono. | ~ | 62 | — | so | = | ao [ns | | 34 [Clock High to 8G Negated tcnon | — | 62 | — | 0 | — [a0 [ ns | | 35 [eR Asserted to BG Asserted 'BRLGL [is [as [is [as [is [as [cis | 3 [_ 36" [BR Negated to BG Negated tBRHGH | 37_[BGACK Asserted to BG Negated tac | 15 | as | 1s [35 [15 | 35 [cs | 37A?_|BGACK Asserted to BR Negated 'GALBRH 15 | 20 | 15 | 20 | 15 Ciks Chks Clks 38 [BG Asserted to Control, Address, Data Bus tGLz 70 High Impedance (AS Negated) [39 _ [66 wiath Negated | ton [is | — [rs | — [iis | = [ens | | 46 _|BGACK with Low [ toa [os | — [rs [= [is | — [eis | | 47 [Asynchronous input Setup Time [asi | to | — | wo | = [io [| os | | 57_|BGACK Negated to AS, DS, RW Driven tgaso | 18 | — [rs [= [vs | — [cus | |_57A_|BGACK Negated to FC, VMIA Driven wearo | 1 {| — | + [— [1 | — [ous | | 52" _[BR Negated to AS, DS, AW Driven wauso | 15 | — | re | — [15 | — | cus | BR Negated to FC, VA Driven Lsweo | +f — [| 1 PJ] i] ~ [ous | “These specifications represent an improvement over previously published specifications for the 8-, 10-, and 12.5-MHz MC68010 and are valid only for product bearing date codes of 8827 and later. NOTES: _ _ 1. The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before asserting BGACK. 2. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be reasserted. 3-166 M68000 FAMILY REFERENCE MANUAL MOTOROLA

g s FE) E @) 5 is oa oT je =< Da ® ge £ Ss -¢ E 8 > 3 ® &§ iS) ® a 2 ®) $ < ar) an) 82 oa ® as OS & = eet Sy @) Se ge @ 25 | 28 | : : be gz 8 ig g@ 3 29 3 5 Be 2 MOTOROLA Me8000 FAMILY REFERENCE MANUAL 3-167

NOTE: Waveform measurements for all inputs and outputs are specified at: logic high = 2.0 V, logic low = 0.8 V. Figure 13. Bus Arbitration Timing — Idle Bus Case

NOTE: Waveform measurements for all inputs and ‘oulputs are specified at: logic high = 2.0 V, logic low = 0.8 V. Figure 14. Bus Arbitration Timing — Active Bus Case

NOTE: Waveform measurements for all inputs and outputs are specified at: logic high = 2.0 V, logic low = 0.8 V. Figure 15. Bus Arbitration Timing — Multiple Bus Requests

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