MC6800 MOTOROLA | Alldatasheet
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8-BIT MICROPROCESSING UNIT (MPU) The MC6800 isa monolithic8-bitmicroprocessorforming the central controlfunctionforMotorola’sM68~ family.Compatible with TTL, the MC6B~, as with allM6800 system parts,requiresonly one + 5.O-volt power supply,and no externalTTL devices forbus interface. The MC6800 iscapable of addressing64K bytes of memory with its 16-bitaddress lines.The 8-bitdata bus isbidirectionalas wellas three- state,making directmemory addressing and multiprocessingapplica- tionsrealizable.
- 8-BitParallelProcessing
- BidirectionalData Bus . 16-BitAddress Bus – WK Bytes of Addressing
- 72 Instructions– VariableLength . Seven Addressing Modes – Direct,Relative,Immediate, Indexed, Extended, Impliedand Accumulator
- VariableLength Stack ,>:,,*!.“)!.IC,[ . Maskable InterruptVector ‘~”‘%1*F. . Separate Non-Maskable Interrupt– InternalRegistersSaved i#’’::$$ ~..!’. . Six InternalRegisters– Two Accumulators, Index Regist~#?Y’:Y’ Program Counter, Stack Pointerand Condition Code Re~@te~
- DirectMemory Addressing (DMA) and MultipleP~@$esso’r
- Simple Bus InterfaceWithout TTL ,$~~~~i$~’
- Haltand Single InstructionExecutlo*k$~~$bility ,,,~~&Y@’DERING INFORMATION.. w<, .-1.$,) PackageType‘$:,~~equency (MHz) Temperature OrderNumber ceramic+,,:,~f~ “ 1.0 Ooc to70°c MC6800L s suffix 1.0 –40°C to85°C MC@WCS
1.5 O“c to70°c Mc68Ams
1.5 –40°C to85°C Mc68Amcs
2.0 O“c to70°c MC68BOOS
Plastic 1.0 O“c to70°c M C6800P P Suffix 1.0 –40°C to85°C MC6800C P
1.5 O“c to70°c MC68AOOP
1.5 – 40°C to85°C MC68AOOCP
2.0 Ooc to70°c MC68BOOP
I SUFFIXuu. - CERAMIC PACKAGE CASE 715 PIN ASSIGNMENT Vss[ 10 ~ JRESET HALT[ 2 39 ]TSC @l [ 3 38 ]N. C. KQ [ 4 37 342 VMA [ 5 36 ]DBE m[ 6 35 ]N, C. BA [ 7 34 ]Rl~ Vccc 8 33 ] DO AC [ 9 32 ]Dl Al [ 10 31 ] D2 A2 [ 11 30 ] D3 A3[ 12 29 ] D4 A4[ 13 28 ] D5 A5 [ 14 27 ] D6 A6 [ 15 26 ] D7 A7 [ 16 25 ]A15 A8 [ 17 24 ]A14 A9 [ 16 23 JA13 A1O c 19 22 ]A12 Al 1q 20 21 Jvss MOTOROLA INC., lW DS9471-F
M C6~C M C68A~C I I -40to +85 I I Storage Temperature Range I Tsta l-55to +150 I “C I THERMAL RESISTANCE Rating Symbol Value Unit PlasticPackage Im Cerdip Package eJ A 60 “Clw Ceramic Packaqe m POWER CONSIDERATIONS The average chip-junction temperature, TJ, in ‘C can be obtained from: TJ=TA+(PDo OJA) Where: TA = Ambient Temperature, ‘C This devicecontainscircuitryto protectthe inputs against damage due to high static voltagesor electricalfields;however, itisad- vised that normal precautions be taken to avoid applicationof any voltage higher than maximum-rated voltages to this high- impedance circuit.Reliabilityof operation is (1) OJA= Package Thermal Resistance, Junction-to-Ambient, “C/W ;F’s~; ,.,\\\\wy\\~.::$,i~ For most applications PPORT< PINT and can be neglected. P$o~~ may become significant ifthe device is configured to drive Darlington bases or sink LED loads. %i*\\:,+,:,,,**F..,,,.,,\\+,* An approximate relationship between PD and TJ (ifPpO~~$YWbglected) is: ,.>,,,. Solving equations 1 and 2 for K gives: ,J,t::i,}.,(*;{:\\ Where K isa constant pertaining to the parti~$~$~~~it. K can be determined from equation 3 by measuring PD (atequilibrium) for a known TA. Using thisvalue of K the va~~~~:Qft,@Dand TJ can be obtained by solving equations(1) and (2)iterativelyfor any (Vin=Ot&@&~~, Vcc= Max) Logic (Vin~&!0,~~@5 V, Vcc=o V to 5.25 V) Hi-~@bkti@akage Current @l, #2 D&D7 f~#’@&.4 to 2.4 V, Vcc = Max) AO-A15, Rlw ~w~? High Voltage ‘$$lLoad= - 205tiA, Vcc= MinJ DO-D7 “(lLoad= – 1454A, VCC= Min) A&A15, R/~, VMA (lLoad= – 100KA, VCC= Min) BA Output Low Voltage (lLoad= 1.6 mA, VCC = Min) InternalPower Dissipation(Measured at TA = TL) Capacitance (Vin=O, TA=250C, f=l.O MHz) ~1 DGD7 Logic Inputs AO-A15, Rl~, VMA Svmkl VOH VOL PINT Cin Cout VSS–0,3 – VSS+O.8 v VSS–0,3 – VSS+O.4 — 1,0 2.5 PA , [ 1 I VSS+2.4 – – VSS+2.4 – – v VSS+2.41 – I – I I— ! — Ivss+o w,4 v — I 0.5 ] 1,0 w I I I I — 25 35 — 45 70 pF — 10 12.5 — 6.5 10 — — 12 pF (M)MOTOROLA Semjconducfor Products Inc.
CLOCK TIMING (Vcc= 5,0V, *5%, VSS=O, TA=TL to TH unless otherwise noted) Characteristic Symbol Min Typ Max Unit Frequency of Operation MC~ 0.1 – 1.0 MC68AO0 f 0.1 – 1.5 MHz MCWBW 0.1 – 2.0 Cycle Time (Figure1) M Cm 1.000 – 10 M C@AW tcyc O.m — 10 ps MC~BW O.m – 10 Clock PulseWidth @l, @2 – MCmN w – 9m (Measured atVCC– 0.6 V) @l, @2 – MC6BAO0 pW~H Za – 9m ns M C~A~ t“t MC6BBW Rise and FallTime (Measured between VSS +0.4 and VCC– O.6) tr,tf — — 1 Delay Time or Clock Separation (Figure1) , ,,,, (Measured at VOV=VSS+O.6 V@tr=tf=l~ ns) td o %$*t& ns,>+1,:,, (Measured at VOV= VSS + 1.0 V@tr=tf S35 ns} o –$; y<“$,~—.$:~, ?\\:i..$\\*.’, td+ + ‘d+ b,’’” vl~c* ..,,,.,, < Character@i&$iF,~~’ Symbol Unit~\\+,\\-i Min Typ Max Min Typ Max Min Typ Max*,. : ~,t~,,,:y..,,. PeripheralRead Access ~fi&~f: Input Data H@me ‘ tH 10 – – 10 – – 10 – – ns Output D~@ ‘~l,#Time tH 10 25 – 10 25 – 10 25 – ns Addressf&,&,Jime (Address, R/~, VMA) tA H 30 50 – 30 a – m 50 – ns Ena~~i~@Time for DBE Input tEH 450 – – 280 – – 220 – – ns Data ~lav Time (Write) tDDW – – 225 – – 2W – – 160 ns Processor Controls Processor Control Setup Time tpcs 2m – – 140 – – 110 – – Processor Control Rise and FallTime tpcr, tpcf – – Im – – 100 – – 100 8US AvailableDelaV tBA – – 29 – – 165 – – 135 ns Hi-ZEnable tTSE o – 40 0 – 40 0 – m Hi-Z DelaV tTSD – – 270 – – 270 – – 220 Data Bus Enable Down Time During @l Up Time tDBE Iw – – 120 – – 75 – – Data Bus Enable Rise and FallTimes tDBEr, tDBEf – – 25 – – 25 – – 25 — m M070ROLA Semiconductor Products Inc.
FIGURE 2 – READ DATA FROM MEMORY OR PERIPHERALS Start of Cycle @l ‘VIHC ~ 0.4v 7 0.4v Data Not Valid ~ Start of Cvcle ‘):., [ Data 2.4 V From MPU 0.4v I k\\\\\\\\\\\\Y Data Not Valid ktDDw+ NOTES: 1. Voltage levelsshown are VLSO.4, VH> 2.4 V, unless otherwise specified 2. Measurement pointsshown are 0.8 V and 2.0 V, unless otherwise noted MOTOROLA Semiconductor Produck Inc.
I FIGURE 7 – =PANDED BLOCK DIAGRAM A15 A14 A13 A12 All A1O A9 A8 A7 A6 A5 A4 A3 A2 Al AO Clock, @l Clock, @2 RESET Non-Maskable Interrupt HALT Interrupt Request Three-State Control Data Bus Enable Bus Available Valid Memory Address Read/Wtite, Rl~ a Instruction
4 Decode
39 Control
MOTOROLA Semiconductor Products Inc.
To debug programs it is advantageous to step through Iinesare back on the bus. Asingle byte, 2 cycle instruction programs instruction byinstruction .To do this, HALT must such as LSRisused forth isexample also. During the firstcy- be brought high for one MPU cycle and then returned low as cle, the instruction Y is fetched from address M+l. BA shown at point B of Figure 13. Again, the transitions of returns high at tBA on the last cycle of the instruction in- HALT must occur tpcs before the trailingedge of $1. BA dicating the MPU is off the bus. Ifinstruction Y had been willgo low at tBA after the leading edge of the next @l, in- three cycles, the width of the BA low time would have been dicating that the Address Bus, Data Bus, VMA and Rl~ increased by one cycle. FIGURE 10 – MPU FLOWCHART f Y 1 +BA Y I 1 Reset isrecognizedat any positioninthe flowchart. Instructionswhich affectthe l-Bitact upon a on~bh bufferregister, “lTMP.” This has the effectof delayingany CLEARING of the l-Bitone clocktime. Settingthe l-Bit,however, isnot delayed. See Tables 6-11 for detailsof Instruction Execution. m MOTOROLA Semiconductor Products Inc.
MC~ controlprograms. The MC66W has a set of 72 dif- address isobtained during execution. Table 1. There are 197 validmachine codes, 59 of the 256 ~ i~~~
- Unassign4 code indicated by J# * )‘.
01 CMP
70 N EG
73 COM
74 LSR
77 ASR
78 ASL
79 ROL
33 PUL B
34 DES
35 TXS
36 PSH A
37 PSH B
39 RTS
m MOTOROLA Semiconductor Products Inc.
Complement, 1’s Complement, 2’s (Negate) Dec!mal Adi.st, A Decrement ExcI”si”e OR Increment Load Acmltr Or, Inclusive Push Oata Pull Oata Rotate Left Rotate R,ght Shift Left, Ar!thmet!c Sh[ft Right, Arfthmet!c Sh!f! Right, Logic Store Acmltr. Subtract Subtracf Acmltrs. ADDA ADOB ABA AOCA AOCB ANDA ANOB BITA BITE CLR CLRA CLRB CMPA CMPB CBA COM COMA COMB NEG NEGA NEGB OAA OEC oECA OECB EORA EORB INC INCA INCB LOAA LDAB O RAA ORAB PSHA ?SHB PU LA PU LB ROL ROLA ROLB ROR RORA RORB ASL ASLA ASLB ASR ASRA ASRB LSR LSRA LSRB Arithmetic Minus; Boolean ANO: MSP contents Of memow location pointed to be Stack Pointer: Boolean Inclusive OR; & Boolean Exclusive OR; M Complement of M; + Transfer Into; o Bit = Zero;
00 Byte = Zero;
1P-= CON OtTION CODE SYMBOL5 H Hal f.carrv from bit 3; I Interrupt mask N Negative (tign bit) z Zero (byte) v Ovetilow, 2’s complement c Carv from bit 7 R Rewt Always s Set Alwav$ IMPLIEO 1P-= B21 F21 F21 121 1321 i321 lo2f io21 1921 IA21 ,A21 1C21 iC21 !9 2 j9 2 !6 2 j6 2 $8 2 58 2 a7 2 57 2 44 2 54 2 10 2 16 2 17 2 $0 2 50 2 I I BOOLEAN/ARITHMETIC OPERATf ON (All register labels refer to contents) A+ M-A B+M+B A+ MSp, SP-f-SP B-, Msp, SP–l+SP SP+I-SP, MSP-A SP+I+SP, MSP-B M A B }L-’’’’””Jc b7 - bO M A B lk-’’’’”[dc b7 — bO M A o-~ - 0 B b7 bO C A’-M B-M A– M-A B– M-B A– B-A A–M– C-A B- M– C-B A-B B-A M–00 A–00 B–DO CON OITION COOE REGISTER NOTES: (Bit Set if testis true and cleared otherwise] 1 (BitV) Test: Result = 1000OOOO7 2 (Bit C) Test: Result = 000000007 3 (Bit C) Test: Oecimal value of most significant BCO Character greater than nine? ( Not cleared if previously set.] 4 (BitV) Test: Operand= 10000000 priorto execution? 5 (BitV) Test: Operand= 01111111 priorto execution? t Test and set if true, cleared otherwise 6 (BitV) Test: Set equal to resultof N@C aftershifthas occurred
- Not Affected Note – Accumulatoraddresbngmode instructionsareincludedin tho column for IMPLIEO addressing MOTOROLA Semiconductor Products Inc.
PROGRAM CONTROL OPERATIONS Program Control operation can be subdivided into two categories:(1)Index Register/Stack Pointerinstructions;(2) Jump and Branch operations. Index Register/Stack PointerOperations The instructionsfordirectoperationon the MPU’S Index Register and Stack Pointer are summarized in Table 3. Decrement (DEX, DES), increment (INX, INS), load (LDX, LDS), and store (STX, STS) instructionsare provided for both. The Compare instruction,CPX, can be used to com- pare the Index Registerto a 16-bitvalueand update the Con- ditionCode Registeraccordingly. The TSX instructioncauses the Index Registerto be load- ed with the address of the lastdata byte put onto the “stack.” The TXS instructionloadsthe Stack Pointerwith a valueequalto one lessthan the currentcontentsof the Index Register.This causes the next byte to be pulledfrom the “stack” to come from the locationindicatedby the index Register.The utilityof these two instructionscan be clarified by describingthe “stack” concept relativeto the M@W system. The “stack” can be thought of as a sequentiallistof data stored inthe MPU’S read/writememory. The Stack Pointer containsa 16-bitmemory address thatisused to access the listfrom one end on a last-in-first-out(LIFO)basisincontrast to the random access mode used by the MPU’S other ad- dressingmodes. The MC~ instructionset and interruptstructureallow extensiveuse of the stack concept forefficienthandling of data movement, subroutinesand interrupts.The instructi~.os can be used to establishone or more “stacks” anywhg~~~< read/write memory. Stack length is limitedonly <,q~$~~e amount of memory that ismade available. .,is,~,., Operation of the Stack Pointerwith the Pus@,@i~~,Rtillin- structionsisillustratedin Figures 15 and 1~~..%~.$ush in- struction(PS HA) causes the contents ofkd$~~icated ac- cumulator (A inthisexample) to be stor~+in;wemory at the locationindicatedby the Stack Point@r.~Q&Stack Pointeris automaticallydecremented by ~~~~$~t~wing the storage operationand is“pointing”to th~~:~e{$emptystacklocation. The Pullinstruction(PULA ..@~:~%’B)causes the lastbyte stacked to be loaded intothe:w’ropriate accumulator. The Stack Pointerisautomaticallyincremented by one justprior to the data transferso thatitwillpointto the lastbyte stack- ed ratherthan the next empty location.Note thatthe PULL instructiondoes not “remove” the data from memory; inthe example, 1A isstillinlocation(m+ 1)followingexecutionof PULA. A subsequent PUSH instructionwould overw~jt~~at Executionofthe Branch to Subroutine (BSR)a$d.#~rrfpto Subroutine (JSR) instructionscause a returD%~*~ to be saved on the stack as shown in Figures18$~w~@20. The stack isdecremented aftereach byte of,.#$r@?n address is pushed onto the stack. For both of$&~~N@structions, the returnaddress isthe memory locatid~f~jo’wingthe bytes of code thatcorrespond to the B,S$.:an’~:$&SRinstruction.The code requiredfor BSR or Jg~g”~<y be eithertwo or three bytes,depending on whet~r,%~.J S R isinthe indexed (two bytes) or the extende~$~$~$@ bytes) addressing mode. Before itisstacked,t@<&~$Yam Counter isautomaticallyin- cremented the correctRgmber of times to be pointingatthe locationof the ~$~~~$truction.The Return from Subroutine lnstruction,,,@K$~~pusesthe returnaddress to be retrieved and Ioade@ I$tot~e Program Counter as shown inFigure21. There $r~s~$eral operationsthat cause the statusof the M PU.,$0b$wved on the stack.The Software Interrupt(SWI) and$%ait for Interrupt(WAI) instructionsas well as the ~?~,ah~e (~Q) and non-maskable (NMI) hardware inter- -$‘~~@J&allcause the M PU’S internalregisters(exceptforthe,.,,,:f?*,..~,@tackPointeritself)to be stacked as shown in Figure23. “$k MPU statusisrestoredby the Return from Interrupt,RTI, as,,\\. shown in Figure22. Jump and Branch Operation The Jump and Branch instructionsare summarized in Table 4.These instructionsareused to controlthe transferor operationfrom one pointto another inthe controlprogram. The No Operation instruction,NOP, while includedhere, isa jump operationina very limitedsense. Itsonlyeffectisto increment the Program Counter by one. Itisusefulduring program development as a “stand-in” for some other in- structionthatisto be determined duringdebug. Itisalsous- ed forequalizingthe executiontime through alternatepaths ina controlprogram. !*,. .s.. , ‘:. PO 1NT$&Q$~&&?10 NS MNEMONIC OP - = OP - ~ Co mp%~$~:her Reg CPX 8C 3 3 9C 4 2 o~eq~,:~$ndex Reg OEX Oe~.~efit Stack Pntr O ES lnc;&ment Index Reg INX Increment Stack Pntr INS Load Index Reg LOX CE 3 3 OE 4 2 Load Stack Pntr LOS 8E 3 3 9E 4 2 Store Index Reg STX DF 5 2 Store Stack Pntr STS 9F 5 2 Indx Reg +Stack Pntr TXS Stack Pntr * Indx Reg TSX OP— AC EE AE EF AF 162 f OP Bc FE BE FF BF (TNO IMPLIEO I— OP— 30— BOOLEAN/ARITHMETIC OPERATION I X–l+x SP–1-SP X+l+x SP+l+SP MA XH, (M+l) -XL M+ SPH, (M+1)4SPL XH+M, XL+(M+l) SPH+M, SPL~(M+l) X-1-SP SP+l+X @ (Bit N) Test: Sign bit of most significant (MS) byte of result= 1? @ (Bit V) Test: 2s complement o“erfiow from subtraction of m. byte.? @ (Bit N) Test: Result Iesstha” zero? (Bit 15= 1) MOTOROLA Semiconductor Products Inc. — I CO ND. COOEREG
I FIGURE 15 – STACK OPERATION, PUSH INSTRUCTION SP~m .{EI m+l 7F Previously Stacked m+2 63 Data m+3 FD ‘c--(a) Before PSHA MPU m ~’q..i, % (b) Aftar PSHA Pc ~ PULA Next In$tr. MPU I I I ACCA m I m—2 m—1 m SP+m+l mt2 Previously Stacked m+3 Data I P(b) After PULA(a) Before PULA m MOTOROLA Semiconductor Products Inc.
Branch If= Zero Branch If> Zero Branch If>Zero Branch If Higher Branch If< Zero Branch IfLower Or Same Branch If< Zero Branch IfMinus Branch IfNot Equal Zero Branch IfOverflow Clear Branch IfOvefilow Set Branch IfPlus Branch To Subroutine Jump Jump To Subroutine No Operation Return From Interrupt Return From Subroutine So ftwre Interrupt Wait for Interrupt% IAI puts Address Bus, RN, and MNEMONIC BRA BCC B CS BEO BGE BGT BHI BLE B LS B LT BMI BNE BVC BVS BPL BSR JMP JSR NOP RTI RTS Swl WAI ita Businthet TABLE 4 – JUMP AND BRANCH INSTRUCTIONS CONO. COOE REG. RE G G hl— Y z AO m low ..? L I I I I I @ (All) Load Condition Code Register from Stack. (See Special Op$@tic— BRANCH TEST T10 Vc is required to exit the wait state. Execution of the Jump Instruction, JMP, and Branch Always, BRA, affects program flow as shown in Figure 17. When the MPU encounters the Jump (Indexed) instruction, itadds the offset to the value in the Index Register and %, the result as the address of the next instruction to~b~;~x~$ ecuted. In the extended addressing mode, the add[e~~~?he next instruction to be executed isfetched from ,$~$~*~~ca- tionsimmediately following the JM P instructl~~~}K~WBranch Always (BRA) instruction issimilarto the J~~?~#~&nded) in- structionexcept that the relativeaddre&Sin&. fiode applies and the branch is limited to the rang~Wtkm$- 125 or + 127 BRA instruction requires one les$by~ than J M P (extended) but takes one more cycle to @? The effect on program fl~~ f$r the Jump to Subroutine (JSR) and Branch to Sw#rQu{*$ (BSR) isshown in Figures 18 through 20. Note t~%:$@Program Counter isproperlyin- cremented to be$:~~~:n~ at the correct return address before itisstac~&i,;~~#~rationof the Branch to Subroutine and Jump to a~w~’tine (extended)instructionissimilarex- cept forth@~~n~&> The BS R instructionrequireslessopcode than J$$&R{%Q~#esversus 3 bytes)and alsoexecutes one cy- ~ (Bit1) Set when interrupt occurs. if previously set, a Non-MaSk,:~e’’%?errUPt ~+. ‘~.* ‘+~’$..used as the end of a subroutineto returnto the main pro- ~y: gram as indicatedin Figure21, The effectof executing the Software Interrupt,SWI, and the Wait for Interrupt,WAI, and theirrelationshipto the hardware interruptsisshown in Figure22. SW! causes the M PU contents to be stacked and then fetchesthe starting address of the interruptroutinefrom the memory locations thatrespond to the addresses FFFA and FFFB. Note thatas in the case of the subroutine instructions,the Program Counter isincremented to pointatthe correctreturnaddress before being stacked.The Return from Interruptinstruction, RTI, (Figure22) isused at the end of an interruptroutineto restorecontrolto the main program. The SWI instructionis usefulforinsertingbreak pointsinthe controlprogram, that is, it can be used to stop operation and put the MPU registersinmemory where they can be examined. The WAI instructionisused to decrease the time requiredto servicea hardware interrupt;itstacks the MPU contents and then waits for the interruptto occur, effectivelyremoving the stackingtime from a hardware interruptsequence, FIGURE 17 – PROGRAM FLOW FOR JUMP AND BRANCH INSTRUCTIONS [X+K~ [ ,,-, (n+2)*Klxl● K = Signed 7-bitvalue (a)Jump (b)Branch m MOTOROLA Semiconductor Products Inc.
SP-m–2 m—1 m m+l n n+l nt2 nt3 FIGURE 21 – PROGRAM FLOW FOR RTS H m—2 (n+3)H m—1 SH = Subr. Addr. n+l SL = Subr. Addr. n+2 I BLast Subr. Instr. R TS Pc — J a Last Inter. Instr. RTI FLOW FOR RTI m—7 m—6 m—5 m—4 m—3 m—2 m—1 sp~ m Pc— “+1 CCR ACCB ACCA XL PCH PCL I Next Main I“str. I I Last S“br. Instr. I (a) Before Execution (b) After Execution MOTOROLA Semiconductor Products Inc.
I FIGURE ~ – PROGRAM FLOW FOR INTERRUPTS Wait For Hardware Interruptor Interrupt NonMaskable Interrupt(NMI) SoftwarelnterruDt Main Program’ n:=. Main Program Main Program :1= n- 7“Sp + Stack MPU RegisterContents m—7 m—6 m—5 m—4 m—3 m—2 m—1 m WI FFF8 FFFC FFF9 FFFD FFFE FFFF dSet Interrupt Mask (CCR 4) InterruptMemorv Assignment FFF8 I IRQ I Ms FFF9 IRQ LS FFFA Swl MS FFFB Swl LS# FirstInstr. e BvFetching Addr. Formed Q Load Interrupt Vector Into 2.Eytes From Program Counter Per,Mere, Assign. f A InterruotProaram >,. 1 lstlnterruutlnstr.1NOTE: MS= Most SignificantAddress Bvte; LS = LeastS~nificantAddress Byte; I 1 MOTOROLA Semiconductor Products Inc.
FIGURE 24 – CONDITIONAL BRANCH INSTRUCTIONS BMI : N=l ; BEQ : Z=l ; BPL : N=@ ; BNE : Z=4 ; BVC : V=$ ; BCC : C=$ ; BVS : V=l ; BCS : C=l ; BHI : c+ z=@ ; BLT : N@V=l ; BLS : C+z=l ; BGE : N@ V=@ ; BLE : Z+(N@V)=l BGT : Z+(N@V)=@ ; The conditional branch instructions, Figure 24, consists of seven pairs of complementary instructions.They are used to test the results of the preceding operation and either con- tinue with the next instruction in sequence (test fails)or cause a branch to another point in the program (test suc- ceeds). Four of the pairs are used for simple tests of status bits N, Z, V, and C: 1. Branch on Minus (B MI) and Branch On Plus (BPL) tests the sign bit, N, to determine if the previous result was negative or positive, respectively. 2. Branch On Equal (BEQ) and Branch On Not Equal (BNE) are used to test the zero status bit,Z, to determine whether or not the resultof the previous operation was equal to zero. These two instructions are useful following a Com- pare (CMP) instruction to test for equality between an ac- cumulator and the operand. They are also used following the Bit Test (BIT) to determine whether or not the same bitpos~~ 3. Branch On Overflow Clear (BVC) and Branc@$~ns Overflow Set (BVS) tests the state of the V bitto ~&~*e ifthe previous operation caused an arithmetic Q@r,@~ 4. Branch On Carry Clear (BCC) and Branch @~b$rY Set (BCS) tests the state of the C bitto determ~~$$~~~previous operation caused a carry to occur. BCC ~~,~~~b are useful CONDITION for testing relativemagnitude when the values being tested are regarded as unsigned binary numbers, that is,the values are in the range 00 (lowest) to FF (highest). BCC following a comparison (CMP) will cause a branch if the (unsigned) value in the accumulator is higher than or the same as the value of the operand. Conversely, BCS willcause a branch if the accumulator value is lower than the operand. The fifthcomplementary pair,Branch On Higher (Qi&~~~,nd Branch On Lower or Same (BLS) are, in a se~~~/~@~- plements to BCC and BCS. BHI tests for both C ~n@~~O; if used following a CMP, itwillcause a branc~,?k~~pWalue in the accumulator is higher than the oper&~~%50nversely, BLS willcause a branch ifthe unsignq~’~~a~’”value in the accumulator is lower than or the saW:~$J&b operand. The remaining two pairs are u~~l ~ ‘testing results of operations in which the values at% re&~Yded as signed two’s complement numbers. This $%&&}{rom the unsigned binary case in the following sen:~+~~.{~nsigned, the orientation is higher or lower; in si~w’~,wo’s complement, the com- parison is between @$~~g~&~ smaller where the range of values is between – 1~,.,and + 127. Branch On L@$~$anZero (BLT) and Branch On Greater Than Or Eq~#k.~~~’~~G E) test the status bits for N @V= 1 and N e V{~$<,,r~pectively. B LT willalways cause a branch followin$~~s 8~~ration in which two negative numbers were adde,~. in’~dition, itwillcause a branch following a CMP in wh#~$Jhe value in the accumulator was negative and the ,@$&~~n’&was positive. B LT willnever cause a branch follow- .,:t~@,$#CMP in which the accumulator value was positive and ‘*Ncause. a branch following operations in which two positive ,+::> values were added or in which the resultwas zero. The last pair, Branch On Less Than Or Equal Zero (BLE) and Branch On Greater Than Zero (BGT) test the status bits for Z@ (N+V) = 1 and Z@ (N +V) =0, respectively. The ac- tion of BLE isidenticalto that for BLT except that a branch will also occur ifthe result of the previous result was zero, Conversely, BGT issimilarto BGE except that no branch will occur following a zero result. CODE REGISTER‘i$,:,i;;*,,,1.,. . . .,.y ~ The Condition ~~~~Register (CCR) is a 6-bit register to precede any SEI instruction with an odd opcode – such within the MPU~~~kl$*useful in controlling program flow as NOP. These precautions are not necessary for MC~ during system d;%tlon. The bits are defined in Figure 25. processors indicating manufacture in November 1977 or The instr~~lia~% shown in Table 5 are availableto the user later. for dire~#~@@@ulation of the CCR. Systems which require an interruptwindow to be opened A C~,$A/ instruction sequence operated properly, with under program control should use a CLI-NOP-SEI sequence earl~:~~$~~ processors, only ifthe preceding instruction rather than CLI-SEI. was $~d (Least Significant Bit= 1), Similarlyitwas advisable MOTOROLA Semiconductor Products Inc.
L CO ND. COOE REG. E= BOOLEAN OPERATION
1 O+c
1 O+v
1 A+CCR
1 CCR+A
- 00m* R
- .mm R.
- Ore** s
- S. *Q.
- **O s. w The M P&%~&$ates on 8-bit binary numbers presented to it via the..~t~~~?{~us. A given number (byte) may rePresent eithe&~{~~@:or an instruction to be executed, depending on w@.@/~,~s encountered in the control program. The Mm ha$~~tinique instructions, however, itrecognizes and takes actloh on 197 of the 256 possibilitiesthat can occur using an 8-bit word length. This larger number of instructions results from the fact that many of the executive instructions have more than one addressing mode. These addressing modes referto the manner in which the program causes the MPU to obtain itsinstructions and data. The programmer must have a method for addressing the MPU’S internalregistersand allof the external memory loca- tions. Selection of the desired addressing mode is made by the user as the source statements are written. Translation into MOTOROLA appropriate opcode then depends on the method used. If manual translation is used, the addressing mode is inherent in the opcode. For example, the immediate, Direct, Indexed, and Extended modes may allbe used with the ADD instruc- tion. The proper mode is determined by selecting (hex- adecimal notation) 8B, 9B, AB, or BB, respectively. The source statement format includes adequate informa- tion for the selection if an assembler program is used to generate the opcode. For instance, the Immediate mode is selected by the Assembler whenever itencounters the “#” symbol in the operand field.Similarly,an “X” in the operand field causes the Indexed mode to be selected. Only the Relative mode applies to the branch instructions,therefore, the mnemonic instruction itselfisenough for the Assembler to determine addressing mode. Semiconductor Products Inc. ~
For the instructions that use both Direct and Extended “operands” but the space between them and the operator modes, the Assembler selects the Direct mode ifthe operand may be omitted. This is commonly done, resulting in ap- vaiue is in the range O-255 and Extended otherwise. There parent four character mnemonics for those instructions. are a number of instructions for which the Extended mode is The addition instruction, ADD, provides an example of valid but the Direct is not. For these instructions, the dual addressing in the operand field: Assembler automatically selects the Extended mode even if the operand isin the O-255 range. The addressing modes are Operator Operand Comment summarized in Figure 26. ADDA MEM12 ADD CONTENTS OF MEM12 TO j&~$:k or .t;.., Inherent (Includes “Accumulator Addressing” Mode) ADDB MEM12 ADD CONTENTS OF MEM12 %Q #&C~ The successive fields in a statement are normally separated by one or more spaces. An exception to this rule The example used earlierfor the test instru~&~~?ST, also occurs for instructions that use dual addressing in the applies to the accumulators and uses th,$~~~~ohulator ad- operand fieldand for instructions that must distinguish re- dressing mode” to designate which o$,,x’v-accumulators Direct: n DO Instruction Example: SUBB Z Addr. Rane = O–255 A n+l Z = Oprnd Address n+2 Next Instr. (K = One-Bvte Oprnd) z&OR .:,,. (K = Two-Bvte Oprnd) (K = One-Bvte Oprnd) (K = Two-Bvte OPrnd) J ntl ZH = Oprnd Addr-s n+2 ZL = Oprnd Address n+3 Next Instr. OR z [ KH = Operand I *“r, n+2 Next Inst. OR n+2 I KL = Operand I n+3 I Next Instr. I Relative: n I Instruction I Example: BNE K (K = Signed 7-Bit Value) Addr. Range: –125t0 +129 Relative to n. (“+2)’K-~ If Br”ch Tst False, ~ if Brnch Tst True. Indexad: n Instruction I Example: ADDA Z, X ‘+1- Addr. Range: n+2 I Next Instr. O–255 Relative to 1 Index Register, X o (Z = a-Bit Unsignad Value) x+z& MOTOROLA Semiconductor Products Inc.
*:’@o Operator Comment mode, the “address” of the operand is effectively the TSTB TEST CONTENTS OF ACCB memory location immediately following the instruction itself. or Table 7 shows the cycle-by-cycle operation for the im- TSTA TEST CONTENTS OF ACCA mediate addressing mode. A number of the instructions either alone or together with Direct and Extended Addressing Modes – In the Direct an accumulator operand contain allof the address informa- tion that is required, that is, “inherent” in the instruction itself.For instance, the instruction ABA causes the MPU to add the contents of accumulators A and B together and place the result in accumulator A. The instruction INCB, another example of “accumulator addressing,” causes the contents of accumulator B to be increased by one. Similarly,INX, in- crement the Index Register, causes the contents of the Index Register to be increased by one. Program flow for instructions of this type is illustratedin Figures 27 and 28. In these figures,the general case isshown on the leftand a specific example is shown on the right. Numerical examples are in decimal notation. Instructions of this type require only one byte of opcode. Cycle-by-cycle operation of the inherent mode is shown in Table 6. Immediate Addressing Mode – In the Immediate address- ing mode, the operand isthe value that isto be operated on. For instance, the instruction Oper*or Operand Comment LDAA #25 LOAD 25 INTO ACCA causes the M PU to “immediately load accumulator A with the value 25’; no further address reference is required. The Immediate mode isselected by preceding the operand value with the “#” symbol. Program flow for thisaddressing m,~de is illustratedin Figure 29. The operand format allows either properly define$:$ym bols or numerical values. Except for the instru~ti~~’WX, LDX, and LDS, the operand may be any valu~,i~:~e,;~nge O to 255. Since Compare Index Register (C&,~Q$.~~&’d Index Register(LDX), and Load Stack Pointer (~$~;.$e~uire 16-bit values, the immediate mode for these~%re~+ ~tistructionsre- quire two-byte operands. In th~:T~,Yate addressing 4PROGRAM MEMORY Pc INSTR GENERAL FLOW PC = 5000 MPu INDEX a RAM z PROG RAM MEMORY INX t I EXAMPLE and Extended modes of addressing, the operand fieldof the source statement is the address of the value tha$+i$j~o be operated on. The Direct and Extended modes d~ff~$:fi$yin the range of memory locations to which they ~$~~trect the M PU. Direct addressing generates a sin~l~.~~%~ operand and, hence, can address only memory l@~&&~’& O through 255; a two byte operand isgenerated~{&~QEx&&~ded address- ing, enabling the MPU to reach theik~~~J&”hg memory loca- tions, 256 through 65535. An ex~&pl$ O* Direct addressing and itseffect on program flo,~~~ ~&lrated in Figure 30. The M PU, after encoun\\eW@<~e opcode for the instruc- tion LDAA (Direct) at,~~ary location 5004 (Program Counter= 5004), look~~~~$~:~next location, 5005, for the ad- dress of the operan~$~~~{~~ sets the program counter equal to the value foun@ t~~{~100 in the example) and fetches the operand, in t~~~$$e a value to be loaded into accumulator A, from th,~+~p~$$n. For instructions requiring a two-byte operande$~hk~ LDX (Load the index Register),the operand bytes $+~4&Be retrievedfrom locations 100 and 101. Table 8 sh%~ws t~~ cycle-by-cyc4e operation for the direct mode of a*~ssi ng, ,~~’+i$xt~nded addressing, Figure 31, is similar except that a :t:~:+~@-byte address is obtained from locations 5007 and 5008 ~~,,.$$tafterthe LDAB (Extended) opcode shows up in location “e$s 5006. Extended addressing can be thought of as the “stan- ~y>t,$ dard” addressing mode, that is,itis a method of reaching any place in memory. Direct addressing, since only one ad- dress byte is required, provides a faster method of process- ing data and generates fewer bytes of control code. In most applications, the direct addressing range, memory locations O-255, are reserved for RAM. They are used for data buffer- ing and temporary storage of system variables, the area in which faster addressing is of most value. Cycle-by-cycle operation isshown in Table 9 for Extended Addressing. FIGURE Z – ACCUMULATOR ADDRESSING MPU F RAM pROGRAM MEMORY B Pc w INSTR GENERAL FLOW M Pu mACCB m RAM aPROGRAM MEMORY PC = 5001 INC B EXAMPLE MOrOROLA Semiconductor Producfs Inc.
RelativeAddress Mode – Inboth the Directand Extended the unconditionaljump (JMP), jump to subroutine (JSR), nodes, the address obtained by the MPU is an absolute and returnfrom subroutine(RTS) are used. ~umerical address. The Relative addressing mode, im- In Figure 32, when the MPU encounters the opcode for )Iemented for the MPU’S branch instructions,specifiesa BEQ (Branch ifresultof lastinstructionwas zero),itteststhe nemory locationrelativeto the Program Counter’s current Zero bitinthe ConditionCode Register.Ifthatbitis“O,” in- Dcation.Branch instructionsgeneratetwo bytesof machine dicatinga non-zero result,the MPU continues execution :ode, one for the instructionopcode and one for the with the next instruction(inlocationWIO inFigure32).Ifthe ‘relative”address (see Figure32).Since itisdesirableto be previous resultwas zero, the branch conditionissatisfied ibleto branch ineitherdirection,the 8-bitaddress byte isin- and the MPU adds the offset,15 inthiscase,to PC+ 2 and erpretedas a signed 7-bitvalue;the 8th bitof the operand is branches to locationW25 forthe next instruction. rested as a sign bit,“O”= plus and “1”= minus. The re- The branch instructionsallowthe programmer to efficient- naining seven bits represent the numerical value. This Iydirectthe MPU to one pointor another inthe contro$.:~ro- esultsina relativeaddressingrange of * 127 with respectto gram depending on the outcome of testresults.~W~%e he locationof the branch instructionitself,However, the controlprogram isnormallyinread-onlymemory #ti~$@not )ranch range iscomputed with respectto the next instruc- be changed, the relativeaddress used inexecu@~~@t&ranch ion thatwould be executed ifthe branch conditionsare not instructionsis a constant numerical valuq~’~~~@-by-cycle iatisfied.Since two bytesaregenerated,the next instruction operationisshown inTable 10 for relatig&a~Q@ssing. s located at PC + 2. IfD isdefined as the address of the .}:\\A,#‘~,\\ .!-,s.,,i, )ranchdestination,the range isthen: Indexed Addressing Mode – ~~~~d~xed addressing, -!l!,.,,, (PC+2)– 127SD S(PC+2)+127 the numericaladdress isvariableqnd d~ends on the current )r contents of the Index Register@~~$ourcestatement such as.+:Y> hat is,the destinationof the branch instructionmust be Comment STAA X Ut;;:~@&T A IN INDEXED LOCATION vithin– 125 to + 1.29memory locationsof the branch in- *\\+~*%\\.g;~: TABLE 6 – INHERENT MODE CYCLE-BY-CYCLE ~~~~*lON Addre* Mode Cycle VMA ,,+?,:~,,@ ~~’lw and Inmructions Cycles # Lina Address Bus ~t.:.:~’Lina,% Data Bus.r]i, .,,.<,;,,,..-, ABA DAA SEC 1 1 Op Code Address
1 Op Code
ASL DEC SE I ~.i: .$. ASR INC SEV 2 1 OP Code Addrass + 1 ~*.st,&$f~ 1 Op Code of Next Instruction CLC NEG TAP .,?- CLI NOP TBA >~:k(.’ CLR ROL TPA .fi ~~~~, CLV ROR TST ,~~~i~., COM SBA ,\\,,,.\\:$.>, , ..*Y-. “’?. DES 1 1 0 p$**j$dHress 1 Op Code DEX INS 4 2 1 ~~.~~$$e Address+ I 1 Op Code of Next Instruction INX 3 0 *$~~$~~us RegisterContents 1 Irrelevant Data (Note 1 ) 4 1~..~<f;~~~~w Register Contents Irrelevant Data (Note 1 ) PSH 1 ,/S* ‘$~~~?.$OP Code Address 1 Op Code 4 .,t~,.:!,),,,$ Op Code Addrass + 1 1 Op Code of Next Instruction g 3 ‘$$,“’”, Stack Pointer o Accumulator Data ~,q~p.~ # o>,. Stack Pointer – 1 1 Accumulator Data .,. PUL ?4>,,~j$ , ,., .,. Op Code Address 1 Op Code ,{,:.-~\\\\, Op Code Address + 1 1 Op Code of Next instruction $~” ...“J~ 4 2 1 Op Code Address+ 1 1 Op Code of Next Instruction TX$~~~W ““ 1 1 Op Code Address 1 Op Code y;. 4 2 1 OP Code Address+ 1 1 Op Code of Next Instruction 3 0 Index Register 1 Irrelevant Data 4 0 New Stack Pointer 1 Irrelevant Data RTS 1 1 OP Code Address 1 Op Code 2 1 OP Code Address+ 1 1 Irrelevant Data (Note 2) 5 3 0 Stack Pointer 1 IrrelevantData (Note 1 ) 4 1 Stack Pointer + 1 1 Address of Next Instruction (High Order Byte) 5 1 Stack Pointer + 2 1 Address of Next Instruction (Low Order Byte) M070ROLA Semiconductor Products Inc.
TABLE 6 – INHERENT MOOE CYCLE-BY-CYCLE OPERATION (CONTINUED) I Address Mode CVcle VMA R lx and Instructions Cycles # Line Address Bus Line Data Bus WA I 1 1 Op Code Address 1 Op Code 2 1 Op Code Address + 1 1 Op Code of Next Instruction 3 1 Stack Pointer o Return Address (Low Order Byte) 4 1 Stack Pointer – 1 0 Return Address (High Order Byte) ‘Q,,x, 9 5 t:f,s:.,.;:~;$$* 6 1 Stack Pointer – 3 0 Index Register (High Ord:[O &#}$ 7 1 Stack Pointer – 4 0 Contents of Accumula~~. ~~p~ “p 8 1 Stack Pointer – 5 0 Contents of Accurn,~taYM $: 9 1 \\%*~,\\. Stack Pointer – 6 (Note 3) 1 Contents of CondF@5~,Segister .a>~+m., 2 1 Op Code Address+ 1 1 Irrelevant~ata ~@te 2) 4 1 Stack Pointer + 1 1 CoRW~&~ti Cond. Code Register from S*.@” ,,s. 5 1 Stack Pointer + 2 %ts of Accumulator B from Stack1,4:#&q$ 6 1 Stack Pointer + 3 .3**: ‘%ntents of Accumulator A from Stack 7 1 Stack Pointer + 4 ‘f$ac ~y~e~ Register from Stack (High Order 8 1 Stack Pointer + 5 Index Register from Stack (Low Order Byte) 9 1 Stack Pointer + 6 ,>;: Next Instruction Address from Stack ,,,,.?,:*. ‘\\.*:, (High Order Byte) 10 1 Stack Pointer + 7 ,,,.y;,:,~,,,. ~;? ~...k. 1 Next Instruction Address from Stack ,$ ~!’>i,,;i) (Low Order Byte) Sw I 1 1 Op Code Addresq&+,t~S 1 .Op Code,, 2 1 Op Code Address ~{~ 1 Irrelevant Data (Note 1) 3 1 Stack Poi$ter ~; o Return Address (Low Order BVte),><~. 4 1 Stack ,~in~~ – 1 0 Return Address (High Order Byte) 5 1 Sta*~hter – 2{!,<, o IndexRegister (Low Order Byte)-... J 1>j$‘:;t*,# Pointer – 4 0 Contents of Accumulator A 8 ,,{’!~$$;$tack Pointer – 5 0 Contents of Accumulator B %~i> ,:,,i:\\$\\i?, $1 ‘ Stack Pointer – 6 0 Contents of Cond. Code Register $:TO ;6:r$o Stack Pointer – 7 1 Irrelevant Data (Note 1) .>’+):$W,$ 1 Vector Address FFFA (Hex) 1 Address of Subroutine (High Order :.+;l+,.:y Byte) t$.~ ? Dependi,n,~ 4Q b~ capacitance, data from the previous cycle may be retained on the Data Bus. Note 2. Data is,@W~@ bv the MPU, Note 3. Whil@?~$~,~PU iswaiting for the interrupt, Bus Available will go high indicating the following states of the control lines:VMA is lo~@~ess BUS, RM, and Data Bus are allin the high impedancaState. ~.~> ,: th$w.~ory location specified by the contents of the Index Re@ter (recallthat the label“X” isreserved to designate the Index Register). Since there are instructions for manipulating X during program execution (LDX, INX, DEC, etc.),the in- dexed addressing mode provides a dynamic “on the fly”way to modify program activity. The operand fieldcan also contain a numetical value that will be automatically added to X during execution. This for- mat is illustratedin Figure 33. When the MPU encounters the LDAB (Indexed) opcode in location 5006, itlooks in the next memory location for the value to be added to X (5 in the example) and calculates the required address by adding 5 to the present Index Register value of 4~. In the operand format, the offset may be represented by a labelor a numerical value inthe range O-255 as in the example. In the earlier example, STAA X, the operand is equivalent to O, X, that is,the O may be omitted when the desired address isequal to X. Table 11 shows the cycle-by-cycle operation for the Indexed Mode of Address- ing, MOTOROLA Semiconductor Products Inc.
FIGURE = – IMMEDIATE ADDRESSING MODE FIGURE 30 – DIRECT ADDRESSING MODE MPU RAM PROGRAM MEMORY I Pc INSTR DATA GENERAL FLOW MPU m ACCA m RAM MPU m RAM ADOR DATA PROGRAM MEMORY II PROGRAM MEMORY ‘C=’oo’w‘C’*EXAMPLE MPU G ACCA m RAM EXAMPLE 1 Address Mode Cycle VMA ?!i<,,l>; and 1nstructions Cycles # Line Addrass Bus Data Bus.\\.!),,,1?,’ .f’’’*,.., ADC EOR 1 1 Op Code Address .es”’$% ‘“~\\ 1 Op Code ADD LDA AND ORA 2 2 1 Op Code Address+ 1 ‘~+?<q,~’~ 1 Operand Data ~..,?t.,, CMP SUB .Q,. CPX 1 1 Op Code A@dress *’” 1 Op Code LDX 3 2 1 OP CodaL$dd~ss + 1 1 Operand Data (High Order Byte) 3 1 OD C&&hress + 2 1 Oparand Data (Low Order Byte) Address Mode R/~ and Instructions Cycles Addres Bus Line Data Bus ADC EOR Op Code Address 1 Op Code ADD LDA AND ORA Op Code Address+ 1 1 Address of Operand BIT SBC Address of Operand 1 Operand Data CMP SUB ,, CPX Op Code Address 1 Op Code LDS LDX Op Code Address + 1 1 Address of Operand Address of Operand 1 Operand Data (High Order Byte) 4 1 Operand Address + 1 1 Operand Data (Low Order Byte) 1 1 Op Code Address 1 Op Code Op Code Address + 1 1 Destination Address 3 0 Destination Address 1 irrelevant Data (Note 1} 4 1 Destination Address o Data from Accumulator STS 1 1 Op Code Address 1 Op Code STX 2 1 OP Code Address+ 1 1 Address of Operand 5 3 0 Address of Operand 1 Irrelevant Data (Note 1 ) 4 1 Address of Operand o Register Oata (High Order Byte) 5 1 Address of Operand + 1 0 Register Data (Low Ordar BVte) Depending on bus capacitance, data from the previous cycle may be retained on the Data Bus. B MOTOROLA Semiconductor Products Inc.
I FIGURE 31 – EXTENDED ADDRESSING MODE MPU MPu R RAM DATA PROGRAM MEMORY RAM I --- ADOR Pc ADDR = 300 PROGRAM MEMORY I wINSTR ADDR LDA B 300 PC = 5006 5009 MADDR “ AODR > 256 GENERAL FLOW EXAMPLE TABLE 9 – EXTENDED MODE CYCLE-BY-CYCLE Address Mode Cycle VMA and Instructions Cycles = Line STS STX OP Code Address of Operand (High Order Byte) Address of Operand (Low Order Byte) Irrelevant Data (Note 1 ) Operand Data (High Order Byte) Operand Data (Low Order Byte) Op CodeJSR Address of Subroutine (High Order Byte) Address of Subroutine (LOW Order BVte) 3P Code of Next Instruction Return Address (Low Order Bvte) Return Address (High Order BVte) Irrelevant Oata (Note 1 ) Irrelevant Data (Note 1 ) Address of Subroutine (Low Order Bvte) Op Code Jump Address (High Order Bvte) Jump Address (LOW Order Bvte)
3 Op Code Address + 1 II
Address of Operand (High Order BVte) Address of Operand (Low Order Bvte) Operand Data w Op Code Address of Operand (High Order BVte) Address of Operand (LOW Order BVte) Operand Data (High Order BVte) Operand Data (LOW Order Bvte) OP Code Address + 2 I 1Address of Operand 1 Address of Operand + 1 1 OP Code Address 1 Op Code Destination Address (High Order Bvte) Destination Address (Low Order Bvte) Irrelevant Oata (Note 1 ) Data from Accumulator OP Code Op Code Address + 1 1 Op Code Address + 2 1 Operand Destination Address 1 Operand Destination Address o Op Code Address 1ASL LSR ASR NEG CLR ROL Op Code Address + 1 II Address of Operand (High Order Bvte) Address of Operand (Low Order Bvte) Current Operand Data Irrelevant Data (Note 1 ) New Operand Data (Note 2) Op Code Address + 2 I 1Address of Operand 1 COM ROR DEC TST INC Address of Operand 1 Address of Operand o ~te 1. It device which ISaddressed during this cvcle uses VMA, then the Data Bus will go to the high impedance three-state condition, Depending on bus capacitance, data from the previous cycle mav ba retatned on the Data Bus. Note 2. For TST, VMA = O and Operand data does not change, MOTOROLA Semiconductor Products Inc.
FIGURE 32 – RELATIVE ADDRESSING MODE MPU RAM PrOaram i MeGory Pc Instr. Offset (PC + 2) Next Instr. Pc Pc t ADDR = INOX + OFFSET MPU a~AM sProgram Memorv
5008 BEQ
5010 Next Instr. MPu 1,’ ..,. OFFSET< 255 Address Mod.@x,.,.j:,‘ cycle VMA RIG and Instruc,$~~ “r’’’*’fCycles + Line Address Bus Line Data Bus 1 BCC BH#~’B~b’ 1 1 OP Code Address 1 Op Code BE Q $~@\\$~<. BRA 4 1 Op Code Address + 1 1 Branch Offset BG5 &&T ;;: 3 0 Op Code Address t 2 1 Irrelevant Data (Note 1 ) B&?$~’*RM I‘t.,A:”~- 4 0 Branch Address 1 Irrelevant Data (Note 1 ) BS ~: 1 1 OP Code Address 1 Op Code 2 1 Op Code Address+ 1 1 Branch Offset 3 0 Return Address of Main Program 1 Irrelevant Data (Note 1) 8 4 1 Stack Pointer o Return Address (Low Order Byte) 5 1 Stack Pointer – 1 0 Return Address (High Order Byte) 6 0 Stack Pointer – 2 1 Irrelevant Data (Note 1) 7 0 Return Address of Main Program 1 Irrelevant Data (Note 1 ) 8 0 Subroutine Address 1 Irrelevant Data (Note 1) Note 1. Ifdevice which isaddressed during this cycle uses VMA, tnen tne UaTa Bus WIII go TO tne nlgn !mpeaance ~nree-staTe conut~!un. Depending on bus capacitance, data from the previous cycle may be retained on the Oata Bus. MOTOROLA Semiconductor Products Inc.
I TABLE 11 – INDEXEO MOOE CYCLE-BY-CYCLE Address Mode Cycle VMA R 1~ and Instructions Cycles # Line Address Bus Line Deta Bus I INDEXED JMP ADC EOR ADD LDA AND ORA BIT SBC CMP SUB CPX LDS LDX STA ASL LSR ASR NEG CLR ROL COM ROR DEC TST INC ;TS 3TX T T T 3$$ ‘q; ;@p T T Op Code Address OP Code Address + 1 Index Register Index Register Plus Offset (w/o Carry) Op Code Address Op Code Address + 1 Index Register Index Register PIus Offset (w/o Carry) Index Register Plus Offset Op Code Address Op Code Address+ 1 Index Register Index Register Plus Offset (w/o Carry) Index Register Plus Offset Index Register Plus Offset + 1 Op Code Address Op Code Address + 1 ,,,,.7>.,, ,,+y:>, Index Register B:#,$<i?!’.”.,, Index Register Plus Offset (w/o*~/Y) Index Register Plus Offset ,,:~j, ‘k Index Register Plus Off@F?:~ $.\\\\$&h Op Code Address kTi\\$$:~t ~~.,~;,\\ Index Register , ‘.: Index ReQ&er Pyus Offset (w/o Carry),...,,,,, Inde~l.%~,~ter PIus Offset.- ‘.~$+t t#d,* R*gister Plus Offset.;$:,>~:.,! ?n.S,pt:+f“yt{\\, ‘&p Code Address Op Code Address+ 1 Index Register Index Register Plus Offset (w/o Carry) Index Register Plus Offset Index Register Plus Offset Index Resister Plus Offset + 1 Op Code Address Op Code Address+ 1 Index Register Stack Pointer Stack Pointer – 1 Stack Pointer – 2 Index Register Index Register Plus Offset (w/o Carry) ~~y Data (High Order Byte) ~~~$rand Data (Low Order Byte) Op Code Offset IrrelevantData (Note 1) Irrelevant Data (Note 1) Irrelevant Oata (Note 1) Operand Data Op Code Offset Irrelevant Data (Note 1) Irrelevant Data (Note 1 ) Current Operand Data IrrelevantData (Note 1) New Operand Data (Note 2) Op Code Offset IrrelevantData (Note 1 ) Irrelevant Data (Note 1) IrrelevantData (Note 1) Operand Data (High Order Byte) Operand Data (Low Order Byte) Op Code Offset IrrelevantData (Note 1 ) Return Address (Low Order Byte) Return Address (High Order Byte) Irrelevant Data (Note 1) Irrelevant Data (Note 1) Irrelevant Oata (Note 1) Note 1. Ifdevice which isaddressed during this cycle uses VMA, then the Data Bus will go to the high impedance three-state condition. Oepending on bus capacitance, data from the previous cycle may be retained on the Oata Bus. Note 2. For TST, VMA = O and Operand data does not change. MOTOROLA Semiconductor Products Inc.
(PLASTIC) Motorola reserves the rightto make changes toany products herein to improve reliability,functionor design. Motorola does not assume any Iiabilityarising out of the applicationor usa of any product or circuitdescribed herein;neitherdoes itconvey any licenseunder itspatent rightsnor the rightsof others. MOTOROLA Semiconductor Products Inc.
I M070ROLA Semiconductor Products Inc.