MC6800

MC68008 MOTOROLA | Alldatasheet

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ma SEMICONDUQTON —lyEyEyEEEEEs TECHNICAL DATA MC68008 Technical Summary 16-Bit Microprocessor With 8-Bit Data Bus This document contains both a summary of the MC68008 as well as a detailed set of parametrics. For detailed information on the MC68008 refer to M68000 UM/AD, M68000 8-/16-/32-Bit Microprocessor User’s Manual. The MC68008 is a member of the M68000 Family of advanced microprocessors. This device allows the design of cost-effective systems using 8-bit data buses while providing the benefits of a 32-bit microprocessor architecture. The per- formance of the MC68008 is greater than any 8-bit microprocessor and superior to several 16-bit microprocessors. The following resources are available to the MC68008 user: @ 17 32-Bit Data and Address Registers @ 56 Basic Instruction Types @ Extensive Exception Processing @ Memory-Mapped !/O e@ 14 Addressing Modes ®@ Complete Code Compatibility with the MC68000 This document contains information on a new product. Specifications and information herein are subject to change without notice. 3-100 M68000 FAMILY REFERENCE MANUAL MOTOROLA

A system implementation based on an 8-bit data bus reduces system cost in comparison to 16-bit systems due to a more effective use of components and byte-wide memories and peripherals. In addition, the nonmultiplexed address and data buses eliminate the need for external demultiplexers, further simpli- fying the system. The MC68008 has full code compatibility (source and object) with the MC68000, which allows programs to be run on either MPU, depending on performance requirements and cost objectives. The MC68000 is available as a 48-pin dual-in-line package (in plastic or ceramic) and 52-pin quad plastic package. Among the four additional pins of the 52-pin package, two additional address lines are included beyond the 20 address lines of the 48-pin package. The address lines reach of the MC68008 is 1 of 4 Mbytes with the 48- or 52-pin package, respectively. The large nonsegmented linear address space of the MC68008 allows large modular programs to be developed and executed efficiently. A large linear address space allows program segment sizes to be determined by the appli- cation rather than forcing the designer to adopt an arbitrary segment size without regard to the application's individual requirements. The programmer's model is identical to that of the MC68000 (see Figure 1), with 17 32-bit registers, a 32-bit program counter (PC), and a 16-bit status register (SR). The first eight registers (DO-D7) are used as data registers for byte (8-bit), word (16-bit), and long word (32-bit) operations. The second set of seven registers (AQ-A6), the user stack pointer (A7), and the system stack pointer (A7‘) can be used as software stack pointers and base address registers. In addition, the registers can be used for some simple word and long-word data operations. All 17 registers can be used as index registers. MOTOROLA M68000 FAMILY REFERENCE MANUAL 3-101

Figure 1. Programming Model of use when the mode is switched. system stack pointer and the SSP is protected from user modification.

cessor is in the trace (T) mode and/or in the supevisor (S) state. Figure 2. Status Register word data, etc., are provided in the instruction set.

Most instructions can use any of the 14 addressing modes listed in Table 1. for writing relocatable programs. Table 1. Addressing Modes

which are variations or subsets of these instructions, are listed in Table 3. Table 2. Instruction Set Summary

9 SWAP Swap Data Register Halves

Table 3. Variations of Instruction Types

The MC68008 is available in two package sizes (48-pin and 52-pin). The addi- tional four pins of the 52-pin quad package allow for additional signals: A20, A21, BGACK, and IPL2. The input and output signals can be functionally organized into the groups shown in Figure 3(a) for the 48-pin version and in Figure 3(b) for the 52-pin version. The following paragraphs provide a brief description of the signals and a reference (if applicable) to other paragraphs that contain more infor- mation about the function being performed. |ADDRESS BUS Voc [> are.a0 GND) DATABUS Suk Ki 07.0 FCO AS_ PROCESSOR Fer BW ASYNCHRONOUS status ) Fo2 os ‘BUS CONTROL ‘M8808 DTACK sgo0 at Ba Bus BERR —_— same { RESET OF } INTERRUPT CONTROL HALT IPL1 CONTROL (a) 48-Pin Version MOTOROLA M68000 FAMILY REFERENCE MANUAL 3-107

6800 E oR Bus

3 PERIPHERAL VPA 5G ARBITRATION

Figure 3. Functional Signal Groups address strobe, read/write, data strobe, and data transfer acknowledge.

This three-state signal defines the data bus transfer as a read or write cycle. Table 4. When R/W is high, the processor will read from the data bus as in- dicated. When R/W is low, the processor will write to the data bus as shown. Table 4. Data Strobe Control of Data Bus which device will be the bus master.

Bus Request (BR) This input is wire-ORed with all other devices that could be bus masters. This input indicates to the processor that some other device desires to become the bus master. Bus requests may be issued at any time in the cycle or even if no cycle is being performed. Bus Grant (BG) This output indicates to all other potential bus master devices that the processor will release bus control at the end of the current bus cycle. Bus Grant Acknowledge (BGACK) This input, available on the 52-pin version only, indicates that some other device has become the bus master. This signal should not be asserted until the fol- lowing four conditions are met: 1. A bus grant has been received. 2. Address strobe is inactive, which indicates that the microprocessor is not using the bus. 3. Data transfer acknowledge is inactive, which indicates that neither mem- ory nor peripherals are using the bus. 4. Bus grant acknowledge is inactive, which indicates that no other device is claiming bus mastership. NOTES 1, There is a two-clock interval straddling the transition of AS from the inactive state to the active state during which BG can not be issued. 2. If an existing MC68000 system is retrofitted to use the MC68008 48- pin version (using BR and BG only), the existing BR and BGACK signals should be ANDed and the resultant signal connected to the MC68008 BR. INTERRUPT CONTROL (48-Pin: IPLO/IPL2, IPL1; 52-Pin: IPLO, IPL1, IPL2) These input pins indicate the encoded priority level of the device requesting an interrupt. The MC68000 and the 52-pin MC68008 MPUs use three pins to encode a range of 0-7 but, for the 48-pin MC68008, only two pins are available. By connecting the IPLO/IPL2 pin to both the IPLO and IPL2 inputs internally, the 3-110 M68000 FAMILY REFERENCE MANUAL MOTOROLA

48-pin version encodes values of 0, 2, 5, and 7. Level 0 is used to indicate that there are no interrupts pending and level 7 is a nonmaskable edge-triggered interrupt. Except for level 7, the requesting level must be greater than the interrupt mask level contained in the processor status register before the pro- cessor will acknowledge the request. The level presented to these inputs is continually monitored to allow for the case of a requesting level that is less than or equal to the processor status register level to be followed by a request that is greater than the processor status register level. A satisfactory interrupt condition must exist for two suc- cessive clocks before triggering an internal interrupt request. An interrupt ac- knowledge sequence is indicated by the function codes. SYSTEM CONTROL The three system control inputs are used to either reset or halt the processor and to indicate to the processor that bus errors have occurred. Bus Error (BERR) This input informs the processor that there is a problem with the cycle currently being executed. Problems may be a result of: 1, Nonresponding devices 2. Interrupt vector number acquisition failure 3. Illegal access request as determined by a memory management unit 4. Various other application-dependent errors The bus error signal interacts with the halt signal to determine if the current bus cycles should be re-executed or if exception processing should be per- formed. A summarization of the interaction is shown in Table 5: Table 5, Interaction of BERR and HALT J fs [Norma Operation J+ [0 [singte Bus Gycte Operation | [0 [1 ous error — Exception Processing —_——_—| [0 [0 Jeustrror— Rerun Curent Gyele MOTOROLA M68000 FAMILY REFERENCE MANUAL 3-111

lines are put in their high-impedance state. that the processor has stopped. vices with the asynchronous MC68008. input, which indicates that the peripheral! is an M68000 Family device.

7 VPA (TO MC68008)

Figure 4. External VMA Generation

AS has been asserted and the address bus is addressing an M6800 peripheral. be synchronized with the enable (E) signal. indicates that the processor should use automatic vectoring for an interrupt. by the function code output is valid whenever AS is active. Table 6. Function Code Outputs

should be a constant frequency. Power is supplied to the processor using these two signals. Table 7 summarizes the signals discussed in the previous paragraphs. Table 7. Signal Summary

Transfer of data between devices involves the following signals: 1. Address bus A0-A21 2. Data bus DO-D7 3. Control signals The address and data buses are separated nonmultiplexed parallel buses. Data transfer is accomplished with an asynchronous bus structure that uses hand- shakes to ensure the correct movement of data. In all cycles, the bus master assumes responsibility for deskewing all signals it issues at both the start and end of a cycle. In addition, the bus master is responsible for deskewing the 3 acknowledge and data signals from the slave device. The following paragraphs explain the read, write, and read-modify-write cycles. The indivisible read-modify-write cycle is the method used by the MC68008 for interlocked multiprocessor communications. READ CYCLE During a read cycle, the processor receives data from the memory or a pe- ripheral device. The processor reads bytes of data in all cases. If the instruction specifies a word (or double word) operation, the processor reads both bytes in a two-cycle read operation. When the instruction specifies byte operation, the processor uses AO to determine which byte to read and then issues data strobe. WRITE CYCLE During a write cycle, the processor sends data to either the memory or a peripheral device. The processor writes bytes of data in all cases. If the instruc- tion specifies a word operation, the processor writes both bytes in a two-cycle write operation. When the instruction specifies a byte operation, the processor uses AO to determine which byte to write and then activates DS. READ-MODIFY-WRITE CYCLE The read-modify-write cycle performs a byte read, modifies the data in the arithmetic logic unit, and writes the data back to the same address. In the MC68008, this cycle is indivisible in that the address strobe is asserted through- out the entire cycle. The TAS instruction uses the cycle to provide meaningful communication between processors in a multiple processor environment. TAS is the only instruction that uses the read-modify-write cycle; since TAS only Operates on bytes, all read-modify-write cycles are byte operations. MOTOROLA M68000 FAMILY REFERENCE MANUAL 3-115

The MC68008 is always in one of three processing states: normal, exception, or halted. NORMAL PROCESSING The normal processing state is that associated with instruction execution; the memory references are to fetch instructions and operands and to store results.

3 A special case of the normal state is the stopped state which the processor

enters when a STOP instruction is executed. In this state, no further memory references are made. EXCEPTION PROCESSING The exception processing state is associated with interrupts, trap instructions, tracing, and other exceptional conditions. The exception may be internally generated by an instruction or by an unusual condition arising during the execution of an instruction. Externally, exception processing can be forced by an interrupt, a bus error, or a reset. Exception processing is designed to provide an efficient context switch so that the processor may handle unusual conditions. HALTED PROCESSING The halted processing state is an indication of catastrophic hardware failure. For example, if, during the exception processing of a bus error, another bus error occurs, the processor assumes that the system is unusable and halts. Only an external reset can restart a halted processor. Note that a processor in the stopped state is not in the halted state, nor vice versa. 3-116 M68000 FAMILY REFERENCE MANUAL MOTOROLA

INTERFACE WITH M6800 PERIPHERALS Motorola’s extensive line of M6800 peripherals are compatible with the MC68008. Some devices that are particularly useful are as follows: MC6821 Peripheral Interface Adapter MC6840 Programmable Timer Module MC6845_ CRT Controller MC6850 Asynchronous Communications Interface Adapter MC6852_ Synchronous Serial Data Adapter MC6854_ Advanced Data Link Controller To interface the synchronous M6800 peripherals with the asynchronous MC68008, the processor modifies its bus cycle to meet the M6800 cycle re- quirements whenever an M6800 device address is detected. This modification is possible since both processors use memory-mapped |/O. MOTOROLA M68000 FAMILY REFERENCE MANUAL 3-117

• The device contains circuitry ~ ages or electric fields; how- Operating Temperature Range Ta | tuetH | © | preation of voltages higher MC68008 Oto 70 than maximum-rated voltages MC68008C 40 to 85 to these high-impedance cir- level (e.g., either GND or Vcc) enhances seliability of opera t THERMAL CHARACTERISTICS - [___ characteristic | Symbot [vate] symbot [vetue| Rating | Thermal Resistance (Still Air} "A re cw Ceramic, Type LC 40 15¢ Plastic, Type P 40 20° Plastic, Type FN 50 30° *Estimated POWER CONSIDERATIONS The average die-junction temperature, Ty, in °C can be obtained from: TJ=TA+(PD + 8a) (1) where: TA = Ambient Temperature, °C 6ya =Package Thermal Resistance, Junction-to-Ambient, °C/W Pp =PinT+PI/O Pint =!lcc Vcc, Watts — Chip Internal Power PQ = Power Dissipation on Input and Output Pins — User Determined For most applications, P|;Q<PiNT and can be neglected. An appropriate relationship between Pp and Ty (if Pio is neglected) is: Pp=K=(TJ +273 °C) (2) Solving equations (1) and (2) for K gives: K=Pp + (Ta + 273°C) + bJAePD? (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring Pp (at thermal equilibrium) for a known Ta. Using this value of K, the values of Pp and Ty can be obtained by solving equations (1) and (2) iteratively for any value of Ta. 3-118 M68000 FAMILY REFERENCE MANUAL MOTOROLA

just below 1.4 watts at 25°C. AMBIENT TEMPERATURE (Ta), °C. Figure 5. Power Dissipation (Pp) results in a lower semiconductor junction temperature.

that no thermal management is applied (i.e., still air). sloped, power dissipation declines as ambient temperature increases. bient temperature where power dissipation is lowest. Table 8. Power Dissipation and Junction Temperature

4 Pp (W) Ty (Cc) Pp (WwW) Ty (°C)

Table 9. Power Dissipation and Junction Temperature

AC ELECTRICAL SPECIFICATIONS DEFINITIONS The AC specifications presented consist of output delays, input setup and hold times, and signal skew times. All signals are specified relative to an appropriate edge of the clock and possibly to one or more other signals. The measurement of the AC specifications is defined by the waveforms shown in Figure 6. To test the parameters guaranteed by Motorola, inputs must be driven to the voltage levels specified in this figure. Outputs are specified with minimum and/or maximum limits, as appropriate, and are measured as shown in Figure 6. Inputs are specified with minimum setup and hold times, and are 3 measured as shown. Finally, the measurement for signal-to-signal specifica- tions is also shown. Note that the testing levels used to verify conformance to the AC specifications does not affect the guaranteed DC operation of the device as specified in the DC electrical specifications. MOTOROLA M68000 FAMILY REFERENCE MANUAL 3-121

1. This output timing is applicable to all parameters specified relative to the rising edge of the clock.
2. This output timing is applicable to all parameters specified relative to the falling edge of the clock.
3. This input timing is applicable to all parameters specified relative to the rising edge of the clock.
4. This input timing is applicable to all parameters specified relative lo the falling edge of the clock.
5. This timing is applicable to all parameters specilied relative to the assertion/negation of another signal.

‘A. Maximum output delay specification. B. Minimum output hold time. D. Minimum input hold time specification. E. Signal valid to signal valid specification (maximum or minimum). F. Signal valid to signal invalid specification (maximum or minimum). Figure 6. Drive Levels and Test Points for AC Specifications

***During normai operation, instantaneous Vcc current requirements may be as high as 1.5 A. and are valid only for product bearing date codes of 8827 and later. Figure 7. Clock Input Timing Diagram

AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES (Vcc =5.0 Vde + 5%; GND=0 Vdc; Ta=TL to TH; see Figures 8 and 9) fmm | earner [in [x | in [ ma [6 [ooctow to Aare SSS tw P| oe [| of] [sx Joos ngh erevaie cro | ae P| 0 | oe | [7 otc righ to Ades, Daa Bus High impedes Maxima) —[ucuapz | = [00 | — | 70 | os | [e looskigh Adress Felnvat Minmum) —————T icua, | 0 — | 0] — [ow | [ot Joockigh AS, OSAweneg cst | | of 3] | oe | [i [press Vat to AS S Assoned ani AS Assonea rte) [wer | 30 — [20] — [os | [iat [Fc Vata to AS, 05 Asroned ead AS Assenea Wie) | wevsr | 22 | — | 70] — [ve | [12 Jocck tow ioAS. 08 Negoes ecu | oe | op os | [17 FS, 05 Negeed io Actes, FEimaid | tguar | | — | 20] — [oe | [142 [AS lana 05 Read With Assored its P| — Pos | — [os | [aaa fos wath asered wire) rt of — fos | — [oe | [15% [AS. 05 wien Negatea tg [ee | — Ps | — [oe | [16 [ost righ to Control aus igh Impedance [enc |— | | — | 70] ve | [177 [AS.05 Necoted to RWinvoka rc || — P20] — [oe | [87 [ook righ to AW High ese) tc | eo] Poe J [07 [otok High to RWow Wate) vow |e os [0 | a8 | oe | [Boa™ Sas assorted ro AW Vala wets) rasa P= [0 P= Po foe J [217 [Adres Vali to AWtow Wrte) [wa |} — | 0] — [oe | [aiat [rc vaid wo RWow Wie) | rev [so | — | S| — | os | [27 [Rvviow OS Anorea wii) Lg et —] | — [oe | [20 [occ tow to DatwOut vate Winey | apo | - [| — [a] m | [257 [AS. 05 Negeed to Da-Out maha wie) | gwpor| | — [a9] — [ve | [-26? Joot-Ont Valco 05 Aserea Wie) foo. | | — | | — | ws | [27> [pat vaio Gack tow Seup Timea? Reaa) | toa, | w[— |] — | we | [ 28? AS, 0S Nepaed vo OTACK negated iAsychvonows Hom [igupan | 0 [ 268 [0] 160 | vs | [25 [AS 0S Negotedo Btn invod Hold Te on Rese) | ton | 0 | — | 0 | — [oe | [Bk [AS. 08 Neveted to Doe nigh impedance tguoz | — [er | — | 0 | ve | [1-5 [DTAOK Asseredto Dato Vaid Soup Tal [oar | — | | — | | oe | [32 [RACT and RESET np Tension Time] tee [0 | 200 [0 | 200_[ ve | [aa [oocHghios@anered cw |= | ef — | of oe | [aa tock ight BG Negeteg ter P| oe P| oo | [a5 [ak Assrndo mG assoned crue | 18 Las [oe | as [ens | [67 [aR negates 10 5G Negoed Prange | 18 [a5 [18 | 35 [ons | [a7 BGRCK assoned io BG Negated G2 Version Oo) | igagu| 15 [as [15] 25 [ons cela al a A Clks Ciks re (AS Negated) [28_[86 wish Nese re a P= a = Te | [at eek tow to € hanson cee PP sl oe | [a2 |e Output ise and fal timer; TP] ef oe | [at [aS. 08 negeted to VPA Negasa cave | 0 P20 [0 | 20 [oe | 3-124 M68000 FAMILY REFERENCE MANUAL MOTOROLA

(Continued) [45 _[E Low to Control, Address Bus Invalid (Address Hold Time) tecar | 30 | — | 10 | — [ns | [46 _[BGACK Width Low (52-Pin Version Only) [ica [15 [ — fs | — [ous | fAsynchronous Input Setup Time ee eee DTACK Asserted to BERR Asserted tpecva.| 20] — | 20] — | ns | [ 499 _|AS, DS, Negated to E Low tsuer [70] 70 | ss] 55 [ns | [50 |e wiath High [ten | aso | — [sso | — ns | E Width Low | ter | 700 | — | 550] — J ns _| E Low to Data-Out Invalid tELDO! [ 30 [ — | 20] — | ns | [ 55 _|RIW Asserted to Data Bus Impedance Change troppo |_30 [| — | 20| — | ns | [_ 56% [HALT RESET Pulse width wwrpew | to | — [to | — [cies | BGACK Negated to AS, DS, RW Driven (52-Pin Version Only) tcaso | 1.5 | — [15 | — [chs | BGACK Negated to FC, VMA Driven (52-Pin Version Only) toaro | 1] — | 1[ — [chs | BR Negated to AS, DS, RiW Driven treysp | 15 | — [15 [ — | chs | [_s8a7_[BR Negated to FC, VMA Driven taco [1 T — | 1] = Tons] *These specifications represent an improvement over previously published specifications for the 8- and 10-MHz MC68008 and are valid only for product bearing date codes of 8827 and later. NOTES 1. For a loading capacitance of less than or equal to 50 pF, subtract 5 ns from the value given in the maximum columns 2. Actual value depends on clock period 3. If #47 is satisfied for both DTACK and BERR, #48 may be ignored. In the absence of DTACK, BERR is an asynchronous input using the asynchronous input setup time (#47) 4. For power-up, the MC68008 must be held in the RESET state for 100 ms to allow stabilization of on-chip circuitry. After the system is powered up, #56 refers to the minimum pulse width required to reset the processor. 5. If the asynchronous input setup time (#47) requirement is satisfied for DTACK, the DTACK-asserted to data setup time (#31) requirement can be ignored. The data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle. 6. When AS and RW are equally loaded ( = 20%), subtract 5 ns from the values given in these columns. 7. The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before asserting BGACK. 8. The minimum value must be met to guarantee power operation. If the maximum value is exceeded, BG may be reasserted. — 9. The falling edge of $6 triggers both the negation of the strobes (AS and xD5) and the falling edge of E. Either of these events can occur first, depending upon the loading on each signal. Specification #49 indicates the absolute maximum skew that will occur between the rising edge of the strobes and the falling edge of E MOTOROLA M68000 FAMILY REFERENCE MANUAL 3-125

1. Setup time for the asynchronous inputs IPL2 / IPLO, IPL, and VPA (#47) guarantees their recognition
2. BR need fall at this time only to ensure being recognized al the end of the bus cycle.
3. Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V,

range such that the rise or fall is linear between 0.8 V and 2.0 V. Figure 8. Read Cycle Timing Diagram

1. Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V,

range such that the rise or fall is linear between 0.8 V and 2.0 V.

1. Because of loading variations, R/W may be valid after AS even though both are initiated by the rising edge

Figure 9. Write Cycle Timing Diagram

and are valid only for product bearing date codes of 8827 and later.

1. For a loading capacitance of less than or equal to 50 pF, subtract 5 ns from the value given in the maximum columns.
2. The falling edge of S6 triggers both the negation of the strobes (AS and xDS) and the falling edge of E. Either of these

events can occur first, depending upon the loading on each signal. Specification #49 indicates the absolute maximum. Figure 10. MC68008 to M6800 Peripheral Timing Diagram (Best Case)

8 mis ) Kn i: rm : a Gy Se ees ee 8 ie a5 |e 4 * @ = ry F 3 > > 5 > © g € = E 2 (-) * ©) e g 2 : 5 Ee = 2 gs ‘ es » @| ® 5s N 2 8 = 2 a > g 8 = £ o > é $s is] > é 2 = 8 o D So = 2 8 = a oO : Z = > ©) g OF = = = $ % 3 =) Step ley ae a YY ® § EI Ey g © E MOTOROLA M68000 FAMILY REFERENCE MANUAL 3-129

and are valid only for product bearing date codes of 8827 and later.

1. The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before asserting
2. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be

their recognition at the next falling edge of the clock. Figure 12. Bus Arbitration Timing

1. Setup time for the asynchronous inputs BGACK and BR (#47) guarantees their recognition at the next falling edge of
2. Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V.

Figure 13. Bus Arbitration Timing — Idle Bus Case

1. Setup time for the asynchronous inputs BGACK and BR (#47) guarantees their recognition at the next falling edge of the clock
2. Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V.

Figure 14. Bus Arbitration Timing — Active Bus Case

1. Setup time for the asynchronous inputs BGACK and BA (#47) guarantees their recognition at the next falling edge ol the clock
2. Waveform measurements for all inputs and outputs are specified al: logic high 2.0 V, logic low = 0.8 V.

Figure 15. Bus Arbitration Timing — Multiple Bus Requests

48-LEAD DUAL-IN-LINE PACKAGE i 1® 4g [J 2 a 2 47) At as C3 46 [7] Ao as} 4 45 [J Feo arC_]s5 44 [77] Fet aa de 43 [_] Fea 3 asC_]7 42 [777 IPLONPLO Ao C48 41 7) IPL ait Colo 40 [—] BERR At2 (7 10 39 [7] VPA AIS W B E Aig (12 Mc68008 37 |) RESET Nec [7] 13 36 |) HALT ais (a) 14 35 [ ond GND C—] 15 34 [77] clk Aig J 16 33 [BA a7 C17 32 [7] ac Aig [ 18 31 |) DTACK ANS 19 30 RW 07 20 23 os 06 (_] 21 28 [1 aS ps (] 22 27 [bo

4 C] 23 26 [—_) 01

a 25 [1] 2 3-134 M68000 FAMILY REFERENCE MANUAL, MOTOROLA

DOO Or arr) a9) 8 1 46 1 IPL2 Ato] 1) (Pi ang [) BERR aq D WPA ag] De aad [0 RESET a] ‘Mc68008 [5 HALT Vee | [0 eno 3 aq] [7 CLK GNO J (BR Ate C] [0 BGACK a7g [] 8G At8 C] 20 34) DTACK 2 3 DOOD ooooooOoo 2RSSSSSSSBLBE MOTOROLA M68000 FAMILY REFERENCE MANUAL 3-135