MC6173

MC6173 MOTOROLA | Alldatasheet

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@ SEMICONDUCTOR SE TECHNICAL DATA 2400 bps DIGITAL DEMODULATOR Mos (N-CHANNEL, SILICONGATE)

2 The MC6I73 is a MOS subsystem designed to be integrated into a

wide range of equipment utiaing seal data communication 2400 bps The demodulator provides the necessary demodulation and control DEMODULATOR functions to implement a serial data communication link over a voice grade channel, utlzng diferente phase shit Keying (OPSKI at Bt rates of 1200 or 2400 bps. Phase options are provided for both the U.S. and international markets. The MCG173 can be implemented into wide N-channel silicon gate technology permits the MC6173 to operate using @ single voltage supply and be fully TTL compatible. family, and provides medum-speed data communications capability. Yi L SUFFIX = canbe PnCKAGE ‘© Compatible with MC6172 Modulator . D CASED @ 511-Bit CCITT V.52 Test Pattern @ Terminal Interfaces Are TTL Compatible i: @ Compatible Functions for 201B/C and V.26 Data Sets =f ® © CCITT and U.S. Phase Options wh TAY) v © 1200/2400 bps Operation or A} a or P SUFFIX FIGURE 1 ~ TYPIGALAPPLICATIONS © Telephone <7 tine Pass cove [Foe PIN ASSIGNMENT Fer 2 230 rol Tovah Ta he 5 deb qa afl 75a Envelope 3 w tye He aft osc * é 0° bye Gs 200) ax cx é aoc Gs 9B cor AGC & g . > Te 8 2 ood yep Pe a gle aos Ge wh ess & 3 2 RxOew Ye 160 Tin Converter 8 > 5 2 im tho 6 Gs

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MAXIMUM RATINGS This device contains circuitry to protect the: Operating rat i A c circuit. Reliability of operation is enhanced if Storage Temperature Range [ Teig | -55 10+ 150 | °C | unused inputs are tied to an appropriate logic 2 DC ELECTRICAL CHARACTERISTICS (Vcc=5.0 +0.25 Vde, Vgs=0, Ta= TL 10TH Cis Gada ee sho n Fier 3 nest terse noted. [renee Simba [in Pty Tex [Ui | Input Leakage Current pa utp Fgh Vonage (loH= -0.04 mA, Load A) vont | Vss+24 vec | input Capacitance Cin oF Gurput Transition Times (From 10% 10 90% Points! es ee ee input Clock Duty Cycle, 1.8432 MHz Input (Measured at 1.5 V level foc | » |-| » |* | |Data-Clamp Delay Time ‘Option 1 toco1 57 6 63 Option 2 tocoz | 4.198 | 4.17 | 4.206 oven 3 {BCR rms | 2080 | 20005 Option 4 toco4 | 104.135 | 104.17] 104.206 [A/D Clock to A/D Strobe Delay Time tapco] 108 [Tom [is | Enveapeto-Dint Clock Day Tie [wo | wo [| = |e | cece Feaueny, 20.05% [toe | — [remal =~ we | [A/D Strobe Pulse Width [ouaosi]| - | was - | as | [New Sync Input Puise Width | | a MOTOROLA TELECOMMUNICATIONS DEVICE DATA (2-105

FIGURE 2 — DEMODULATOR BLOCK DIAGRAM oats comer ae fw Shift Timing 7 Recovery [J Ea 0° Eve PUL rye, Test Clock L raion x Ae aces Rx Data in (RDI). Input LPR 2 ——_ A/D Strobe Bs S2 LP R12 Date far 2 Fast Sync Carver Py Timing Po See Sm fx Dera Ourput Rx Data ame New tx be oe Se tah Gon | arene | Vee | | vemos | Joy ore cr "I | i a a: | Soh. ARer | = 1 oe M7000 | | or Equiv. | | simiowes tito Comin Mites = CT = 20 pF = total parasitic capacitance, which includes: Yvabe wing and aud capsctoncer ee MOTOROLA TELECOMMUNICATIONS DEVICE DATA (2-106

GENERAL DESCRIPTION training allows for large corrections to be made in the inter- ‘The MC6173 Phase-Shift Key (PSK) Demodulator serves nal timing of the demodulator. After the fast training period, as an integral part of a system to recover synchronous data the timing should be reasonably well adjusted. Small adjust- from an 1800 Hz PSK modulated carrier. Data rates of 1200 ‘ments aro made automatically to maintain proper phase rela- ‘and 2400 bits-per-second are available. In the case of 1200 tionships internally after the fast-train period. bps operation, the MC6173 detects phase shifts of 0 to 180 The FCar input, which normally comes from the carrier degrees to represent digital “Os” and “1s”. When 2400 bps threshold detect circuits, must remain at a low level during operations is desired, the MC6173 detects phase shifts of 0, the entire period of baud and carrier synchronization. 90, 180, and 270 (option A) or 45, 135, 225, and 315 (option ‘A positive level on the FCar input will disable the baud and 8} degrees to represent two bits of data called dibits, These carrier correction circuitry. Baud and carrier timing are then phase shifts decode to 00, 01, 10, and 11, respectively. in direct derivatives of the 1.8432 MHz clock as illustrated in either data rate, the 1800 Hz carrier is modulated at @ 1200 Figure 4 rate. The first positive edge of the envelope (Env) input will be Figure 1 shows the MCB173 demodulator in a typical appli totally asynchronous to the demodulator. This will be + % cation, The band-pass filter, equalizer, analog-to-digital cycle of the 2400 clock (+208 ys) The nine following {A/D) converter, 1200 Hz envelope filter, AGC amplifier, and positive edges will introduce added tolerance equal to nine 1800 He carrier detector are external to the MCB173. The times the offset of Env from the absolute 1200 Hz (as defined band-pass filter passes roughly 300 Hz to 3000 Hz eliminating by the 1.8432 MHz +0.005% clock). Thus noise, 60 Hz and 120 Hz pickup, and harmonics of 1800 Hz Max Fast Train Time=4.17 ms+9 fEqy-+0.21 ms The output of this filter is fed to the equalizer which adjusts =4.38 ms+9/tEnw phase versus amplitude such that @ constant amplitude is Min Fast Train Time =4.17 ms-0.21 ms+9/feny maintained regardless of phase and is fed into the carrier =3.96 ms+8/tEny detect circuit. The AGC amplifier provides a constant level rdless of the input level fr izer. The om external circuitry, Le., the A/D converter, and 1200 Hz {enables the selection of one of four delays during which Rx eho . Data is held to a logic-high condition. This delay is measured he TD converter samples each 1200 Hz cycle or dibit 12 from the negative edge of FCar. The four options are avail able at one pin through the use of the internal multiplexing in times. After each sample, digital data is clocked serially to The MOStI3 seconee data’ input (RDI). The MCBI73 the demodulator, Options 3 and 4 are available by demult- dibit clock as demonstrated in Figure 5. The generates the sampling clock for AD Strobe (ADS) and the plexing the ¢ available delay options are listed in Table 1, these times will serial clock (ADC) from the 1.8432 MHz internal oscillator. Hee ren oeiee to tein diect relationship to the Env " i vont af Me ence ust aang fat runing tod OL unig the ret 3 me. Ao, se nes a ute 1 wi - depen fected to the envelope fm pie i used for internal assume no carrier offset and that Env is synchronous with timing. the Tx Clk. Figure 4 is illustrative of the timing and sequene- ‘The carrier detect circuit is used to signal the fast carrier ing of this circuit. (FCar) input that a carrier is present. Immediately after FTar t loc saints 8 The BOD Oe See bes ‘sie has received a negative transition, the internal phase-lock i" loop temporarily widens its band width so that it can quickly stant high or low level which will produce options | end 2. it ‘adjust the internal timing of the MC6173 with respect to the the input’"A" is exclusive ORed with the dibit clock options 3

1200 Hz Env input {this is called fast Sync or fast training) and 4 are produced at the same input pin

‘The timing adjustments are made so that each dibit can be TELGPE (EF), Pin 10 — The env sampled at the most advantageous places. EN 5 — The envelope input comes The internal circuitry digests the dibit samples and pro- from the 1200 Hz envelope detection circuitry. Envelope duces the digital data (Rx Data) along with the receive data detection will normally consist of a 1200 Hz filter and @ clock (Rx Ck). These two signals are used to drive a seria voltage comparator to generate an approximate limited to-parallel interface such as an MC6852 Synchronous Serial square wave, Tiss normaly derives from a constant mark Interface Adapter. signal sent by the modulator for Sync acquisition purposes. PIN DESCRIPTION Each positive edge that is input to Env will reset both baud timing andthe bit loc toa logie "0. The optimum tring FAST CARRIER (FCar), Pin 2 — A negative transition on of the positive transition at the Env input will be tep prior to this input will force a period of approximately 8.3 ms of fast the falling edge of the dibit clock. Timing is illustrated in training for both baud and carrier timing.” Fast Sync or fast Figure 6. be oft he baud iti ‘Av will be effective in the training of baud timing and dibit clock only it FCar is in the active low state. Minimum positive pulse width at the Env is 22.17 as. *The postive transition of the 1200 Hz signal, present at the NEW-SYNC (NSynd), Pin 11 — This input port is normally Env input, provides a divide-by-20 counter with every other controlled by the business machine. If FCar is at an active clock. This will cause approximately 8.3 ms of fast training low, then an active low pulse in excess of 0.84 ms on the to the incoming signal at the demodulator. Syne lead will put the demodulator into the fast-Sync a — MOTOROLA TELECOMMUNICATIONS DEVICE DATA 2.107

FRGURE 4 DEMODULATOR SYNE TMING DAGRAM 1 1 1 fe ye $9) | ogy i} 1

2 Carer TAN AG A A A A AVA 1 NN A

tt L) it ' i 8.3m | ! 10 Bauds >» | — J FCar I ! 1 i | ! 1 —_ ' i cB 1 t ! ! ' vo Sone oom | ! Input \\ ! Low Sus i} ! High 4.17 ms I ! High @ DBC 20.83 ms 1 1 i) po To To ays [31 Pose] pec | 208smss%—s | ° feo} || [#2 [ove [ose Pion 7 sass | t = ¢ ia at Oe MOTOROLA TELECOMMUNICATIONS DEVICE DATA 2-108

FIGURE 6 — ENVELOPE CLOCK TIMING DIAGRAM |— Diet —| | I ine | | Signal 2 | ! | I | 1 | \\ | | Rectified | | Line Signal Env oo pec or fast-train mode (these terms are synonymous). There are nine 1 4s positive pulses occuring at 2 460 kHz Activation of NSync allows large corrections to be made rate. The first pulse, along with ADS, is used to begin the to both baud and carrier timing similar to initial activation of ‘A/D conversion sequence. The next seven positive edges the FCar tead. These corrections will be applied for approxi- strobe data serially from the A/D converter to the mately 8.3 ms. The receiver must complete the 8.3 ms period ‘demodulator input (RD!) enabling the demodulator to pro- of fast Sync before another NSync is recognized perly decode the A/D data. This signal is also used to clock 0 and 90 degree eye data TARRIER-SYNC (GarS), Pin 15 — When CarS is taken to out of the demodulator. This is described in the Eve Pattern ‘an active low, baud timing will be taken from the Env input. section. When TEn is fow, ADC monitors check accumulator In addition, the slow carrier correction will be doubled in the ‘output (see TEn} 2400 baud mode as defined by the data-rate select (DRS) {and phase-shift select (PSS) inputs. (This is not the same as . ‘the fast training that is incorporated when FCar or NSync are A/D STROBE (ADS}, Pin 8 — A positive going, approxi: active, which is a changing of the bandwidth of the internal mately 11 s, pulse is used as an enable signal for a sample phase lock loop [PLL]}. This widening of the PLL band width ‘and hold circuit prior to the A/D converter. The negative ‘will allow a faster search and lock on the 1800 Hz carrier. This edge of this pulse is used to start the conversion process. Carrier-Sync mode will remain active as long as CarS is held Pulse rate of this signal is 14.4 kHz which allows each dibit to in the active state. The normal application of this option be sampled 12 tes. (See Figure 7.) When TEnis ow, ADS would be to extend the training or Sync time under the mark monitors zero crossings (see TEn). input data condition that exceeds 8.3 ms. If FGar is at a logic 1” inactive state, this input is ignored by the demodulator. RECEIVER DATA INPUT (RDI), Pin 23 — The digital decode of the line signal magnitude, as sampled by the A/D, A/D CLOCK {ADC}, Pin 6 — This output will allow, in a is input to the demodulator at this port. The data format is serial format, the six A/D data bits plus sign information to scaled binary. This sign bit occurs on the second A/D clock, be synchronously clocked into the demodulator. (See Figure followed by six magnitude bits which begin with the most- 8) significant bit as shown in Figure 8. The data is strobed syn- a MOTOROLA TELECOMMUNICATIONS DEVICE DATA 2-108

FIGURE 7 — ANALOG TO DIGITAL SAMPLE SCHEME 203 uy 23 " , 10 1 10 4 4 8 9 Line A - \\ J Js ss—tLittitititits teri t pri iy y Cchronously with the positive edges of the ADC. data marks and spaces (Rx Datal. Receive clock is present at 4 logic one in the sign bit slot wil represent @ positive the demodulator chip output at all times; is not clamped to value. The magnitude of the six data bits increases from an inactive state when the carrier detected is not presented (000000 to 111111 with all ones always representing the most- ‘on FTar, nor is Rx Clk clamped by any other combination of Positive value as illustrated below: inputs to the demoduiator. Timing corrections to the receive clock, that are generated internally, are made following FTat going active. AS describ- [son [owss tsa T vaue | Fear, it Cars ed in FCar, if CarS is held active the receive clock is con- 4 ee eo tinuously updated from dibit Sync. 1 9 9 9 0 8 0 ° The positive transition of the Receive Clock, which occurs i id in the middle of the data bit, should be used to strobe data o jo io o o o 0} -6 from the demodulator, under normal operating conditions. When TPE scrambler/descrambier is being incorporated, RECEIVE DATA OUTPUT (Rx Data), Pin 9 ~ This pin is then the negative edge ofthe x ik wil occur inthe center the demodulator output for mark and space serial data. Data of the data bit is synchronous with the receiver clock output with the Receive Clock wil be 2400 bps or 1200 bps depending on Positive going edge of the receiver clock occuring in the the logic input at the DAS input. The Rx Cik edges described Center of the data bit. A mark is represented by 2 logic high above apply to elther 2400 bps or 1200 bps dat rates ("1") level except for the conditions described under PSe Under TPE active, the Dibit relation to Rx Cik does not and TPE change. See Figure 9 for relative timing of Rx Clk, DBC and The Rx Data output is inhibited in a logic-high level when. Rx Data, - Faris in the inactive high state. The delay from the positive Figure 10 depicts the requirements at the demodulator if edge of FCF to the inhibiting of data is 2 ns the data scrambler is being incorporated. The exclusive Nor gating of TPE and Ax Clk would then maintain proper phas- RECEIVE CLOCK (Rx Clk), Pin 20 — The receive clock ing of Rx Clk as it goes to the RS-232 driver. This circuit output provides the 2400 Hz 0.008% timing signal to the would be required since the positive edge of Receive Clock is business machine for sampling the demodulated received 2 Date Communications Standard. sssessSssssSSsSSSSSSSSSsSsssSsssssssesese MOTOROLA TELECOMMUNICATIONS DEVICE DATA 2.110

FIGURE 8 — ANALOG-TO-DIGITAL TIMING DIAGRAM fe twaosi_—>| —_= 7 ADS 1 i | 1 I | 2 apc H Li PLIL i] ! ii

01 PTTL LLL LLL TA =] Pe T+T3 | VILITTTLL

— — ADs 508 taco *WIADCH eye! apc 50% 0% tos 10H DATA RATE SELECT (DRS), Pin 24 — The following ‘The phase shifts shown are the difference in phase between levels are valid for either phase-shift select: the signal at the end of one dibit period and the new signal at Logie high equals 2400 bps, the beginning of the next dibit, Logic low equals 1200 bps. If the logic level inputs to PSS are EXORed with DBC {dibit clock) or OBC, then the test-pattern enable option may PHASE-SHIFT SELECT (PSS), Pin 17 — Option A be selected and produce the compliment of normal data at (CCITT) or option B (U.S.) phase shift can be selected for Rx Data as explained in the TPE description. (See Figure 11.) 2400 bps operation. The input data format and phase shift _ relationship for these two options are as follows: ‘TEST-PATTERN ENABLE (TPE), Pin 18 — incorporated in, the demodulator is the 611-bit test pattern shift register that PSS=0 | PSS=1 is in accord with CCITT specification V62. This is the pattern Option A | Option B that is generated by feedback from the Sth and 9th stages of (Degrees) | (Degrees) a Sbit shift register. Cy ° +85 When the TPE input is allowed to be pulled up internally, o +90 | +135 there is normal data flow through the receiver. When the " +1 | +205 ‘TPE input is pulled low, the incoming data is passed through wo | +270 | +315 this self-synchronous decoder which will produce the inverse of the 511-bit CCITT V52 pattern For 1200 bps operation, option A (CCITT) or option B(U.S.} TPE works in coordination with PSS. if PSS is directly phase shift can be selected 2s follows: pulled high or fow to represent option A or option B, then the presence of the 511-test patter at the (RDI) input and PSB=0 | PSS=1 TPE active will result in logic "1" condition at Rx Data out- Option A | Option 6 pur it the DBC option is being utilized at the PSS input and {(Deonrees! | (Degrees) is active while the 511-bit test pattern is being received, [< | wm | fe | the receiver data output will equal a logic “0”. These options +270 +25 {Figure 11) are summarized in Table 2. a MOTOROLA TELECOMMUNICATIONS DEVICE DATA

This assumes the modulator is sending the 611-bit test If the TPE inputis in the active state, itis important to note pattern with Rx Data being either a constant mark (logic "1") that the Rx Cik phase changes. The necessary circuit to ‘0r space (logic “0"). If a logic"0" is received in options 1 or 2 tegain proper phase is shown in Figure 10 ‘oF 8 logic “1” is received in options 3 or 4, then a trensmis- A scheme for programming the phase-shift select is ilus- sion error has occurred. The number of errors-per-unit time trated in Figure 11. The PSS input may either be a constant is @ measure of the transmission line quality high or low level which will produce options 1 and. Ifthe in- A feature of the above type of pattern detector is that it put “A” is exclusive ORed with the dibit clock, options 3 and 2 willbe self-synchronizing. It should be pointed out that there 4 are produced at the same input pin. will be at least two error counts each time an error is detected. FIGURE 9 — CLOCK TIMING DIAGRAM

2400 BPS A or B OPTION 1200 BPS A or B OPTION

Ax Ck LF. n ] Fx Che l | J Rx Data Rx Data me? LLL eee Ax Data Rx Data TPE=0 Teo J Dibit Cock TPE=0 ores SLIT LIL own coee fF TLS ‘SETUP AND HOLD TIME Ax Ck teu i Note: Timing measurements are refer fenced to and from a low voltage Px Dota of 0.8 volts and a high voltage of 2.0 vats, unless otherwise noted FIGURE 10 ~ DEMODULATOR DATA SCRAMBLER RECEIVE CLOCK PHASE CORRECTION REQUIREMENTS x Cik From Demodulator > “ TRE Rx Che t J t RxCik J l f Rx Data Rx Data J | TrE=0 TEI esesessssSsSssssssSSsssSSSSSSSSSsSssessFssSsSsSsSMSsseee MOTOROLA TELECOMMUNICATIONS DEVICE DATA 2412

FIGURE 11 — PHASE-SHIFT SELECT DEMULTIPLEXER, FOR TEST PATTERN ENABLE A 6 } > ° fA a2 ss oc qe “Y : Ic pac Dibt Clock] MC6I73 Pat Generator_| Demodulator TABLE2 — TEST PATTERN ENABLE OPTIONS ‘TEST ENABLE (TEnI, Pin 16; 0° Eye, Pin 6; 90° Eye, Pin4; 0° Car, Pin 7; Cor, Pin 19 — These pins allow the monitor- ing of ten internal points within the demodulator. A low level Opto demodulator such as in a production test environment or in- pos fo fifo fa fo} x daw Ouiput= 1] coming testing. Activation of Tén affects internal timing. [2 To Jol o [78 [1] Ax Oats ourpur= 7] [3 [0 [i foac] a” |osc | fx Date Ourout=0 | ‘TABLE 3 — INTERNAL MONITORS [Teepe Pe Teor ovree] Comma [Re [ten "ADS | H | See Description Under ADS (Pin 8) (Pin | L | Monitors Zoro Crossings CLOCK (Ck), Pin 14 — A 1.8432 MHz signal input ‘adc | | See Description Under ADC (Pin 6) + 0.005% is required at this port. The clock requirements are (Ping) | L_ | Monitors Check Accumulator Output the same as the modulator clock specifications. See Figure ODegree | Hi | Monitors Degree Eye 2s Complement 12 for a suggested clock circuit oe Information from 6 Tap Fiter The receive clock is generated by dividing down the 1.8432 Pins) | L | Monitors 0 Dagroe Eye 28 Complement MHz. Since receive clock accuracy must be at least Information from 12 Tap Fiter +0.005%, the clock source must be of the same accuracy. % Degree] H | Monitors 90 Degree Eye 2s Complement In- eve formation from 12 Top Fitter Pin) TEST-CLOCK (TCIk), Pin 13 — This input is used for pro- ‘orcer | H | Monitors 0 Dagree Carrier duction testing of the demodulator device. In normal opera: (Pin 7) | L_ | Monitors Check Accumulator Compare Errors tion this pin should be left open which will enable the internal ccor | H | Monitors Cartier Correction Enable pullup resistor. «Pin 19) | L_ | Monitors Carter Cartection Direction DIBIT CLOCK (DBC), Pin 21 — This output is a 1200 Hz ‘clack which is derived from incoming data envelope and pro- Pin& | 0 Degree Eve Vides a dibit reference. This signal is representative of “data ere Se derived timing.” When studying the quality of the ie opearee ore demodulated signal, through the use of eye pattems, this aries Correction output is necessary for proper synchronization of the oscilloscope. TEST STROBE (TSt), Pin 22 — This input is used to ‘These test outputs are explained in the test enable (TEN) _ facilitate testing of the demodulator during the manufactur- description below. ing process, It should be left unconnected which will result in eee MOTOROLA TELECOMMUNICATIONS DEVICE DATA 2413

derived time is that it allows data to be sampied at optimum A/D strobe then latches the data sample into the “D” type times. The demodulated signals, in differential phase-shift ‘storage devices. The output of the storage devices taken keying, take the form of “eye patterns” as shown in Figure ‘across the scaled resistors will then represent the appropriate 14, The demodulator, in optimizing its performance for value of the sample taken. To properly observe the actual minimum error rates, strobes data at the point of maximum eye patterns, it is necessary to Sync on dibit clock while ‘eye opening. The demodulator constantly examines the eye ‘observing the 0 to 90 degree eye data. Overlaying the two opening to assure that the data sample is being taken at patterns produces a two-level digital-eye pattern from which exactly the optimum point. As a result of constantly ad- the quality of the incoming signal may be judged. justing timing control, correct sampling is maintained. This Figures 15 thru 17 show a typical receive/ demodulator and technique provides improvements in reception that are ‘transmit/modulator circuit, respectively. The transmit filter ‘significant, especially in @ poor communications media en- illustrated in Figure 17 limits the bandwidth of the signal to vironment. those frequencies allowed on a telephone line. The receive The circuit in Figure 16 is required to observe the eye pat- filter and equalizer in Figure 15 clean up and normalize the in- terns. This circuit was built using Motorola CMOS devices. coming signal for the A/D network, 1200 Hz envelope detec- The 0 and 90 degree eye data is strobed from pins 4 and 5, ‘tor, and 1800 Hz carrier detector. respectively, into the shift register by the A/D clock. The FIGURE 14 ~ EYE PATTERN i 1 1 1 {<> ! 1 H 1 ! i i 1 ' i H t H H t Bye 1 Pattern i i i ni T H . i fl H | i { 1 r 1 t fi H 1 i 1 i 1 H H 1 1 1 H H fl H { 1 ‘ H i 1 i 1 1 i i H Hl ii i H H i H H noon 1 LS LI Ur LI Li Lt a MOTOROLA TELECOMMUNICATIONS DEVICE DATA 2-115

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