MC56F80XXX NXP | Alldatasheet
Document overview
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Technical content
Features
- This family of digital signal controllers (DSCs) is based on the 32-bit 56800EF core. On a single chip, each device combines the processing power of a DSP and the functionality of an MCU, with a flexible set of peripherals to support many target applications: – Industrial control – Motion control – Home appliances – General-purpose inverters – Smart sensors, fire and security systems – Switched-mode power supply and power management – Uninterruptible power supplies (UPS) – Solar inverter – Medical monitoring applications
- DSC based on 32-bit 56800EF core – Up to 100 MIPS at 100 MHz core frequency – DSP and MCU functionality in a unified, C-efficient architecture – Enhanced single-precision Floating Point math Unit (eFPU) – COordinate Rotation DIgital Compute (CORDIC) engine
- On-chip memory – Up to 64 KB flash memory – 8 KB data/program RAM – Both on-chip flash memory and RAM can be mapped into both program and data memory spaces
- Analog – Two high-speed, 12-bit ADCs with dynamic x1, x2, and x4 programmable amplifier – Up to two operational amplifiers, programmable gain up to x16 – Three analog comparators with integrated 8-bit DAC references – On-chip temperature sensors
- One high resolution eFlexPWM module with up to 12 PWM outputs, including up to 8 channels with 312ps resolution NanoEdge placement
- Communication interfaces – Up to two high-speed queued SCI (QSCI) modules with LIN slave functionality – One queued SPI (QSPI) module (in MC56F807xx only) – One LPI2C module (supports Full PMBus)
- Timers – One 16-bit quad timer (1 x 4Ch) – Three 32-bit Periodic Interval Timers (PITs) – One enhanced Quadrature Decoder (eQDC) (in MC56F807xx only)
- Security and integrity – Cyclic Redundancy Check (CRC) generator – Windowed Computer operating properly (COP) watchdog – External Watchdog Monitor (EWM)
- Clocks – On-chip oscillators: 200 kHz, and 8/2MHz IRC – Crystal / resonator oscillator
- System – 4-channel enhanced DMA controller, supporting up to 63 request sources – Integrated power-on reset (POR) and low-voltage interrupt (LVI) and brown-out reset module – Inter-Module Crossbar and Event Generator – JTAG/enhanced on-chip emulation (EOnCE) for unobtrusive, real-time debugging
- Operating characteristics – Single supply: 2.7 V to 3.6 V – Operation ambient temperature (V grade temperature): -40℃ to 105℃ – Operation ambient temperature (M grade temperature): -40℃ to 125℃
- 64-pin LQFP, 48-pin LQFP packages (32-pin LQFP and QFN optional) NXP Semiconductors Document Number MC56F80XXX Data Sheet: Technical Data Rev. 2, 11/2022 NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.
MC56F80xxx, Rev. 2, 11/2022
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1.1 Product Family
Table 1. MC56F80xxx Family
48 LQFP 32 LQFP2
- Only include the PWM channels with output pins. All internal 8 channels PWM are available through the on-chip inter-
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- The 32 LQFP and 32 QFN packages for this product are not yet available. However, the pin-out and pricing information of these packages are readily available. These devices are then committed for sampling and production based on customer demand. 1.2 56800EF 32-bit Digital Signal Controller (DSC) core
- 100 MHz CPU frequency
- Efficient 32-bit 56800EF Digital Signal Processor (DSP) engine with modified dual Harvard architecture:
- Three internal address buses
- Four internal data buses: two 32-bit primary buses, one 16-bit secondary data bus, and one 16-bit instruction bus
- 32-bit data accesses
- Supports concurrent instruction fetches in the same cycle, and dual data accesses in the same cycle
- 20 addressing modes
- Enhanced single-precision Floating Point math Unit (eFPU):
- Supports floating-point instruction acceleration based on the IEEE 754-2008 standard
- Beside normal operations (add, subtract, multiply and divide), it also supports operations such as: min, max, square root, as well as a rich set of data format conversions
- COordinate Rotation DIgital Compute (CORDIC) engine:
- Uses 32-bit fixed-point signed fractional numbers in Q5.27 format
- Trigonometric Math: Supports calculations of selected trigonometric, inverse trig, hyperbolic and exponentiation functions using circular and hyperbolic coordinates in both rotation and vector modes Calculates trigonometric and hyperbolic functions using simple, small iterative hardware structure
- Instruction set supports both fractional arithmetic and integer arithmetic
- 32-bit internal primary data buses support 8-bit, 16-bit, and 32-bit data movement, plus addition, subtraction, and logical operations
- Single-cycle 16 × 16-bit -> 32-bit and 32 x 32-bit -> 64-bit multiplier-accumulator (MAC) with dual parallel moves
- 32-bit arithmetic and logic multi-bit shifter
- Fast integer and fraction 32/16 and 32/32 divide instructions
- Four 36-bit accumulators, including extension bits
- Parallel instruction set with unique DSP addressing modes
- Hardware DO and REP loops
- Bit reverse address mode, which effectively supports DSP and Fast Fourier Transform algorithms Overview MC56F80xxx, Rev. 2, 11/2022 NXP Semiconductors 5
- Full shadowing of the register stack for zero-overhead context saves and restores: nine shadow registers correspond to nine address registers (R0, R1, R2, R3, R4, R5, N, N3, M01)
- Instruction set supports both DSP and controller functions
- Controller-style addressing modes and instructions enable compact code
- Enhanced bit manipulation instruction set
- Efficient C compiler and local variable support
- Software subroutine and interrupt stack, with the stack's depth limited only by memory
- Priority level setting for interrupt levels
- JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging that is independent of processor speed
1.3 Operation Parameters
- Operation ambient temperature: V grade temperature: -40 oC to 105oC M grade temperature: -40 oC to 125oC
- Single power supply Supply range: VDD - VSS = 2.7 V to 3.6 V, VDDA - VSSA = 2.7 V to 3.6 V
1.4 Interrupt Controller
- Five interrupt priority levels
- Three user-programmable priority levels for each interrupt source: level 0, level 1, level 2
- Unmaskable level 3 interrupts include illegal instruction, hardware stack overflow, misaligned data access, SWI3 instruction
- Interrupt level 3 is highest priority and non-maskable. Its sources include:
- Illegal instructions
- Hardware stack overflow
- SWI instruction
- EOnCE interrupts
- Misaligned data accesses
- Lowest-priority software interrupt: level LP
- Support for nested interrupts, so that a higher priority level interrupt request can interrupt lower priority interrupt subroutine
- Masking of interrupt priority level is managed by the 56800EF core
- Two programmable fast interrupts that can be assigned to any interrupt source Overview MC56F80xxx, Rev. 2, 11/2022
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- Notification to System Integration Module (SIM) to restart clock when in wait and stop states
- Ability to relocate interrupt vector table Peripheral highlights
1.5.1 Enhanced Flex Pulse Width Modulator (eFlexPWM)
- 16 bits of resolution for center, edge-aligned, and asymmetrical PWMs
- 6 bit addition for high resolution PWM
- Fractional delay for enhanced resolution of the PWM period and edge placement
- Arbitrary PWM edge placement
- 312 ps PWM frequency and duty-cycle and deadtime resolution when NanoEdge functionality is enabled.
- PWM outputs can be configured as complementary output pairs or independent outputs
- Dedicated time-base counter with period and frequency control per submodule
- Independent top and bottom deadtime insertion for each complementary pair
- Independent control of both edges of each PWM output
- Enhanced input capture and output compare functionality on each input:
- Channels not used for PWM generation can be used for buffered output compare functions.
- Channels not used for PWM generation can be used for input capture functions.
- Enhanced dual edge capture functionality
- Synchronization of submodule to external hardware (or other PWM) is supported.
- Double-buffered PWM registers
- Integral reload rates from 1 to 16
- Half-cycle reload capability
- Multiple output trigger events can be generated per PWM cycle via hardware.
- Support for double-switching PWM outputs
- Up to eight fault inputs can be assigned to control multiple PWM outputs
- Programmable filters for fault inputs
- Independently programmable PWM output polarity
- Individual software control of each PWM output
- All outputs can be programmed to change simultaneously via a FORCE_OUT event.
- PWMX pin can optionally output a third PWM signal from each submodule
- Option to supply the source for each complementary PWM signal pair from any of the following: 1.5 Peripheral highlights MC56F80xxx, Rev. 2, 11/2022 NXP Semiconductors 7
- Crossbar module outputs
- External ADC input, taking into account values set in ADC high and low limit registers
- Direct phase shift controls among each submodule
- Trigger signal can share the same load frequency as reload signal in each submodule 1.5.2 12-bit Analog-to-Digital Converter (Cyclic type)
- Two independent 12-bit analog-to-digital converters (ADCs):
- 2 x 14-channel external inputs
- Built-in x1, x2, x4 programmable gain pre-amplifier
- Maximum ADC clock frequency up to 12.5 MHz, having period as low as 80 ns
- Single conversion time of 10 ADC clock cycles
- Additional conversion time of 8 ADC clock cycles
- Support of analog inputs for single-ended and differential (including unipolar differential) conversions
- Sequential and parallel scan modes. Parallel mode includes simultaneous and independent scan modes.
- Samples of each ADC have offset, limit and zero-crossing calculation supported
- ADC conversions can be synchronized by any module connected to the internal crossbar module, such as PWM, timer, GPIO, and comparator modules.
- Support for hardware-triggering and software-triggering conversions
- Support for a multi-triggering mode with a programmable number of conversions on each trigger
- Each ADC has ability to scan and store up to 10 conversion results.
- Current injection protection
1.5.3 Operational Amplifier (OPAMP)
- Capability of being configured as various types of amplifier:
- standalone operational amplifier
- unity gain follower (voltage follower)
- x2, x4, x8, x16 programmable gain amplifier (PGA)
- differential amplifier
- low-pass filter
- 4-to-1 input multiplexer on inverting and non-inverting input
- 4 set configurations including multiplexer inputs can be managed by internal modules and synchronized with ADCs, PWMs and timers
- Operation modes: high speed mode and low power mode Peripheral highlights MC56F80xxx, Rev. 2, 11/2022
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1.5.4 Comparator
- Full rail-to-rail comparison range
- Support for high and low speed modes
- Selectable input source includes external pins and internal DACs
- Programmable output polarity
- 8-bit programmable DAC as a voltage reference per comparator
- Three programmable hysteresis levels
- Selectable interrupt on rising-edge, falling-edge, or toggle of a comparator output
1.5.5 Periodic Interrupt Timer (PIT)
- 32-bit counter with programmable count modulo
- PIT0/1 can be master and PIT2 is slave mode only (if synchronizing with other PITs)
- The output signals of both PIT0 and PIT1 are internally connected to a peripheral crossbar module
- Can run when the CPU is in Wait/Stop modes. Can also wake up the CPU from Wait/Stop modes.
- In addition to System Bus Clock (IPBus Clock), alternate clock sources for the counter clock are also available:
- Crystal oscillator output
- 8 MHz / 2 MHz internal RC output
- On-chip low-power 200 kHz oscillator
1.5.6 Quadrature Decoder (QDC)
- Includes logic to decode quadrature signals
- Inputs can be connected to a general purpose timer to make low speed velocity measurements
- Configurable digital filter for inputs
- Quadrature decoder filter can be bypassed
- 32-bit position counter capable of modulo counting
- Position counter can be initialized by software or external events
- 16-bit position difference register
- Compare function can indicate when shaft has reached a defined position
- A watchdog timer can detect a non-rotating shaft condition
- Preloadable 16-bit revolution counter
- Maximum count frequency equals the peripheral clock rate
- Optional interrupt when both PHASEA and PHASEB inputs change in the same cycle Peripheral highlights MC56F80xxx, Rev. 2, 11/2022 NXP Semiconductors 9
1.5.7 Inter-Module Crossbar and Event Generator (EVTG) logic
- Provides generalized connections between and among on-chip peripherals: ADCs, comparators, quad-timers, eFlexPWMs, EWM, quadrature decoder, and select I/O pins
- User-defined input/output pins for all modules connected to the crossbar
- DMA request and interrupt generation from the crossbar
- Write-once protection for all registers
- The EVTG module mainly includes two parts: Two AND/OR/INVERT (known simply as the AOI) modules and one configurable Flip-Flop. It supports the generation of a configurable number of EVENT signals. The inputs are from crossbar (XBAR) outputs, and the outputs feed to XBAR inputs.
1.5.8 Quad Timer
- Four 16-bit up/down counters, with a programmable prescaler for each counter
- Operation modes: edge count, gated count, signed count, capture, compare, PWM, signal shot, single pulse, pulse string, cascaded, quadrature decode
- Programmable input filter
- Counting start can be synchronized across counters
1.5.9 Queued Serial Communications Interface (QSCI) modules with
- Operating clock can be up to two times the CPU operating frequency
- Four-word-deep FIFOs available on both transmit and receive buffers
- Standard mark/space non-return-to-zero (NRZ) format
- 16-bit integer and 3-bit fractional baud rate selection
- Full-duplex or single-wire operation
- Programmable 8-bit or 9-bit data format
- Error detection capability
- Two receiver wakeup methods:
- Idle line
- Address mark
- 1/16 bit-time noise detection
- Support for Local Interconnect Network (LIN) slave operation
1.5.10 Queued Serial Peripheral Interface (QSPI) modules
- Maximum 25 Mbit/s baud rate Peripheral highlights MC56F80xxx, Rev. 2, 11/2022
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- Selectable baud rate clock sources for low baud rate communication
- Baud rate as low as the maximum Baud rate / 4096
- Full-duplex operation
- Master and slave modes
- Double-buffered operation with separate transmit and receive registers
- Four-word-deep FIFOs available on transmit and receive buffers
- Programmable length transmissions (2 bits to 16 bits)
- Programmable transmit and receive shift order (MSB or LSB as first bit transmitted)
1.5.11 Low Power Inter-Integrated Circuit (LPI2C)
The LPI2C supports:
- Standard, Fast, Fast+ and Ultra Fast modes are supported
- High speed mode (HS) in slave mode
- High speed mode (HS) in master mode, if SCL pin implements current source pull- up (device-specific)
- Multi-master support, including synchronization and arbitration. Multi-master means any number of master nodes can be present. Additionally, master and slave roles may be changed between messages (after a STOP is sent).
- Clock stretching: Sometimes multiple I2C nodes may be driving the lines at the same time. If any I2C node is driving a line low, then that line will be low. I2C nodes that are starting to transmit a logical one (by letting the line float high) can detect that the line is low, and thereby know that another I2C node is active at the same time.
- When node detection is used on the SCL line, it is called clock stretching, and clock stretching is used as a I2C flow control mechanism for multiple laves.
- When node detection is used on the SDA line, it is called arbitration, and arbitration ensures that there is only one I2C node transmitter at a time.
- General call, 7-bit and 10-bit addressing
- Software reset, START byte and Device ID (also require software support) The LPI2C master supports:
- Command/transmit FIFO of 4words.
- Receive FIFO of 4words.
- Command FIFO will wait for idle I2C bus before initiating transfer
- Command FIFO can initiate (repeated) START and STOP conditions and one or more master-receiver transfers
- STOP condition can be generated from command FIFO, or generated automatically when the transmit FIFO is empty
- Host request input to control the start time of an I2C bus transfer Peripheral highlights MC56F80xxx, Rev. 2, 11/2022 NXP Semiconductors 11
- Flexible receive data match can generate interrupt on data match and/or discard unwanted data
- Flag and optional interrupt to signal Repeated START condition, STOP condition, loss of arbitration, unexpected NACK, and command word errors
- Supports configurable bus idle timeout and pin-stuck-low timeout The LPI2C slave supports:
- Separate I2C slave registers to minimize software overhead because of master/slave switching
- Support for 7-bit or 10-bit addressing, address range, SMBus alert and general call address
- Transmit data register that supports interrupt or DMA requests
- Receive data register that supports interrupt or DMA requests
- Software-controllable ACK or NACK, with optional clock stretching on ACK/ NACK bit
- Configurable clock stretching, to avoid transmit FIFO underrun and receive FIFO overrun errors
- Flag and optional interrupt at end of packet, STOP condition, or bit error detection
1.5.12 Windowed Computer Operating Properly (COP) watchdog
- Programmable windowed timeout period
- Support for operation in all power modes: run mode, wait mode, stop mode
- Causes loss of reference reset 128 cycles after loss of reference clock to the PLL is detected
- Selectable reference clock source in support of EN60730 and IEC61508
- Selectable clock sources:
- External crystal oscillator
- On-chip low-power 200 kHz oscillator
- System bus clock (IPBus clock)
- 8 MHz / 2 MHz IRC
- Support for interrupt generation
1.5.13 External Watchdog Monitor (EWM)
- Monitors external circuit as well as the software flow
- Programmable timeout period
- Interrupt capability prior to timeout
- Independent output (EWM_OUT_b) that places external circuit (but not CPU and peripheral) in a safe mode when EWM timeout occurs Peripheral highlights MC56F80xxx, Rev. 2, 11/2022
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- Selectable reference clock source in support of EN60730 and IEC61508
- Wait mode and Stop mode operation is not supported.
- Selectable clock sources:
- External crystal oscillator
- On-chip low-power 200 kHz oscillator
- System bus clock (IPBus clock)
- 8 MHz / 2 MHz IRC
1.5.14 Power supervisor (PMC)
- Power-on reset (POR) is released after VDD is greater than the Low-Voltage Warning threshold during supply is ramped up; CPU, peripherals, and JTAG/EOnCE controllers exit RESET state
- Brownout reset (V DD < 2.0 V)
- Critical low-voltage alarm interrupt (LVI_2p2)
- Peripheral low-voltage warning interrupt (LVI_2p65)
1.5.15 Phase-locked loop
- Output frequency range is optimized from 200 MHz to 550 MHz
- Input reference clock frequency: 8 MHz to 16 MHz
- Detection of loss of lock and loss of reference clock
- Ability to power down Clock sources
1.5.16.1 On-chip oscillators
- Tunable 8 MHz RC oscillator with 2 MHz at standby mode
- 200 kHz low frequency clock as secondary clock source for COP, EWM, PIT
1.5.16.2 Crystal oscillator
- Support for both high ESR crystal oscillator (ESR greater than 100 Ω) and ceramic resonator
- Operating frequency: 4–16 MHz
1.5.17 Cyclic Redundancy Check (CRC) generator
- Hardware 16/32-bit CRC generator
- High-speed hardware CRC calculation 1.5.16 Clock sources MC56F80xxx, Rev. 2, 11/2022 NXP Semiconductors 13
- Programmable initial seed value
- Programmable 16/32-bit polynomial
- Error detection for all single, double, odd, and most multi-bit errors
- Option to transpose input data or output data (CRC result) bitwise or bytewise, 1 which is required for certain CRC standards
- Option for inversion of final CRC result
1.5.18 General Purpose I/O (GPIO)
- Individual control of peripheral mode or GPIO mode for each pin
- Programmable push-pull or open drain output
- Configurable pullup or pulldown on all input pins
- All pins (except JTAG, RESET_B ) default to be GPIO inputs
- Controllable output slew rate
1.6 System Block Diagram
The following figure shows the maximum memory configurations supported. 1. A bytewise transposition is not possible when accessing the CRC data register via 8-bit accesses. In this case, user software must perform the bytewise transposition. Clock sources MC56F80xxx, Rev. 2, 11/2022
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Figure 1. System block diagram
2 Signal and pin descriptions
Table 2. Signal descriptions output required for proper device operation. reset, the default state is TDI. Table continues on the next page...
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Table 2. Signal descriptions (continued) rising edge of TCK and has an internal pullup resistor. After reset, the default state is TMS. capability. Otherwise, directly tie to VDD. Except being configured as GPIO. Input Reset — A direct hardware reset on the processor. internal clocks after a fixed number of internal clocks. After reset, the default state is RESET_B. and up to 22 µF for time delay if required. COP reset, or software reset. Input ANA0 — ADCA channel 0 input. (CMPC_O) Output Analog comparator C output. Input ANA1 — ADCA channel 1 input. CMPA_IN0 — Analog comparator A input 0. OPAMPA_IN0 — Operational amplifier A input 0. Table continues on the next page...
Input ANA2 — ADCA channel 2 input. VREFHA — ADCA analog reference high. CMPA_IN1 — Analog comparator A input 1. or VREFHA in the ADC Calibration Register. Input ANA3 — ADCA channel 3 input. VREFLA — ADCA analog reference low. CMPA_IN2 — Analog comparator A input 2. or VREFLA in the ADC Calibration Register. Input ANA40 — ADCA channel 4 expansion MUX input 40. CMPA_IN4 — Analog comparator A input 4. Input ANA5 — ADCA channel 5 input. CMPB_IN4 — Analog comparator B input 4. Input ANA6 — ADCA channel 6 input. CMPC_IN4 — Analog comparator C input 4. OPAMPA_IN1 — Operational amplifier A input 1. Table continues on the next page...
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Input ANA7 — ADCA channel 7 input. OPAMPA_IN2 — Operational amplifier A input 2. Input ANB0 — ADCB channel 0 input. CMPB_IN3 — Analog comparator B input 3. OPAMPB_IN3 — Operational amplifier B input 3. Input ANB1 — ADCB channel 1 input. CMPB_IN0 —Analog comparator B input 0. OPAMPB_IN0 — Operational amplifier B input 0. Input ANB2 — ADCB channel 2 input. VREFHB — ADCB analog reference high. CMPC_IN3 — Analog comparator C input 3. or VREFHB in the ADC Calibration Register. Input ANB3 — ADCB channel 3 input. VREFLB — ADCB analog reference low. CMPC_IN0 _ Analog comparator C input 0. or VREFLB in the ADC Calibration Register. Input ANB40 — ADCB channel 4 expansion MUX input 40. CMPC_IN1 — Analog comparator C input 1. Table continues on the next page...
Input ANB5 — ADCB channel 5 input. CMPC_IN2 — Analog comparator C input 2. Input ANB6 — ADCB channel 6 input. CMPB_IN1 — Analog comparator B input 1. OPAMPB_IN1 — Operational amplifier B input 1. Input ANB7 — ADCB channel 7 input. CMPB_IN2 — Analog comparator B input 2. OPAMPB_IN2 — Operational amplifier B input 2. (CLKIN0) Input External clock input 0 to OCCS. Table continues on the next page...
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(XB_OUT11) Output Crossbar module output 11. (XB_IN2) Input Crossbar module input 2. (CLKO0) Output Buffered clock output 0. SIM_CLKOUT[CLKOSEL0] bits in SIM. Quad timer channel 0 input/output. (CMPA_O) Output Analog comparator A output. (RXD0) Input SCI0 receive data input. (CLKIN1) Input External clock input 1 to OCCS. Quad timer channel 1 input/output. (CMPB_O) Output Analog comparator B output. (XB_IN8) Input Crossbar module input 8. (OPAMPA_OUT) Output Operational amplifier A output. (ANB4d) Input ADCB channel 4 expansion MUX input 4d. (XB_IN7) Input Crossbar module input 7. Quad timer channel 2 input/output. (XB_IN3) Input Crossbar module input 3. (CMP_REF) Input Input 5 of analog comparator A and B and C. (XB_IN8) Input Crossbar module input 8. Table continues on the next page...
(XB_OUT6) Output Crossbar module output 6. (RXD0) Input SCI0 receive data input. (XB_IN9) Input Crossbar module input 9. (XB_IN4) Input Crossbar module input 4. (XB_OUT8) Output Crossbar module output 8. (XB_IN5) Input Crossbar module input 5. (XB_OUT9) Output Crossbar module output 9. (LP_SCLS0) Output I2C0 secondary serial clock line. output for voltage level shift. (ANB4b) Input ADCB channel 4 expansion MUX input 4b. (PWMA_0X) Output PWM submodule 0, output X or input capture X. (LP_SDAS0) Output I2C0 secondary serial data line. output for voltage level shift. (ANA4b) Input ADCA channel 4 expansion MUX input 4b. (PWMA_1X) Output PWM submodule 1, output X or input capture X. Table continues on the next page...
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Quad timer channel 3 input/output. (XB_IN6) Input Crossbar module input 6. (EWM_OUT_B) Output External Watchdog Module output. (XB_OUT4) Output Crossbar module output 4. (PWMA_FAULT4) Input PWM Fault input 4 for disabling selected PWM outputs. (ANB4c) Input ADCB channel 4 expansion MUX input 4c. NOTE: In 4-wire mode, this is the I2C slave SCL input. (XB_OUT5) Output Crossbar module output 5. (PWMA_FAULT5) Input PWM Fault input 5 for disabling selected PWM outputs. ANA4c Input ADCA channel 4 expansion MUX input 4c. XB_OUT4 Output Crossbar module output 4. (XB_OUT5) Output Crossbar module output 5. XB_OUT6 Output Crossbar module output 6. (XB_OUT7) Output Crossbar module output 7. Table continues on the next page...
(XB_OUT8) Output Crossbar module output 8. (XB_IN3) Input Crossbar module input 3. (XB_OUT9) Output Crossbar module output 9. (ANB4e) Input ADCB channel 4 expansion MUX input 4e. (XB_OUT10) Output Crossbar module output 10. (XB_IN5) Input Crossbar module input 5. (ANA4e) Input ADCA channel 4 expansion MUX input 4e. (XB_OUT11) Output Crossbar module output 11. (OPAMPB_OUT) Output Operational amplifier B output. (CLKO1) Output Buffered clock output 1. SIM_CLKOUT[CLKOSEL1] bits in SIM. (XB_IN7) Input Crossbar module input 7. (ANA4d) Input ADCA channel 4 expansion MUX input 4d. (ANA4a) Input ADCA channel 4 expansion MUX input 4a. Table continues on the next page...
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(ANB4a) Input ADCB channel 4 expansion MUX input 4a. NOTE: In 4-wire mode, this is the I2C slave SCL input. PWM submodule 0, output X or input capture X. (PWMA_FAULT6) Input PWM Fault input 6 for disabling selected PWM outputs. (RXD1) Input SCI1 receive data input. (XB_OUT9) Output Crossbar module output 9. PWM submodule 1, output X or input capture X. (PWMA_FAULT7) Input PWM Fault input 7 for disabling selected PWM outputs. (ANB4f) Input ADCB channel 4 expansion MUX input 4f. PWM submodule 3, output X or input capture X. (XB_IN2) Input Crossbar module input 2. (ANA4f) Input ADCA channel 4 expansion MUX input 4f. (CMPC_O) Output Analog comparator C output. (XB_IN3) Input Crossbar module input 3. (RXD0) Input SCI0 receive data input. (XB_OUT10) Output Crossbar module output 10. (CMPD_O) Output Analog comparator D output. (PWMA_2X) Output PWM submodule 2, output X or input capture X.
- The glitch on this pin during ADC sampling may interfere with other analog inputs shared on this pin.
3 Signal groups
detailed in the following table. Table 3. Functional Group Pin Allocations
- QSCI1 is not available in the 32-pin package.
- 4-wire mode is not supported.
- Only LPI2C0 supports 4-wire mode.
4.1 Signal Multiplexing and Pin Assignments
for selecting which ALT functionality is available on each pin.
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Pin Name Default ALT0 ALT1 ALT2 ALT3 2 2 2 RESET_B RESET_B GPIOD4 3 3 — GPIOC0 GPIOC0 EXTAL CLKIN0 4 4 — GPIOC1 GPIOC1 XTAL 5 5 3 GPIOC2 GPIOC2 TXD0 XB_OUT11 XB_IN2 CLKO0 6 — — GPIOF8 GPIOF8 RXD0 XB_OUT10 PWMA_2X 7 6 4 GPIOC3 GPIOC3 TA0 CMPA_O RXD0 CLKIN1 8 7 5 GPIOC4 GPIOC4 TA1 CMPB_O XB_IN8 OPAMPA_OUT 9 — — GPIOA7 GPIOA7 ANA7+OPAMPA_IN2 10 — — GPIOA6 GPIOA6 ANA6+OPAMPA_ IN1+CMPC_IN4 11 — — GPIOA5 GPIOA5 ANA5+CMPB_IN4 12 8 — GPIOA4 GPIOA4 ANA40+CMPA_IN4 13 9 6 GPIOA0 GPIOA0 ANA0+CMPA_ IN3+OPAMPA_IN3 CMPC_O 14 10 7 GPIOA1 GPIOA1 ANA1+CMPA_ IN0+OPAMPA_IN0 15 11 8 GPIOA2 GPIOA2 ANA2+VREFHA+CMPA_ IN1 16 12 — GPIOA3 GPIOA3 ANA3+VREFLA+CMPA_ IN2 17 — — GPIOB7 GPIOB7 ANB7+CMPB_ IN2+OPAMPB_IN2 18 13 — GPIOC5 GPIOC5 ANB4d XB_IN7 19 — — GPIOB6 GPIOB6 ANB6+CMPB_ IN1+OPAMPB_IN1 20 — — GPIOB5 GPIOB5 ANB5+CMPC_IN2 21 14 — GPIOB4 GPIOB4 ANB40+CMPC_IN1 22 15 9 VDDA VDDA 23 16 10 VSSA VSSA 24 17 11 GPIOB0 GPIOB0 ANB0+CMPB_ IN3+OPAMPB_IN3 25 18 12 GPIOB1 GPIOB1 ANB1+CMPB_ IN0+OPAMPB_IN0 26 19 — VCAP VCAP 27 20 13 GPIOB2 GPIOB2 ANB2+VREFHB+CMPC_ IN3 28 21 — GPIOB3 GPIOB3 ANB3+VREFLB+CMPC_ IN0 29 — — VDD VDD 30 22 14 VSS VSS 31 23 15 GPIOC6 GPIOC6 TA2 XB_IN3 CMP_REF SS0_B 32 24 — GPIOC7 GPIOC7 SS0_B TXD0 XB_IN8 XB_OUT6 33 25 16 GPIOC8 GPIOC8 MISO0 RXD0 XB_IN9 34 26 17 GPIOC9 GPIOC9 SCLK0 XB_IN4 TXD0 XB_OUT8 Pinout MC56F80xxx, Rev. 2, 11/2022 NXP Semiconductors 27
Pin Name Default ALT0 ALT1 ALT2 ALT3 35 27 18 GPIOC10 GPIOC10 MOSI0 XB_IN5 MISO0 XB_OUT9 36 28 — GPIOF0 GPIOF0 XB_IN6 OPAMPB_OUT 37 29 — GPIOC11 GPIOC11 LP_SCLS0 ANB4b TXD1 PWMA_0X 38 30 — GPIOC12 GPIOC12 LP_SDAS0 ANA4b RXD1 PWMA_1X 39 — 19 GPIOF2 GPIOF2 ANA4a XB_OUT6 LP_SDA0 40 — 20 GPIOF3 GPIOF3 ANB4a XB_OUT7 LP_SCL0 41 — — GPIOF4 GPIOF4 TXD1 XB_OUT8 PWMA_0X PWMA_FAULT6 42 — — GPIOF5 GPIOF5 RXD1 XB_OUT9 PWMA_1X PWMA_FAULT7 43 31 — VSS VSS 44 32 — VDD VDD 45 33 21 GPIOE0 GPIOE0 PWMA_0B XB_OUT4 46 34 22 GPIOE1 GPIOE1 PWMA_0A XB_OUT5 47 35 23 GPIOE2 GPIOE2 PWMA_1B XB_OUT6 48 36 24 GPIOE3 GPIOE3 PWMA_1A XB_OUT7 49 37 — GPIOC13 GPIOC13 TA3 XB_IN6 EWM_OUT_B 50 38 — GPIOF1 GPIOF1 CLKO1 XB_IN7 ANA4d 51 39 25 GPIOE4 GPIOE4 PWMA_2B XB_IN2 XB_OUT8 52 40 26 GPIOE5 GPIOE5 PWMA_2A XB_IN3 XB_OUT9 53 — — GPIOE6 GPIOE6 PWMA_3B XB_IN4 ANB4e XB_OUT10 54 — — GPIOE7 GPIOE7 PWMA_3A XB_IN5 ANA4e XB_OUT11 55 41 — GPIOC14 GPIOC14 LP_SDA0 XB_OUT4 PWMA_FAULT4 ANB4c 56 42 — GPIOC15 GPIOC15 LP_SCL0 XB_OUT5 PWMA_FAULT5 ANA4c 57 43 27 VCAP VCAP 58 — — GPIOF6 GPIOF6 ANB4f PWMA_3X XB_IN2 59 — — GPIOF7 GPIOF7 ANA4f CMPC_O XB_IN3 60 44 28 VDD VDD 61 45 29 VSS VSS 62 46 30 TDO TDO GPIOD1 63 47 31 TMS TMS GPIOD3 64 48 32 TDI TDI GPIOD0
4.2 Pinout diagrams
The following diagrams show pinouts for the packages. For each pin, the diagrams show the default function. However, many signals may be multiplexed onto a single pin. Pinout MC56F80xxx, Rev. 2, 11/2022
28 NXP Semiconductors
Figure 2. 64-pin LQFP
Figure 3. 48-pin LQFP
30 NXP Semiconductors
Figure 4. 32-pin LQFP
5.1 Determining valid orderable parts
5.2 Part number list
The following table shows a part number list for this device.
Table 4. Part numbers
- The 32 LQFP and 32 QFN packages for this product are not yet available. However, the pin-out and pricing information of
6 Part identification
6.1 Description
values of these fields to determine the specific part you have received.
6.2 Format
6.3 Fields
32 NXP Semiconductors
Q Qualification status • MC = Fully qualified, general market flow
- PC = Prequalification 56F8 DSC family with flash memory and DSP56800/ DSP56800E/DSP56800EX/DSP56800EF core
- 56F8
0 DSC subfamily • 0
C Maximum CPU frequency (MHz) • 6 = 100 MHz
- 7 = 100 MHz F Primary program flash memory size • 2 = 32 KB
- 3 = 48 KB
- 4 = 64 KB P Pin count • 3 = 32
- 6 = 48
- 8 = 64 T Temperature range (℃) • V = –40 to 105
- M = –40 to 125
- FM = 32QFN
- LF = 48LQFP
- LH = 64LQFP N Packaging type • R = Tape and reel
- (Blank) = Trays
6.4 Example
This is an example part number: MC56F80748VLH
7 Terminology and guidelines
7.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip.
7.1.1 Example
This is an example of an operating requirement: Terminology and guidelines MC56F80xxx, Rev. 2, 11/2022 NXP Semiconductors 33
Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage 0.9 1.1 V
7.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions.
7.2.1 Example
This is an example of an operating behavior: Symbol Description Min. Max. Unit IWP Digital I/O weak pullup/ pulldown current 10 130 µA
7.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements.
7.3.1 Example
This is an example of an attribute: Symbol Description Min. Max. Unit CIN_D Input capacitance: digital pins — 7 pF
7.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: Terminology and guidelines MC56F80xxx, Rev. 2, 11/2022
34 NXP Semiconductors
- Operating ratings apply during operation of the chip.
- Handling ratings apply when the chip is not powered.
7.4.1 Example
This is an example of an operating rating: Symbol Description Min. Max. Unit VDD 1.0 V core supply voltage –0.3 1.2 V
7.5 Result of exceeding a rating
Failures in time (ppm) The likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. Terminology and guidelines MC56F80xxx, Rev. 2, 11/2022 NXP Semiconductors 35
7.6 Relationship between ratings and operating requirements
- No permanent failure - Correct operation Normal operating rangeFatal range Expected permanent failure Fatal range Expected permanent failure Operating rating (max.)Operating requirement (max.)Operating requirement (min.)Operating rating (min.) Operating (power on) Degraded operating range Degraded operating range No permanent failure Handling rangeFatal range Expected permanent failure Fatal range Expected permanent failure Handling rating (max.)Handling rating (min.) Handling (power off) - No permanent failure - Possible decreased life - Possible incorrect operation - No permanent failure - Possible decreased life - Possible incorrect operation
7.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
- Never exceed any of the chip’s ratings.
- During normal operation, don’t exceed any of the chip’s operating requirements.
- If you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible.
7.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
- Lies within the range of values specified by the operating behavior
- Given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions Typical values are provided as design guidelines and are neither tested nor guaranteed. Terminology and guidelines MC56F80xxx, Rev. 2, 11/2022
36 NXP Semiconductors
7.8.1 Example 1
This is an example of an operating behavior that includes a typical value: Symbol Description Min. Typ. Max. Unit IWP Digital I/O weak pullup/pulldown current 10 70 130 µA
7.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and temperature conditions: 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 °C 105 °C 25 °C –40 °C VDD (V) I (μA)DD_STOP TJ
7.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as specified): Symbol Description Value Unit TA Ambient temperature 25 °C VDD 3.3 V supply voltage 3.3 V Terminology and guidelines MC56F80xxx, Rev. 2, 11/2022 NXP Semiconductors 37
8 Ratings
8.1 Thermal handling ratings
- Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
- Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
8.2 Moisture handling ratings
- Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
8.3 ESD and latch-up ratings
temperature, unless specified otherwise in the device specification. Table 5. ESD and latch-up ratings
38 NXP Semiconductors
- Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions
- Determined according to ANSI/ESDA/JEDEC Standard JS-001-2017, For Electrostatic Discharge Sensitivity Testing,
Human Body Model (HBM) - Component Level.
- Determined according to ANSI/ESDA/JEDEC Standard JS-002-2018, For Electrostatic Discharge Sensitivity Testing,
Charged Device Model (CDM) - Device Level.
- Determined according to JEDEC Standard JESD78F, IC Latch-Up Test.
8.4 Voltage and current operating ratings
Table 6. Voltage and current operating ratings
9 General
9.1 General characteristics
unused inputs are tied to an appropriate voltage level.
9.2 AC electrical characteristics
points, as shown in Figure 5. Figure 5. Input signal measurement references output pins have the following characteristics.
- C L=30 pF loads
- Slew rate disabled
- Normal drive strength Figure 6 shows the definitions of the following signal states:
- Active state, when a bus or signal is driven, and enters a low impedance state
- Tri-stated, when a bus or signal is placed in a high impedance state
- Data Valid state, when a signal level has reached V OL or VOH
- Data Invalid state, when a signal level is in transition between V OL and VOH Data Invalid State Data1 Data3 Valid Data2 Data3 Data1 Valid Data Active Data Active Data2 Valid Data Tri-stated
Figure 6. Signal states
9.3 Nonswitching electrical specifications
40 NXP Semiconductors
9.3.1 Voltage and current operating requirements
This section includes information about recommended operating conditions. Table 7. Voltage and current operating requirements
- 2.7 V ≤ V DD ≤ 3.6 V 0.7 × VDD V VIL Input low voltage
- 2.7 V ≤ V DD ≤ 3.6 V 0.35 × VDD V VHYS Input hysteresis 0.06 × VDD — V — VIHOSC Oscillator Input Voltage High XTAL driven by an external clock source 2.0 VDD + 0.3 V — VILOSC Oscillator Input Voltage Low -0.3 0.8 V — IICIO IO pin negative DC injection current—single pin
- V IN < VSS–0.3V –3 — mA IICcont Contiguous pin DC injection current —regional limit, includes sum of negative injection currents of 16 contiguous pins
- Negative current injection –25 — mA 1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|.
9.3.2 LVD and POR operating requirements
Table 8. PMC Low-Voltage Detection (LVD) and Power-On Reset (POR) Parameters
- During 3.3-volt VDD power supply ramp down
- During 3.3-volt VDD power supply ramp up (gated by LVI_2p65)
9.3.3 Voltage and current operating behaviors
Table 9. Voltage and current operating behaviors
- 2.7 V ≤ V DD ≤ 3.6 V, IOH = –5 mA VDD – 0.5 V VOH Output high voltage — High drive pad (except RESET)
- 2.7 V ≤ V DD ≤ 3.6 V, IOH = –20 mA VDD – 0.5 V 2, 1 IOHT Output high current total for all ports — 100 mA — VOL Output low voltage — Normal drive pad (except RESET)
- 2.7 V ≤ V DD ≤ 3.6 V, IOL = 5 mA 0.5 V VOL Output low voltage — High drive pad (except RESET)
- 2.7 V ≤ V DD ≤ 3.6 V, IOL = 20 mA 0.5 V 2, 1 IOLT Output low current total for all ports — 100 mA — IIN Input leakage current (per pin) for full temperature range — 1 μA 3 IIN Input leakage current (per pin) at 25 °C — 0.025 μA 3 IIN Input leakage current (total all pins) for full temperature range — 41 μA 3 IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA — RPU Internal pullup resistors 20 50 kΩ 4 RPD Internal pulldown resistors 20 50 kΩ 5 1. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When configured as a GPIO output, it acts as a pseudo open drain output. 2. GPIOC2, GPIOC7~12, GPIOF2~3 and GPIOC14~15 support high drive strength mode. 3. Measured at VDD = 3.6 V 4. Measured at VDD supply voltage = VDD min and Vinput = VSS 5. Measured at VDD supply voltage = VDD min and Vinput = VDD
9.3.4 Power mode transition operating behaviors
Parameters listed are guaranteed by design. All address and data buses described here are internal.
42 NXP Semiconductors
Table 10. Reset, stop, wait, and interrupt timing
- If the RESET pin filter is enabled by setting the RST_FLT bit in the SIM_CTRL register to 1, the minimum pulse assertion
must be greater than 21 ns. Recommended a capacitor of up to 0.1 µF on RESET. MHz (used coming out of reset and stop modes), T=250 ns. Table 11. Power mode transition behavior
2.7 V to when the first instruction executes (over the operating
- Wakeup times are measured from GPIO toggle for wakeup till GPIO toggle at the wakeup interrupt subroutine from
- Clock configuration: CPU clock=4 MHz. System clock source is 8 MHz IRC in normal mode.
- CPU clock = 200 kHz and 8 MHz IRC on standby. Exit by an interrupt on PORTA GPIO.
- Using 64 kHz external clock; CPU Clock = 32 kHz. Exit by an interrupt on PORTA GPIO.
- Clock configuration: CPU and system clocks = 100 MHz. Bus Clock = 100 MHz. Exit by interrupt on PORTA GPIO
9.3.5 Power consumption operating behaviors
Table 12. Current Consumption (Unit: mA)
3.3 V, 25°C
3.6 V, 105°C
- Regulators are in full regulation
- Relaxation Oscillator on
- PLL powered on Table continues on the next page... General MC56F80xxx, Rev. 2, 11/2022 NXP Semiconductors 43
Table 12. Current Consumption (Unit: mA) (continued)
- Continuous MAC instructions with fetches from Program Flash
- All peripheral modules enabled. SCIs using 1X bus clock
- NanoEdge within eFlexPWM using 2X peripheral clock
- ADC/DAC (all 8-bit DACs) powered on and clocked
- Comparator powered on WAIT 100 MHz • 50 MHz Core and Peripheral clock
- Regulators are in full regulation
- Relaxation Oscillator on
- PLL powered on
- Processor Core in WAIT state
- All Peripheral modules enabled. SCIs using 1X bus clock
- NanoEdge within PWMA using 2X peripheral clock
- ADC/DAC (all 8-bit DACs), Comparator powered off STOP 4 MHz • 4 MHz Device Clock
- Regulators are in full regulation
- Relaxation Oscillator on
- PLL powered off
- Processor Core in STOP state
- All peripheral module and core clocks are off
- ADC/DAC/Comparator powered off LPRUN (LsRUN)
2 MHz • 200 kHz Device Clock from Relaxation
- ROSC in standby mode
- Regulators are in standby
- PLL disabled
- Repeat NOP instructions
- All peripheral modules enabled, except NanoEdge and cyclic ADCs. All 8-bit DACs enabled. 3
- Simple loop with running from platform instruction buffer LPWAIT (LsWAIT)
- ROSC in standby mode
- Regulators are in standby
- PLL disabled
- All peripheral modules enabled, except NanoEdge and cyclic ADCs. All 8-bit DACs enabled.3
- Processor core in wait mode LPSTOP (LsSTOP)
- ROSC in standby mode
- Regulators are in standby Table continues on the next page... General MC56F80xxx, Rev. 2, 11/2022
44 NXP Semiconductors
- PLL disabled
- Only PITs and COP enabled; other peripheral modules disabled and clocks gated off3
- Processor core in stop mode VLPRUN 200 kHz • 32 kHz Device Clock
- Clocked by a 64 kHz external clock source
- Oscillator in power down
- All ROSCs disabled
- Large regulator is in standby
- Small regulator is disabled
- PLL disabled
- Repeat NOP instructions
- All peripheral modules, except COP and EWM, disabled and clocks gated off
- Simple loop running from platform instruction buffer VLPWAIT 200 kHz • 32 kHz Device Clock
- Clocked by a 64 kHz external clock source
- Oscillator in power down
- All ROSCs disabled
- Large regulator is in standby
- Small regulator is disabled
- PLL disabled
- All peripheral modules, except COP, disabled and clocks gated off
- Processor core in wait mode VLPSTOP 200 kHz • 32 kHz Device Clock
- Clocked by a 64 kHz external clock source
- Oscillator in power down
- All ROSCs disabled
- Large regulator is in standby.
- Small regulator is disabled.
- PLL disabled
- All peripheral modules, except COP, disabled and clocks gated off
- Processor core in stop mode 1. No output switching, all ports configured as inputs, all inputs low, no DC loads. 2. Parameter value is achieved by design characterization by measuring a statistically relevant sample size across process variations. 3. In all chip LP modes and flash memory VLP modes, the maximum frequency for flash memory operation is 250 kHz due to the fixed frequency ratio of 1:4 between the CPU clock and the flash clock when running with 2 MHz external clock input and CPU running at 1 MHz.
9.3.6 Designing with radiated emissions in mind
- Perform a keyword search for “EMC design.”
9.3.7 Capacitance attributes
Table 13. Capacitance attributes
9.4 Switching specifications
9.4.1 Device clock specifications
Table 14. Device clock specifications
- using relaxation oscillator
- using external clock source 0.001 100 100 MHz fBUS Bus clock — 50 MHz
9.4.2 General switching specifications
These general-purpose specifications apply to all signals configured for GPIO signals. Table 15. General switching specifications
- The synchronous and asynchronous timing must be met.
- This is the shortest pulse that is guaranteed to be recognized.
46 NXP Semiconductors
9.5 Thermal specifications
9.5.1 Thermal operating requirements
Table 16. Thermal operating requirements
9.5.2 Thermal attributes
(heavy loads), the difference between pin voltage and VSS or VDD is very small. See Thermal design considerations for more detail on thermal design considerations.
- Thermal test board meets JEDEC specification for this package (JESD51-7, 2s2p and JESD51-3, 1s).
- Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this report is
meant to predict the performance of a package in an application-specific environment.
- Junction-to-Case (Top) thermal resistance is determined using an isothermal cold plate attached to the package top. Case
(Top) temperature refers to the mold surface temperature at the center.
10.1 Core modules
10.1.1 JTAG timing
Table 17. JTAG timing Figure 7. Test clock input timing diagram
48 NXP Semiconductors
Figure 8. Test access port timing diagram
10.2.1 Voltage regulator specifications
Table 18. Regulator 1.2 V parameters Table 19. Bandgap electrical specifications
- Typical value is trimmed at 25℃. There could be ±50 mV variation due to temperature change.
10.3 Clock modules
10.3.1 External clock operation timing
Parameters listed are guaranteed by design. Table 20. External clock operation timing requirements
- See the "External clock timing" figure for details on using the recommended connection of an external clock driver.
- The chip may not function if the high or low pulse width is smaller than 6.25 ns.
- External clock input rise time is measured from 10% to 90%.
- External clock input fall time is measured from 90% to 10%.
Note: The midpoint is V IL + (V IH – V IL )/2. Figure 9. External clock timing
10.3.2 Phase-Locked Loop timing
Table 21. Phase-Locked Loop timing
- An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
The PLL is designed for 8 MHz ~ 16 MHz input, but optimized for 8 MHz input.
- The frequency of the core system clock cannot exceed 100 MHz. If the NanoEdge PWM is available, the PLL output must
- This is the time required after the PLL is enabled to ensure reliable operation.
50 NXP Semiconductors
10.3.3 External crystal or resonator requirement
Table 22. Crystal or resonator requirement
10.3.4 RC Oscillator Timing
Table 23. RC Oscillator Electrical Specifications
8 MHz Output Frequency1
8 MHz)
8 MHz Frequency Variation over 25°C
- Frequency after factory trim
- Frequency after factory trim
- Power down to run mode transition
Figure 10. RC Oscillator Temperature Variation (Typical) After Trim (Preliminary)
10.4 Memories and memory interfaces
10.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
10.4.1.1 Flash timing specifications — program and erase
active and do not include command overhead. Table 24. NVM program/erase timing specifications Table continues on the next page...
52 NXP Semiconductors
Table 24. NVM program/erase timing specifications (continued)
- Maximum time based on expectations at cycling end-of-life.
10.4.1.2 Flash timing specifications — commands
Table 25. Flash command timing specifications
- Assumes 25 MHz flash clock frequency.
- Maximum times for erase parameters based on expectations at cycling end-of-life.
10.4.1.3 Flash high voltage current behaviors
Table 26. Flash high voltage current behaviors
10.4.1.4 Reliability specifications
Table 27. NVM reliability specifications Table continues on the next page...
Table 27. NVM reliability specifications (continued)
- Typical data retention values are based on measured response accelerated at high temperature and derated to a constant
- Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
- Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 135 °C. If the product application is
exposed to Tj > 125 °C, the reduced W/E spec applies independent of the number of W/E cycles in the high Tj band.
10.5 Analog
Table 28. 12-bit ADC Electrical Specifications Table continues on the next page...
54 NXP Semiconductors
Table 28. 12-bit ADC Electrical Specifications (continued)
- The ADC functions up to VDDA = 2.7 V. When VDDA is below 3.0 V, ADC specifications are not guaranteed
- ADC clock duty cycle is 45% ~ 55%
- Conversion range is defined for x1 gain setting. For x2 and x4 the range is 1/2 and 1/4, respectively.
- In unipolar mode, positive input must be ensured to be always greater than negative input.
- First conversion takes 10 clock cycles.
- INL/DNL is measured from VIN = VREFL to VIN = VREFH using Histogram method at x1 gain setting
- Least Significant Bit = 0.806 mV at 3.3 V VDDA, x1 gain Setting
- Offset measured at 2048 code
- Measured converting a 1 kHz input full scale sine wave
- When code runs from internal RAM
- The current that can be injected into or sourced from an unselected ADC input without affecting the performance of the
- Any off-channel with 50 kHz full-scale input to the channel being sampled with DC input (isolation crosstalk)
- From a previously sampled channel with 50 kHz full-scale input to the channel being sampled with DC input (memory
10.5.1.1 Equivalent circuit for ADC inputs
- Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling =
- Parasitic capacitance due to the chip bond pad, ESD protection devices and signal
- S1 and S2 switch phases are non-overlapping and depend on the ADC clock
Figure 11. Equivalent circuit for A/D loading
10.5.2 OPAMP electrical specifications
56 NXP Semiconductors
Table 29. OPAMP electrical specifications
- high-speed mode
- low-power mode 500 100 μA VOS Input offset voltage
- high-speed mode
- low-power mode ±1.5 ±6.5 mV VIN Common input voltage VSSA — VDDA - 1.2 V VOUT Output voltage range 0.15 — VDDA - 0.15 V CMRR Input common mode rejection ratio 60 80 — dB PSRR Power supply rejection ratio 60 80 — dB SR Slew rate 1
- high-speed mode
- low-power mode V/μs GBW Unity gain bandwidth 1
- high-speed mode
- low-power mode — 8 1.5 — MHz 1. RL = 5 ~ 10 kΩ, CL = 30 ~ 50 pf
10.5.3 CMP and 8-bit DAC electrical specifications
Table 30. Comparator and 8-bit DAC electrical specifications
- CR0[HYSTCTR] = 00 2
- CR0[HYSTCTR] = 01 1
- CR0[HYSTCTR] = 10 1
- CR0[HYSTCTR] = 11 1 105 148 mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1)3 — 25 70 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0)3 — 60 200 ns Analog comparator initialization delay4 — 40 — μs Table continues on the next page... System modules MC56F80xxx, Rev. 2, 11/2022 NXP Semiconductors 57
Table 30. Comparator and 8-bit DAC electrical specifications (continued)
- Measured with input voltage range limited to 0.7≤Vin≤VDD-0.8
- Measured with input voltage range limited to 0 to VDD
- Comparator initialization delay is defined as the time of switching the comparator from the disabled state to the enabled
state, with the comparator output settling to a stable level. Figure 12. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0) Figure 13. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
58 NXP Semiconductors
10.6.1 Enhanced NanoEdge PWM characteristics
Table 31. NanoEdge PWM timing parameters
- Reference IPbus clock of 100 MHz in NanoEdge Placement mode.
- Temperature and voltage variations do not affect NanoEdge Placement step size.
- Powerdown to NanoEdge mode transition.
10.6.2 Quad Timer timing
Parameters listed are guaranteed by design. Table 32. Timer timing
- T = clock cycle. For 100 MHz operation, T = 10 ns.
Figure 14. Timer timing
10.6.3 QDC Timing Specifications
Parameters listed are guaranteed by design. Table 33. Quadrature Decoder Timing
- In the formulas listed, T equals the system clock cycle. For 50 MHz operation, T = 20 ns. For 100 MHz operation,
Figure 15. Quadrature Decoder Timing
10.7 Communication interfaces
10.7.1 Queued Serial Peripheral Interface (SPI) timing
Parameters listed are guaranteed by design. Table 34. SPI timing Table continues on the next page...
60 NXP Semiconductors
Table 34. SPI timing (continued) Figure 16. SPI master timing (CPHA = 0)
62 NXP Semiconductors
Figure 19. SPI slave timing (CPHA = 1)
10.7.2 Queued Serial Communication Interface (SCI) timing
Parameters listed are guaranteed by design. Table 35. SCI timing
- fMAX is the frequency of operation of the SCI clock in MHz, which can be selected as the bus clock (max.50 MHz
depending on part number) or 2x bus clock (max. 100 MHz) for the devices.
64 NXP Semiconductors
Figure 20. RXD pulse width Figure 21. TXD pulse width
10.7.3 LPI2C
Table 36. LPI 2C specifications
- Hs-mode is only supported in slave mode.
- The maximum SCL clock frequency in Fast mode with maximum bus loading (400pF) can only be achieved with
information on the required pull-up devices, see I2C Bus Specification.
- See the section "General switching specifications".
11.1 Thermal design considerations
PD = Power dissipation in the package (W). The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single-layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which TJ value is closer to the application depends on the power dissipated by other components on the board.
- The T J value obtained on a single layer board is appropriate for a tightly packed printed circuit board.
- The T J value obtained on a board with the internal planes is usually appropriate if the board has low-power dissipation and if the components are well separated. When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to- case thermal resistance and a case-to-ambient thermal resistance: RΘJA = RΘJC + RΘCA where RΘJA = Package junction-to-ambient thermal resistance (°C/W) RΘJC = Package junction-to-case thermal resistance (°C/W) RΘCA = Package case-to-ambient thermal resistance (°C/W). RΘJC is device related and cannot be adjusted. You control the thermal environment to change the case to ambient thermal resistance, RΘCA. For instance, you can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. To determine the junction temperature of the device in the application when heat sinks are not used, the thermal characterization parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (ΨJT × PD) where TT = Thermocouple temperature on top of package (°C/W) ΨJT = Thermal characterization parameter (°C/W) PD = Power dissipation in package (W). Design Considerations MC56F80xxx, Rev. 2, 11/2022
66 NXP Semiconductors
The thermal characterization parameter is measured per JESD51–2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. To determine the junction temperature of the device in the application when heat sinks are used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction-to- case thermal resistance.
11.2 Electrical design considerations
This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, take normal precautions to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Use the following list of considerations to assure correct operation of the device:
- Provide a low-impedance path from the board power supply to each V DD pin on the device and from the board ground to each VSS (GND) pin.
- The minimum bypass requirement is to place 0.01–0.1 µF capacitors positioned as near as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum capacitors tend to provide better tolerances.
- Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND) pins are as short as possible.
- Bypass the V DD and VSS with approximately 100 µF, plus the number of 0.1 µF ceramic capacitors.
- PCB trace lengths should be minimal for high-frequency signals. Design Considerations MC56F80xxx, Rev. 2, 11/2022 NXP Semiconductors 67
- Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits.
- Take special care to minimize noise levels on the V REF, VDDA, and VSSA pins.
- Using separate power planes for V DD and VDDA and separate ground planes for VSS and VSSA are recommended. Connect the separate analog and digital power and ground planes as near as possible to power supply outputs. If an analog circuit and digital circuit are powered by the same power supply, then connect a small inductor or ferrite bead in serial with VDDA. Traces of VSS and VSSA should be shorted together.
- Physically separate analog components from noisy digital components by ground planes. Do not place an analog trace in parallel with digital traces. Place an analog ground trace around an analog signal trace to isolate it from digital traces.
- Because the flash memory is programmed through the JTAG/EOnCE port, SPI, SCI, or I2C, the designer should provide an interface to this port if in-circuit flash programming is desired.
- If desired, connect an external RC circuit to the RESET pin. The resistor value should be in the range of 4.7 kΩ–10 kΩ; the capacitor value should be in the range of 0.1 µF–4.7 µF.
- Configuring the RESET pin to GPIO output in normal operation in a high-noise environment may help to improve the performance of noise transient immunity.
- Add a 2.2 kΩ external pullup on the TMS pin of the JTAG port to keep EOnCE in a reset state during normal operation if JTAG converter is not present. Furthermore, configure TMS, TDI, TDO and TCK to GPIO if operation environment is very noisy.
- During reset and after reset but before I/O initialization, all the GPIO pins are at tri- state.
- To eliminate PCB trace impedance effect, each ADC input should have a no less than 33 pF 10Ω RC filter.
11.3 Power-on Reset design considerations
11.3.1 Improper power-up sequence between VDD/VSS and VDDA/
VSSA: It is recommended that VDD be kept within 100 mV of VDDA at all times, including power ramp-up and ramp-down. Failure to keep VDD within 100 mV of VDDA may cause a leakage current through the substrate, between the VDD and VDDA pad cells. This leakage current could prevent operation of the device after it powers up. The voltage Design Considerations MC56F80xxx, Rev. 2, 11/2022
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section). Also see the table in "Voltage and current operating requirements" section.
11.3.2 Heavy capacitive load on power supply output:
well before it reaches the regulation point, which is roughly around 2.5V to 2.7V. Figure 22. Supply Voltage Drop
- After POR is released, run a few hundred NOP instructions from the internal
relaxation oscillator; this gives time for the supply voltage to stabilize.
- Configure the peripherals (except the ADC) to the desired settings; the ADC should
- After the PLL locks, switch the clock from PLL prescale to postscale.
12 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to nxp.com and perform a keyword search for the drawing's document number: Drawing for package Document number to be used 32LQFP 98ASH70029A 32QFN 98ASA00473D 48-pin LQFP 98ASH00962A 64-pin LQFP 98ASS23234W The following table provides a revision history for this document. Table 37. Revision history
Revision history
MC56F80xxx, Rev. 2, 11/2022
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