MC74HC4052 ONSEMI | Alldatasheet

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This document, MC74HC4051/D has been canceled and replaced by MC74HC4051A/D LAN was sent 9/28/01 http://onsemi.com

MC54/74HC4051 MC74HC4052 MC54/74HC4053 Analog Multiplexers/ Demultiplexers High–Performance Silicon–Gate CMOS The MC54/74HC4051, MC74HC4052 and MC54/74HC4053 utilize sili- con–gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/ demultiplexers control analog voltages that may vary across the complete power supply range (from V CC to VEE ). The HC4051, HC4052 and HC4053 are identical in pinout to the metal–gate MC14051B, MC14052B and MC14053B. The Channel–Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off. The Channel–Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors they are compatible with LSTTL outputs. These devices have been designed so that the ON resistance (R on) is more linear over input voltage than Ron of metal–gate CMOS analog switches. For multiplexers/demultiplexers with channel–select latches, see HC4351, HC4352 and HC4353.

  • Fast Switching and Propagation Speeds
  • Low Crosstalk Between Switches
  • Diode Protection on All Inputs/Outputs
  • Analog Power Supply Range (V CC – VEE ) = 2.0 to 12.0 V
  • Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V
  • Improved Linearity and Lower ON Resistance Than Metal–Gate Counterparts
  • Low Noise
  • In Compliance With the Requirements of JEDEC Standard No. 7A
  • Chip Complexity: HC4051 — 184 FETs or 46 Equivalent Gates HC4052 — 168 FETs or 42 Equivalent Gates HC4053 — 156 FETs or 39 Equivalent Gates LOGIC DIAGRAM MC54/74HC4051 Single–Pole, 8–Position Plus Common Off X0 13 X1 14 X2 15 X3 12 X4 1 X5 5 X6 2 X7 4 A 11 B 10 C 9 ENABLE 6 MULTIPLEXER/ DEMULTIPLEXER X3 ANALOG INPUTS/ CHANNEL INPUTS PIN 16 = VCC PIN 7 = VEE PIN 8 = GND COMMON OUTPUT/ INPUT 1516 14 13 12 11 10 21 34567 VCC X2 X1 X0 X3 A B C X4 X6 X X7 X5 Enable V EE GND Pinout: MC54/74HC4051 (Top View) OUTPUTS SELECT L L L L H H H H X L L H H L L H H X L H L H L H L H X MC54/74HC4051 MC74HC4052 MC54/74HC4053 FUNCTION TABLE – MC54/74HC4051 Control Inputs ON ChannelsEnable Select CBA NONE L L L L L L L L H X = Don’t Care D SUFFIX SOIC PACKAGE CASE 751B–05 N SUFFIX PLASTIC PACKAGE CASE 648–08 J SUFFIX CERAMIC PACKAGE CASE 620–10

ORDERING INFORMATION

CASE 948F–01 DW SUFFIX SOIC PACKAGE CASE 751G–021

MC54/74HC4051 MC74HC4052 MC54/74HC4053 LOGIC DIAGRAM MC74HC4052 Double–Pole, 4–Position Plus Common Off X0 12 X1 14 X2 15 X3 11 Y0 1 Y1 5 Y2 2 Y3 4 A 10 B 9 ENABLE 6 X SWITCH Y SWITCH X13 ANALOG INPUTS/OUTPUTS CHANNELSELECT INPUTS PIN 16 = VCC PIN 7 = VEE PIN 8 = GND COMMON OUTPUTS/INPUTS L L H H X L H L H X FUNCTION TABLE – MC74HC4052 Control Inputs ON ChannelsEnable Select BA L L L L H X = Don’t Care Pinout: MC74HC4052 (Top View) 1516 14 13 12 11 10 21 34567 VCC X2 X1 X X0 X3 A B Y0 Y2 Y Y3 Y1 Enable V EE GND NONE LOGIC DIAGRAM MC54/74HC4053 Triple Single–Pole, Double–Position Plus Common Off X0 12 X1 13 A 11 B 10 C 9 ENABLE 6 X SWITCH Y SWITCH X14 ANALOG INPUTS/OUTPUTS CHANNELSELECT INPUTS PIN 16 = VCC PIN 7 = VEE PIN 8 = GND COMMON OUTPUTS/INPUTS L L L L H H H H X L L H H L L H H X L H L H L H L H X FUNCTION TABLE – MC54/74HC4053 Control Inputs ON ChannelsEnable Select CBA L L L L L L L L H X = Don’t Care Pinout: MC54/74HC4053 (Top View) 1516 14 13 12 11 10 21 34567 VCC Y X X1 X0 A B C Y1 Y0 Z1 Z Z0 Enable V EE GND NONE Y0 2 Y1 1 Y15 Z0 5 Z1 3 Z4Z SWITCH NOTE: This device allows independent control of each switch. Channel–Select Input A controls the X–Switch, Input B controls the Y–Switch and Input C controls the Z–Switch

MC54/74HC4051 MC74HC4052 MC54/74HC4053 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* ÎÎÎ ÎÎÎ Symbol ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Parameter ÎÎÎÎÎÎ ÎÎÎÎÎÎ Value ÎÎÎ ÎÎÎ Unit ÎÎÎ Î Î Î ÎÎÎ VCC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Positive DC Supply Voltage (Referenced to GND) (Referenced to VEE ) ÎÎÎÎÎÎ Î ÎÎÎÎ Î ÎÎÎÎÎÎ – 0.5 to + 7.0 – 0.5 to + 14.0 ÎÎÎ Î Î Î ÎÎÎ V ÎÎÎ ÎÎÎ VEE ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Negative DC Supply Voltage (Referenced to GND) ÎÎÎÎÎÎ ÎÎÎÎÎÎ – 7.0 to + 5.0 ÎÎÎ ÎÎÎ V ÎÎÎ Î Î Î ÎÎÎ VIS ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Analog Input Voltage ÎÎÎÎÎÎ Î ÎÎÎÎ Î ÎÎÎÎÎÎ VEE – 0.5 to VCC + 0.5 ÎÎÎ Î Î Î ÎÎÎ V ÎÎÎ ÎÎÎ Vin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Digital Input Voltage (Referenced to GND) ÎÎÎÎÎÎ ÎÎÎÎÎÎ – 0.5 to VCC + 0.5 ÎÎÎ ÎÎÎ V ÎÎÎ ÎÎÎ I ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Current, Into or Out of Any Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ ± 25 ÎÎÎ ÎÎÎ mA ÎÎÎ Î Î Î ÎÎÎ PD ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation in Still Air, Plastic or Ceramic DIP† ÎÎÎÎÎÎ Î ÎÎÎÎ Î ÎÎÎÎÎÎ 750 500 450 ÎÎÎ Î Î Î ÎÎÎ mW ÎÎÎ ÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature Range ÎÎÎÎÎÎ ÎÎÎÎÎÎ – 65 to + 150 ÎÎÎ ÎÎÎ C ÎÎÎ Î Î Î ÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package Ceramic DIP ÎÎÎÎÎÎ Î ÎÎÎÎ Î ÎÎÎÎÎÎ 260 300 ÎÎÎ Î Î Î ÎÎÎ C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. †Derating — Plastic DIP: – 10 mW/C from 65 to 125C Ceramic DIP: – 10 mW/C from 100 to 125C RECOMMENDED OPERATING CONDITIONS ÎÎÎÎ ÎÎÎÎ Symbol ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Parameter ÎÎÎ ÎÎÎ Min ÎÎÎ ÎÎÎ Max ÎÎÎ ÎÎÎ Unit ÎÎÎÎ Î ÎÎ Î ÎÎÎÎ VCC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Positive DC Supply Voltage (Referenced to GND) (Referenced to VEE ) ÎÎÎ Î Î Î ÎÎÎ 2.0 2.0 ÎÎÎ Î Î Î ÎÎÎ 6.0 12.0 ÎÎÎ Î Î Î ÎÎÎ V ÎÎÎÎ ÎÎÎÎ VEE ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Negative DC Supply Voltage, Output (Referenced to GND) ÎÎÎ ÎÎÎ – 6.0 ÎÎÎ ÎÎÎ GND ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ VIS ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Analog Input Voltage ÎÎÎ ÎÎÎ VEE ÎÎÎ ÎÎÎ VCC ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ Vin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Digital Input Voltage (Referenced to GND) ÎÎÎ ÎÎÎ GND ÎÎÎ ÎÎÎ VCC ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ VIO* ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Static or Dynamic Voltage Across Switch ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 1.2 ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ TA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Operating Temperature Range, All Package Types ÎÎÎ ÎÎÎ – 55 ÎÎÎ ÎÎÎ + 125 ÎÎÎ ÎÎÎ C ÎÎÎÎ Î ÎÎ Î Î ÎÎ Î ÎÎÎÎ tr, tf ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Rise/Fall Time V CC = 2.0 V (Channel Select or Enable Inputs) VCC = 4.5 V VCC = 6.0 V ÎÎÎ Î Î Î Î Î Î ÎÎÎ ÎÎÎ Î Î Î Î Î Î ÎÎÎ 1000 500 400 ÎÎÎ Î Î Î Î Î Î ÎÎÎ ns * For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance cir- cuit. For proper operation, V in and Vout should be constrained to the range GND (Vin or Vout) VCC . Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.

MC54/74HC4051 MC74HC4052 MC54/74HC4053 DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted VCC Guaranteed Limit Symbol Parameter Condition VCC V –55 to 25°C ≤85°C ≤125°C Unit VIH Minimum High–Level Input Voltage, Channel–Select or Enable Inputs R on = Per Spec 2.0 4.5 6.0 1.50 3.15 4.20 1.50 3.15 4.20 1.50 3.15 4.20 V VIL Maximum Low–Level Input Voltage, Channel–Select or Enable Inputs R on = Per Spec 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V Iin Maximum Input Leakage Current, Channel–Select or Enable Inputs Vin = VCC or GND, VEE = – 6.0 V ICC Maximum Quiescent Supply Current (per Package) Channel Select, Enable and V IS = VCC or GND; V EE = GND VIO = 0 V V EE = – 6.0 6.0 6.0 160 µA DC CHARACTERISTICS — Analog Section Guaranteed Limit Symbol Parameter Condition VCC VEE –55 to 25°C ≤85°C ≤125°C Unit R on Maximum “ON” Resistance Vin = VIL or VIH; VIS = VCC to VEE ; IS ≤ 2.0 mA (Figures 1, 2) 4.5 4.5 6.0 0.0 – 4.5 – 6.0 190 120 100 240 150 125 280 170 140 Ω Vin = VIL or VIH; VIS = VCC or VEE (Endpoints); IS ≤ 2.0 mA (Figures 1, 2) 4.5 4.5 6.0 0.0 – 4.5 – 6.0 150 100 190 125 100 230 140 115 ΔR on Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package Vin = VIL or VIH; VIS = 1/2 (VCC – VEE ); IS ≤ 2.0 mA 4.5 4.5 6.0 0.0 – 4.5 – 6.0 Ω Ioff Maximum Off–Channel Leakage Current, Any One Channel Vin = VIL or VIH; VIO = VCC – VEE ; Switch Off (Figure 3) µA Maximum Off–Channel HC4051 Leakage Current, HC4052 Common Channel HC4053 Vin = VIL or VIH; VIO = VCC – VEE ; Switch Off (Figure 4) 6.0 6.0 6.0 – 6.0 – 6.0 – 6.0 0.2 0.1 0.1 2.0 1.0 1.0 4.0 2.0 2.0 Ion Maximum On–Channel HC4051 Leakage Current, HC4052 Channel–to–Channel HC4053 Vin = VIL or VIH; Switch–to–Switch = VCC – VEE ; (Figure 5) 6.0 6.0 6.0 – 6.0 – 6.0 – 6.0 0.2 0.1 0.1 2.0 1.0 1.0 4.0 2.0 2.0 µA

MC54/74HC4051 MC74HC4052 MC54/74HC4053 AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) VCC Guaranteed Limit Symbol Parameter VCC V –55 to 25°C ≤85°C ≤125°C Unit tPLH , tPHL Maximum Propagation Delay, Channel–Select to Analog Output (Figure 9) 2.0 4.5 6.0 370 465 550 110 ns tPLH , tPHL Maximum Propagation Delay, Analog Input to Analog Output (Figure 10) 2.0 4.5 6.0 ns tPLZ , tPHZ Maximum Propagation Delay, Enable to Analog Output (Figure 11) 2.0 4.5 6.0 290 364 430 ns tPZL , tPZH Maximum Propagation Delay, Enable to Analog Output (Figure 11) 2.0 4.5 6.0 345 435 515 103 ns C in Maximum Input Capacitance, Channel–Select or Enable Inputs 10 10 10 pF C I/O Maximum Capacitance Analog I/O 35 35 35 pF (All Switches Off) Common O/I: HC4051 HC4052 HC4053 130 130 130 Feedthrough 1.0 1.0 1.0 Typical @ 25°C, VCC = 5.0 V, VEE = 0 V C PD Power Dissipation Capacitance (Figure 13)* HC4051 HC4052 HC4053 pF

MC54/74HC4051 MC74HC4052 MC54/74HC4053 ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V) VCC VEE Limit* Symbol Parameter Condition VCC V VEE V 25°C Unit BW Maximum On–Channel Bandwidth Mi i F R fin = 1MHz Sine Wave; Adjust fin Voltage to Obt i 0dB t V If F ‘51 ‘52 ‘53 MHz or Minimum Frequency Response (Figure 6) Obtain 0dBm at VOS ; Increase fin Frequency Until dB Meter Reads –3dB; R L = 50Ω , CL = 10pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 120 120 120 — Off–Channel Feedthrough Isolation (Figure 7) fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600Ω , CL = 50pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 –50 –50 –50 dB fin = 1.0MHz, RL = 50Ω , CL = 10pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 –40 –40 –40 — Feedthrough Noise. Channel–Select Input to Common I/O (Figure 8) Vin ≤ 1MHz Square Wave (tr = tf = 6ns); Adjust RL at Setup so that IS = 0A; Enable = GND R L = 600Ω , CL = 50pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 105 135 mV PP R L = 10kΩ , CL = 10pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 145 190 — Crosstalk Between Any Two Switches (Figure 12) (Test does not apply to HC4051) fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600Ω , CL = 50pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 –50 –50 –50 dB fin = 1.0MHz, RL = 50Ω , CL = 10pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 –60 –60 –60 THD Total Harmonic Distortion (Figure 14) fin = 1kHz, RL = 10kΩ , CL = 50pF THD = THD measured – THDsource VIS = 4.0VPP sine wave VIS = 8.0VPP sine wave VIS = 11.0VPP sine wave 2.25 4.50 6.00 –2.25 –4.50 –6.00 0.10 0.08 0.05 * Limits not tested. Determined by design and verified by qualification.

MC54/74HC4051 MC74HC4052 MC54/74HC4053 OUTLINE DIMENSIONS J SUFFIX CERAMIC PACKAGE CASE 620–10 ISSUE V N SUFFIX PLASTIC PACKAGE CASE 648–08 ISSUE R 19.05 6.10 /C0266 0.39 1.40 0.21 3.18 19.93 7.49 5.08 0.50 1.65 0.38 4.31 0.51 15° 1.01

1.27 BSC

2.54 BSC

7.62 BSC

0.750 0.240 /C0266 0.015 0.055 0.008 0.125 0.785 0.295 0.200 0.020 0.065 0.015 0.170

0.050 BSC

0.100 BSC

0.300 BSC

A B C D E F G J K L M N 0.020 15° 0.040 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. 916 C KN G E F D 16 PL –SEATING PLANE M L J 16 PL 0.25 (0.010) T AM S 0.25 (0.010) T BM S MIN MINMAX MAX INCHES MILLIMETERS DIM A B C D F G H J K L M S 18.80 6.35 3.69 0.39 1.02 0.21 2.80 7.50 0.51 19.55 6.85 4.44 0.53 1.77 0.38 3.30 7.74 10° 1.01 0.740 0.250 0.145 0.015 0.040 0.008 0.110 0.295 0.020 0.770 0.270 0.175 0.021 0.070 0.015 0.130 0.305 10° 0.040 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B 916 F H G D 16 PL S C SEATING PLANE K J M L TA0.25 (0.010) M M 0.25 (0.010) T B AM S S MIN MINMAX MAX MILLIMETERS INCHES DIM A B C D F G J K M P R 9.80 3.80 1.35 0.35 0.40 0.19 0.10 5.80 0.25 10.00 4.00 1.75 0.49 1.25 0.25 0.25 6.20 0.50 0.386 0.150 0.054 0.014 0.016 0.008 0.004 0.229 0.010 0.393 0.157 0.068 0.019 0.049 0.009 0.009 0.244 0.019 1.27 BSC 0.050 BSC NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 1 8 916 D16PL K C G –SEATING PLANE R X 45° M J F P 8 PL 0.25 (0.010) BM M D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J

MC54/74HC4051 MC74HC4052 MC54/74HC4053 OUTLINE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F–01 ISSUE O ÇÇ ÇÇ ÇÇ DIM MIN MAX MIN MAX INCHESMILLIMETERS A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0 8 0 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. SECTION N–N SEATING PLANE IDENT. PIN 1 1 8 16 9 DETAIL E J B C D A K H G ÉÉ ÉÉ ÉÉ DETAIL E F M L 2X L/2 –U– SU0.15 (0.006) T SU0.15 (0.006) T SUM0.10 (0.004) V ST 0.10 (0.004) –T– –V– –W– 0.25 (0.010) 16X REFK N N DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G–02 ISSUE A DIM MIN MAX MIN MAX INCHESMILLIMETERS A 10.15 10.45 0.400 0.411 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 F 0.50 0.90 0.020 0.035 G 1.27 BSC 0.050 BSC J 0.25 0.32 0.010 0.012 K 0.10 0.25 0.004 0.009 M 0 7 0 7 P 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029 MBM0.010 (0.25) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. –A– –B– P 8X G14X D16X SEATING PLANE –T– SAM0.010 (0.25) B ST 16 9 F J R X 45 M C K

MC54/74HC4051 MC74HC4052 MC54/74HC4053 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION JAPAN : ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone : 81–3–5740–2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. MC74HC4051/D Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone : 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800–282–9855 Toll Free USA/Canada