MC54HC138 MOTOROLA | Alldatasheet

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[aS MOTOROLA SC {LOGIC} D2 ve b3b7252 OO8020b 3 Tr D i MOTOROLA Y-lob-Qiesg mz SEMICONDUCTOR saute ene . | 1-of-8 Decoder/Demultiplexer i High-Performance Silicon-Gate CMOS 4 surx ‘The MC54/74HC138 is identical in pinout to the L$138. The device inputs, are La CASE 620-09 compatible with standard CMOS outputs; with pullup resistors, they are compatible . with LSTTL outputs. SUFFIX ‘The HC138 decodes a three-bit Address to one-of-eight active-low outputs. This PLASTIC device features three Chip Select inputs, two active-low and one active-high to fa- CASE 648-06 cilitate the demultiplexing, cascading, and chip-selecting functions. The demultiplex- ” ing function is accomplished by using the Address inputs to select the desired 1 device output; one of the Chip Selects is used as a data input while the other Chip D SUFFIX Selects are held in their active states, te soic @ Output Drive Capability: 10 LSTTL Loads Dae CASE 7518-03 © Outputs Directly Interface to CMOS, NMOS, and TTL @ Operating Voltage Range: 2 to 6 V @ Low Input Current: 1 pA ORDERING INFORMATION . @ High Noise immunity Characteristic of CMOS Devices - . ‘@ In Compliance with the Requirements Defined by JEDEC Standard No. 7A MC74HCXXXN- Plastic @ Chip Complexity: 116 FETs or 29 Equivalent Gates MC54HCXXXJ Ceramic MG7™HHOKXD SOIC | Ta= 85° to 125°C forall packages. . Dimensions in Chapter 7. LOGIC DIAGRAM | ao — 18 yo PIN ASSIGNMENT Address: 2 4 fie 166 A2 3 13 2 1 2 mas by 9 | Active tow A ‘Outputs cs2 94 130 Y2 csofs wp va 10. Y6 csi ge Wp Y¥4 2 6 wy wh vs 7 eno qs 9p v6 wv FUNCTION TABLE css —8 chip. . Select { CS2 puts Inputs css —. [cSt C82 CS3|A2 At AO| vO V1 2 V3 Y4 Y5 Y6 Y7 XX HIXX X[K HHH HHH Pint0=Vec XH OX|X XH HHH Pin 8 =GND bX X/X X X}/H OH HH HH HH H L LIL L LIL HHHHHHH Ho L LIL LH}H LHHHHHH H L LIL HLIHHLHHHHH Hot Lit HH}H HH LH HHH H L LIHL LH HHHLHHH Ho L LJHL HH HHHHLHH H L LIH HLTH HHHRHLH Hot CIWWHIWHHH HHA ‘ Hs high level (steady stato) L=low level (steady state) X=-don't care PCT MOTOROLA HIGH-SPEED CMOS LOGIC DATA 5-142

MOTOROLA SC {LOGIC} D2 DEB L3b7252 oosnz07 5 fF 80207 oO MC54/74HC138 J-lolo-a) -SS MAXIMUM RATINGS* [-Srmbei[_Peramater_ [Valu | unit] [This dovco contane protean ieuity to guard egsnet damage [x DC Supply Voltage (Referer to GND) to +7.0 due to high stati voltages or eloctric DC input Vatage(Roerenced to GND) fli. However, precsutons rant . DC Output Voltage (Referenced to GND) =05 0 Voc+0.65 bbe taken to avoid applications of any votage higher than maximum rated [tin |e inp pe [a | enone Se ne” mena te circuit. For proper operation, Vip and [Ico [06 suv Curent Voc od GND Pins [260 [ma] | Venn shoul be constranca ne ‘Power Dissipation in Still Air, Plastic or Ceramio DIPt 750 range GND s(Vjq oF Vout) Vcc. SOIC Packaget 500 Unused inputs must always be tied [Taig |Stoteoe Temperate | | to an spropea log votge lve a_i Tongans —______ | ee fea, ether OND of Voc), Unused i. | ead Temperature, Tenor Gao Tor 0 Seconds 5 ier GND or Vcc) (Plastic DIP or SOIC Package) 260 = line . (Ceramic DIP) 300 ‘Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended ‘Operating Conditions. ‘tDerating — Plastic DIP: ~ 10 mW/°C from 66° to 125°C. Goran DIP) 10 mW/°C tom 100 to 1580 ‘SOIC Package: —7 mW/°C from 65° to 125°C . For high frequency or heavy lad considerations, see Chapter 4. . RECOMMENDED OPERATING CONDITIONS. [ Symbor[ Parameter (Min ‘| Max | Unie | [_ Voc _|Be Supply Veaoe Reernced to GNDY [20 [eo | v_| [Win Vour]0C input Vetge, Output Veage (Referenced to GNOV | 0 | Veo |v | Operating Temperature, Al Package Types [=e [+15 | -c_| | Te 2 ]put fn end Fl Tine Veo=20v] ‘00 | (Figure 2) Vec=4.5V. 600 Veco =6.0V 400 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) ‘Symbol Test Conditions 25°C to asec Vin | Minimum High-Level Input Vout=0.1 Vor Vog-0.1 V 20 15 165 Vv Voltage Houtl $20 2A 45 3.15 3.15 @o a2 _| 42 Vit | Meximum Low-Level Input Vout=0.1 V or Vec—0.1V 20 03 Vv Voltage Houtl $20 pA 45 09 6.0 12 Von | Minimum Wah tee Oust Vins W 20] 18] 18 ta] Vatege Neate a as | aa | de | de 6.0 5.9 59 59 Vin= Vin or ViL Toutl=4.0mA] 4.6 | 3.98 3.70 VoL | Maximum Low-Level Output | Vin=Viy or Vin. 20 01 Vv Voltage Houtl $20 nA 45 ot oo a Vin=Vin or Vi, Toutl=4.0mA| 45 | 0.26 033 0.40 [in [Moxirum input tsatage Curent |Vip=Veger@no | 60 | 201 | ato] sta] A] 'c¢ [Maximum Quiescent Supply | Vin= Vcc or GND oA . Current (per Package) lout=0 nA ‘NOTE: Information on typical parametric values can be found in Chapter 4, . MOTOROLA HIGH-SPEED CMOS LOGIC DATA . 5-143

TS | MOTOROLA SC {LOGIC} O2 DEP b3n72s2 ooanens 7 Jo MC54/74HC138 T- ble-Q1-55 AC ELECTRICAL CHARACTERISTICS (C, =50 pF, Input t,=t,=6 ns) wow . 55°C Maximum Propagation Delay, input A to Output Y_ 20 160 190 25 a | 2 | 3 | 3 PHL 20 250 300

45 J 60

6.0 a 51 1PLH. | Maximum Propagation Delay, CS1 to Output 20 | 160 190 25 tpHL | (Figures 2 and 4) 45 30 Ey 45 6.0 26 33 3B Maximum Propagation Delay, CS2 or CS3 to Output Y 20 150, 190 2 (Figures 3 and 4) 45 cy 3 45 6.0 26 3 3 aL 20] ms] a0] 28s

45 KJ 4 iJ

TTL, | Meximum Output Transition Time, Any Output B 6 110 THLE (Figures 2 and 4) 16 19 2 . = 13 16 19 [Cin [Maximum input Capacities | | tO | tt TS | NOTES: | 1 sc propagation delays with loads ther than 80 p se Chapter 4. | 2: (aoe on tye! parame values canbe fase a Chota 4, Power UsspationCapacanca (Pr Package Used to determine the no-load dynamic power consumption: Po=Cpp Vec*t+Icc Veo Peon ore rass, oe Chapt 4. SWITCHING WAVEFORMS : FIGURE 1 FIGURE 2 -Valid- -Valid- te tf Vee — Veo avo fi) on tPLH- PHL tPHL- tPLH 190% Output Y 50% Output Y ht tTHL- tTLH FIGURE 3 FIGURE 4 — TEST CIRCUIT ty ty Test Point Veo i It 50%. . Output ceo ess | 80% Device css Ge — ono Under . APHL *PLH Test cu iy L ATHL ‘TLH * Includes all probe and jig capacitance. MOTOROLA HIGH-SPEED CMOS LOGIC DATA 5-144 . .

a MOTOROLA SC {LOGIC} O2 DEB e3e7252 oosoeo4 4 i D — | : MC54/74HC138 V-lalo-21-55 PIN DESCRIPTIONS . ADDRESS INPUTS: ‘outputs follow the Address inputs. For any other combination of CS1, A0, Al, A2 (PINS 1, 2, 3) ~ Address inputs. These inputs, when C2, and CS3, the outputs are at a logic high. ; tho chip io slated, dotemine whsh ofthe eight eutpt te bene. : tow. OUTPUTS ‘YO-Y7 (PINS 16, 14, 13, 12, 11, 10, 9, 7) — Active-ow Decoded CONTROL INPUTS ‘outputs, These outputs assume # low level when addressed and the CS1, CS2, CS3 (PINS 6, 4, 6) — Chip select inputs. For CS1 at a chip is selected. These outputs remain high when not addressed or high level and CS2, CS3 at a low level, the chip is selected and the ‘the chip is not selected. | EXPANDED LOGIC DIAGRAM tp -D Doo : ==>: ¢ “ . FOP D Dan 2 wt {> Hisage pre LS TED ED “Leet | Ef SOD pe nfo {> LL Py Py LO 0 FOE D 5 d cS3. a D == ee ,; cd es qa [ove cl TT MOTOROLA HIGH-SPEED CMOS LOGIC DATA . . 5-145