MC5474HC4060A MOTOROLA | Alldatasheet

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/C0077/C0079/C0084/C0079/C0082/C0079/C0076/C0065 SEMICONDUCTOR TECHNICAL DATA 3–1 REV 6 Motorola, Inc. 1995 10/95 3–1 REV 1 Motorola, Inc. 1996 /C0049/C0052/C0045/C0083/C0116/C0097/C0103/C0101 /C0066/C0105/C0110/C0097/C0114/C0121 /C0082/C0105/C0112/C0112/C0108/C0101 /C0067/C0111/C0117/C0110/C0116/C0101/C0114 /C0087/C0105/C0116/C0104 /C0079/C0115/C0099/C0105/C0108/C0108/C0097/C0116/C0111/C0114 High–Performance Silicon–Gate CMOS The MC54/74C4060A is identical in pinout to the standard CMOS MC14060B. The device inputs are compatible with standard CMOS out- puts; with pullup resistors, they are compatible with LSTTL outputs. This device consists of 14 master–slave flip–flops and an oscillator with a frequency that is controlled either by a crystal or by an RC circuit connected externally. The output of each flip–flop feeds the next and the frequency at each output is half of that of the preceding one. The state of the counter advances on the negative–going edge of the Osc In. The active–high Reset is asynchronous and disables the oscillator to allow very low power consumption during stand–by operation. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with Osc Out 2 of the HC4060A.

  • Output Drive Capability: 10 LSTTL Loads
  • Outputs Directly Interface to CMOS, NMOS, and TTL
  • Operating Voltage Range: 2 to 6 V
  • Low Input Current: 1 µA
  • High Noise Immunity Characteristic of CMOS Devices
  • In Compliance With JEDEC Standard No. 7A Requirements
  • Chip Complexity: 390 FETs or 97.5 Equivalent Gates LOGIC DIAGRAM Q47 Q55 Q64 Q76 Q814 Q913 Q1015 Q121 Q132 Q143 Osc In 11 Reset 12 Pin 16 = VCC Pin 8 = GND Osc Out 1 Osc Out 2 910 1516 14 13 12 11 10 21 3 4 5 6 7 VCC Q10 Q8 Q9 Reset Osc In Osc Out 1 Osc Out 2 Q12 Q13 Q14 Q6 Q5 Q7 Q4 GND Pinout: 16–Lead Plastic Package (Top View) /C0077/C0067/C0053/C0052/C0047/C0055/C0052/C0072/C0067/C0052/C0048/C0054/C0048/C0065 FUNCTION TABLE Clock Reset Output State X L L H No Charge Advance to Next State All Outputs Are Low D SUFFIX SOIC PACKAGE CASE 751B–05 N SUFFIX PLASTIC PACKAGE CASE 648–08 J SUFFIX CERAMIC PACKAGE CASE 620–10

ORDERING INFORMATION

CASE 748C–03

MOTOROLA High–Speed CMOS Logic Data DL129 — Rev 6 3–2 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Symbol ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Parameter ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ Value ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Unit ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ VCC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Supply Voltage (Referenced to GND) ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ – 0.5 to + 7.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ V ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Vin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Input Voltage (Referenced to GND) ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ – 0.5 to VCC + 0.5 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ V ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Vout ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Output Voltage (Referenced to GND) ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ – 0.5 to VCC + 0.5 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ V ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Iin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Input Current, per Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ±/n63686172000000000000000020 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mA ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Iout ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Output Current, per Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ±/n63686172000000000000000025 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mA ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ICC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Supply Current, VCC and GND Pins ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ±/n63686172000000000000000050 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mA ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ PD ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation in Still Air, Plastic or Ceramic DIP† ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ 750 500 450 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mW ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature Range ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ – 65 to + 150 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ /C0095C ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP , SOIC or TSSOP Package Ceramic DIP ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ 260 300 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ /C0095C *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. †Derating — Plastic DIP: – 10 mW//C0095C from 65/C0095 to 125/C0095C Ceramic DIP: – 10 mW//C0095C from 100/C0095 to 125/C0095C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ Symbol ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Parameter ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Min ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Max ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Unit ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VCC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Supply Voltage (Referenced to GND) ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 2.5* ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 6.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ Vin, Vout ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Input Voltage, Output Voltage (Referenced to GND) ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ VCC ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ TA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Operating T emperature Range, All Package Types ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ – 55 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ + 125 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ /C0095C ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tr, tf ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Rise/Fall Time V CC = 2.0 V (Figure 1) V CC = 4.5 V VCC = 6.0 V ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 1000 500 400 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns * The oscillator is guaranteed to function at 2.5 V minimum. However, parametrics are tested at 2.0 V by driving Pin 11 with an external clock source. DC CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Condition VCC V Guaranteed Limit UnitSymbol Parameter Condition VCC V –55 to 25°C ≤85°C ≤125°C Unit VIH Minimum High–Level Input VoltageVout = 0.1V or VCC –0.1V |Iout| ≤ 20µA 2.0 3.0 4.5 6.0 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 V VIL Maximum Low–Level Input VoltageVout = 0.1V or VCC – 0.1V |Iout| ≤ 20µA 2.0 3.0 4.5 6.0 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 V VOH Minimum High–Level Output Voltage (Q4–Q10, Q12–Q14) Vin = VIH or VIL |Iout| ≤ 20µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V Vin =VIH or VIL |Iout| ≤ 2.4mA |Iout| ≤ 4.0mA |Iout| ≤ 5.2mA 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance cir- cuit. For proper operation, Vin and Vout should be constrained to the range GND /C0118 (Vin or Vout) /C0118 VCC . Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC ). Unused outputs must be left open.

High–Speed CMOS Logic Data DL129 — Rev 6 3–3 MOTOROLA DC CHARACTERISTICS (Voltages Referenced to GND) Symbol Unit Guaranteed LimitVCC VConditionParameterSymbol Unit≤125°C≤85°C–55 to 25°C VCC VConditionParameter VOL Maximum Low–Level Output Voltage (Q4–Q10, Q12–Q14) Vin = VIH or VIL |Iout| ≤ 20µA 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V Vin = VIH or VIL |Iout| ≤ 2.4mA |Iout| ≤ 4.0mA |Iout| ≤ 5.2mA 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 VOH Minimum High–Level Output Voltage (Osc Out 1, Osc Out 2) Vin = VCC or GND |Iout| ≤ 20µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V Vin =VCC or GND |Iout| ≤ 0.7mA |Iout| ≤ 1.0mA |Iout| ≤ 1.3mA 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 VOL Maximum Low–Level Output Voltage (Osc Out 1, Osc Out 2) Vin = VCC or GND |Iout| ≤ 20µA 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V Vin =VCC or GND |Iout| ≤ 0.7mA |Iout| ≤ 1.0mA |Iout| ≤ 1.3mA 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0µA 6.0 4 40 160 µA NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). AC CHARACTERISTICS (CL = 50 pF , Input tr = tf = 6 ns) Symbol Parameter VCC V Guaranteed Limit UnitSymbol Parameter VCC V –55 to 25°C ≤85°C ≤125°C Unit fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) 2.0 3.0 4.5 6.0 6.0 9.0 8.0 MHz tPLH , tPHL Maximum Propagation Delay, Osc In to Q4* (Figures 1 and 4) 2.0 3.0 4.5 6.0 300 180 375 200 450 250 ns tPLH , tPHL Maximum Propagation Delay, Osc In to Q14* (Figures 1 and 4) 2.0 3.0 4.5 6.0 500 350 250 200 750 450 275 220 1000 600 300 250 ns tPHL Maximum Propagation Delay, Reset to Any Q (Figures 2 and 4) 2.0 3.0 4.5 6.0 195 245 100 300 125 ns tPLH , tPHL Maximum Propagation Delay, Qn to Qn+1 (Figures 3 and 4) 2.0 3.0 4.5 6.0 125 ns

MOTOROLA High–Speed CMOS Logic Data DL129 — Rev 6 3–4 AC CHARACTERISTICS (CL = 50 pF , Input tr = tf = 6 ns) – continued Symbol Parameter VCC V Guaranteed Limit UnitSymbol Parameter VCC V –55 to 25°C ≤85°C ≤125°C Unit tTLH , tTHL Maximum Output Transition Time, Any Output (Figures 1 and 4) 2.0 3.0 4.5 6.0 110 ns C in Maximum Input Capacitance 10 10 10 pF NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High– Speed CMOS Data Book (DL129/D). * For TA = 25°C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations: C PD Power Dissipation Capacitance (Per Package)* Typical @ 25°C, VCC = 5.0 V pFC PD Power Dissipation Capacitance (Per Package)* 35 pF * Used to determine the no–load dynamic power consumption: PD = CPD VCC 2f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). TIMING REQUIREMENTS (Input tr = tf = 6 ns) Symbol Parameter VCC V Guaranteed Limit UnitSymbol Parameter VCC V –55 to 25°C ≤85°C ≤125°C Unit trec Minimum Recovery Time, Reset Inactive to Clock (Figure 2) 2.0 3.0 4.5 6.0 100 125 100 150 120 ns tw Minimum Pulse Width, Clock (Figure 1) 2.0 3.0 4.5 6.0 110 ns tw Minimum Pulse Width, Reset (Figure 2) 2.0 3.0 4.5 6.0 110 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 2.0 3.0 4.5 6.0 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Figure 5. Expanded Logic Diagram Figure 6. Oscillator Circuit Using RC Configuration

3 RtcC tc

The formula may vary for other frequencies. Figure 7. Pierce Crystal Oscillator Circuit

TABLE 1. CRYSTAL OSCILLATOR AMPLIFIER SPECIFICATIONS (TA = 25°C; Input = Pin 11, Output = Pin 10)

5.0 Expected Minimum

4.0 Expected Minimum

3.3 Expected Minimum

3.1 Expected Minimum

Figure 8. Equivalent Crystal Networks Value are supplied by crystal manufacturer (parallel resonant crystal). Figure 9. Series Equivalent Crystal Load Figure 10. Parasitic Capacitances of the Amplifier the load. Ca and Rf typically have minimal effect below 2MHz. Values are listed in Table 1.

MOTOROLA High–Speed CMOS Logic Data DL129 — Rev 6 3–8 DESIGN PROCEDURES The following procedure applies for oscillators operating below 2MHz where Z is a resistor R1. Above 2MHz, additional impedance elements should be considered: Cout and Ca of the amp, feedback resistor Rf, and amplifier phase shift error from 180°C. Step 1: Calculate the equivalent series circuit of the crystal at the frequency of oscillation. Ze /C0043 /C0042jXC o(Rs /C0041jXLs /C0042jXC s) /C0042jXC o /C0041R s /C0041jXLs /C0042jXC s /C0043R e /C0041jXe Reactance jXe should be positive, indicating that the crystal is operating as an inductive reactance at the oscillation frequency. The maximum R s for the crystal should be used in the equation. Step 2: Determine β, the attenuation, of the feedback network. For a closed-loop gain of 2,Aνβ = 2,β = 2/Aν where Aν is the gain of the HC4060A amplifier. Step 3: Determine the manufacturer’s loading capacitance. For example: A manufacturer may specify an external load capaci- tance of 32pF at the required frequency. Step 4: Determine the required Q of the system, and calculate Rload, For example, a manufacturer specifies a crystal Q of 100,000. In-circuit Q is arbitrarily set at 20% below crystal Q or 80,000. Then Rload = (2πfoLS/Q) – Rs where Ls and Rs are crystal parameters. Step 5: Simultaneously solve, using a computer, /C0098/C0043XC /C0064XC2 R /C0064R e /C0041XC2 (Xe /C0042XC ) ( Eq 1 )(with feedback phase shift = 180°) Xe /C0043XC2 /C0041XC /C0041R eXC2 R /C0043XC load ( Eq 2 )(where the loading capacitor is an external load, not including Co) R load/C0043 RX C oXC2 [(XC /C0041XC2 )(XC /C0041XC o)/C0042XC (XC /C0041XC o /C0041XC2 )] X2C2 (XC /C0041XC o)2 /C0041R 2(XC /C0041XC o /C0041XC2 )2 ( Eq 3 ) Here R = Rout + R1. Rout is amp output resistance, R1 is Z. The C corresponding to XC is given by C = C1 + Cin. Alternately, pick a value for R1 (i.e, let R1 = RS). Solve Equations 1 and 2 for C1 and C2. Use Equation 3 and the fact that Q = 2πfoLs/(Rs + Rload) to find in-circuit Q. If Q is not satisfactory pick another value for R1 and repeat the procedure. CHOOSING R1 Power is dissipated in the effective series resistance of the crystal. The drive level specified by the crystal manufacturer is the maximum stress that a crystal can withstand without damage or excessive shift in frequency. R1 limits the drive level. To verify that the maximum dc supply voltage does not overdrive the crystal, monitor the output frequency as a func- tion of voltage at Osc Out 2 (Pin 9). The frequency should increase very slightly as the dc supply voltage is increased. An overdriven crystal will decrease in frequency or become unstable with an increase in supply voltage. The operating supply voltage must be reduced or R1 must be increased in value if the overdriven condition exists. The user should note that the oscillator start-up time is proportional to the value of R1. SELECTING R f The feedback resistor, Rf, typically ranges up to 20MΩ . Rf determines the gain and bandwidth of the amplifier. Proper bandwidth insures oscillation at the correct frequency plus roll-off to minimize gain at undesirable frequencies, such as the first overtone. Rf must be large enough so as to not affect the phase of the feedback network in an appreciable manner. ACKNOWLEDGEMENTS AND RECOMMENDED REFERENCES The following publications were used in preparing this data sheet and are hereby acknowledged and recommended for reading: Technical Note TN-24, Statek Corp. Technical Note TN-7, Statek Corp. D. Babin, “Designing Crystal Oscillators”, Machine Design, March 7, 1985. D. Babin, “Guidelines for Crystal Oscillator Design”, Machine Design, April 25, 1985. ALSO RECOMMENDED FOR READING: E. Hafner, “The Piezoelectric Crystal Unit-Definitions and Method of Measurement”, Proc. IEEE, Vol. 57, No. 2, Feb., 1969. D. Kemper, L. Rosine, “Quartz Crystals for Frequency Control”, Electro-Technology, June, 1969. P. J. Ottowitz, “A Guide to Crystal Selection”, Electronic Design, May, 1966.

Figure 11. Timing Diagram

MOTOROLA High–Speed CMOS Logic Data DL129 — Rev 6 3–10 OUTLINE DIMENSIONS J SUFFIX CERAMIC PACKAGE CASE 620–10 ISSUE V N SUFFIX PLASTIC PACKAGE CASE 648–08 ISSUE R 19.05 6.10 0.39 1.40 0.21 3.18 19.93 7.49 5.08 0.50 1.65 0.38 4.31 0.51 15° 1.01

1.27 BSC

2.54 BSC

7.62 BSC

0.750 0.240 0.015 0.055 0.008 0.125 0.785 0.295 0.200 0.020 0.065 0.015 0.170

0.050 BSC

0.100 BSC

0.300 BSC

A B C D E F G J K L M N 0.020 15° 0.040 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. 1 8 916 C KN G E F D 16 PL –SEATING PLANE M L J 16 PL 0.25 (0.010) T AM S 0.25 (0.010) T BM S MIN MIN MAX MAX INCHES MILLIMETERS DIM A B C D F G H J K L M S 18.80 6.35 3.69 0.39 1.02 0.21 2.80 7.50 0.51 19.55 6.85 4.44 0.53 1.77 0.38 3.30 7.74 10° 1.01 0.740 0.250 0.145 0.015 0.040 0.008 0.110 0.295 0.020 0.770 0.270 0.175 0.021 0.070 0.015 0.130 0.305 10° 0.040 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B 1 8 916 F H G D 16 PL S C SEATING PLANE K J M L T A0.25 (0.010)M M 0.25 (0.010) T B AM S S MIN MIN MAX MAX MILLIMETERS INCHES DIM A B C D F G J K M P R 9.80 3.80 1.35 0.35 0.40 0.19 0.10 5.80 0.25 10.00 4.00 1.75 0.49 1.25 0.25 0.25 6.20 0.50 0.386 0.150 0.054 0.014 0.016 0.008 0.004 0.229 0.010 0.393 0.157 0.068 0.019 0.049 0.009 0.009 0.244 0.019 1.27 BSC 0.050 BSC NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 1 8 916 D 16 PL K C G –SEATING PLANE R X 45° M J F P 8 PL 0.25 (0.010) BM M D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J

High–Speed CMOS Logic Data DL129 — Rev 6 3–11 MOTOROLA OUTLINE DIMENSIONS DT SUFFIX TSSOP PACKAGE CASE 948C–03 ISSUE B A B PIN 1 IDENTIFICATION L 1 8 916 D C SEATING G H F M DIM A MIN MAX MIN MAX INCHES MILLIMETERS B 4.30 4.50 0.169 0.177 D 0.05 0.25 0.002 0.010 F 0.45 0.55 0.018 0.022 G 0.65 BSC 0.026 BSC H 0.22 0.23 0.009 0.010 J 0.09 0.24 0.004 0.009 K 0.16 0.32 0.006 0.013 L 6.30 6.50 0.248 0.256 M 0 10 0 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM PLANE –U–. ° ° ° ° J1 0.09 0.18 0.004 0.007 K1 0.16 0.26 0.006 0.010 K J SECTION A–A A A 16x REFK 0.100 (0.004)M 0.200 (0.008)M T PLANE –P– –T– –U– How to reach us: USA/EUROPE : Motorola Literature Distribution; JAPAN : Nippon Motorola Ltd.; T atsumi–SPD–JLDC, T oshikatsu Otsuki, P .O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 6F Seibu–Butsuryu–Center, 3–14–2 T atsumi Koto–Ku, T okyo 135, Japan. 03–3521–8315 INTERNET : http://Design–NET .com 51 Ting Kok Road, T ai Po, N.T ., Hong Kong. 852–26629298 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MC54/74HC4060A/D /C0042/C0077/C0067/C0053/C0052/C0047/C0055/C0052/C0072/C0067/C0052/C0048/C0054/C0048/C0065/C0047/C0068/C0042 ◊ CODELINE