MC54/74HC4051

MC54HC4051 MOTOROLA | Alldatasheet

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/C0077/C0079/C0084/C0079/C0082/C0079/C0076/C0065 SEMICONDUCTOR TECHNICAL DATA 1 REV 7 Motorola, Inc. 1995 /C0065/C0110/C0097/C0108/C0111/C0103 /C0077/C0117/C0108/C0116/C0105/C0112/C0108/C0101/C0120/C0101/C0114/C0115/C0047 /C0068/C0101/C0109/C0117/C0108/C0116/C0105/C0112/C0108/C0101/C0120/C0101/C0114/C0115 High–Performance Silicon–Gate CMOS The MC54/74HC4051, MC74HC4052 and MC54/74HC4053 utilize sili- con–gate CMOS technology to achieve fast propagation delays, low ON resistances, and low O FF leakage currents. These analog m ultiplexers/ demultiplexers control analog voltages that may vary across the complete power supply range (from VCC to VEE ). The HC4051 , HC405 2 and HC405 3 are identical in pinout to the metal–gate MC14051B, MC14052B and MC14053B. The Channel–Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by m eans of an analog switch, to the Commo n Output/Input. When the Enable pin is HIGH, all analog switches are turned off. The Channel–Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors they are compatible with LSTTL outputs. These devices have been designed so that the ON resistance (Ron) is more linear over input voltage than Ron of metal–gate CMO S analog switches. For m ultiplexers/demultiplexers with channel–select latches, see HC4351, HC4352 and HC4353.

• Fast Switching and Propagation Speeds
• Low Crosstalk Between Switches
• Diode Protection on All Inputs/Outputs
• Analog Power Supply Range (VCC – VEE ) = 2.0 to 12.0 V
• Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V
• Improved Linearity and Lower ON Resistance Than Metal–Gate Counterparts
• Low Noise
• In Compliance With the Requirements of JEDEC Standard No. 7A
• Chip Complexity: HC4051 — 184 FETs or 46 Equivalent Gates HC4052 — 168 FETs or 42 Equivalent Gates HC4053 — 156 FETs or 39 Equivalent Gates LOGIC DIAGRAM MC54/74HC4051 Single–Pole, 8–Position Plus Common Off X0 13 X1 14 X2 15 X3 12 X4 1 X5 5 X6 2 X7 4 A 11 B 10 C 9 ENABLE 6 MULTIPLEXER/ DEMULTIPLEXER X3 ANALOG INPUTS/ CHANNEL INPUTS PIN 16 = VCC PIN 7 = VEE PIN 8 = GND COMMON OUTPUT/ INPUT 1516 14 13 12 11 10 21 3 4 5 6 7 VCC X2 X1 X0 X3 A B C X4 X6 X X7 X5 Enable V EE GND Pinout: MC54/74HC4051 (Top View) OUTPUTS SELECT L L L L H H H H X L L H H L L H H X L H L H L H L H X /C0077/C0067/C0053/C0052/C0047/C0055/C0052/C0072/C0067/C0052/C0048/C0053/C0049 /C0077/C0067/C0055/C0052/C0072/C0067/C0052/C0048/C0053/C0050 /C0077/C0067/C0053/C0052/C0047/C0055/C0052/C0072/C0067/C0052/C0048/C0053/C0051 FUNCTION TABLE – MC54/74HC4051 Control Inputs ON ChannelsEnable Select C B A NONE L L L L L L L L H X = Don’t Care D SUFFIX SOIC PACKAGE CASE 751B–05 N SUFFIX PLASTIC PACKAGE CASE 648–08 J SUFFIX CERAMIC PACKAGE CASE 620–10

ORDERING INFORMATION

CASE 948F–01 DW SUFFIX SOIC PACKAGE CASE 751G–021

MC54/74HC4051 MC74HC4052 MC54/74HC4053 MOTOROLA High–Speed CMOS Logic Data DL129 — Rev 6 LOGIC DIAGRAM MC74HC4052 Double–Pole, 4–Position Plus Common Off X0 12 X1 14 X2 15 X3 11 Y0 1 Y1 5 Y2 2 Y3 4 A 10 B 9 ENABLE 6 X SWITCH Y SWITCH X13 ANALOG INPUTS/OUTPUTS CHANNEL-SELECT INPUTS PIN 16 = VCC PIN 7 = VEE PIN 8 = GND COMMON OUTPUTS/INPUTS L L H H X L H L H X FUNCTION TABLE – MC74HC4052 Control Inputs ON ChannelsEnable Select B A L L L L H X = Don’t Care Pinout: MC74HC4052 (Top View) 1516 14 13 12 11 10 21 3 4 5 6 7 VCC X2 X1 X X0 X3 A B Y0 Y2 Y Y3 Y1 Enable V EE GND NONE LOGIC DIAGRAM MC54/74HC4053 Triple Single–Pole, Double–Position Plus Common Off X0 12 X1 13 A 11 B 10 C 9 ENABLE 6 X SWITCH Y SWITCH X14 ANALOG INPUTS/OUTPUTS CHANNEL-SELECT INPUTS PIN 16 = VCC PIN 7 = VEE PIN 8 = GND COMMON OUTPUTS/INPUTS L L L L H H H H X L L H H L L H H X L H L H L H L H X FUNCTION TABLE – MC54/74HC4053 Control Inputs ON ChannelsEnable Select C B A L L L L L L L L H X = Don’t Care Pinout: MC54/74HC4053 (Top View) 1516 14 13 12 11 10 21 3 4 5 6 7 VCC Y X X1 X0 A B C Y1 Y0 Z1 Z Z0 Enable V EE GND NONE Y0 2 Y1 1 Y15 Z0 5 Z1 3 Z4Z SWITCH NOTE: This device allows independent control of each switch. Channel–Select Input A controls the X–Switch, Input B controls the Y–Switch and Input C controls the Z–Switch

MC54/74HC4051 MC74HC4052 MC54/74HC4053 High–Speed CMOS Logic Data DL129 — Rev 6

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Symbol ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Parameter ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ Value ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Unit ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ VCC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Positive DC Supply Voltage (Referenced to GND) (Referenced to VEE ) ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ – 0.5 to + 7.0 – 0.5 to + 14.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ V ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ VEE ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Negative DC Supply Voltage (Referenced to GND) ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ – 7.0 to + 5.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ V ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ VIS ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Analog Input Voltage ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ VEE – 0.5 to VCC + 0.5 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ V ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Vin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Digital Input Voltage (Referenced to GND) ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ – 0.5 to VCC + 0.5 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ V ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ I ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Current, Into or Out of Any Pin ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ±/n63686172000000000000000025 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mA ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ PD ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation in Still Air, Plastic or Ceramic DIP† ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ 750 500 450 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ mW ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Tstg ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature Range ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ – 65 to + 150 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ /C0095C ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ TL ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP , SOIC or TSSOP Package Ceramic DIP ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ 260 300 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ /C0095C *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. †Derating — Plastic DIP: – 10 mW//C0095C from 65/C0095 to 125/C0095C Ceramic DIP: – 10 mW//C0095C from 100/C0095 to 125/C0095C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ Symbol ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Parameter ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Min ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Max ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ Unit ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VCC ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Positive DC Supply Voltage (Referenced to GND) (Referenced to VEE ) ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 2.0 2.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 6.0 12.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VEE ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Negative DC Supply Voltage, Output (Referenced to GND) ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ – 6.0 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ GND ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VIS ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Analog Input Voltage ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ VEE ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ VCC ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ Vin ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Digital Input Voltage (Referenced to GND) ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ GND ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ VCC ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ VIO* ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Static or Dynamic Voltage Across Switch ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 1.2 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ V ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ TA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Operating T emperature Range, All Package Types ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ – 55 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ + 125 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ /C0095C ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ tr, tf ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Rise/Fall Time V CC = 2.0 V (Channel Select or Enable Inputs) VCC = 4.5 V VCC = 6.0 V ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ 1000 500 400 ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ns * For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance cir- cuit. For proper operation, Vin and Vout should be constrained to the range GND /C0118 (Vin or Vout) /C0118 VCC . Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC ). Unused outputs must be left open.

MC54/74HC4051 MC74HC4052 MC54/74HC4053 MOTOROLA High–Speed CMOS Logic Data DL129 — Rev 6 DC CHARACTERISTICS — Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted Symbol Parameter Condition VCC V Guaranteed Limit UnitSymbol Parameter Condition VCC V –55 to 25°C ≤85°C ≤125°C Unit VIH Minimum High–Level Input Voltage, Channel–Select or Enable Inputs R on = Per Spec 2.0 4.5 6.0 1.50 3.15 4.20 1.50 3.15 4.20 1.50 3.15 4.20 V VIL Maximum Low–Level Input Voltage, Channel–Select or Enable Inputs R on = Per Spec 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V Iin Maximum Input Leakage Current, Channel–Select or Enable Inputs Vin = VCC or GND, VEE = – 6.0 V 6.0 ±/n6368617200000000000000000.1 ±/n6368617200000000000000001.0 ±/n6368617200000000000000001.0 µA ICC Maximum Quiescent Supply Current (per Package) Channel Select, Enable and VIS = VCC or GND; V EE = GND VIO = 0 V V EE = – 6.0 6.0 6.0 160 µA NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). DC CHARACTERISTICS — Analog Section Symbol Parameter Condition VCC VEE Guaranteed Limit UnitSymbol Parameter Condition VCC VEE –55 to 25°C ≤85°C ≤125°C Unit R on Maximum “ON” Resistance Vin = VIL or VIH; VIS = VCC to VEE ; IS ≤ 2.0 mA (Figures 1, 2) 4.5 4.5 6.0 0.0 – 4.5 – 6.0 190 120 100 240 150 125 280 170 140 Ω Vin = VIL or VIH; VIS = VCC or VEE (Endpoints); IS ≤ 2.0 mA (Figures 1, 2) 4.5 4.5 6.0 0.0 – 4.5 – 6.0 150 100 190 125 100 230 140 115 ΔR on Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package Vin = VIL or VIH; VIS = 1/2 (VCC – VEE ); IS ≤ 2.0 mA 4.5 4.5 6.0 0.0 – 4.5 – 6.0 Ω Ioff Maximum Off–Channel Leakage Current, Any One Channel Vin = VIL or VIH; VIO = VCC – VEE ; Switch Off (Figure 3) µA Maximum Off–Channel HC4051 Leakage Current, HC4052 Common Channel HC4053 Vin = VIL or VIH; VIO = VCC – VEE ; Switch Off (Figure 4) 6.0 6.0 6.0 – 6.0 – 6.0 – 6.0 0.2 0.1 0.1 2.0 1.0 1.0 4.0 2.0 2.0 Ion Maximum On–Channel HC4051 Leakage Current, HC4052 Channel–to–Channel HC4053 Vin = VIL or VIH; Switch–to–Switch = VCC – VEE ; (Figure 5) 6.0 6.0 6.0 – 6.0 – 6.0 – 6.0 0.2 0.1 0.1 2.0 1.0 1.0 4.0 2.0 2.0 µA

MC54/74HC4051 MC74HC4052 MC54/74HC4053 High–Speed CMOS Logic Data DL129 — Rev 6

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AC CHARACTERISTICS (CL = 50 pF , Input tr = tf = 6 ns) Symbol Parameter VCC V Guaranteed Limit UnitSymbol Parameter VCC V –55 to 25°C ≤85°C ≤125°C Unit tPLH , tPHL Maximum Propagation Delay, Channel–Select to Analog Output (Figure 9) 2.0 4.5 6.0 370 465 550 110 ns tPLH , tPHL Maximum Propagation Delay, Analog Input to Analog Output (Figure 10) 2.0 4.5 6.0 ns tPLZ , tPHZ Maximum Propagation Delay, Enable to Analog Output (Figure 11) 2.0 4.5 6.0 290 364 430 ns tPZL , tPZH Maximum Propagation Delay, Enable to Analog Output (Figure 11) 2.0 4.5 6.0 345 435 515 103 ns C in Maximum Input Capacitance, Channel–Select or Enable Inputs 10 10 10 pF C I/O Maximum Capacitance Analog I/O 35 35 35 pF (All Switches Off) Common O/I: HC4051 HC4052 HC4053 130 130 130 Feedthrough 1.0 1.0 1.0 NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High– Speed CMOS Data Book (DL129/D). C PD Power Dissipation Capacitance (Figure 13)* HC4051 HC4052 HC4053 Typical @ 25°C, VCC = 5.0 V, VEE = 0 V pFC PD Power Dissipation Capacitance (Figure 13)* HC4051 HC4052 HC4053 pF * Used to determine the no–load dynamic power consumption: PD = CPD VCC 2f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

MC54/74HC4051 MC74HC4052 MC54/74HC4053 MOTOROLA High–Speed CMOS Logic Data DL129 — Rev 6 ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V) Symbol Parameter Condition VCC V VEE V Limit* UnitSymbol Parameter Condition VCC V VEE V 25°C Unit BW Maximum On–Channel Bandwidth or Minimum Frequency Response (Figure 6) fin = 1MHz Sine Wave; Adjust fin Voltage to Obtain 0dBm at VOS ; Increase fin Frequency Until dB Meter Reads –3dB; R L = 50Ω , CL = 10pF 2.25 4.50 6.00 ‘51 ‘52 ‘53 MHz or Minimum Frequency Response (Figure 6) Obtain 0dBm at VOS ; Increase fin Frequency Until dB Meter Reads –3dB; R L = 50Ω , CL = 10pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 120 120 120 — Off–Channel Feedthrough Isolation (Figure 7) fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600Ω , CL = 50pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 –50 –50 –50 dB fin = 1.0MHz, RL = 50Ω , CL = 10pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 –40 –40 –40 — Feedthrough Noise. Channel–Select Input to Common I/O (Figure 8) Vin ≤ 1MHz Square Wave (tr = tf = 6ns); Adjust RL at Setup so that IS = 0A; Enable = GND R L = 600Ω , CL = 50pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 105 135 mV PP R L = 10kΩ , CL = 10pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 145 190 — Crosstalk Between Any Two Switches (Figure 12) (Test does not apply to HC4051) fin = Sine Wave; Adjust fin Voltage to Obtain 0dBm at VIS fin = 10kHz, RL = 600Ω , CL = 50pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 –50 –50 –50 dB fin = 1.0MHz, RL = 50Ω , CL = 10pF 2.25 4.50 6.00 –2.25 –4.50 –6.00 –60 –60 –60 THD Total Harmonic Distortion (Figure 14) fin = 1kHz, RL = 10kΩ , CL = 50pF THD = THD measured – THDsource VIS = 4.0VPP sine wave VIS = 8.0VPP sine wave VIS = 11.0VPP sine wave 2.25 4.50 6.00 –2.25 –4.50 –6.00 0.10 0.08 0.05 *Limits not tested. Determined by design and verified by qualification.

MC54/74HC4051 MC74HC4052 MC54/74HC4053 High–Speed CMOS Logic Data DL129 — Rev 6

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Figure 1a. Typical On Resistance, VCC – VEE = 2.0 V Figure 1b. Typical On Resistance, V CC – VEE = 4.5 V Figure 1c. Typical On Resistance, VCC – VEE = 6.0 V Figure 1d. Typical On Resistance, V CC – VEE = 9.0 V Figure 1e. Typical On Resistance, VCC – VEE = 12.0 V Figure 2. On Resistance Test Set–Up 1.0 2.0 300 250 200 150 100 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO V EE R on , ON RESISTANCE (OHMS) 120 100 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO V EE R on , ON RESISTANCE (OHMS) 120 105 VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO V EE R on , ON RESISTANCE (OHMS) VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO V EE R on , ON RESISTANCE (OHMS) VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO V EE R on , ON RESISTANCE (OHMS) 25°C – 55°C 125°C 25°C – 55°C 125°C 5.0 5.5 6.0 25°C – 55°C 125°C 25°C – 55°C 125°C 25°C – 55°C 125°C PLOTTER MINI COMPUTER PROGRAMMABLE POWER SUPPLY DC ANALYZER VCC DEVICE UNDER TEST ANALOG IN COMMON OUT GND VEE

MC54/74HC4051 MC74HC4052 MC54/74HC4053 High–Speed CMOS Logic Data DL129 — Rev 6

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Figure 9a. Propagation Delays, Channel Select to Analog Out Figure 9b. Propagation Delay, Test Set–Up Channel Select to Analog Out Figure 10a. Propagation Delays, Analog In to Analog Out Figure 10b. Propagation Delay, Test Set–Up Analog In to Analog Out Figure 11a. Propagation Delays, Enable to Analog Out Figure 11b. Propagation Delay, Test Set–Up Enable to Analog Out VCC GND CHANNEL SELECT ANALOG OUT 50% tPLH tPHL 50% ON/OFF VCC C L* *Includes all probe and jig capacitance CHANNEL SELECT TEST POINT COMMON O/I OFF/ON ANALOG I/O VCC VCC GND ANALOG IN ANALOG OUT 50% tPLH tPHL 50% ON VCC C L* *Includes all probe and jig capacitance TEST POINT COMMON O/IANALOG I/O ON/OFF ENABLE VCC ENABLE 90% 50% 10% tf tr VCC GND ANALOG OUT tPZL ANALOG OUT tPZH HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE 10% 90% tPLZ tPHZ 50% 50% ANALOG I/O C L* TEST POINT VCC 1kΩ POSITION 1 WHEN TESTING t PHZ AND tPZH POSITION 2 WHEN TESTING t PLZ AND tPZL

11 MOTOROLA

Figure 15. Application Example Figure 16. External Germanium or Figure 17. Interfacing LSTTL/NMOS to CMOS Inputs Figure 18. Function Diagram, HC4051

MC54/74HC4051 MC74HC4052 MC54/74HC4053 High–Speed CMOS Logic Data DL129 — Rev 6

13 MOTOROLA

CASE 620–10 ISSUE V N SUFFIX PLASTIC PACKAGE CASE 648–08 ISSUE R 19.05 6.10 0.39 1.40 0.21 3.18 19.93 7.49 5.08 0.50 1.65 0.38 4.31 0.51 15° 1.01

1.27 BSC

2.54 BSC

7.62 BSC

0.750 0.240 0.015 0.055 0.008 0.125 0.785 0.295 0.200 0.020 0.065 0.015 0.170

0.050 BSC

0.100 BSC

0.300 BSC

A B C D E F G J K L M N 0.020 15° 0.040 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. 1 8 916 C KN G E F D 16 PL –SEATING PLANE M L J 16 PL 0.25 (0.010) T AM S 0.25 (0.010) T BM S MIN MIN MAX MAX INCHES MILLIMETERS DIM A B C D F G H J K L M S 18.80 6.35 3.69 0.39 1.02 0.21 2.80 7.50 0.51 19.55 6.85 4.44 0.53 1.77 0.38 3.30 7.74 10° 1.01 0.740 0.250 0.145 0.015 0.040 0.008 0.110 0.295 0.020 0.770 0.270 0.175 0.021 0.070 0.015 0.130 0.305 10° 0.040 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B 1 8 916 F H G D 16 PL S C SEATING PLANE K J M L T A0.25 (0.010)M M 0.25 (0.010) T B AM S S MIN MIN MAX MAX MILLIMETERS INCHES DIM A B C D F G J K M P R 9.80 3.80 1.35 0.35 0.40 0.19 0.10 5.80 0.25 10.00 4.00 1.75 0.49 1.25 0.25 0.25 6.20 0.50 0.386 0.150 0.054 0.014 0.016 0.008 0.004 0.229 0.010 0.393 0.157 0.068 0.019 0.049 0.009 0.009 0.244 0.019 1.27 BSC 0.050 BSC NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 1 8 916 D 16 PL K C G –SEATING PLANE R X 45° M J F P 8 PL 0.25 (0.010) BM M D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J

MC54/74HC4051 MC74HC4052 MC54/74HC4053 MOTOROLA High–Speed CMOS Logic Data DL129 — Rev 6 OUTLINE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F–01 ISSUE O ÇÇ ÇÇ ÇÇ ÇÇ ÇÇ DIM MIN MAX MIN MAX INCHESMILLIMETERS A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.18 0.28 0.007 0.011 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0 8 0 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE –W–. /C0095 /C0095 /C0095 /C0095 SECTION N–N SEATING PLANE IDENT. PIN 1 1 8 16 9 DETAIL E J B C D A K H G ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ DETAIL E F M L 2X L/2 –U– SU0.15 (0.006)T SU0.15 (0.006)T SUM0.10 (0.004) V ST 0.10 (0.004) –T– –V– –W– 0.25 (0.010) 16X REFK N N DW SUFFIX PLASTIC SOIC PACKAGE CASE 751G–02 ISSUE A DIM MIN MAX MIN MAX INCHESMILLIMETERS A 10.15 10.45 0.400 0.411 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 F 0.50 0.90 0.020 0.035 G 1.27 BSC 0.050 BSC J 0.25 0.32 0.010 0.012 K 0.10 0.25 0.004 0.009 M 0 7 0 7 P 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029 MBM0.010 (0.25) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. –A– –B– P 8X G14X D16X SEATING PLANE –T– SAM0.010 (0.25) B ST 16 9 F J R X 45/C0095 /C0095 /C0095 /C0095 /C0095M C K

MC54/74HC4051 MC74HC4052 MC54/74HC4053 High–Speed CMOS Logic Data DL129 — Rev 6

15 MOTOROLA

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