MC50XS4200CEK

MC50XS4200 NXP | Alldatasheet

Document overview

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• PDF pages: 66

Technical content

Features

• Two fully-protected 50 mΩ (at 25 °C) high-side switches
• Up to 1.65 A steady state current per channel
• Separate bulb and DC motor la tched overcurrent handling
• Individually programmable intern al/external PWM clock signals
• Overcurrent, short-circuit, a nd overtemperature protection with programmable autoretry functions
• Accurate temperature and current sensing
• Open load detection (channel in O FF and ON state), also for LED applications (7.0 mA typ.)
• Normal operating range: 8.0 to 36 V, extended range: 6.0 to 58 V
• 3 . 3 V and 5.0 V compatible 16-bit SPI port for device control, configuration and diagnostics at rates up to 8.0 MHz

Figure 1. Simplified application diagram

32 PIN SOIC (10 mm X 11 mm)

Applications

• Truck, bus and 24 V tr ansportation systems
• Resistive, capacitive, and inductive loads CEK SUFFIX (PB-FREE) 98ASA00894D

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1 Orderable parts

Table 1. Orderable part variations

1. To order parts in tape and reel, add the R2 suffix to the par t number.

2 Internal block diagram

Figure 2. Internal block diagram

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3 Pin assignment

Figure 3. Device pin assignments The function of each pin is described in the section Functional description. Table 2. 50XS4200 pin description PWM mode. This pin has an internal pull-down current source.

2 RSTB Input Reset

direct input signals. This pin is connected to GND by an internal pull-down resistor.

3 CSB Input Chip Select

This input pin is connected to the SPI chip-select output of an external microcontroller. CSB is internally pulled up to VDD by a current source IUP. internally connected to a pull-down current source IDWN.

5 SI Input Serial Input

connected to a pull-down current source IDWN. 6 VDD Power Digital Drain Voltage This is the positive supply pin of the SPI interface.

7 SO Output Serial Output

consumption in case of GND disconnection. electrical parameter accuracy purpose, the ground pins must be shorted in the board.

9 FSB Output Fault Status

device enters Fault mode (see Fault mode). NC N/A Not connected These pins may not be connected. HS0 Output Power Switch Outputs Output pins of the switches, to be connected to the load.

26 SYNC Output

operating mode. SYNC is open drain and requires a pull-up resistor to VDD.

27 CSNS Output

interface. An external pull-down resistor must be connected between CSNS and GND. by internal pull-down resistors.

30 FSOB Output Fail-safe Output

This open drain output requires an external pull-up resistor to VPWR. (bulb/DC motor) for each of both channels. CONF requires a pull-down resistor to GND. Table 2. 50XS4200 pin description (continued)

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4 Electrical characteristics

4.1 Maximum ratings

Table 3. Maximum ratings All voltages are relative to ground unless mentioned otherwise. Exceeding these ratings may cause permanent damage.

• Load dump at 25 °C (350 ms)
• Reverse battery at 25 °C
• Fast negative transient pulses (ISO 7637-2 pulse #1, VPWR=28 V & Ri=10 Ω) -32 -60 V VDD VDD supply voltage range -0.3 to 5.5 V VMAX,LOGIC Voltage on input pins (except IN[0:1]) and Output pins) (except HS[0:1]) -0.3 to 5.5 V (2) (3) VFSO Voltage on fail-safe output (FSOB) -0.3 to 58 V VSO Voltage on SO pin -0.3 to VDD+0.3 V VIN,MAX Voltage (continuous, max. allowable) on IN[0:1] Inputs 58 V VHS[0:1] Voltage (continuous, max. allowable) on output pins (HS [0:1]) -32 to 58 V IHS[0:1] Rated continuous output current per channel 1.65 A (4) ECL [0:1]_SING Maximum allowable energy dissipation per channel and two parallel channels, single-pulse method 17 mJ (5) VESD1 VESD2 VESD3 VESD4 ESD voltage
• Human Body Model (HBM) for HS[0:1], VPWR and GND
• Human Body Model (HBM) for other pins
• Charge Device Model (CDM) Package corner pins (1, 13, 19, 20) All other pins ± 8000 ± 2000 ± 750 ± 500 V (6) Notes: 2. Concerned input pins are: CONF[0:1], RSTB, SI, SCLK, Clock, a nd CSB. 3. Concerned output pins are: CSNS, SYNC, and FSB. 4. Output current rating valid as long as maximum junction temperature is not exceeded. For computation of the maximum allowable output current, the thermal resistance of the package and the underlying heatsink must be taken into account 5. Single pulse energy dissipati on, Single-pulse short-circuit method (LL = 0.5 mH, R = 48 mΩ, VPWR = 28 V, TJ = 150 °C initial). 6. ESD testing is performed in accordance with the Human Body Mo del (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF).

4.2 Static electrical characteristics

• Ambient
• Junction - 40 to 125 - 40 to 150 TSTG Storage temperature - 55 to 150 °C RθJC Thermal Resistance Junction to Case (Exposed pad) 2.7 °C/ W RθJA Thermal Resistance Junction to Ambient 24 °C/ W (7) TPPRT Peak package reflow temperature during reflow Note 9 °C (8),(9) Notes: 7. Four layer board (2s2p), per J EDEC JESD51-6 with the board (JESD51-7) horizontal 8. Pin soldering temperature lim it is for 40 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. 9. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes), enter the core ID to view all orderable parts, and review parametrics.

Table 4. Static electrical characteristics values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.

• Full specification compliant
• Extended mode 8.0 6.0 58 V (10) IPWR(ON) VPWR supply current, device in wake-up mode, channel On, Open Load
• Outputs in ON state, HS[0 : 1] open, IN[0:1] > VIH – 6.5 8.5 mA IPWR(SBY) VPWR supply current, device in wake-up mode (Standby), channel Off Open Load in OFF state detection disabled, HS[0 : 1] shorted to ground with VDD = 5.5 V and RSTB > VWAKE – 6.5 8.5 mA IPWR(SLEEP) Sleep state supply current VPWR = 24 V, RSTB = IN[0:1] < VWAKE, HS[0 : 1] connected to ground
• T A = 25 °C
• T A = 125 °C 3.0 10.0 60.0 μA VDD(ON) VDD supply voltage 3.0 – 5.5 V IDD(ON) VDD supply current at VDD = 5.5 V
• No SPI communication
• 8 . 0 MHz SPI communication 5.0 2.2 mA (11) IDD(SLEEP) VDD Sleep state current at VDD = 5.5 V with or without VPWR – – 5.0 μA VPWR(OV) Overvoltage shutdown threshold 39 42 45.5 V VPWR(OVHYS) Overvoltage shutdown hysteresis 0.2 0.8 1.5 V VPWR(UV) Undervoltage shutdown threshold 5.0 – 6.0 V (12) VPWR(POR) VPWR Power-On-Reset (POR) voltage threshold 2.2 2.6 4.0 V (12) VDD(POR) VDD Power-On-Reset (POR) voltage threshold 1.5 2.0 2.5 V (12)

Table 3. Maximum ratings (continued) All voltages are relative to ground unless mentioned otherwise. Exceeding these ratings may cause permanent damage.

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1. In extended mode, availability o f several device functions (channel control, value of RDS(on), overtemperature protection) is guaranteed, but

VPWR(OV), the channels can only be turned ON when the overvoltage detection function has been disabled.

1. Typical value guaranteed per design.
2. When the device recovers from undervoltage and returns to no rmal mode (6.0 V < VPWR < 58 V) before the end of the auto-retry period (see Auto-

Table 4. Static electrical characteristics (continued) values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.

• V PWR = 8.0 V
• V PWR = 28 V
• V PWR = 36 V mΩ RDS(on)150 ON-Resistance, Drain-to-Source (IHS = 1.0 A,TJ = 150 °C) CSNS_ratio = 0
• V PWR = 8.0 V
• V PWR = 28 V
• V PWR = 36 V 100 100 100 mΩ ΔRDS(on)150 ON-Resistance, Drain-to-Source difference from one channel to the other in parallel mode (IHS = 1.0 A,TJ = 150 °C) CSNS_ratio = X -2.0 – 2.0 mΩ RSD(on)150 ON-Resistance, Source-Drain (IHS = -1.0 A, TJ = 150 °C, VPWR = -24 V) – – 100 mΩ LSHORT Max. detectable wiring length (2.5 mm²) for severe short-circuit detection (see Severe short-circuit fault (Latchable fault)):
• High slew rate selected
• Medium slew rate selected
• Low slew rate selected 175 210 580 350 990 cm I_OCH1_0 I_OCH2_0 I_OCM1_0 I_OCM2_0 I_OCL1_0 I_OCL2_0 I_OCL3_0 Overcurrent detection thresholds with CSNS_ratio bit = 0 (CSR0) 10.3 6.6 4.1 2.5 1.7 1.1 0.6 13.20 8.40 5.20 3.20 2.16 1.44 0.72 16.1 10.2 6.3 3.9 2.6 1.8 0.9 A I_OCH1_1 I_OCH2_1 I_OCM1_1 I_OCM2_1 I_OCL1_1 I_OCL2_1 I_OCL3_1 Overcurrent detection thresholds with CSNS_ratio bit = 1(CSR1) 3.43 2.18 1.35 0.83 0.56 0.37 0.19 4.40 2.80 1.73 1.07 0.72 0.48 0.24 5.37 3.42 2.11 1.31 0.88 0.59 0.29 A IOUT_LEAK Output (HS[x]) leakage current in Sleep state (positive value = outgoing)
• V HS,OFF = 0 V (VHS,OFF = output voltage in OFF state)
• V HS,OFF = VPWR, device in Sleep state (VPWR = 24 V)
• V HS,OFF = VPWR, device in Sleep state (VPWR = 36 V) -120 -1400 +2.0 +5.0 +5.0 µA IOUT_OFF Output biasing current in OFF state (positive value = outgoing) with OL_OFF disabled (worst case for VPWR = 36 V, VHS,OFF = 34 V)
• Fast slew rate selected
• Medium slew rate selected
• Slow slew rate selected
• With OL_OFF disabled and ECU ground disconnected (VPWR = 32 V) -500 -370 -300 -400 -300 -250 -300 -230 -200 -1000 µA VD_GND(CLAMP) Switch turn-on threshold for supply overvoltage (VPWR -GND) 58 – 67 V VDS(CLAMP) Switch turn-on threshold for Drain-Source overvoltage (measured at IOUT = 500 mA 58 – 66 V

values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.

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• CSNS_ratio bit = 0 (high current mode)
• CSNS_ratio bit = 1 (low current mode) – (13) I_LOAD_MIN Minimum measurable load current with compensated error – – 20 mA (14) ICSR_LEAK CSNS leakage current in OFF state (CSNSx_en = 0, CSNS_ratio bit_x = 0) -4.0 – +4.0 µA I_LOAD_ERR_SYS Systematic offset error (see Current sense errors) – -1.6 – mA I_LOAD_ERR_RAND Random offset error -30 – 30 mA ICSNS,MAX CSNS pin current sourcing capability, absolute upper limit 5.15 – – mA ESR0_ERR ESR0 Output Current Sensing Error (%), uncompensated at output Current level (Sense ratio CSR0 selected): TJ = -40 °C
• 1 . 2 A
• 0 . 6 A
• 0 . 3 A
• 0 . 1 5 A TJ = 125 °C
• 1 . 2 A
• 0 . 6 A
• 0 . 3 A
• 0 . 1 5 A TJ = 25 °C to 125 °C
• 1 . 2 A
• 0 . 6 A
• 0 . 3 A
• 0 . 1 5 A -12 -12 -15 -25 -10 -9.0 -12 -12 -10 -9.0 -12 -15 9.0 9.0 % (15) Notes: 13. Current Sense Ratio C SRx = ICSNS / (IHS[x] +I_LOAD_ERR_SYS) 14. See note (15), but with ICSNS_MEAS obtained after compensation of I_LOAD_ERR_RAND (see Activation and use of offset compensation). Further accuracy improvements can be obtained by performing a 1 or 2 point calibration. 15. E SRx_ERR=(ICSNS_MEAS / ICSNS_MODEL) -1, with ICSNS_MODEL = (I(HS[x])+ I_LOAD_ERR_SYS) * CSRx , (I_LOAD_ERR_SYS defined above, see section Current sense error model). With this model, load current becomes: I(HS[x]) = ICSNS / CSRx - I_LOAD_ERR_SYS

values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.

• 1 . 2 A
• 0 . 6 A
• 0 . 3 A
• 0 . 1 5 A TJ = 125 °C
• 1 . 2 A
• 0 . 6 A
• 0 . 3 A
• 0 . 1 5 A TJ = 25 °C to 125 °C
• 1 . 2 A
• 0 . 6 A
• 0 . 3 A
• 0 . 1 5 A -11 -11 -11 -11 -9.0 -8.0 -8.0 -9.0 -9.0 -8.0 -9.0 -9.0 9.0 8.0 8.0 9.0 9.0 8.0 9.0 9.0 % (16) ESR1_ERR ESR1 Output Current Sensing Error (%), uncompensated at output Current level (Sense ratio CSR1 selected): TJ = -40 °C
• 0 . 3 A TJ = 125 °C
• 0 . 3 A TJ = 25 °C to 125 °C
• 0 . 3 A -15 -12 -12 % (16) ESR1_ERR(Comp) ESR1 Output Current Sensing Error (%) after offset compensation at output Current level (Sense ratio CSR1 selected): TJ = -40 °C
• 0 . 3 A
• 0 . 1 A
• 0 . 0 5 A
• 0 . 0 3 A TJ = 125 °C
• 0 . 3 A
• 0 . 1 A
• 0 . 0 5 A
• 0 . 0 3 A TJ = 25 °C to 125 °C
• 0 . 3 A
• 0 . 1 A
• 0 . 0 5 A
• 0 . 0 3 A -11 -13 -18 -29 -9.0 -10 -12 -12 -9.0 -10 -13 -16 9.0 9.0 % (17) Notes: 16. E SRx_ERR=(ICSNS_MEAS / ICSNS_MODEL) -1, with ICSNS_MODEL = (I(HS[x])+ I_LOAD_ERR_SYS) * CSRx , (I_LOAD_ERR_SYS defined above, see section Current sense error model). With this model, load current becomes: I(HS[x]) = ICSNS / CSRx - I_LOAD_ERR_SYS 17. See note (18), but with ICSNS_MEAS obtained after compensation of I_LOAD_ERR_RAND (see Activation and use of offset compensation). Further accuracy improvements can be obtained by performing a 1 or 2 point calibration.

values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.

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• 1 . 2 A
• 0 . 6 A TJ = 125 °C
• 1 . 2 A
• 0 . 6 A TJ = 25 °C to 125 °C
• 1 . 2 A
• 0 . 6 A -10 -11 -8.0 -8.0 -9.0 -9.0 8.0 8.0 9.0 9.0 % (18) VCL(CSNS) Current sense clamping voltage (condition: R(CSNS) > 10 kOhm) 5.5 – 7.5 V IOLD(OFF) Open load detection current threshold in OFF state 30 – 100 μA (18) VOLD(THRES) Open load fault detection voltage threshold 4.0 – 5.5 V (18) IOLD(ON) Open load detection current threshold in ON state (see Open load detection in ON state (OL_ON)):
• CSNS_ratio bit = 0
• CSNS_ratio bit = 1 (fast slew rate SR[1:0] = 10 mandatory for this function) 4.0 7.0 100 mA tOLLED Time period of the periodically activated Open Load in ON state detection for CSNS_ratio bit = 1 105 150 195 ms VOSD(THRES) Output shorted-to-VPWR detection voltage threshold (channel in OFF state) VPWR-1.2 VPWR-0.8 VPWR-0.4 V VCL Switch turn-on threshold for negative output voltages (protects against negative transients) - (measured at IOUT = 100 mA, Channel in OFF state) -38 – -32 V ΔVCL Switch turn-on threshold for negative output voltages difference from one channel to the other in parallel mode - (measured at IOUT = 100 mA, Channel in OFF state) -2.0 – +2.0 V VHS_TH Switching state (ON/OFF) discrimination thresholds 0.45*VPWR 0.5*VPWR 0.55*VPWR V TSD Shutdown temperature (Power MOSFET junction; 6.0 V < VPWR <

58 V) 160 175 190 °C

1. Minimum required value of open load impedance for detection of openload in OFF state: 200 kΩ (VOLD(THRES) = VHS at IOLD(OFF))

values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.

• ( IOH = 1.0 mA) VDD-0.4 – – V VSOL SYNC, SO, FSOB and FSB Low state output voltage ISO(LEAK) SYNC, SO, CSNS, FSOB and FSB tri-state leakage current:
• (0.0 V < V(SO) < VDD, or V(FS) or V(SYNC) = 5.5 V, or V(FSO) = 36 V or V(CSNS) = 0.0 V - 2.0 0.0 2.0 μA RCONF CONF[0:1]: Required values of the external pull-down resistor
• Lighting applications
• DC motor applications 1.0 Infinite kΩ Notes 19. High and low voltage ranges apply to SI, CSB, SCLK, RSTB, IN [0:1] and CLOCK input signals. The IN[0:1] signals may be derived from VPWR and can tolerate voltages up to 58 V. 20. Voltage above which the device wakes up 22. Valid for V CSB < 2.0 V. CSB has an internal pull-up current source derived from VDD 23. Pins CONF[0:1] are connected to an internal current source, derived from an internal voltage regulator (VREG ~ 3.0 V). 24. Input capacitance of SI, CSB, SCLK, RSTB, IN[0:1], CONF[0:1] , and CLOCK pins. This parameter is guaranteed by the manufacturing process but is not tested in production.

values evaluated under nominal conditions TA = 25 °C, VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.

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4.3 Dynamic electrical characteristics

Table 5. Dynamic electrical characteristics values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.

• V PWR = 16 V
• V PWR = 28 V
• V PWR = 36 V 0.5 0.6 0.7 2.0 2.4 2.8 V/μs (25) SRR_01 SRF_01 Rising and falling edges low slew rate (SR[1:0] = 01)
• V PWR = 16 V
• V PWR = 28 V
• V PWR = 36 V 0.2 0.3 0.35 1.0 1.2 1.4 V/μs (25) SRR_10 SRF_10 Rising and falling edges high slew rate / SR[1:0] = 10)
• V PWR = 16 V
• V PWR = 28 V
• V PWR = 36 V 1.0 1.2 1.4 4.0 4.8 5.6 V/μs (25) Δ SR Rising/falling edge slew rate matching (SRR /SRF)
• 16 V < VPWR < 36 V 0.75 – 1.25 ΔSR Edge slew rate difference from one channel to the other in parallel mode

16 V < VPWR < 36 V

• 1 6 V < VPWR < 36 V 6.0 – 60 μs (26) t DLY_01 Output Turn-ON and Turn-OFF delays (low slew rate/SR[1:0] = 01)
• 1 6 V < VPWR < 36 V 10 – 120 μs (26) t DLY_10 Output Turn-ON and Turn-OFF delays (high slew rate/SR[1:0] = 10)
• 1 6 V < VPWR < 36 V 4.0 – 35 μs (26) Δ t RF_00 Turn-ON and Turn-OFF delay time matching (t DLY(ON) - t DLY(OFF))
• f PWM = 400 Hz, 16 V < VPWR < 36 V, duty cycle on Δ t RF_01 Turn-ON and Turn-OFF delay time matching (t DLY(ON) - t DLY(OFF))
• f PWM = 200 Hz, 16 V < VPWR < 36 V, duty cycle on Δ t RF_10 Turn-ON and Turn-OFF delay time matching (t DLY(ON) - t DLY(OFF))
• f PWM = 1.0 kHz, 16 V < VPWR < 36 V, duty cycle on Notes 25. Rising and falling edge slew rates specified for a 20% to 80 % voltage variation on a 25.0 Ω resistive load (see Output voltage slew rate and delay). 26. Turn-on delay time measured as delay between a rising edge of the channel control signal (IN[0 : 1] = 1) and the associated rising edge of the output voltage up to: VHS[0 : 1] = VPWR / 2 (where RL = 25 Ω). Turn-OFF delay time is measured as time between a falling edge of the channel control signal (IN[0 : 1] = 0) and the associated falling edge of the output voltage up to the instant at which: VHS[0 : 1] = VPWR / 2 (RL = 25 Ω)

• 16 V < VPWR < 36 V 0.0 – 200 μs (30) t CSNSVAL_01 Current sense output settling Time for SR[1:0] = 01(low slew rate)
• 16 V < VPWR < 36 V 0.0 – 315 μs (30) t CSNSVAL_10 Current sense output settling Time for SR[1:0] = 10 (high slew rate)
• 16 V < VPWR < 36 V 0.0 – 165 μs (30) t SYNCVAL_00 SYNC output signal delay for SR[1:0] = 00 (medium SR) 20 – 120 μs (30) t SYNCVAL_01 SYNC output signal delay for SR[1:0] = 01 (low SR) 40 – 240 μs (30) t SYNCVAL_10 SYNC output signal delay for SR[1:0] = 10 (high SR) 10 – 60 μs (30) t SYNREAD_00 Recommended sync_to_read delay SR[1:0] = 00 (medium slew rate) 0.0 – 150 µs (30) t SYNREAD_01 Recommended sync_to_read delay SR[1:0] = 01 (low slew rate) 0.0 – 150 µs (30) t SYNREAD_10 Recommended sync_to_read delay SR[1:0] = 10 (high slew rate) 0.0 – 150 µs (30) tOCH1 tOCH2 Upper overcurrent threshold duration 6.0 12.0 8.6 17.2 11.2 22.4 ms tOCM1_L tOCM2_L Medium overcurrent threshold duration (CONF = 0; Lighting Profile) 48 137 178 ms tOCM1_M tOCM2_M Medium overcurrent threshold duration (CONF = 1; DC motor Profile) 48 137 178 ms Notes 27. Rising and falling edge slew rates specified for a 20% to 80 % voltage variation on a 10.0 Ω resistive load (see Output voltage slew rate and delay). 28. Time required to detect and report the fault to the FSB pin. 29. Time required to switch off the channel after detection of o vertemperature (OT), overcurrent (OC), SC or UV error (time measured between start of the negative edge on the FSB pin and the falling edge on the output voltage until V(HS[0:1)) = 50% of VPWR 30. Settling time ( = t CSNSVAL_XX), SYNC output signal delay ( = t SYNCVAL_XX) and Read-out delay ( = t SYNREAD_XX) are defined for a stepped load current (100 mA< I(LOAD)<IOCLX A FOR CSNS_RATIO_S = 1, AND 300 mA< I(LOAD)<IOCLX A_0 FOR CSNS_RATIO_S = 0). (see Figure 9 and Output current monitoring (CSNS))

Table 5. Dynamic electrical characteristics (continued) values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.

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• OL_OFF
• OL_ON
• O S 0.0 0.0 100 % (32) RPWM_400_M Available duty cycle range, fPWM = 400 Hz, medium slew rate, PWM mode
• OL_OFF
• OL_ON
• O S 0.0 0.0 100 % (32) RPWM_400_H Available duty cycle range, fPWM = 400 Hz, high slew rate, PWM mode
• OL_OFF
• OL_ON
• O S 0.0 0.0 100 % (32) RPWM_200_L Available duty cycle range, fPWM = 200 Hz, low slew rate mode, PWM mode
• OL_OFF
• OL_ON
• O S 0.0 0.0 100 % (32) RPWM_200_M Available duty cycle range, fPWM = 200 Hz, medium slew rate, PWM mode
• OL_OFF
• OL_ON
• O S 0.0 0.0 100 % (32) RPWM_100_L Available duty cycle range, fPWM = 100 Hz in low slew rate, PWM mode
• OL_OFF
• OL_ON
• O S 0.0 8.0 0.0 100 % (32) AFPWM(CAL) Deviation of the internal clock PWM frequency after calibration -10 – +10 % (33) fPWM(0) Default output frequency when using an uncalibrated oscillator 280 400 520 Hz Notes VHS = 50 % VPWR. For low duty cycle values, the effective value also depends on the value of the selected slew rate. 32. The device can be operated outside the specified duty cycle and frequency ranges (basic protective functions OC, SC, UV, OV, OT remain active) but the availability of the diagnostic functions OL_ON, OL_OFF, OS is affected. 33. Values guaranteed from 60 Hz to 1.0 kHz (recommended switching frequency range for internal clock operation).

values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.

• Auto_period bits = 00
• Auto_period bits = 01
• Auto_period bits = 10
• Auto_period bits = 11 105 52.5 26.2 13.1 150 37.5 17.7 195 97.5 47.8 24.4 ms GND pin temperature sensing function TOTWAR Thermal prewarning detection threshold 110 125 140 °C (35) TFEED Temperature sensing output voltage at TA = 25 °C (470 Ω < RCSNS < 10 kΩ) 918 1078 1238 mV DTFEED Gain temperature sensing output at TA = 25 °C (470 Ω < RCSNS < 10 kΩ) 10.7 11.1 11.5 mV/°C (35) TFEED_ERROR Temperature sensing error, range [-40 °C, 150 °C], default -15 – +15 °C (35) TFEED_ERROR_CAL Temperature sensing error, [-40 °C, 150 °C] after 1 point calibration at Notes 34. Only when the WD_dis bit set to logic [0] (default). Watchdog timeout defined from the rising edge on RST to rising edge HS[0,1] 35. Values were obtained by lab. characterization

values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.

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• C L = 80 pF – – 20 ns t FSO SO fall time
• C L = 80 pF – – 20 ns t RSI SI, CSB, SCLK, max. rise time allowing operation at fSPI = 8.0 MHz – – 11 ns (39) t FSI SI, CSB, SCLK, max. fall time allowing operation at fSPI = 8.0 MHz – – 11 ns (39) tVALID Time from rising edge of SCLK to reach a valid level at the SO pin – – 44 ns (40) t SOEN Time from falling edge of CSB to reach low-impedance on SO (access time) – – 30 ns (41) t SODIS Time from falling edge of CSB to reach high-impedance on SO pin (turn off time) – – 30 ns Notes: 36. Parameters guaranteed by design. It is recommended to tie un used SPI-pins to GND by resistors 1.0 k <R <10 k 37. RSTB low duration is defined as the minimum time required to switch off the channel when previously put ON in SPI mode (direct inputs inactive). 38. Minimum setup time required for the device is the minimum re quired time that the microcontroller must wait or remain in a given state. 39. Rise and Fall time of incom ing SI, CSB, and SCLK signals. 40. Time required for output data to be available for use at SO, measured with a 1.0 kΩ series resistor connected CSB. 41. Time required for output data to be terminated at SO measure d with a 1.0 kΩ series resistor connected CSB. 42. For clock frequencies > 4.0 MHz, series resistors on the SPI pins should preferably be removed. Otherwise, 470 pF (VMAX. > 40 V) ceramic speed- up capacitors in parallel with the >8.0 kΩ input resistors are required on pins SCLK, SI, SO, CS

values evaluated under nominal conditions TA = 25 °C,VPWR = 28 V and VDD = 5.0 V, unless specified otherwise.

4.4 Timing diagrams

Figure 4. Output voltage slew rate and delay Figure 5. Overcurrent protection profile for bulb applications Static overcurrent protection profile activated once per turn-on.

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Figure 6. Overcurrent protection profile for applications with inductive loads (DC motors, solenoids) Figure 7. Timing requirements during SPI communication

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5 Functional description

5.1 Introduction

The 50XS4200 is a two-channel, 24 V high-side switch with integrated control and diagnostics designed for truck and bus applications. The device provides a high number of protective functions. Both low RDS(on) channels (<50 mΩ) can independently drive various load types like light bulbs, solenoid actuators, or DC motors. Device control and diagnostics are configured through a 16-bit SPI port with daisy chain capability. Independently programmable output voltage slew rates allow satisfying electromagnetic compatibility (EMC) requirements. Both channels can independently be operated in three different switching modes: internal clock and internal PWM mode (fully autonomous operation), external clock and internal PWM mode, and direct control switching mode. Current sensing with an adjustable ratio is available on both channels, allowing both high current (bulbs) and low current (LED) monitoring. By activating the Track & Hold mode, current monitoring can be performed during the switch-off phase. This allows random access to the current sense functionality. A patented offset compensation technique further enhances current sense accuracy. To avoid turning off upon inrush current, while being able to monitor it, the device features a dynamic overcurrent threshold profile. For bulbs, this profile is a stair function with stages of which the height and width are programmable through the SPI port. DC motors can be protected from overheating by activating a specific window-shaped overcurrent profile that allow stall currents of limited duration. Whenever communication with the external micro-controller is lost, the device enters Fail-safe operation mode, but remains operational, controllable, and protected.

5.2 Pin assignment and functions

Functions and register bits that are implemented independently for both channels have extension “_s”. Max. ratings of the pins are given in Table 3.

5.2.1 Output current monitoring (CSNS)

The CS pin allows independent current monitoring of channel 0 or channel 1 up to the steady state overcurrent threshold. It can also be used to sense the device temperature. The different functions are selected by setting bits CSNS1_en and CSNS0_en to the appropriate value (Table 23). When the CSNS pin is sensed during switch-off in the (optional) Track & Hold mode (see Figure 9), it outputs the scaled value of the load current as it was just before turn-Off. When several devices share the same pull-down resistor, the CSNS pins of devices the current of which is not monitored must be tri-stated. This is accomplished by setting CSNS0_en = 0 and CSNS1_en = 0 in the GCR register (Table 10). Settling time (tCSNSVAL_XX) is defined as the time between the instant at the middle of the output voltage’s rising edge (HS[0:1] = 50% of VPWR), and the instant at which the voltage on the CSNS-pin has settled to ±5.0% of its final value. Anytime an overcurrent window is active, the CSNS pin is disabled (see Overcurrent detection on resistive and inductive loads). The current and temperature sensing functions are unavailable in Fail-safe mode and in Normal mode when operating without the VDD supply voltage. In order to generate a voltage output, a pull-down resistor is required (R(CSNS)=1.0 kΩ typ. and 470 < R(CSNS) < 10 k). When the current sense resistor connected to the CSNS pin is disconnected, the CSNS voltage is clamped to VCL(CSNS). The CSNS pin can source currents up to about 5.6 mA.

5.2.2 Current sense synchronization (SYNC)

To synchronize current sensing with an external process, the SYNC signal can be connected to a digital input of an external MCU. SYNC is asserted logic low when the current sense signal is accurate and ready to be read. The current sense signal on the CSNS pin has the specified accuracy tSYNREAD_XX seconds after the falling edge on the SYNC pin (Figure 9) and remains valid until a rising edge is generated. The rising edge that is generated by the SYNC pin at the turn-OFF instant (internal or external) may also be used to implement synchronization with the external MCU. Parameter tSYNCVAL_XX is defined as the time between the instant at the middle of the output- voltage rising edge (HS[0:1] = 50% of VPWR), and the instant at which the voltage on the SYNC-pin drops below 0.4 V (VSOL). The SYNC pins of different devices can be connected together to save µ-controller input channels. However, in this configuration, the CSNS function of only one device should be active at a time. Otherwise, the MCU does not determine the origin of the SYNC signal. The SYNC pin is open drain and requires an external pull-up resistor to VDD.

5.2.3 Direct control i nputs (IN0 and IN1)

The IN[0:1] pins allow direct control of both channels. A logic [0] level turns off the channel and a logic[1] level turns it on (Channel control in normal mode). When the device is in Sleep mode, a transition from logic 0 to logic 1 on any of these pins wake it up (Sleep mode). If it is desired to automatically turn on the channels after a transition to Fail-safe mode, inputs IN[0] and IN[1] must be externally connected internally connected to a pull-down resistor.

5.2.4 Configuration inpu ts (CONF0 and CONF1)

The CONF[0 :1] input pins allow configuring both channels for the appropriate load type. CONF = 0 activates the bulb overcurrent protection profile, and CONF = 1 the DC motor profile. These inputs are connected to an internal voltage regulator of 3.3 V by an internal pull-up current source IUP. Therefore, CONF = 1 is the default value when these pins are disconnected. Details on how to configure the channels are given in Table 9.

5.2.5 Fault status (FSB)

This open drain output is asserted low when any of the following faults occurs (see Fault mode): overcurrent (OC), overtemperature (OT), Output connected to VPWR, Severe short-circuit (SC), open load in ON state (OL_ON), open load in OFF state (OL_OFF), External Clock- fail (CLOCK_fail), overvoltage (OV), undervoltage (UV). Each fault type has its own assigned bit inside the STATR, FAULTR_s, or DIAGR_s register. Fault type identification and fault bit reset are accomplished by reading out these registers. They are part of the SO register (Fault mode) and are accessed through the SPI port.

5.2.6 PWM clock (CLOCK)

This pin is the input for an external clock signal that controls the internal PWM module.The clock signal is monitored by the device. The PWM module controls ON-time and turn-ON delay of the selected channels. The CLOCK pin should not be confused with the SCLK pin, which is the clock pin of the SPI interface. CLOCK has an internal pull-down current source (IDWN) to GND.

5.2.7 Reset (RSTB)

All SPI register contents are reset when RSTB = 0. When RSTB = 0, the device returns to Sleep mode tIN sec. after the last falling edge of the last active IN[0:1] signal. As long as the Reset input (RSTB pin) is at logic 0 and both direct input states are low, the device remains in Sleep mode (Channel configuration through the SPI). A 0-to-1 transition on RSTB wakes up the device and starts a watchdog timer to check the continuous presence of the SPI signals. To do this, the device monitors the contents of the first bit (WDIN bit) of all SPI words following that transition (regardless the register it is contained in). When this contents is not alternated within a duration tWDTO, SPI communication is considered lost, and Fail-safe mode is entered (Entering fail-safe mode). RSTB is internally pulled-down to GND by resistor RDWN.

5.2.8 Chip select (CSB)

Data communication over the SPI port is enabled when the CSB pin is in the logic [0] state. Data from the Input Shift registers are locked in the addressed SI registers on the rising edge of CSB. The device transfers the contents of one of the eight internal registers to the SO register on the falling edge of CSB. The SO output driver is enabled when CSB is logic [0]. CSB should transition from a logic [1] to a logic [0] state only when SCLK is at logic [0] (Figure 7 and Figure 8). CSB is internally pulled up to VDD through IUP.

5.2.9 SPI serial clock (SCLK)

The SCLK pin clocks the SPI data communication of the device. The serial input pin (SI) transfers data to the SI shift registers on the falling edge of the SCLK signal while data in the SO registers are transferred to the SO pin on the rising edge of the SCLK signal. The SCLK pin must be in low state when CSB makes any transition. For this reason, it is recommended to have the SCLK pin in the logic [0] state when the device is not accessed (CSB is at logic [1]). When CSB is set to logic [1], the signals at the SCLK and SI pins are ignored and the SO output is tri-stated (high-impedance). The SCLK pin is connected to an internal pull-down current source IDWN.

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5.2.10 Serial input (SI)

Serial input (SI) data bits are shifted in at this pin. SI data is read on the falling edge of SCLK. 16-bit data packages are required on the SI pin (see Figure 7), starting with bit D15 (MSB) and ending with D0 (LSB). All the internal device registers are addressed and controlled by a 4-bit address (D9-D12) described in Table 14. Register addresses and function attribution are described in Table 15. The SI pin is internally connected to a pull-down current source, IDWN.

5.2.11 Supply of the di gital circuitry (VDD)

This pin supplies the SPI circuit (3.3 V or 5.0 V). When lost, all circuitry becomes supplied by a VPWR derived voltage, except the SPI’s SO shift-register that can no longer be read.

5.2.12 Ground (GND)

This is the GND pin common for both the SPI and the other circuitry.

5.2.13 Positive supply pin (VPWR)

This pin is the positive supply and the common input pin of both switches. A 100 nF ceramic capacitor must be connected between VPWR and GND, close to the device. In addition, it is recommended to put a ceramic capacitor of at least 1.0 µF in parallel with this 100 nF capacitor.

5.2.14 Serial output (SO)

The SO pin is a tri-stateable output pin that conveys data from one of the 13 internal SO registers or from the previous SI register to the outside world. The SO pin remains in a high-impedance state (tri-state) until the CSB pin becomes logic [0]. It then transfers the SPI data (device state, configuration, fault information). The SO pin changes state at the rising edge of the SCLK signal. For daisy-chaining, it can be read out on the falling edge of SCLK. VDD must be present before the SO registers can be read. The SO register assignment is described in Table 13.

5.2.15 Power switch out put pins (HS0 and HS1)

HS0 and HS1 are the output pins of the power switches, to be connected to the loads. A ceramic capacitor (<= 22 nF (+/- 20%) is recommended between these pins and GND for optimal EMC performances.

5.2.16 Fail-safe output (FSOB)

This pin (active low) is used to indicate loss of SPI communication or loss of SPI supply voltage, VDD. This open drain output requires an external pull-up resistor to VPWR.

5.3 Functional internal block description

Figure 10. Internal block description

5.3.1 Power supply

guarantees a low quiescent current in Sleep mode.

5.3.2 Switch output pins HS0 and HS1

active clamp circuitry that may be activated when switching off inductive loads. Many protective and diagnostic functions are available. parallel, which guarantees good switching synchronization.

5.3.3 Communication interface and device control

or by a 3.3 V voltage supply. For direct input control, VDD is not required. communication is required to set these options.

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6 Functional device operation

6.1 Operation and operating modes

The device possesses two high-side switches (channels) each of which can be controlled independently. The device has four fundamental operating modes: Sleep, Normal, Fail-safe, and Fault mode, as shown in Table 6. Each channel can be controlled in three different ways in Normal mode: by a signal on the Direct Input pin, by an internal clock signal (autonomous operation) or by an external clock signal. For bidirectional SPI communication, a second supply voltage is required (VDD = 5.0 V or 3.3 V). When only the direct inputs IN[x] are used, VDD isn’t required.

6.1.1 Device start-up sequence

To put the device in a known configuration and guarantee predictable behavior, the device must undergo a wake-up sequence. However, it should not be woken up earlier than the moment at which VPWR has exceeded its undervoltage threshold, VPWR(UV), and VDD has exceeded its supply failure threshold, VDD(FAIL). In applications using the SPI port, the device is typically put in wake mode by setting RSTB=1. Wake-up of applications with direct input control can be achieved by having signals IN_ON[0] = 1 or IN_ON[1 ]= 1 (see Figure 11). After wake-up, all SPI register contents are reset (as defined in Table 12 and Table 13) and Normal mode is entered. All the device functions are available 50 µs later (typically). If the start-up sequence is not performed at device start-up, its configuration may be undetermined and correct operation is not guaranteed. In situations where the above described start-up sequence can not be performed, it is recommended to generate a wake-up event after the moment VPWR has reached the undervoltage threshold.

6.1.2 Channel configuration through the SPI

6.1.2.1 Setting the channel configuration

The channel configuration is determined by the contents of the pulse-width (PWMR_s), the configuration (CONFR_s) and the overcurrent (OCR_s) registers. They allow setting, among others, the following parameters: duty cycle, delay, Slew Rate, PWM enable (PWM_en), clock selection (CLOCK_sel), prescaler (PR), and direct_input disable (DIR_dis). Extension “_s” means that these registers exist for each of both channels. Function assignment is described in detail in the section SI register addressing.

6.1.2.2 Reading back the channel’s status and settings

The channel’s global switching and operating states (On/Off, normal/fault) are all contained in the SO-STATR register (see Table 16). The precise fault type can be found by reading out the FAULTR_s and STATR registers. The current channel settings (channel configuration) can be known by reading the PWMR, CONF, OCR, RETRYR, GCR, and DIAG registers (see section Serial output register assignment and beyond).

6.1.3 Normal mode

Normal mode (bit NM = 1) can be entered in two ways: either by driving the device through the direct inputs (IN[x]) or by establishing SPI communication (requires RSTB =high). Bidirectional SPI communication additionally requires the presence of VDD. To maintain the device in Normal mode, communication must take place regularly (see Entering and maintaining normal mode). The device is in Normal mode (NM) when:

• V PWR (and VDD) are within the normal range and
• wake-up = 1, and
• fail-safe = 0, and
• f a u l t = 0.

6.1.3.1 Channel control in normal mode

In direct input mode, the channel’s switching state (ON/OFF) is controlled by the logic state of the direct input signal with the default values (00) of turn-on delay and slew rate, specified in Table 5.

In internal clock mode, the switching state is controlled by an internal clock signal (Internal clock and internal PWM (Clock_int_s bit = 1)). frequency of the external clock controls the output's PWM frequency, but slew rate, duty cycle, and turn-on delay are still programmable.

6.1.3.2 Factors determining the channel’s switching state

controlled by the value of the direct input signal or by that of the internal/external clock signals combined with the SPI register settings. hson[x] = [(IN[x] and DIR_dis[x]) or (On bit [x] and Duty_cycle[x] and PWM_en[x] = 1) or (On bit [x] and PWM_en[x] = 0)].

• short-circuits to GND, before automatic turn-Off (t < t FAULT)
• short-circuits to V PWR when the channel is set to Off
• V PWR < 13 V when open load in OFF state detection is selected and the load is actually lost
• during the turn-on transition as long as V(HS[x])< V PWR/2
• during the turn-off transit ion as long as V(HS[x]) > VPWR/2

6.1.3.3 Entering and maintaining normal mode

must take place on a regular basis. mode), provided reset = RSTB = 0. Figure 11. Relation between signals IN(x) and IN_ON[x]

6.1.3.4 Direct control mode

6.1.3.5 Going from normal to fa il-safe, fault or sleep mode

value of the following signals (see Table 6).

• wake-up = RSTB or IN_ON[0] or IN_ON[1]
• f a i l - s a f e = (VDD Failure and VDD_FAIL_en) or (SPI watchdog timeout (tWDTO) and WD_dis = 0)
• f a u l t = OC[0:1] or OT[0:1] or SC[0:1] or UV or (OV and OV_dis) IN_ON[x] IN[x] tIN

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Figure 12. Device operating modes

6.1.4 Sleep mode

• V PWR (and VDD) are within the normal range, and
• wake-up = 0 (wake-up = RSTB or IN_ON[0] or IN_ON[1])
• and
• fail-safe = X and
• f a u l t = X When employed, VDD must be kept in the normal range. Sleep mode is the default mode after the first application of the supply voltage (VPWR), prior to any I/O communication (RSTB and the internal states IN_ON[0:1] are still at logic [0]). All SPI register contents remain in their default state during sleep mode.

Table 6. Device operating modes Sleep 0 x x All channels are OFF. Fault 1 X 1 The channels are OFF, see Fault mode.

6.1.5 Fail-safe mode

6.1.5.1 Entering fail-safe mode

Fail-safe mode is entered either upon loss of SPI communication or after loss of optional SPI supply voltage VDD (VDD out of range). The FSOB pin goes low and the channels are only controlled by the direct inputs (IN[0:1]). All protective functions remain fully operational. Previously latched faults are delatched and SPI register contents is reset (except bits POR and PARALLEL). The SPI registers can not be accessed. These conditions are also described by the following expressions:

• V PWR is within the normal voltage range, and
• wake-up = 1, fault = 0, and
• f a i l - s a f e = 1 ((VDD Failure and VDD_FAIL_en=1 before) or (t(SPI)> tWDTO and WD_dis = 0). The last condition describes the loss of SPI communication which is detailed in the next section.

6.1.5.2 Watchdog on SPI commu nication and fail-safe mode

When VDD is present, the SPI watchdog timer is started upon a rising edge on the RSTB pin. Thereafter the device monitors the state of the first bit (WDIN) of all received SPI words. When the state of this bit is not alternated at least once within a data stream of duration tWDTO = 310 ms typ., the device considers that SPI communication has been lost and enters Fail-safe mode. This behavior can be disabled by setting the bit WD_DIS = 1. The value of watchdog timeout is derived from an internal oscillator.

6.1.5.3 Returning from f ail-safe to normal mode

To exit Fail-safe mode and return to normal mode again, first a SPI data word with its WDIN bit = 1 (D15) must be received by the device (regardless the register it is contained in and regardless the values of the other bits in this register). Next, a second data word must be received within the timeout period (tWDTO = 310 ms typ.) to be able to change any SPI register contents. Upon entering Normal mode, the FSOB pin returns to logic high and previously set faults and SPI registers are reset, except bits POR, PARALLEL and fault bits of latchable faults that had actually been latched.

6.1.6 Fault mode

The device enters Fault mode when any of the following faults occurs in Normal or Fail-safe mode:

• Overtemperature fault, (latchable fault)
• Overcurrent fault, (latchable fault)
• Severe short-circuit fault, (latchable fault)
• Output shorted to V PWR in OFF state (default: disabled)
• Open load fault in OFF state (default: disabled)
• Open load fault in ON s tate (default: disabled)
• External Clock Failure (default: enabled)
• Overvoltage fault (e nabled by default)
• Undervoltage fault, (latchable fault) The Fault Status pin (FSB) asserts a fault occurrence on any channel in real time (active low). Additionally, the assigned fault bit in the STATR_s or FAULTR_s register is set to one. Conversely to the FSB pin, a fault bit remains set until the corresponding register is read, even if the fault has disappeared. These bits can be read via the SO pin. Fault occurrence results in a turn-off of the incurred channel, except for the following faults: openload (ON and OFF state), external clock failure and output(s) shorted to VPWR. Under and overvoltage occurrences cause simultaneous turn-off of both channels. Details on the device’s behavior after the occurrence of one of the above faults can be found in Protection and diagnostic features. Fault mode (Operation and operating modes) is entered when:
• V PWR (+VDD) were within the normal voltage range, and
• wake-up = 1, and
• f a i l - s a f e = X, and
• f a u l t = 1 (see Going from normal to fail-safe, fault or sleep mode)

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6.1.6.1 Resetting FAULT bits

Registers STATR_s and FAULTR_s contain global and channel-specific fault information. Reading the register the fault bit is contained in clears it, provided failure cause disappearance was detected and the fault wasn’t latched.

6.1.6.2 Entering fault mode from fail-safe mode

When a Fault occurs in Fail-safe mode, the device is in Fault/Fail-safe mode and behaves according to the description of fault mode. However, SPI registers remain reset and can not be accessed. Only the Direct Inputs control the channels.

6.1.6.3 Returning from fault mode to fail-safe mode

When disappearance of the fault previously produced in Fail-safe mode has been detected, the device returns to Fail-safe mode and behaves accordingly. FSB goes high, but the auto-retry counter is not reset. Latched faults are not delatched. SPI registers remain reset.

6.1.7 Latchable faults

An auto-retry function (see Auto-retry) controls how the device responds to the so-called latchable faults. Latchable faults are: overcurrent (OC), severe short-circuit (SC), overtemperature (OT), and undervoltage (UV). If a latchable fault occurs, the channel is turned off, the FSB terminal goes low, and the assigned fault bit is set. These bits can not be reset before the next turn-on event is generated by auto- retry. Next, the channel automatically turns on at a programmable interval (provided auto-retry was enabled and the channel wasn’t latched). If the failure disappears prior to the expiration of the available amount of auto-retries, the FSB pin automatically returns to logic [1], but the fault bit remains set. It can then still be reset by reading the SPI register it is contained in. However, the fault actually gets latched if the failure cause hasn’t disappeared at the first turn-on event following expiration of the available amount of auto-retries (see Auto-retry). In that case, the channel gets latched and the FSB terminal remains low. The fault bit can not be reset by reading out the associated SPI register prior to performing a delatch sequence (Fault delatching).

6.1.7.1 Fault delatching

To delatch a latched channel and be able to turn it on again, a delatch sequence must be executed after disappearance of the failure cause. Delatching resets the fault bit of latched faults (see Resetting FAULT bits). To reset the FSB pin, both channels must be delatched. Delatching is achieved either by alternating the state of the channels’ fault control signal fc[x] (generating a 1_0_1 sequence), or by resetting the auto-retry counter (provided retry is enabled). See Reset of the auto-retry counter. Delatching then actually occurs at the rising edge of the turn-on event. Signal fc[x] is an internal signal used by the device’s internal logic circuitry to control the diagnostic functions. The value of fc[x] depends on the state of the variables IN_ON[x], DIR_dis[x] and ON[x] and is expressed as follows: fc[x] = ((IN_ON[x] and DIR_dis[x] = 0) or ON[x] = 1) Alternating the fc[x] signal is achieved differently according to the way the user controls the device.

• In direct-input cont rolled mode (DIR_dis_s = 0), the IN[x] pin must be set low, remain low for at least tIN seconds, and set high again (be switched On). This might happen automatically when operating at frequencies f<4.0 Hz.
• In SPI-controlled mode, the ON_bi t state (D8 of the PWMR_s reg.) must be alternated (‘toggled’). No minimum OFF state duration is required in this case. Performing a delatch sequence anytime during an ongoing auto-retry sequence (before latching) allows turning the channel on unconditionally. When a Power-ON event occurs (see Loss of VPWR, loss of VDD, and power-on reset (POR)), latched channels are also delatched and faults are reset. When Fail-safe mode is entered (fault=1, fail-safe becomes 1) during operating in Fault mode (fault=1, fail-safe=0), previously latched faults are delatched and SPI register content is reset (except bits POR and PARALLEL). The device is then in a combined Fail-safe/Fault mode. When the device was already in Fail-safe mode (fault=1, failsafe=1) and (new) faults occurs, the internal auto-retry counter does not reset and latched channels are not delatched until a delatching sequence has been performed (see Protection and diagnostic features).

6.1.8 Programmable PWM module

Each channel has a fully independent PWM module activated by setting PWM_en_s. It modulates an internal or external clock signal. Setting Clock_int_s = 1 (bit D6 of the OCR_s register) activates the internal clock, and setting Clock_int_s = 0 activates the external clock.

Figure 13. Internal and external clock operation EMC is to use an external clock with a staggered switch on delay.

6.1.8.1 External clock and i nternal PWM (CLOCK_int_s = 0)

single clock signal. Simultaneously setting PWM_en_1=1 and PWM_en_0=1 synchronizes the channels. Table 7. PWM duty cycle value assignment

0 X OFF

Table 8. Switch-on delay in PWM mode

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clock has to be within the authorized range again.

6.1.8.2 Internal clock and inte rnal PWM (Clock_int_s bit = 1)

about +/-30% to +/-10%. The programming procedure is initialized by sending a dedicated word to the SI-CALR register (see Table 7). value of the channel’s switching period is obtained by multiplying the internal clock period by 256. Figure 14. Internal clock calibration and the internal clock frequency remains unchanged. If the value (fPWM(0)) has not been previously calibrated, it remains at its default level.

6.1.8.3 Synchronization of both channels

switch on delay (see Table 8).

6.1.9 Parallel operation

There are two ways to configure the On/Off control: SPI-configured PWM control and Direct Input Control.

• SPI configured Parallel mode: The switching configuration is solely defined by the (SI) PWMR_0, CONFR_0, OCR_0, and RETRY_0 registers. As soon as PARALLEL=1, the contents of the corresponding registers in bank 1 are replaced by that of bank 0, except bits D6-D8 of the CONFR_1 register (configuration of the open load/output short-circuited diagnostics). It is recommended to disable the OFF state open load for the HS1 output (not necessary for 50XS4200). After setting PARALLEL=1, contents of SO registers in bank 0 are copied to registers of bank 1 only when new information is written in them. Bits OD3, OD4 and OD5 of both FAULTR_s registers (OLON, OLOFF, OS) are always reported independently.
• Direct Input controlled Parallel mode: The IN0 and IN1 pins must be connected externally. 2- Diagnostics in parallel mode: The Diagnostics in Parallel mode operate as follows: CSB SI CALR_s SI command ignored Internal clock period of channel s tCSB tCSB

• Open load in OFF state an d open load in ON state: The OL_ON and OL_OFF bits of both FAULTR registers independently report failures of the channels according to the settings of bits D7 and D6 of the CONFR_s register.
• Current sensing: See Table 23 for a description of the various current sensing modes. Only the Current sense ratio of bank 0 (D5 of the OCR_0 register) is considered. The corresponding bit in the OCR_1 register is copied from that of the OCR_0 register.
• output shorted to battery: The OS-bit (OD3) of each of both FAULT registers independently report this fault, according to the settings of bit D8 of the CONFR_s reg. 3- Protections in parallel mode:
• Overcurrent: -Only the Configuration of overcurrent thresholds and blanking windows of channel 0 are considered. -If overcurrent (OC) occurs on any channel, both channels are turned-off. Regardless the order of occurrence of OC, both OC-bits (OD0) in the FAULT registers are simultaneously set to logic 1.
• severe short-circuit: In case of SC detection on any channel, both channels are turned-off and the SC bits (OD1) in both FAULT registers are simultaneously set to logic 1.
• overtemperature: In case of OT detection on any channel, both channels are turned-off and both OT bits in the FAULT registers (OD2) are simultaneously set to logic 1.
• auto-retry: Only one 4-bit auto-retry counter specifies the number of successive turn-on events on paralleled channels (RETRYR_0). The counter value in register RETRYR_1 (OD4…OD7) is copied from that in RETRYR_0. To delatch the channels, only channel 0 needs to be delatched.

6.2 Protection and diagnostic features

6.2.1 Protective functions

6.2.1.1 Overtemperature fault (Latchable fault)

The channels have individual overtemperature detection. As soon as a channel’s junction temperature rises above TSD (175 °C typ.), it is turned OFF, the overtemperature bit (OT = OD2) is set, and FSB = 0. FSB can only be reset by turning ON the channel when the junction temperature of both channels has dropped below the threshold: TJ<TSD. Overtemperature is detected in ON and in OFF state:

• If the channel is ON, the asso ciated output is switched OFF, the OT bit is set, and FSB = 0.
• If the channel is OFF: FSB goes to logic [0] and remain low until the temperature of both channels is below TSD and any of the channels is turned on again. The auto-retry function (if activated) automatically turns the channel on when the junction temperature has dropped below TSD. The OT fault bit can only be reset by reading out the FAULTR register, provided that TJ<TSD and FSB = 1 again.

6.2.1.2 Overcurrent fault (Latchable fault)

When overcurrent (OC) is detected, the channel is immediately turned Off (after t FAULT seconds). The OC-bit is set to 1 and FSB becomes low [0]. Overcurrent is detected anytime the load current crosses an overcurrent threshold or exceeds the window width of the selected overcurrent protection profile. This profile is a stair function with windows the height and width of which are preselected through the SPI port. The maximum allowable value of the load current at a particular moment in time is defined by levels I_OCH and I_OCM and windows tOCM_x and tOCH (programmable by SPI bits). The steady state overcurrent protection level I_OCL is defined by the settings of the OCL and HOCR bits. Anytime an overcurrent window is active, current sensing is blanked and SYNC becomes 1.

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6.2.1.3 Overcurrent duration counter

retry (if enabled). An internal overcurrent duration counter is employed for this function.

6.2.1.4 Overcurrent detection on resistive and inductive loads

a resistor with the appropriate value between the CONF[0:1] pins and GND (Table 9). input pin. The SPI-SO CONF bit reporting shall combine external hardware configuration and SPI settings. Figure 15. Current sense blanking during overcurrent window activity Activation of the lighting profile is time driven and activation of the DC motor profile is event driven, as explained below. or a window width is exceeded. Figure 6. This window is opened anytime the output current exceeds the selected lower overcurrent threshold (IOCLx). In this case, the allowed overcurrent duration is defined by parameters tOCM1_M, tOCM2_M, tOCH1 and tOCH2. Table 9. Overcurrent profile selection

6.2.1.5 Auto-retry aft er overcurrent shut off

retries (described in section Auto-retry).

6.2.1.6 Switch mode operation and overcurrent duration

much later in switch mode than in fully-on mode, since the duration counter only counts overcurrent during on-times. Figure 16. Overcurrent shutdown in PWM mode (solid line) and fully-on mode (dashed line)

6.2.1.7 Reset of the duration counter

is also reset automatically at each auto-retry (but not in DC motor mode). overcurrent ([hson[x]=1 for any duration). Reset then actually occurs at the first turn-off instant following that on-period. In switch mode, the duration counter is not reset by normal PWM activity unless delatching is performed.

6.2.1.8 Severe short-circuit fault (Latchable fault)

When a severe short-circuit (SC) is detected at turn-ON (wiring length LLOAD< LSHORT, see Table 4), the channel is shut off immediately. auto-retry. SC is of the latchable fault type (see Protection and diagnostic features and Fault delatching).

6.2.1.9 Overvoltage detection (enabled by default)

the ranges specified in Table 4.

37 NXP Semiconductors

6.2.1.10 Undervoltage f ault (latchable fault)

(common) UV bit is set to [1].

• If the channel’s internal control signal hson[x] is off, FSB returns to logic [1], but the UV bit remains set until at least one output is turned on (warning).
• If the channel’s control signal is on, the channel is turned on if a delatch or POR sequence is performed prior to the turn on request. The UV bit can then only be reset by reading out the STATR register. Auto-retry (if enabled) starts as soon as the UV condition disappears.

6.2.1.11 Extended mode protection

detection should be disabled (by setting OV_dis = 1 in the GCR register).

• V DD < VDD(FAIL) with VPWR in the normal voltage range
• V DD and VPWR are below the VSUPPLY(POR) voltage threshold
• The corresponding SPI register is read after the disappearance of the failure cause (and delatching)

6.2.1.12 Drain/source overvoltage protection

6.2.1.13 Supply overvoltage protection

feature is not operational in cases of ground loss.

6.2.1.14 Negative output voltage protection

VCL, the channel is switched on automatically. This feature is not guaranteed after a device ground loss. Figure 17. The values of the clamping diodes are those specified in Table 4. Coupling factor k represents the current ratio between the current in the supply-voltage measurement-diode (zener) and the current injected into the MOSFET’s gate to turn it on.

Figure 17. Supply and output voltage protections

6.2.1.15 Reverse voltage protection on V PWR

VDD pin needs reverse voltage protection from an externally connected diode (Figure 24).

6.2.1.16 Load and system ground loss

the channels are turned off.

6.2.1.17 Device ground loss

pins in common like FSB, FSOB, and SYNC. In the following description, all voltages are referenced to the system (module) GND.

• all unused pins are t ied to the overall system’s GND connection by resistors > 8.0 k
• any device pin connected to external system components has a series resistors > 8.0 k (except pins Vpwr, VDD, HS[0], HS[1], and R(CSNS)>2.0 k)
• the FSB, FSOB, and SYNC pins are in the logic high state when they are shared with other devices. This means that none of the other devices is in Fault or Fail-safe mode, nor should current sensing be performed on any one of them when GND is lost When no series resistors are employed, the channel state after GND loss is determined by the voltage on pins IN[0:1] and the voltage shift of the device GND. Device GND shift is determined by the lowest value of the external voltage applied to either pin of the following list: CLOCK, FSB, IN[0:1], FSOB, SCLK, CS,SI, SO, RSTB, CONF[0:1], SYNC, and CSNS. When the device GND voltage becomes logic low (V(GND)< VIL), the SPI port continues to operate and the device operates normally. When the GND voltage becomes logic high (V(GND)> VIH), SPI communication is lost and Fail-safe mode is entered. When the voltage applied to the IN[0:1] input is VPWR, the channel is turned on when it is VDD, the channel is turned off if (VDD - V(GND)) < VIH.

39 NXP Semiconductors

6.2.2 Supply voltages out of range

6.2.2.1 V DD out of range

lost, the device remains SPI-controlled, even though the SPI registers can’t be read. No current flows from the VPWR to the VDD pin.

6.2.2.2 V PWR supply voltage out of range

flows from the VDD to the VPWR pin.

6.2.2.3 Loss of V PWR, loss of VDD, and power-on reset (POR)

• V PWR > VPWR (POR), after a period VPWR < VPWR (POR) (and VDD < VDD (POR) before and after)
• V DD > VDD (POR) after a period with VDD < VDD (POR) (VPWR < VPWR (POR) before and after) POR is also set at the transition to wake-up (by setting RSTB =1 or IN[x]=1) when VPWR > VPWR (POR) (before and after) or VDD >VDD(POR) (before and after). POR is not performed when VPWR > VPWR (POR) after a period VPWR < VPWR (POR) (and VDD > VDD (POR) permanently).

Figure 18. State machine: fault occurrence and auto-retry

6.2.3 Auto-retry

Retry[x] = OC[x] or SC[x] or OT[x] or UV.

6.2.3.1 Auto-retry configuration

and the retry condition applies (Retry[x]=1, see Auto-retry). bit remains set until it is cleared. This guarantees a maximum device availability without preventing fault detection.

6.2.3.2 Amount of auto-retries

remains powered. The channel never latches off. diagnostic features and Fault delatching). the retry counter. The value of the auto-retry counter can be read back in Normal mode only (SO-RETRYR register bits OD7-OD4).

6.2.3.3 Reset of the auto-retry counter

• Fail-safe is entered ( Fail-safe mode)
• Sleep mode is left ( Sleep mode)
• POR occurs ( Supply voltages out of range)
• the retry function is set to unlimited (bit Retry-unlimited_s = 1 (D1 = 1))
• the retry function is disabled (retry_s bit= D0 of the RETRY_s register under goes a 1-0 transition for CONF = 1 and a 0-1 transition for CONF = 0). If the channel is latched at the moment the auto-retry counter was reset (case 4), the channel is delatched, and turned on after one retry period (if retry was enabled).

Table 10. Auto-retry activation for lamps (CONF=0) and DC motors (CONF=1)

41 NXP Semiconductors

6.2.3.4 Auto-retry and overcurrent duration

During the on-period following an auto-retry, the load current profile is compared to the length and height of the selected overcurrent threshold profile, as described in the section on overcurrent protection (See Overcurrent fault (Latchable fault)). When the lighting profile is activated, the overcurrent duration counter is reset at each auto-retry (to allow sustaining new inrush currents). For DC motor mode however, it is only reset at the turn-off event of the first PWM period without any overcurrent (see Reset of the duration counter). Figure 18 gives a description of the retry state machine with the various transitions between operating modes.

6.2.4 Diagnostic features

Diagnostic functions open load-in-On state (OLON), open load-in-Off-state (OLOFF) and output short-circuited to VPWR (OS) are operational over the frequency and duty cycle ranges specified in Table 5 for PWM mode, but the precise values also depend on the way the device is controlled (direct/internal PWM), on the current sense ratio and on the optional activation of the open load-in-On-state detection. As an example, in direct input (DIR_dis_s = 0), Low-Current mode (CSR1), OLON, OLOFF and OS detection are performed for duty cycle values up to: RPWM_400_h = 85% (instead of 90%) when open load in ON state detection is enabled (OLON_dis=0). Occurrence of an OLON, OLOFF or OS fault sets the associated bit in the FAULTR_s register but does not trigger automatic turn-off. Any of these diagnostic functions can be disabled by setting OLON_dis_s=1, OLOFF_dis_s=1, or OS_dis_s=1 (bits D8...D6 of the CONFR reg.). The functions are guaranteed over the specified ranges for output capacitor values up to 22 nF (+/-20%).

6.2.4.1 Output shorted-to-V PWR fault

The device detects short-circuits between the output and VPWR. The detection is performed during the OFF state. The output-shorted- to-VPWR fault-bit (OS_s) is set whenever the output voltage rises above VOSD(THRES). The fault is reported in real time on the FSB pin and saved by the OS_s bit. Occurrence of this fault does not trigger automatic turn-off. Even if the short-circuit disappears, the OS_s bit is not cleared until the FAULTR register is read. The function may be disabled by setting OS_dis_s=1. The function operates over the duty cycle ranges specified in Diagnostic features. This type of event shall be limited to 1000 min. during the vehicle lifetime. In case of permanent output shorted to the battery condition, it is needed to turn-on the corresponding channel.

6.2.4.2 Open load detection in OFF state

Open load-in-OFF-state detection (OL_OFF) is performed continuously during each OFF-state (both for CSR0 and CSR1). This function is implemented by injecting a small current into the load (IOLD(OFF)). When the load is disconnected, the output voltage rises above VOLD(THRES). OL_OFF is then detected and the OL_OFF bit in the FAULTR register is set. If disappearance of the open load fault is detected, the FSB output pin returns to a high immediately, but the OL_OFF bit in the fault register remains set until it is cleared by a read out of the FAULTR register. The function may be disabled by setting OLOFF_dis_s=1. The function operates over the duty cycle ranges specified in Diagnostic features.

6.2.4.3 Open load detection in ON state (OL_ON)

Open load in ON state detection (OLON) is performed continuously during the ON state for CSR0 over the ranges specified in section Diagnostic features. An open load in ON state fault is detected when the load current is lower than the open load current threshold asserted low and the OLON bit in the fault register is set to 1 but the channel remains On. FSB goes high as soon as disappearance of the failure cause is detected, but the OL_ON bit remains set. In high current mode (CSR0), open load in ON state detection is done continuously during the ON state and the OLON-bit remains set even if the fault disappears. In high current mode, the OLON-bit is cleared when the FAULTR register is read during the Off state, even if the fault has not disappeared. The OLON-bit is also cleared when the FAULTR register is read during the ON state, provided the failure cause (load disconnected) has disappeared. In low current mode (CSR1), OL_ON is done periodically instead of continuously and only operates when fast slew rate is selected. When the internal PWM module is used with an internal or external clock (case 1), the period is 150 ms (typ.). When the direct inputs are used (case 2), the period is that of the input signal. The detection instants in both cases are given by the following: 1. In internal PWM (int./ext. clock), low current mode (CSR1), open load in ON state detection is not performed each switching period, but at a fixed frequency of about 7.0 Hz (each tOLLED =150 ms typ.). The function is available for a duty cycle of 100%.

OLON detection is also performed at 7.0 Hz, at the first turn-off event occurring 150 ms after the previous OL_ON detection event (before OS and OL_OFF). 2. In direct input, low current mode (CSR1), OL_ON is performed each switching period (at the turn-off instant) but the duty cycle is restricted to the values. Consequently, when the signal on the IN[x] pin has a duty cycle of 100%, OL_ON is not performed. To solve this problem, either the internal PWM function must be activated with a duty cycle of 100%, or the channel’s direct input must be disabled by setting Dir_dis_s=1 (bit D5 of the CONFR-s register). The OLON-bit is only reset when the FAULTR register is read after occurrence of an OL_ON detection event without fault presence.

6.2.4.4 Open load detection in discontinuous conduction mode

If small inductive loads (solenoids / DC motors) are driven at low frequencies, discontinuous conduction mode may occur. Undesired open load in ON state errors may then be detected, as the inductor current needs some time to rise above the open load detection threshold after turn-on. This problem can be solved by increasing the switching frequency or by disabling the function and activating open load in OFF state detection instead. When small DC motors are driven in discontinuous conduction mode, undesired open load in OFF state detection may also occur when the load current reaches 0.0 A during the OFF state. This problem can be solved by increasing the switching frequency or by enabling open load in OFF state detection only during a limited time, preferably directly after turn-off (see Diagnostic features). The signal on the SYNC pin can be used to identify the turn-off instant.

6.2.5 Current and temperature sensing

The scaled values of either of the output currents or the temperature of the device’s GND pins (8 and 25) can be made available at the CSNS pin. To monitor the current of a particular channel or the general device temperature, the CSNS0_en and CSNS1_en bits (see Table 23) in the General Configuration Register (GCR) must be set to the appropriate values. When overcurrent windows are active, current sensing is disabled and the SYNCB pin remains high.

6.2.5.1 Instantaneous and sampled current sensing

The device offers two possibilities for load current sensing: instantaneous (synchronous) sensing mode and Track & Hold mode (see Figure 9). In synchronous mode, the load current is mirrored through the current sense pin (Output current monitoring (CSNS)) and is therefore synchronous with it. After turn-off, the current sense pin does not output the channel current. In Track & Hold mode however, the current sense pin continues to mirror the load current as it was just before turn-off. Synchronous mode is activated by setting the T_H_en bit to 0, and Track & Hold mode by setting the T_H_en bit to 1.

6.2.5.2 Current sense ratio selection

The load current is mirrored through the CSNS pin with a sense ratio (Figure 19) selected by the CSNS_ratio bit in the OCR register. To achieve optimal accuracy at low current levels, the lower current sensing ratio, called CSR1, must be selected. In that case, the overcurrent threshold levels are decreased. The best accuracy that can be obtained for either ratio is shown in Figure 21. The amount of current the CSNS pin can sink is limited to ICSNS,MAX..The CSNS pin must be connected to a pull-down resistor (470 Ω < R(CSNS) <10 kΩ, 1.0 kΩ typical), in order to generate a voltage output. A small low-pass filter can be used for filtering out switching transients (Figure 24). Current sensing operates for load currents up to the lower overcurrent threshold (OCLx A).

6.2.5.3 Synchronous c urrent sensing mode

For activation of synchronous mode, T_H_en must be set to 0 (default). After turn-on, the CSNS output current accurately reflects the value of the channel’s load current after the required settling time. From this moment on (CSNS valid), the SYNC pin goes low and remains low until a switch off signal (internal/external) is received. This allows synchronization of the device’s current sensing feature with an external process running on a separate device (see Current sense synchronization (SYNC)). After turn-off, the load current does not flow through the switch, and the load current cannot be monitored.

6.2.5.4 Track & Hold current sensing mode

In Track & Hold mode (T&H) (T_H_en = 1), conversely from synchronous mode, the CSNS output current is available even after having switched off the load. This feature is useful when the device operates autonomously (internal clock/PWM), since it allows current monitoring without any synchronization of the device. An external sample and hold (S/H) capacitor is not required. After turn on, the CSNS output current reflects the channel’s load current with the specified accuracy after occurrence of the negative edge on the SYNC pin, as

43 NXP Semiconductors

at the moment the current is monitored on the other channel. Track & Hold mode should not be used for frequencies below 60 Hz. then turn on before sensing a new current. Figure 19. Current sensing ratio versus output current Figure 20. CSRO limit construction versus population of devices

6.2.5.5 Current sense errors

average value of zero, but with high spread. The random offset error is subject to part-to-part variations and also depends on the values of supply voltage and device temperature. The device has a special feature called offset compensation, allowing an almost complete compensation of the random offset error (see ESR0_ERR). This offset compensation technique greatly minimizes this error. Computing the compensated current sensing value is illustrated in the next sections.

6.2.5.6 Activation and u se of offset compensation

According to the settings of the OFP_s bit (in the RETRYR_s register), opposite values of the random offset error are generated. To compensate the random offset error, two separate measurements with opposite values of the random offset error are required. The measured values must be saved by an external µ-processor. Compensation of the random offset error is achieved by computing the average of both. When a dedicated bit called Offset Positive (OFP = bit D8 of the RETRYR_s register) is set to 1, the current sunk through the CSNS pin (ICSNS) can be described by: ICSNS1=CSRx *(ILOAD+ I_LOAD_ERR_SYS+ I_LOAD_ERR_RAND)( 2 ) When bit OFP is set to 0, ICSNS can be described by: ICSNS2 = CSRx *(ILOAD+ I_LOAD_ERR_SYS - I_LOAD_ERR_RAND) (3) The random offset term I_LOAD_ERR_RAND can be computed from equations (2) and (3) as follows: I_LOAD_ERR_RAND = (ICSNS1 - ICSNS2) / (2*CSRx)( 4 ) The compensated current sense value ICSNS,COMP can be obtained by computing the average value of measurements ICSNS1 and ICSNS2 as follows: ICSNS,COMP = (ICSNS1 + ICSNS2) / 2 (5) When equations 2 and 3 are substituted in equation 5, the random offset error cancels out, as shows eq. 6: ICSNS,COMP = (I_LOAD_ERR_SYS + ILOAD) * CSRx (6) The systematic offset error I_LOAD_ERR_SYS is referenced at the operating point 28 V and 25 °C. It can eventually be fine tuned by performing a calibration. Gain errors at 25 °C (=current sense ratio errors, represented by εGAIN0 and εGain1) can also be reduced by performing a calibration at a point in the range of interest. If calibration can not be done, it is recommended to use the typical value of I_LOAD_ERR_SYS (see ESR0_ERR).

6.2.5.7 Current sense error model

The figures of uncompensated and compensated current sense accuracy mentioned in Table 4 have been obtained applying the error model of eq. 7 to the data: ICSNS_MODEL = (I(HS[x])+ I_LOAD_ERR_SYS) * CSRx (7) ESRx_ERR = (ICSNS1 - ICSNS_MODEL)/ICSNS_MODEL (8) ESRx_ERR(COMP)= (ICSNS,COMP - ICSNS_MODEL)/ICSNS_MODEL (9) The computation has been applied to each of the specified measurement points. Model parameters I_LOAD_ERR_SYS and CSRx have the nominal values, specified in ESR0_ERR. The load current can be computed from this model as: I(HS[x]) = ICSNS / CSRx - I_LOAD_ERR_SYS (10) I(HS[x]) = ICSNS,COMP / CSRx - I_LOAD_ERR_SYS (11) Using expression (11) generally gives more accurate values than expression (10), since in expression (11), random offset errors have been compensated.

6.2.5.8 Offset compensation in Track & Hold mode

In Track & Hold mode, the last observed sense current (ICSNS) is sampled at the switch off instant. This takes into account the currently active settings of the OFP_s offset compensation bit. Changing the value of the OFP bit during the switch’s off time produces an identical value of the current sense output. Consequently, to implement the before mentioned offset compensation technique, the channel must have been turned on at least once prior to sensing the output current with an opposite value of the OFP bit.

45 NXP Semiconductors

6.2.5.9 System requirement s for current monitoring

that is used to read the current sense voltage V(csns) must have sufficient resolution to avoid introducing additional errors.

6.2.5.10 Accuracy with and wit hout offset compensation

accuracy with offset compensation and dotted lines without offset compensation). Figure 21. Current sense accuracy versus output current as a function of the switch-off time is displayed, for CSR0 and CSR1). Track & Hold mode should not be used below f = 60 Hz. Figure 22. Track & Hold current sense accuracy

6.2.5.11 Temperature prewarning detection

1. Accuracy ranges are six-sigma constructed.

moment that temperature T °C < TOTWAR.

6.2.5.12 Switching state monitoring

determining the channel’s switching state).

6.2.6 EMC performances

per IEC62132-4 specification). The device meets CISPR-25 Class5 from 150 kHz to 1.0 GHz. See AN5000 for EMC result details.

6.3 Logic commands and SPI registers

6.3.1 SPI protocol description

VDD and SPI pins (Table 3) are not exceeded. Unused SPI pins must be tied to GND, eventually by resistors (see Device ground loss). Figure 23. 16-bit SPI interface timing diagram

6.3.2 Serial input communication protocol

assignment. Bit names with extension “_s” refer to functions that have been implemented independently for each of both channels.

1. RST must be in a logic [1] state during data transfer.
2. Data enter the SI pin starting with D15 (MSB) and ending with bit D0.
3. Data are available on the SO pin starting with bit 0D15 (MSB) and ending with bit 0(OD0).

Notes 1. RSTB must be in a logic [1] state during data transfer.

1. Data enter the SI pin starting with D15 (MSB) and ending with bit D0.
2. Data are available on the SO pin starting with bit 0D15 (MSB) and ending with bit 0(OD0).

47 NXP Semiconductors

6.3.3 Serial port operation

contents. This allows daisy chaining and data integrity verification.

6.3.3.1 Daisy chain operation

addressed device, it can be executed by setting CSB=1. Table 11. SI message bit assignment

Table 12. Serial input register addresses and function assignment

10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 PARALLEL T_H_en WD_dis VDD_FAIL_en CSNS1_en CSNS0_e

contents

reset*

0 X 0 X X X 0 0 0 0** 0 0 0 0 0 0

• = RSTB = 0 or VDD(FAIL) after VDD = 5.0 V or POR ** = except bit D6 (PARALLEL) of the GCR register that is saved when VDD(FAIL) occurs, provided VDD = 5.0 V and VDD_FAIL_EN = 1 before X = register address, P = parity bit

49 NXP Semiconductors

6.3.4 SI register addressing

Table 13. Serial output register bit assignment

0 NM OV UV POR R_FUL

0 FAULT1 FAULT0 OUT1 OUT0

0 NM OTW 0 0 OLON_

0 NM ON_s

0 NM OS_d

0 NM HOC

0 NM OFP R3 R2 R1 R0 Auto_perio

0 NM CON

Table 14. Value of bit A0 required for addressing register banks 0 or 1

6.3.5 Address A 0000 — status register (STATR_s)

PWMR_s, CONFR_s, OCR_s, RETRY_s, GCR, and DIAGR (Table 13).

6.3.6 Address A 0001— PWM control register (PWMR_s)

as shown in Table 7. To start the PWM function at a known point in time, the PWM_en_s bit (both in the GCR register) must be set to 1.

6.3.7 Address A 0010— channel configuration register (CONFR_s)

value [0] enables the feature. enables this feature (Table 15). that case, the channel state is determined by the settings of the internal PWM functions. slew rate. Rising and falling edge slew rates are identical.

6.3.8 Address A 0100 — overcurrent protection configuration register (OCR_s)

Table 15. Selection of open load detection features Table 16. Slew rate selection

51 NXP Semiconductors

applicable overcurrent protection profile (see I_OCH1_0). windows are active, current sensing is not available. causes the external clock to be divided by 512. When PR_s = 0, the divider is 256. range. The default value [0] activates the “high-current” sensing ratio CSR0 (Table 17). configuration as shown in Table 18. (CONF[x]=0: bulb, CONF[x]=1: DC motor). first of these windows is either tOCH1 or tOCH2. The width of the second window is either tOCM1_L or tOCM2_L (see Table 18). case, the maximum overcurrent duration is selected among four values: tOCM1_M, tOCM2_M, tOCH1 and tOCH2. highest value, and [1] to the lowest value (Table 19). lowest value (Table 20). In DC motor mode, there is no middle overcurrent threshold and the value of this bit has no influence. Table 17. Current sense ratio selection

0 CRS0 (default)

1 CRS1

Table 18. Dynamic overcurrent threshold activation times for bulb and DC motor profiles Table 19. OCH upper current threshold selection

0 I_OCH1_s (default)

1 I_OCH2_s

Bit D0 (OCL_s) and D8 (HOCR) set the value of the lowest overcurrent threshold, as shown in Table 21.

6.3.9 Address A 0101 — Auto-retry register (RETRYR_s)

current sense function, and the overcurrent profile. in the offset current being subtracted from the sensed current. Setting D3 and D2 (Table 22) to the appropriate values allows selection of the value of the auto-retry period among four predefined values. neither resets after delatching, nor when the fault disappears. Setting bit D0 (retry_s) enables or disable auto-retry, accordingly to setting of the CONF pin. For CONF[x] = 0 (Lighting profile configured), setting retry_s = 1 disables auto-retry. The default value [0] enables it. For CONF[x] = 1 (DC motor), setting retry_s = 1 enables auto-retry. The default value [0] disables it. Setting bit D4 to 0 (CONF_SPI_s = 0) will configure the overcurrent profile as the CONF pin. Setting bit D4 to 1 (CONF_SPI_s = 1) will configure the overcurrent profile as the opposite of the CONF pin.

6.3.10 Address 0110 — global configuration register (GCR)

The GCR register is used to activate various functions and diagnostic functions. operation should be followed. information of bank 0 (A0 = 0) is available in this setting (see Parallel operation). Table 20. OCM current threshold selection

0 I_OCM1_s (default)

1 I_OCM2_s

Table 21. OCL current threshold selection Table 22. Auto-retry period

53 NXP Semiconductors

is kept available after turn-off. Setting bit D4 (WD_dis = 1) disables the SPI watchdog function. A logic [0] enables the SPI watchdog. selected (bit D8 of the OCR register, HOCR = 0), the device’s CSNS pin only outputs scaled values of a single channel’s load current. Setting bit D0 (OV_dis = 1 of the GCR reg.) disables overvoltage protection. Setting this bit to [0] (default), enables it.

6.3.11 Address A 0111 — calibration register (CALR_s)

specific calibration procedure. See Internal clock and internal PWM (Clock_int_s bit = 1).

6.3.12 SO register addressing

diagnostics status (Table 13). These registers are FAULTR_s, PWMR_s, CONFR_s, OCR_s, and RETRYR_s. determines which register bank is addressed (bank 0 or 1). Data is made available the next cycle after register addressing. the previous SPI cycle was invalid. In this case, the device outputs the contents of the last successfully addressed SO register.

6.3.13 Serial output register assignment

The output register shifted out through the SO pin is previously addressed by bits D13, D2, D1, and D0 of the STATR_s SI register. STATR_s required to address it.

• Bit OD15 (MSB) repor ts the state of the watchdog bit from the previously clocked-in SPI message.
• Bit OD14 (PF, active 1) reports an eventual parity error on the previously transferred SI register contents.
• Bits OD13:OD10 echo the state o f bits D13, D2, D1, and D0 (SOA3: SOA0) of the previously received SI word.
• Bit OD9: Normal mode (NM) reports the device state. In Normal Mode, NM = 1.
• B i t s O D 8 : OD0 are the contents of the selected SO register (addressed by bit D13 and bits D2 : D0 of the previous SI STATR register).

Table 23. Current sense pin functionality selection

6.3.14 Previous address SOA 3 : SOA0 = 0000 (STATR)

When bits SOA3…SOA0 of the previously received SI STATR_s register = 0000, the SO STATR register is addressed. Bits OD8: OD0 contain the relevant channel information: Faults, channel state, and supply voltage errors.

• B i t s O D 8 : OD6 report failures common to both channels
• Bit OD8 = OV = 1: overvoltage fault
• Bit OD7 = UV = 1: undervoltage fault
• Bit OD6 = POR = 1: power-on reset (POR) has occurred Power-ON-Reset occurs when VPWR<VSUPPLY(POR). The OV, UV, and POR bits can be reset by a reading the STATR register. Bits OD5: OD4 (RFULL) of the STATR register are set to logic [1] when the auto-retry counter of the corresponding channel is full. These bits are automatically cleared by resetting the corresponding auto-retry counter (see Reset of the auto-retry counter) Bits OD3 (FAULT1) and OD2 (FAULT0) are set to logic [1] when channel-specific (non-generic) faults are detected: FAULTs = OC_s + SC_s + OT_s + OS_s + OLOFF_s + OLON_s. The FAULTs bit can be reset by reading out the common STATR register or the individual FAULTR_s register (provided the fault has disappeared). Bits OD1: OD0 (OUT1 and OUT0) report the channel’s switching state (On/Off) in real time.

6.3.15 Previous address SOA 3 : SOA0 = A0001 (FAULTR_s)

Bit OD8 of both Fault registers (FAULTR_s) is set simultaneously when the overtemperature prewarning (OTW) condition occurs, but the channels are not switched off (temperature of the common GND pins (8 and 25)> TOTWAR). Reading either FAULT register clears both OTW bits. Bits OD5: OD0 of the Fault register (FAULTR_s) report the faults that occurred on the channel previously selected by bit SOA3 = A0 (Table 14).

• bit OD0 = OC_s: overcurrent fault on channel s,
• bit OD1 = SC_s: severe short-circuit on channel s,
• bit OD3 = OS_s: output shorted to VPWR on channel s,
• bit OD4 = OLOFF_s: open load in OFF state on channel s,
• bit OD5 = OLON_s: open load in ON state on channel s. (The threshold value above which this fault is triggered depends on the selected current sense ratio; for CSR0 at 150 mA typ. and for CSR1 at 7.0 mA typ.). The Fault Status pin (FSB) is set to 0 (active Low) upon occurrence of any of the above mentioned faults. Latched faults can only be delatched by the procedure described in Fault delatching. The FAULTR_s register is reset when it is read out, provided that the failure cause has disappeared and latched faults have been delatched.

6.3.16 Previous address SOA 3 : SOA0 = A0010 (PWMR_s)

The device outputs the contents of the addressed PWMR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1).

6.3.17 Previous address SOA 3 : SOA0 = A0011 (CONFR_s)

The device outputs the contents of the addressed CONFR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1).

6.3.18 Previous address SOA 3 : SOA0 = A0100 (OCR_s)

The device outputs the contents of the addressed OCR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1).

6.3.19 Previous address SOA 3 : SOA0 = A0101 (RETRYR_s)

The device outputs the contents of the addressed RETRYR_s register (A0 = 0 for bank 0 and A0 = 1 for bank 1). Bit OD8 contains the value of the OFP bit (offset positive), used for current sense offset compensation. Bits OD7: OD4 contain the real time value of the auto-retry counter. When these bits contain [0000], either auto-retry has not been enabled or Auto-retry did not occur.

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6.3.20 Previous address SOA 3 : SOA0 = 0110 (GCR)

The device outputs the contents of the general configuration register (GCR) common to both channels.

6.3.21 Previous address SOA 3 : SOA0 = 0111 (DIAGR_s)

Bit OD8 ( Ch. 1 = CONF1) and bit OD7 ( Ch. 0 = CONF0) of the DIAGR_s register contain the values of the channels’ configuration bits (0 = bulb, 1 = DC motor) Bits OD6:OD5 contain the product identification (ID) number, equal to 01 for the present dual 50 mΩ product. Bits OD4:OD3 report the logic state of the direct inputs IN[1:0] in real time (1 = On, 0 = OFF), OD4 = Ch. 1, OD3 = Ch. 0. Bit OD2 reports a logic [1] in case an external clock error occurred (if an external clock was selected by Clock_int = 0) Bit OD1:OD0 report logic [1] in case a calibration failure occurred during calibration of a channel’s internal clock period.

7 Typical applications

control in case Fail-safe mode is activated (FSOB goes low). This circuit allows keeping full control of both channels in case of SPI failure. Figure 24. Typical application with two different load types

57 NXP Semiconductors

Figure 25. Two channels in parallel/recommended external current sense circuit

8 Packaging

8.1 Package mechanical dimensions

Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and perform a keyword search for the drawing’s document number. Package Suffix Package outline drawing number

32 Pin SOIC-EP

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61 NXP Semiconductors

63 NXP Semiconductors

65 NXP Semiconductors

9 Revision history

Revision Date Description of changes 1.0 3/2014 • Initial release 2.0 9/2014

• Updated turn-on and turn-off delay time
• Updated overcurrent detection thresholds
• Updated output current sensing error
• Updated delay time difference from one channel to the other in parallel mode 3.0 1/2015 • Thermal parameter update per PB#16607 6/2015 • Corrected typo 8/2016 • Updated to NXP document form and style 4.0 4/2018
• Updated as per CIN 201805020I
• Changed steady state current value from 1.2 to 1.65 A listed u nder features on page 1
• Updated I HS[0:1] value in Table 3 (changed 1.2 to 1.65)
• Added clarification for diagnostic range to Table 5
• Corrected typo in Reverse voltage protection on VPWR (changed -28 V to -32 V)
• Corrected typo in Open load detection in ON state (OL_ON) (changed 150 mA to 60 mA)
• Corrected typo in Previous address SOA3 : SOA0 = 0111 (DIAGR_s) (changed 22 mΩ to 50 mΩ)
• Updated Track & Hold current sensing mode 5.0 6/2018 • Added MC50XS4200CEK part to Table 1 and associated 98ASA00894D package information

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