MC44462 MOTOROLA | Alldatasheet

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/C0077/C0067/C0052/C0052/C0052/C0054/C0050 SEMICONDUCTOR TECHNICAL DATA Y–C PICTURE–IN–PICTURE (PIP) CONTROLLER B SUFFIX PLASTIC PACKAGE CASE 859 (SDIP) Order this document from Analog Marketing Device Operating Temperature Range Package

ORDERING INFORMATION

MC44462B T J = –65° to +150°C SDIP 1MOTOROLA ANALOG IC DEVICE DATA /C0080/C0114/C0111/C0100/C0117/C0099/C0116 /C0080/C0114/C0101/C0118/C0105/C0101/C0119 /C0089/C0045/C0067 /C0080/C0105/C0099/C0116/C0117/C0114/C0101/C0045/C0105/C0110/C0045/C0080/C0105/C0099/C0116/C0117/C0114/C0101 /C0040/C0080/C0073/C0080/C0041 /C0067/C0111/C0110/C0116/C0114/C0111/C0108/C0108/C0101/C0114 The MC44462 Y–C PIP controller is a low cost member of a family of high performance PIP controllers and video signal processors for television. It is a follow–up to the MC44461 PIP and has a modified input selection to allow higher performance in TV systems which have S–Video inputs on the back panel. The S–Video input is separate luma (luminance) and chroma components. It is NTSC compatible and contains all the analog signal processing, control logic and memory necessary to provide for the overlay of a small picture from a second non synchronized source onto the main picture of a television. All control and setup of the MC44462 is via a standard two pin I2C bus interface. The device is fabricated using BICMOS technology. It is available in a 56–pin shrink dip (SDIP) package. The main features of the MC44462 are:

  • Switchable PIP Composite Video Signals – Video 1 and Video 2
  • S–Video Output Allows High Performance in TV
  • Two PIP Sizes; 1/16 and 1/9 Screen Area
  • Freeze Field Feature
  • Variable PIP Position in 64–X by 64–Y Steps
  • PIP Border with Programmable Color
  • Programmable PIP Tint and Saturation Control
  • Automatic Main to PIP Contrast Balance
  • Vertical Filter
  • Integrated 64 k Bit DRAM Memory Resulting in Minimal RFI
  • Minimal RFI Allows Simple Low Cost Application into TV
  • I2C Bus Control – No External Variable Adjustments Needed
  • Operates from a Single 5.0 V Supply
  • Economical 56–Pin Shrink DIP Package YC–PIP System Diagram Video Processor Yin C in CV Main (unused) Ymain out C main out CV 1 CV 2 YC PIP MC44462 Ymain in C main in S W M T R X Y C Comb Filter (MC141625) IIC IIC CV Tuner/IF Cable Y C CV Back Panel S–VHS Inputs Back Panel Composite Video Input R G B This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.  Motorola, Inc. 1996 Issue 2

2 MOTOROLA ANALOG IC DEVICE DATA

ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Power Supply Voltage ÁÁÁÁ ÁÁÁÁ VDD ÁÁÁÁÁ ÁÁÁÁÁ –0.5 to +6.0 ÁÁÁ ÁÁÁ V ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Power Supply Voltage ÁÁÁÁ ÁÁÁÁ VCC ÁÁÁÁÁ ÁÁÁÁÁ –0.5 to +6.0 ÁÁÁ ÁÁÁ V ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Voltage Range ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ VIR ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁÁ –0.5, VDD + 0.5 ÁÁÁ Á Á Á ÁÁÁ V ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Output Current ÁÁÁÁ ÁÁÁÁ IO ÁÁÁÁÁ ÁÁÁÁÁ 160 ÁÁÁ ÁÁÁ mA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Power Dissipation ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Maximum Power Dissipation @ 70°C ÁÁÁÁ PD ÁÁÁÁÁ 1.3 ÁÁÁ W ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Thermal Resistance, Junction–to–Air ÁÁÁÁ ÁÁÁÁ R θJA ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ °C/W ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Junction Temperature (Storage and Operating) ÁÁÁÁ ÁÁÁÁ TJ ÁÁÁÁÁ ÁÁÁÁÁ –65 to +150 ÁÁÁ ÁÁÁ NOTE: ESD data available upon request. ELECTRICAL CHARACTERISTICS (VCC = VDD = 5.0 V, TA = 25°C, unless otherwise noted.) Characteristic Symbol Min Typ Max Unit POWER SUPPLY ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Total Supply (Pins 8, 15, 43 and 50) ÁÁÁÁÁ ÁÁÁÁÁ Total ISupply ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 100 ÁÁÁÁ ÁÁÁÁ 160 ÁÁÁ ÁÁÁ mA VIDEO ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Composite Video Input (Pin 34 or 36) ÁÁÁÁÁ ÁÁÁÁÁ CVi ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 1.0 ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ Vpp ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Luma Output (Pin 49, Unterminated) ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 2.0 ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ Vpp ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Video Output DC Level (Sync Tip) ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 1.0 ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ Vdc ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Video Gain ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 6.0 ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ dB ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Video Frequency Response (Main Video to –1.0 dB) ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ MHz ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Color Bar Accuracy ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ±4.0 ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ deg ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Video Crosstalk (@ 75% Color Bars) ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ dB ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Main to PIP ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ PIP to Main ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Output Impedance ÁÁÁÁÁ Á ÁÁÁ Á ÁÁÁÁ Á ÁÁ Á ÁÁÁÁ Á ÁÁ Á 5.0 ÁÁÁÁ Á ÁÁ Á ÁÁÁ ÁÁ Á Ω HORIZONTAL TIMEBASE ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Free Run HPLL Frequency (Pin 16) ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 15734 ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ Hz ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ HPLL Pull–In Range ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ±400 ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ Hz ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ HPLL Jitter ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ±4.0 ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ns ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Burst Gate Timing (from Trailing Edge Hsync, Pin 24) ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 1.0 ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ µs ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Burst Gate Width ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 4.0 ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ µs VERTICAL TIMEBASE ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Vertical Countdown Window ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 232 – 296 ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ H lines ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Vertical Sync Integration Time ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ µs ANALOG TO DIGITAL CONVERTER ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Resolution ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ Bits ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Integral Non–Linearity ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ LSB ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Differential Non–Linearity ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ +2/–1 ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ LSB ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ADC – Y Frequency Response @ –5.0 dB ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 1.0 ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ MHz ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ADC – U, V Frequency Response @ –5.0 dB ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 200 ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ kHz ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Sample Clock Frequency (4/3 FSC ) ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 4.773 ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ MHz

Figure 1. Representative Block Diagram This device contains approximately 500,000 active transistors.

3.0 MHz

57.28 MHz90°0°

14.32 MHz

16 FSC PLL

28 Sync Sep

4 MOTOROLA ANALOG IC DEVICE DATA

Figure 2. Application Circuit

16 FSC Filter

frequency capacitors. As a guideline, a 10 µF in parallel with a 0.1 µF at each supply pin is recommended.

5MOTOROLA ANALOG IC DEVICE DATA I2C REGISTER DESCRIPTIONS Base write address = 24h Base read address = 25h Read Register There are two active bits in the single read byte available from the MC44462 as follows: Write Vertical Indicator (WVI0) – D7 When 0 indicates that the write operation specified by the last I2C command has been completed. PIP Sync Detect Bit (PSD0) – D1 When 0 indicates that the PIP video H pulses are present and the horizontal timebase oscillator is within acceptable limits. Write Registers Read Start Position/Write Start Position Registers Sub–address = 00h Write Raster Position Start Bits (WPS0–2) – D0–D2 Establishes the horizontal beginning of the PIP and its black level measurement gate. This beginning may be varied by approximately 3.0 µs. The position of this pulse may be observed through the Multi Test Pin 30 (See Test Mode Register Sub–address 03h). Read Raster Position Bits (RPS0–3) – D4–D7 Establishes the clamp gate position for the black level reference for the main picture. This position may be varied by approximately 5.0 µs. The position of this pulse may be observed through the Multi Test Pin 30 (See Test Mode Register Sub–address 03h). Pip Switch Delay/Vertical Filter Register Sub–address = 01h PIP Switch Delay Bits (PSD0–3) – D0–D3 Delays the start of PIP on time relative to the PIP picture. These bits are used to center the PIP border and PIP picture in the horizontal direction. Vertical Filter Bit (VFON) – D4 When the filter is activated (VFON = 1) a three line weighted average is taken to provide the data stored in the field memory. Border Color Register Sub–address = 02h Border Color Bits (BC0–2) – D0–D2 These Bits control the color of the border. Note that when using one of the saturated border colors it is possible to get objectionable dot crawl at the edge of the border in some TVs unless appropriate comb filtering is used in the TV circuitry. ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ BC (2:0) ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Border Color ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ 000 ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Black ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ 001 ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ White 70% ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ 010 ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ No Border (clear) ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ 011 ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ No Border (clear) ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ 100 ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Blue ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ 101 ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Green ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ 110 ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Red ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ 111 ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ White Test Mode/Main Vertical and Horizontal Polarity Register Sub–address = 03h Internal Test Mode Register (ITM0–2) – D0–D2 Sets the Multi Test Pin output to provide one of several internal signals for test and production alignment. Also controls the test memory address counter. ÁÁÁÁÁÁ ÁÁÁÁÁÁ ITM (2:0) ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Multi–Test I/O and Function ÁÁÁÁÁÁ ÁÁÁÁÁÁ 000 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Input – Analog Test mode ÁÁÁÁÁÁ ÁÁÁÁÁÁ 001 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Input – Digital Test mode ÁÁÁÁÁÁ ÁÁÁÁÁÁ 010 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Output – Sync Detect ÁÁÁÁÁÁ ÁÁÁÁÁÁ 011 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Output – PIP Switch ÁÁÁÁÁÁ ÁÁÁÁÁÁ 100 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Output – PIP H Detect ÁÁÁÁÁÁ ÁÁÁÁÁÁ 101 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Output – PIP V Detect ÁÁÁÁÁÁ ÁÁÁÁÁÁ 110 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Output – PIP Clamp ÁÁÁÁÁÁ ÁÁÁÁÁÁ 111 ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Output – Main Clamp Main vertical polarity select bit (MVP0) – D6 Selects polarity of active level of vertical reference input. 0 = positive going, 1 = negative going. Main horizontal polarity select bit (MHP0) – D7 Selects polarity of active level of horizontal reference input. 0 = positive going, 1 = negative going. PIP Freeze/PIP Size/Main and PIP Video Source Register Sub–address = 04h PIP Freeze Bit (STIL0) – D4 When set to one, the most recently received field is continuously displayed until the freeze bit is cleared. PIP Size Bit (PSI90) – D5 Switches the PIP size between 1/16 main size (when 0) and 1/9 main size (when 1). Video Type Select Bit (YCPSEL) – D6 Selects which video type will be applied to the PIP input. PIP Video Source Select Bit (PSEL0) – D7 Selects which composite video input will be applied to the video decoder to provide the PIP video in CV mode. ÁÁÁÁ ÁÁÁÁ PSEL ÁÁÁÁ ÁÁÁÁ YCPSEL ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Function ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ YC Input to PIP ÁÁÁÁ ÁÁÁÁ 0 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ CV 1 Input to PIP ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ CV 1 Input to PIP CV 2 Input to PIP PIP On/PIP Blank Register Sub–address = 05h PIP On Bit (PON0) – D0 When on (1) turns the PIP on. PIP Blanking Bit (PBL0) – D4 When on (1) sets the PIP to black. If the PIP is off, then it will be black if it is turned on. Overrides all other settings of the PIP control. PIP X Position Register Sub–address = 06h X Position Bits (XPS0–5) – D0–D5 Moves the PIP start position from the left to the right edge of the display in 64 steps. There is protection circuitry

6 MOTOROLA ANALOG IC DEVICE DATA

to prevent the PIP from interfering with the main picture sync pulses. PIP Y Position Register Sub–address = 07h Y Position Bits (YPS0–5) – D0–D5 Moves the PIP start position from the top to the bottom edge of the display in 64 steps. There is protection circuitry to prevent the PIP from interfering with the main picture sync pulses. PIP Chroma Level Register Sub–address = 08h Chroma (C0–5) – D0–D5 The color of the PIP can be adjusted to suit viewer preference by setting the value stored in these bits. A total of 64 steps varies the color from no color to maximum. This control acts in conjunction with the auto phase control. PIP Tint Level Register Sub–address = 09h Tint (T0–5) – D0–D5 An auto phase control compares the main color burst to the internally generated pseudo color burst so that the tints are matched. In addition to this, the tint of the PIP can be varied ±10° in a total of 64 steps by changing the value of these bits to suit viewer preference. PIP Luma Delay Register Sub–address = 0Ah Y Delay (YDL0–2) – D0–D2 Since the Chroma passes through a bandpass filter and the color decoder, it is delayed with respect to the Luma signal. Therefore, to time match the Luma and Chroma these bits are set to a single value determined to be correct in the application. Pip Fill/Test Register Sub–address = 0Ch PIP Fill Bits (PIPFILL0–1) – D0–D1 May be used to fill the PIP with one of three selectable solid colors Test Register Bits (INTC0 and MACR0) – D6–D7 Used for production test only. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ I2C REGISTER TABLE ÁÁÁÁ ÁÁÁÁ Sub – ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Data Bit ÁÁÁÁ ÁÁÁÁ Sub – address ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ RPS3 ÁÁÁÁÁ ÁÁÁÁÁ RPS2 ÁÁÁÁÁ ÁÁÁÁÁ RPS1 ÁÁÁÁÁ ÁÁÁÁÁ RPS0 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ WPS2 ÁÁÁÁÁ ÁÁÁÁÁ WPS1 ÁÁÁÁÁ ÁÁÁÁÁ WPS0 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ VFON ÁÁÁÁ ÁÁÁÁ PSD3 ÁÁÁÁÁ ÁÁÁÁÁ PSD2 ÁÁÁÁÁ ÁÁÁÁÁ PSD1 ÁÁÁÁÁ ÁÁÁÁÁ PSD0 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ BC2 ÁÁÁÁÁ ÁÁÁÁÁ BC1 ÁÁÁÁÁ ÁÁÁÁÁ BC0 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ MHP0 ÁÁÁÁÁ ÁÁÁÁÁ MVP0 ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ITM2 ÁÁÁÁÁ ÁÁÁÁÁ ITM1 ÁÁÁÁÁ ÁÁÁÁÁ ITM0 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ PSEL0 ÁÁÁÁÁ ÁÁÁÁÁ YCPSEL ÁÁÁÁÁ ÁÁÁÁÁ PSI90 ÁÁÁÁÁ ÁÁÁÁÁ STIL0 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ PBL0 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ PON0 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ XPS5 ÁÁÁÁÁ ÁÁÁÁÁ XPS4 ÁÁÁÁ ÁÁÁÁ XPS3 ÁÁÁÁÁ ÁÁÁÁÁ XPS2 ÁÁÁÁÁ ÁÁÁÁÁ XPS1 ÁÁÁÁÁ ÁÁÁÁÁ XPS0 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ YPS5 ÁÁÁÁÁ ÁÁÁÁÁ YPS4 ÁÁÁÁ ÁÁÁÁ YPS3 ÁÁÁÁÁ ÁÁÁÁÁ YPS2 ÁÁÁÁÁ ÁÁÁÁÁ YPS1 ÁÁÁÁÁ ÁÁÁÁÁ YPS0 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ YDL2 ÁÁÁÁÁ ÁÁÁÁÁ YDL1 ÁÁÁÁÁ ÁÁÁÁÁ YDL0 ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ

7MOTOROLA ANALOG IC DEVICE DATA B SUFFIX PLASTIC PACKAGE CASE 859–01 (SDIP) ISSUE O OUTLINE DIMENSIONS 51.69 13.72 3.94 0.36 0.81 0.20 2.92 0.51 52.45 14.22 5.08 0.56 1.17 0.38 3.43 1.02 MILLIMETERS 2.035 0.540 0.155 0.014 0.032 0.008 0.115 0.020 2.065 0.560 0.200 0.022 0.046 0.015 0.135 0.040 -T- SEATING PLANE C D 56 PL E F J 56 PL K MG N 12 8 56 29 NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH. MAXIMUM MOLD FLASH 0.25 (0.010).MIN MIN MAX MAX INCHES DIM A B C D E F G H J K L M N 15.24 BSC0.600 BSC

1.778 BSC

7.62 BSC

0.070 BSC

0.300 BSC

0.89 BSC0.035 BSC L H -A- -B- 0.25 (0.010) T AM S 0.25 (0.010) T BM S Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution;JAPAN : Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–54543–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 INTERNET : http://Design–NET.com 51 Ting Kok R oad, Tai Po, N.T., Hong Kong. 852–26629298 MC44462/D /C0042/C0077/C0067/C0052/C0052/C0052/C0054/C0050/C0047/C0068/C0042