MC44302A

MC44302A MOTOROLA | Alldatasheet

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/C0077/C0067/C0052/C0052/C0051/C0048/C0050/C0065 SEMICONDUCTOR TECHNICAL DATA ADVANCED MULTI–STANDARD VIDEO/SOUND IF

ORDERING INFORMATION

TA = 0° to +70°C SO–28L Plastic DIP P SUFFIX PLASTIC PACKAGE CASE 710 (Top View) PIN CONNECTIONS Order this document by MC44302A/D DW SUFFIX PLASTIC PACKAGE CASE 751F (SO–28L) Intercarrier Sound OutputDC Volume Control Sound Input (FM) Audio Input/ Audio–Video Switch Sound De–Emphasis (FM) Negative Video Out Positive Video Out Sound AFT Filter/ Peak White Filter Video IF Input Video IF Input Video Mode Switch AFT Output AFT Mode Switch RF AGC Output Video IF AGC Filter Audio Output (Variable) Sound Quadrature Coil (FM) VCC Audio Output (Constant) Sound Input (AM) Gnd VCO Coil VCO Coil PLL Filter (Main VCO Loop) Lock Detector/Filter (Acquisition Circuit) Flyback/Video Input Horizontal PLL Filter RF AGC Delay 1MOTOROLA ANALOG IC DEVICE DATA /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0073/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0065/C0100/C0118/C0097/C0110/C0099/C0101/C0100 /C0077/C0117/C0108/C0116/C0105/C0045/C0083/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0084/C0086 /C0086/C0105/C0100/C0101/C0111/C0047/C0083/C0111/C0117/C0110/C0100 /C0073/C0070 The MC44302A is a multi–standard single channel TV Video/Sound IF and PLL detector system specifically designed for use with all standard modulation techniques including NTSC, PAL, and SECAM. This device enables the designer to produce a high quality IF system with a minimum number of external components. The MC44302A contains a high gain video IF with an AGC range of 80 dB, enhanced phase–locked loop carrier regenerator for low static phase error, doubly balanced full wave synchronous video demodulator featuring wide bandwidth positive and negative video outputs with extremely low differential gain and phase distortion, video AFT amplifier, multistage sound IF limiter with FM quadrature detector and AFT for self tuning, AM sound detector, constant and variable audio outputs, dc volume control for reduced hum and noise pickup, unique signal acquisition circuit that prevents false PLL lockup and AFT push out, horizontal gating system with sync separator and phase–locked loop circuitry for self–contained RF/IF AGC operation, RF AGC delay circuitry, and programmable control logic that allows operation in NTSC, and PAL SECAM systems. This device is available in wide body 28 pin dual–in–line and surface mount plastic packages.

• Multi–Standard Detector System for NTSC, PAL, and SECAM
• High Gain Video IF Amplifier with 80 dB AGC Range
• Enhanced PLL Carrier Regenerator for Low Static Phase Error
• Synchronous Video Demodulator with Positive and Negative Video Outputs
• Sound IF with Self Tuning FM Quadrature Detector
• AM Sound Detector
• DC Volume Control
• Unique Signal Acquisition Circuit Prevents False PLL Lockup
• Horizontal Gating System for Self Contained RF/IF AGC Operation
• RF AGC Delay Circuitry This document contains information on a new product. Specifications and information herein are subject to change without notice.  Motorola, Inc. 1997 Rev 0 Simplified Television Block Diagram DC Volume Control MC44302A Vertical & Horizontal Scan Circuitry Power Supply VHF/UHF Tuner Video IF Audio Amp Video Detector Sound IF Sound Detector Video Drivers Luma & Chroma Processor SAW Filter Horizontal Gating System RF/IF AGC Mode Switch AFT

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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Power Supply Voltage ÁÁÁÁ ÁÁÁÁ VCC ÁÁÁÁÁ ÁÁÁÁÁ 7.0 ÁÁÁ ÁÁÁ V ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Input Voltage Range ÁÁÁÁ ÁÁÁÁ VIR ÁÁÁÁÁ ÁÁÁÁÁ –0.3 to VCC ÁÁÁ ÁÁÁ V Video IF (Pins 8, 9) FM Sound IF (Pin 2) AM Sound IF (Pin 23) AFT Switch (Pin 12) Audio Input/Audio Switch/Video Invert (Pin 3) Mode Switch (Pin 10) RF AGC Delay (Pin 15) Volume Control (Pin 1) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Sound Quadrature Coil Voltage (Pin 26) ÁÁÁÁ ÁÁÁÁ VQC ÁÁÁÁÁ ÁÁÁÁÁ VCC ÁÁÁ ÁÁÁ V ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ VCO Coil Voltage (Pins 20, 21) ÁÁÁÁ ÁÁÁÁ VVCO ÁÁÁÁÁ ÁÁÁÁÁ VCC ÁÁÁ ÁÁÁ V ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Flyback/Video Input Current (Pin 17) ÁÁÁÁ ÁÁÁÁ Iin ÁÁÁÁÁ ÁÁÁÁÁ ±1.0 ÁÁÁ ÁÁÁ mA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Output Current ÁÁÁÁ ÁÁÁÁ IO ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ mA Positive and Negative Video (Pins 5, 6) 15 Intercarrier Sound (Pin 28) 15 Constant and Variable Audio (Pins 24, 27) 15 RF AGC, Internally Limited (Pin 13) 2.0 AFT Source or Sink (Pin 11) 4.0 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Power Dissipation and Thermal Characteristics ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁ DW Suffix, Plastic Package Case 751F Maximum Power Dissipation @ TA = 70°C PD 800 mW Thermal Resistance, Junction–to–Air R θJA 100 °C/W P Suffix, Plastic Package Case 710 Maximum Power Dissipation @ TA = 70°C PD 1000 mW Thermal Resistance, Junction–to–Air R θJA 80 °C/W ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Operating Junction Temperature ÁÁÁÁ ÁÁÁÁ TJ ÁÁÁÁÁ ÁÁÁÁÁ +150 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Operating Ambient Temperature ÁÁÁÁ ÁÁÁÁ TA ÁÁÁÁÁ ÁÁÁÁÁ 0 to +70 ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Storage Temperature ÁÁÁÁ ÁÁÁÁ Tstg ÁÁÁÁÁ ÁÁÁÁÁ –65 to +150 ÁÁÁ ÁÁÁ NOTE: ESD data available upon request. ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TA = 25°C.) Characteristic Symbol Min Typ Max Unit VIDEO IF AMPLIFIER Differential Input Impedance Components Parallel Resistance R in(VIF) – 3.4 – kΩ Parallel Capacitance C in(VIF) – 4.0 – pF Differential Input Voltage for Full Video Output Swing DV in(VIF) – 40 – µVrms Automatic Gain Control Range AGC VIF – 80 – dB Noise Figure (Vin = 1.0 mV, RS = 300 Ω ) NF – 7.0 – dB Bandwidth, –3.0 dB (RS = 300 Ω ) BW VIF – 120 – MHz Sound Intercarrier Output, 4.5 MHz (Vin = 1.0 mV, Note 2) VO(Snd IC) – 0.1 – Vrms VIDEO DETECTOR Output Voltage Swing (Pin 5 or 6, RL = 2.0 k, Note 1) VO(VD) – 2.2 – Vpp Output Impedance (Pin 5 or 6, 1.0 MHz, 1.0 mA) |ZO | – 100 – Ω Bandwidth, –3.0 dB, (RL = 2.0 k) BW VD MHz Negative Output (Pin 5) – 8.0 – Positive Output (Pin 6) – 7.0 – Output Distortion, Uncorrected (RL = 2.0 k, Note 1) Differential Gain DG % Negative Video Output – 2.0 5.0 Positive Video Output – 2.0 5.0 Differential Phase DP Deg Negative Video Output – 1.0 5.0 Positive Video Output – 1.0 5.0

3MOTOROLA ANALOG IC DEVICE DATA ELECTRICAL CHARACTERISTICS (continued) (VCC = 5.0 V, TA = 25°C.) Characteristic UnitMaxTypMinSymbol VIDEO DETECTOR (CONTINUED) Residual 920 kHz Beat Output, dB Below 100% Modulated Video BO – –60 – dB (Pin 5 or 6, Note 2) FM SOUND IF AND DETECTOR Input Impedance Components Parallel Resistance R in(FM) – 2.2 – kΩ Parallel Capacitance C in(FM) – 4.0 – pF Input Limiting Threshold (f = 4.5 MHz) Vin(Snd) – 80 – µV AM Rejection (Vin = 10 mV, Notes 4, 5, 6) AMR dB f = 4.5 MHz – 50 – f = 5.5 MHz – 50 – Recovered Audio Output (Pin 24, Vin = 10 mV, Note 4) VO(Snd) Vpp Output Distortion (Pin 24, Vin = 10 mV, Note 4) THD % Sound AFT (Note 7) ΔfAFT(Snd) MHz Pull–in Range – ±0.6 – Hold–in Range – ±0.6 – Sound De–Emphasis Internal Resistance (Pin 4) R DE – 18 – kΩ AM Detector Crosstalk CtlkAM – –6.0 – dB AM DETECTOR Input Impedance Components Parallel Resistance R in(AM) – 5.6 – kΩ Parallel Capacitance C in(AM) – 4.0 – pF Recovered Audio Output (Pin 24, Vin = 100 mV, Note 5) VO(Snd) – 2.0 – Vpp Output Distortion (Pin 24, Vin = 10 mV, Note 5) THD – 1.0 – % FM Sound IF and Detector Crosstalk CtlkFM – –60 – dB DC VOLUME CONTROL Volume Control Range (Pin 1, Pin 3 = Vin) ΔVO(Snd) – +12 to –70 – dB Output Signal at Minimum Volume Setting (Pin 1 = Gnd, Pin 3 = Vin ) VO(Snd) – 1.0 – mV Video Detector Sync to Audio Channel Crosstalk CtlkVD dB Fixed Output – –60 – Variable Output – –60 – Audio Channel Crosstalk CtlkSnd dB Fixed Output to Variable Output – –60 – Variable Output to Fixed Output – –60 – 2. Vin = 100 µVrms signal at 41.25 MHz added to signal in Note 1. 3. Differential carrier level at video IF inputs to cause the negative detector output to go positive by 0.1 V from ground. 4. FM Modulation =±25 kHz deviation at 1.0 kHz for 4.5 MHz intercarrier. ±50 kHz deviation at 1.0 kHz for 5.5 MHz intercarrier. 6. AM Rejection (dB) = 20 log 7. Tested with 15 µH sound quadrature coil in parallel with 68 pF and 10 kΩ . 8. The AFT output can be disabled by leaving Pin 12 disconnected or by biasing it to the voltage level shown above. When disabled, the output will be internally clamped to one half of VCC . VO(FM) VO(AM)

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ELECTRICAL CHARACTERISTICS (continued) (VCC = 5.0 V, TA = 25°C.) Characteristic UnitMaxTypMinSymbol PHASE–LOCKED LOOP Acquisition Circuit Filter Voltage (Pin 18) VPLL(Acq) V Unlocked with No–Signal – 2.7 – Unlocked to Locked Sweep Range upon Signal Acquisition – 1.2 to 4.3 – Locked, Final Static Condition – 4.3 – VCO Filter Voltage (Pin 19) VPLL(VCO) V Unlocked – 3.2 – Locked, Final Static Condition – 3.2 – Video IF Lock–Up Time tIF(lock) – 5.0 – ms HORIZONTAL GATING SYSTEM Sync Separator Input Threshold Voltage (Pin 17) Vth(Sync) – 3.4 – V PLL Filter Voltage, Locked or Unlocked with No–Signal (Pin 16)VPLL(Horiz) – 2.9 ± 1.1 – V RF AGC RF AGC Delay Voltage Range (Pin 15) VAGC(DLY) – 1.7 to 2.4 – V RF AGC Output Current (Pin 13) IO(sink) 1.0 2.0 – mA LOGIC CONTROL Mode Select Voltage Range (Pin 10) Vth(Mode) V PAL 1 4.7 to 5.0 4.6 to 5.0 – PAL 2 3.5 to 4.1 3.4 to 4.2 – SECAM 2.3 to 2.9 2.2 to 3.0 – NTSC 0 to 0.3 0 to 0.4 – AFT Switch Threshold (Pin 12) Vth(AFT) AFT Output, Pin 11, Sourcing when IF Frequency is Low – 5.0 – AFT Output, Pin 11, Sinking when IF Frequency is Low – 0 – AFT Output, Pin 11, Disabled (Note 8) – 2.5 – Audio Switch/Video Invert Voltage Range (Pin 3) Vth(AS/VI) V Audio 1, Internal Audio (AM or FM) appears at Pins 24 and 27, 3.4 to 5.0 3.3 to 5.0 – Positive Video appears at Pin 6, Negative Video appears at Pin 5 Audio 2, Internal Audio (AM or FM) appears at Pin 24, 1.8 to 2.2 1.7 to 2.3 – External Audio appears at Pin 27, Positive Video appears at Pin 6, Negative Video appears at Pin 5 Video 1, Internal Audio (AM or FM) appears at Pins 24 and 27, 0.6 to 0.9 0.5 to 1.0 – Positive Video appears at Pin 6, Negative Video appears at Pin 5 Video 2, Internal Audio (AM or FM) appears at Pins 24 and 27, 0 to 0.2 0 to 0.3 – Positive Video appears at Pin 5, Negative Video appears at Pin 6 TOTAL DEVICE Operating Voltage VCC V TA = 25°C 4.5 5.0 5.5 TA = 0°C to 70°C 4.75 – 5.5 Power Supply Current (VCC = 5.0 V) ICC – 100 – mA 2. Vin = 100 µVrms signal at 41.25 MHz added to signal in Note 1. 3. Differential carrier level at video IF inputs to cause the negative detector output to go positive by 0.1 V from ground. 4. FM Modulation =±25 kHz deviation at 1.0 kHz for 4.5 MHz intercarrier. ±50 kHz deviation at 1.0 kHz for 5.5 MHz intercarrier. 6. AM Rejection (dB) = 20 log 7. Tested with 15 µH sound quadrature coil in parallel with 68 pF and 10 kΩ . 8. The AFT output can be disabled by leaving Pin 12 disconnected or by biasing it to the voltage level shown above. When disabled, the output will be internally clamped to one half of VCC . VO(FM) VO(AM)

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Figure 7. Video Output Frequency Response Figure 8. Vectorscope Display of Figure 9. FM Sound AFT Filter Voltage Figure 10. FM Sound Intercarrier Self–Tuning Figure 11. FM Sound Detector Relative Output, and

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Figure 19. Representative Block Diagram This device contains 2,641 active transistors.

9MOTOROLA ANALOG IC DEVICE DATA FUNCTIONAL DESCRIPTION Introduction The MC44302A is an advanced high performance multistandard IF system specifically designed for use with all of the world’s major television modulation techniques including NTSC, PAL, and SECAM. This device performs the function of intermediate frequency (IF) amplification, automatic gain control (AGC), automatic frequency tuning (AFT) and signal demodulation for transmitting systems that use either positive or negative amplitude modulated video along with frequency modulated (FM) or amplitude modulated (AM) sound. The television designer is offered a new level of circuit simplicity along with enhanced system performance when compared to present day television IF amplifiers. Numerous unique design techniques are incorporated resulting in only a single tuned circuit adjustment for a completely aligned video and sound IF system with tuner AFT output. Special design attention was given to enhance noise performance and to reduce differential gain and phase distortion. Additional internal circuitry is provided to meet the European Peritel socket requirements along with a means for descrambling video signals that use either or both amplitude modulated sync and alternate line video inversion. A detailed block diagram of the internal architecture is shown in Figure 19 and an operating description of the major circuit blocks is given below. IF Amplifier and AGC The IF amplifier consists of four cascaded ac coupled gain stages yielding an input sensitivity of 40 µV for a full video output swing of 2.2 Vpp. This level of sensitivity allows the use of a single IF block filter without incurring the additional cost of a preamplifier. A quite acceptable level of signal to noise performance is achievable by utilizing a tuner with a gain of 33 dB to 36 dB combined with a low insertion loss (≤18 dB) surface acoustic wave (SAW) or passive block filter. The first three stages of the IF amplifier are gain controlled to provide an AGC range of 80 dB. This extended AGC range enhances the signal handling capability, resulting in superior differential phase and gain performance with a significant reduction of intermodulation products. AGC of the first stage is internally delayed so as to preserve the amplifier’s low noise figure characteristics. An on–chip sync separator and horizontal phase–locked loop oscillator is provided for noise immune AGC gating in self contained applications where a horizontal scan signal may not be available. A positive going sync source connected to the Flyback/Video input at Pin 17 is used to lock the PLL and generate an internal AGC keying pulse. The sync separator allows direct use of the Negative Video output at Pin 5 as a source for the keying pulse. If horizontal scan circuitry is available, a positive going flyback pulse can also be used to set the keying pulse. A video signal and a reference level are required to implement automatic gain control of the lF and tuner. The video AGC reference is selected for a specific modulation standard by the Video Mode Switch voltage setting at Pin 10; refer to Table 2. With PAL 1, PAL 2, or NTSC mode selected, a black level reference is established by AGC keying during the tip of sync. With SECAM mode selected, a black level reference is established by AGC keying during the back porch. In order to correct for the inconsistent back porch level that is common between SECAM transmitters, a long time constant non–keyed peak white reference level is also established, and is used in conjunction with the black level reference to control the video output level. The peak white level is used in effect to slowly readjust the black level reference threshold over a limited range of ±10%. With this dual reference approach, the accuracy associated with a typical peak white detecting system is maintained without the usual sacrifice of speed, thus allowing a quick AGC response to airplane flutter and channel changes. The tuner AGC control function consists of an RF AGC delay adjustment at Pin 15 and an RF AGC output at Pin 13. The delay adjustment sets the threshold where tuner gain reduction is to begin. This usually corresponds to a signal level of 1.0 mV to 2.0 mV at antenna input. The AGC output is designed to control a reverse AGC type of tuner. As the antenna signal level increases, the voltage at Pin 13 decreases, causing a gain reduction in the tuner. Since Pin 13 is an NPN open collector output, an external pull–up resistor must be added if one is not provided in the tuner. Pin 13 is guaranteed to sink a minimum of 1.0 mA. Note that when operating with a tuner that requires in excess of 5.6 V, current will flow into Pin 13 due to conduction of the upper internal clamp diode. Carrier Regeneration Carrier regeneration is attained by the use of a phase–locked loop, thus enabling true synchronous demodulation to be achieved with all of its advantages. Following the IF amplifier and preceding the PLL phase detector is a limiting amplifier designed to remove the amplitude modulation that is present on the carrier. The amplifier consists of two cascaded differential stages with direct coupled feedback to set a closed loop gain of 40 dB. This two stage approach has several distinct advantages when compared to conventional integrated demodulators that utilize a single stage limiter. With a two stage limiter, the gain requirement to remove the video amplitude modulation can be designed–in without the large voltage swings that are required by a single stage limiter with equivalent gain. The large voltage swings lead to poor differential phase and gain performance, and consequently the need for an external tuned circuit with two cross coupled limiting diodes. Use of direct coupled feedback diminishes the effects of the amplifier’s input offset voltage which can be an additional source for differential phase and gain errors. The combination of low voltage swing per stage with dc feedback eliminates the need for a tuned circuit at the output of the limiter. This results in a significant component and alignment cost savings as well as removing the necessity to pin out a high level IF signal. This high level signal is a potential radiation source that can result in IF instability at low signal levels. The only problem of using the two stage limiter is the potential for an additional static phase shift which will result in a change of the demodulating angles at both the video and sound demodulators inputs. This problem is solved by placing an identical two stage limiter between the frequency doubler output and the phase detector input. This adds an identical amount of static phase shift to bring the demodulating angles back to 0° and 90°.

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Figure 20. Phase Detector

1.0 MHz

Figure 20. Switches SW1, SW2, and SW3 are driven by a 1.0 MHz square wave with an accurate 1:1 mark/space ratio. shift between the two phase detector inputs. control bias that is applied to the reactance stage input. doubled to picture carrier frequency by a balanced multiplier. one that operates at one half of the IF frequency. Figure 21. VCO and Frequency Doubler

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large inductance. Parasitic layout and coil capacitance must be considered for optimum performance. Suggested component values are given in Table 3. The sound AFT time constant is set by an external capacitor that is connected from Pin 7 to ground. This capacitor is driven by an internal 300 µA current source and sink. The demodulated sound bandwidth is in excess of 100 kHz making this device well suited for MTS (multi–channel television sound) stereo and SAP (second audio program) TV applications. Sound de–emphasis is controlled by the time constant of an internal 18 kΩ resistor and an external capacitor that is connected from Pin 4 to ground. The FM IF is active in PAL 1, PAL 2 and NTSC modes, and provides 2.0 Vpp of audio at the Variable and Constant outputs. With the AM IF, intercarrier sound is amplified and detected by a fully balanced exalted carrier demodulator. The detector provides in excess of 2.0 Vpp recovered audio output at Pin 24. An internal low pass filter is incorporated to suppress any high frequency harmonics that may be present at the demodulator output. The AM IF is active in both the SECAM and NTSC modes. Audio Input/ Audio–Video Switch The Audio Input/Audio–Video Switch is a multifunction input that selects the source for the audio that appears at Pin 27, and the polarity of the video that appears at Pins 5 and 6. There are four possible modes for this input and they are each selected by applying a specific dc voltage level to Pin 3. Refer to Table 1 and to the circuit description for Pin 3 in Table 3. Audio 1 is intended for applications where internally demodulated audio is present at the Variable and Constant outputs. The Variable output can be used internal to the TV chassis and the Constant output can be connected to a jack for earphone or recorder use. Audio 1 is selected by not having a dc path from Pin 3 to ground. Internally demodulated audio (AM or FM) will appear at Pins 24 and 27, negative video at Pin 5, and positive video at Pin 6. If there is an ac coupled audio source present at Pin 3, it will be internally disconnected. Audio 2 is intended for European applications where internal and external audio sources must be routed through the Peritel socket. Internally demodulated audio present at the Constant output can be routed out the Peritel socket while external audio can be routed in, ac coupled to Pin 3, and level adjusted at Pin 1 for use within the TV chassis. Audio 2 is selected by connecting a 22 kΩ resistor from Pin 3 to ground. Internally demodulated audio (AM or FM) appears at Pin 24, negative video at Pin 5, positive video at Pin 6, and the ac coupled external audio source at Pin 3 appears at Pin 27 inverted. The audio level into Pin 3 must be limited so that the selected mode of operation is not changed during the peak excursions with Audio 2 selected, and the valley excursion with Audio 1 selected. With the component values shown in Table 3, the audio level should be limited to less than 1.1 Vrms. Video 1 and 2 modes provide a simple means to recover scrambled video in systems that use some form of alternate line video inversion. Descrambling is accomplished by switching between the two video modes. Video 1 is selected by connecting a 3.3 kΩ resistor from Pin 3 to ground. Internally demodulated audio (AM or FM) will appear at Pins 24 and 27, negative video at Pin 5, and positive video at Pin 6. Video 2 is enabled when Pin 3 is grounded, usually by an IC or a transistor that is gated on alternate or multiple lines. Internally demodulated audio (AM or FM) appears at Pins 24 and 27, positive video with white spot inversion at Pin 5, and negative video at Pin 6. Note that Video 1 mode is identical to Audio 1. Video 1 is provided so that when descrambling, Pin 3 does not have to pass through the voltage range that selects Audio 2. This prevents unwanted switching noise and buzz from appearing at the audio outputs. It should be noted that when combining the features of Pin 3 with the Peritel socket, the TV chassis can provide the audio and video source to drive an external monitor or video recorder. Also an externally generated audio and video source can be used to drive the TV chassis as a monitor. DC Volume Control The dc volume control consists of an electronically controlled audio amplifier that has a range of 12 dB gain, to 60 dB attenuation. The audio output level is set by applying a control voltage to Pin 1. This can be derived from an electronic source such as a digital to analog converter, or a manual source such as the wiper of a potentiometer that is connected from VCC to ground. The potentiometer should be 20 kΩ or less. Because no audio signal is present on Pin 1, any potential for hum and noise pickup can easily be bypassed by connecting a capacitor from this pin to ground. In most cases, an unshielded wire or printed circuit board trace is all that is required to connect the variable voltage source to the IF board.

Table 1. Audio Input/Audio–Video Switch NOTES: 1. Refer to Table 2 to determine the active demodulator (AM and or FM) and the associated audio output pins.

1. The Variable output audio level is controlled by Pin 1.

Table 2. Television Standard Modes demodulation, sound intercarrier demodulation, and AGC. modulated on the sound carrier. the tuner local oscillator (LO) after phase lock is established. instability due to coil radiation.

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The MC44302A is unique in that it uses the VCO loop as a frequency reference for the tuner AFT loop. After signal acquisition and phase lock, the VCO and AFT loops will reach a steady state condition. The VCO will have moved only a small amount from it’s nominal frequency (ΔfVCO ) with the tuner local oscillator (ΔfLO ) correcting for the majority of the frequency error (Δfe). Therefore in steady state condition Δfe = ΔfVCO + ΔfLO , and ΔfLO >> ΔfVCO . This is due to the much higher gain in the tuner LO loop when compared to that of the VCO loop. In this way, the VCO can be used as the frequency reference for the AFT system provided that the PLL can be initially locked to the incoming IF signal. This combination of the tuner LO loop and the VCO loop forms a double loop PLL system. Analysis shows that the overall system stability can be assured by treating the VCO loop as a single stand alone PLL. This is valid if the VCO loop has low gain and high bandwidth which guarantees initial capture, while the tuner LO loop has high gain and low bandwidth which minimizes frequency and phase offsets. The AFT system is designed to acquire the vision carrier, without false locking to the sound or adjacent sound carriers, with an initial tuner LO frequency error of ±2.0 MHz. This error is reduced to less than ±10 kHz upon establishing acquisition and after both the VCO loop and tuner AFT loop have reached their steady state condition. In contrast, the discriminator coil type of AFT has a highly asymmetric lock characteristics with a frequency error in the range of about –2.0 MHz to 1.0 MHz. This large frequency error is due to the effects of lower loop gain combined with the IF filter slope. Higher loop gain can be incorporated into the discriminator coil type of AFT but circuit problems due to large dc offsets, and IF stability due to coil radiation at the picture carrier frequency can be difficult to resolve. In order to achieve a high performance level, without encountering the ill effects associated with high gain discriminator circuits, a novel approach to establishing PLL lock up was developed. Figures 24 and 25 graphically illustrate the Acquisition Circuit operation. In the absence of an IF signal, the Acquisition Circuit examines the state of the Video (I) and Sound (Q) demodulators, detecting that the VCO is out of lock. On loss of lock, the AFT Output at Pin 11 (tuner LO drive) is clamped, and the Lock Detector output at Pin 18 is placed in a sink mode, causing its filter capacitor to discharge. As the capacitor voltage falls below 3.7 V, the application of a VCO offset starts and is completed at 3.0 V. The capacitor voltage will continue to fall stopping at 2.7 V until the Acquisition Circuit detects a signal. At this point both the tuner and IF are offset by the same amount from their nominal frequency of 45.75 MHz. Thus a picture carrier would now be converted to 43.75 MHz and the Main VCO Loop voltage at Pin 19 would be centered within its dynamic range at 3.2 V. The AFT offset is controlled by the system designer to approximately –2.0 MHz. This is done so that if a nominal IF signal appeared, its picture carrier would be centered in the IF filter passband where there is minimum attenuation. Note that even if the tuner LO drifts by as much as ±2.0 MHz, the signal will still not be significantly attenuated. On the arrival of a signal, beat notes are detected at the output of the demodulators, and the Lock Detector output is again placed in a sink mode to further discharge the filter capacitor. When the capacitor voltage falls below 1.3 V, the VCO Sweep is initiated at Pin 19. This causes the VCO to be swept an additional –2.0 MHz from its out of lock nominal centered IF frequency. During this negative sweep, the PLL Phase Detector is inhibited so that a phase lock cannot be obtained. When the capacitor voltage at Pin 19 falls to 2.0 V, the Phase Detector is made active and the VCO is swept in a positive direction from –2.0 MHz to 2.0 MHz of the out of lock centered IF frequency. The PLL will therefore lock to the first carrier it encounters. This in fact has to be a vision carrier since the sound carrier is more than 2.0 MHz below the nominal frequency, and the adjacent lower channel sound carrier is higher than the vision carrier. PLL lock can occur at any point during the positive going sweep of Pin 19 from 2.0 V to 4.2 V. On achieving lock, the Lock Detector output is released allowing the voltage across the filter capacitor to rise. When this voltage reaches 3.0 V, a gradual removal of the VCO offset starts. At 3.7 V removal is completed, the VCO Sweep circuit is inhibited, and the AFT clamp is removed. The phase detector remains permanently enabled. Upon removal of the AFT Clamp, the error voltage that appears at the AFT Amplifier output will drive the incoming signal towards the nominal IF frequency of 45.75 MHz. The Main VCO Loop will track the incoming IF signal while maintaining phase and frequency lock as the loops settle. This is attainable because the tuner AFT loop response is slow while the Main VCO loop is fast. For large frequency errors during this period, the slew rate of the tuner LO loop is automatically increased but not to the extent where it would cause a VCO tracking problem. This technique allows the acquisition time of the circuit to be reduced considerably while still using a larger than normal time constant in the tuner LO loop. In this way, any possibility of phase modulating the LO with video is removed. The amount of AFT offset is controlled by the output swing of Pin 11, the voltage to frequency sensitivity of the tuner’s AFT input, voltage gain or attenuation of any interface level shifting circuitry, and the alignment accuracy of the VCO coil. The amount of VCO offset and VCO sweep is controlled by the change in capacitance ratio of the internal tuning capacitance to that of the fixed external tank capacitors C19 and C20. To insure proper PLL lock, it is recommended that the VCO sweep is limited to less than 5.0 MHz and that C19 and C20 are not be less than 33 pF.

Figure 24. Acquisition Circuit Operation be centered in the IF passband. Channel with an initial 2.0 MHz offset.

2.0 MHz mistuning of the Desired

Channel with an initial 2.0 MHz offset. to shift the PLL reference oscillator.

16 MOTOROLA ANALOG IC DEVICE DATA

Figure 25. Acquisition Circuit Timing Lock Detector/Filter (Acquisition Circuit) Pin 18 – 4.0 ms when slewing up from 0.8 V to 4.3 V. AFT Output Pin 11 – 12 ms when slewing from 4.5 V or 0.5 V to the final static condition of 2.5 V.

18 MOTOROLA ANALOG IC DEVICE DATA

Pin No. Equivalent Internal Circuit Description 0.01 VCC VCC 10 k VCC Volume Control DC Volume Control A potentiometer of 20 kΩ or less, connected as shown, is used to adjust the audio output level at Pin 27. There is no audio signal present at this pin, allowing the use of unshielded wire between the IF board and the potentiometer. To prevent hum and noise pickup, a bypass capacitor connects from this pin to ground. Refer to Figure 17. From Ceramic Sound IF Filter at Pin 28 VCC 2.2 k VCC Sound Input (FM) Sound Input (FM) This pin is the input of the FM IF. The intercarrier sound output at Pin 28 connects to this input through a ceramic bandpass filter. The FM detector is active in PAL 1, PAL 2, and NTSC modes. Refer to Table 2. 15.5 k From External Audio Source 27 k Audio Input/ Audio–Video Switch VCC Audio 2 Audio 1 Video 1 Video 2 0.1V 3.3 k 22 k Audio Input/Audio–Video Switch This is a multifunction input that selects the audio source that appears at Pin 27, and the video polarity at Pins 5 and 6. Audio 1 is without a dc path from Pin 3 to ground. Internally demodulated audio (AM of FM) appears at Pins 24 and 27, negative video at Pin 5, and positive video at Pin 6. The audio source at Pin 3 is internally disconnected. Audio 2 is with the 22 kΩ resistor connected. Internally demodulated audio (AM or FM) appears at Pin 24, negative video at Pin 5, positive video at Pin 6, and the audio source at Pin 3 appears at Pin 27. Video 1 is with the 3.3 kΩ resistor connected. Internally demodulated audio (AM or FM) appears at Pins 24 and 27, negative video at Pin 5, and positive video at Pin 6. Video 2 is with Pin 3 grounded. Internally demodulated audio (AM of FM) appears at Pins 24 and 27, positive video at Pin 5, and negative video at Pin 6. Refer to Table 1. 0.0033 VCC Sound De–Emphasis (FM) VCC 18 k 200 µA 100 µA Sound De–Emphasis (FM) A capacitor is connected from this pin to ground. It is used in conjunction with internal 18 kΩ resistor to set the FM sound de–emphasis time constant. The typical de–emphasis time constant required for a flat audio response is 75 µs in the United States and 50 µs in Europe. The FM sound detector frequency response for different de–emphasis capacitor values is shown in Figure 12.

19MOTOROLA ANALOG IC DEVICE DATA PIN FUNCTION DESCRIPTION (continued) Pin No. DescriptionEquivalent Internal Circuit VCC Negative Video Output VCC 1.0 mA 2.0 k 6 3.4 1.2 Negative Video Output Negative going video appears at this output and it is intended to drive a sync separator. Positive going video will appear at this output when Pin 3 is grounded. This feature provides a simple means for descrambling the video signal in systems that use alternate line video inversion. Refer to the description of Pin 3. The video output is designed to drive a resistive load that is in the range of 2.0 kΩ . Lower resistance values will tend to increase output distortion. VCC Positive Video Output VCC 1.0 mA 2.0 k 6 3.4 1.2 Positive Video Output Positive going video appears at this output and is intended to drive the luma and chroma channels. Negative going video will appear at this output when Pin 3 is grounded. This feature provides a simple means for descrambling the video signal in systems that use alternate line video inversion. Refer to the description of Pin 3. The positive going video signal always contains white spot inversion whether it appears at output Pins 5 or 6. The video output is designed to drive a resistive load that is in the range of 2.0 kΩ . Lower resistance values could increase output distortion. Sound AFT Filter/ Peak White Filter VCC VCC 0 to ±300 µA VCC SECAMPAL NTSC Sound AFT Filter/Peak White Filter A capacitor connected from this pin to ground is used to adjust the sound AFT time constant in PAL and NTSC modes, and video peak white AGC time constant in SECAM mode. The sound AFT filter voltage controls the internal tuning capacitance that is placed across the sound quadrature coil at Pin 26. Refer to Figure 9. 8, 9 Video IF Input VCC 3.4 k Video IF Input These pins are the inputs to the video IF amplifier. The amplifier consists of four ac coupled stages with an input sensitivity of 40 µV for a 2.2 Vpp video output swing. This sensitivity eliminates the need for a preamplifier when used with suitable surface acoustic waves or passive block filters. The IF block filter must be located close to the IC package inputs to prevent unwanted pickup and possible instability problems. The input lead lengths must be kept short with a symmetrical printed circuit board layout.

20 MOTOROLA ANALOG IC DEVICE DATA

PIN FUNCTION DESCRIPTION (continued) Pin No. DescriptionEquivalent Internal Circuit Video Mode Switch 3.0 k VCC VCC 2.4 k 5.1 k PAL 1 PAL 2 SECAM NTSC Video Mode Switch A dc voltage at this input selects the proper video AGC and sound demodulation technique for PAL, SECAM, and NTSC. With PAL 1 selected, AGC is keyed on the sync pulse by the horizontal PLL which is locked to the flyback or video sync pulse present at Pin 17. The FM sound IF and detector is active. The PAL 2 selection is identical to PAL 1 with the addition of sound muting when the acquisition circuit is unlocked or vertical sync is absent. With SECAM selected, the video level is established by both, a long time constant peak white detector, and a back porch keyed AGC that corrects for transmitted black level errors while maintaining fast AGC response. The AM sound detector is active. With NTSC selected, AGC and sound muting is the same as in PAL 1 mode. The FM and AM detectors are both active with the FM output at Pin 27 and the AM output at Pin 24. Refer to Table 2. 11AFT Ouput VCC 3.3 VCC Digital Slew Rate Control To Tuner AFT Input. IO must be externally limited < 4.0 mA. 0 to ±500 µA or ±2.0 mA Variable Reference Clamp Voltage AFT Output With detent type tuners, the automatic fine tuning output can be used to directly control the tuner local oscillator varactor. The varactor control input must be high impedance in order to maintain high AFT loop gain with acceptable dynamic response. This output has a linear sink and source current range of 0 to 500 µA, and is digitally switched to ±2.0 mA for large frequency errors. The capacitor from Pin 11 to ground limits the bandwidth of the tuner local oscillator loop. Digital phase–locked loop tuning systems can also be controlled with the addition of a varactor diode used to shift the PLL reference oscillator. Refer to Figures 6, 24, and 25. AFT Mode Switch VCC VCC VCC 24 k 24 k 5.1 k AFT Mode Switch This input is used to activate the output of the AFT control amplifier that appears at Pin 11, and to select the control voltage polarity versus IF frequency. This feature allows the AFT output to work with all types of varactor tuned local oscillators. With the AFT Mode Switch input connected to VCC , Pin 11 is placed in a sourcing mode when the IF carrier frequency is below nominal. With the AFT Mode Switch input grounded, Pin 11 is placed in a sinking mode when the IF carrier frequency is below nominal. With the AFT Mode Switch input disconnected, Pin 11 is internally clamped to one half of VCC , refer to Figures 6 and 25. VCC VCCVCC RF AGC Output 10 k To Tuner AGC Input RF AGC Output This output is designed to control a reverse AGC tuner. As the antenna signal level increases, the voltage at Pin 13 decreases, causing a gain reduction in the tuner RF stage. An external pull–up resistor must be added if one is not provided in the tuner. Pin 13 is guaranteed to sink a minimum of 1.0 mA. Note that when operating with a tuner that requires in excess of 5.6 V, current will flow into Pin 13 due to conduction of the upper internal clamp diode.

21MOTOROLA ANALOG IC DEVICE DATA PIN FUNCTION DESCRIPTION (continued) Pin No. DescriptionEquivalent Internal Circuit

14 VCC

0.1 Horizontal Gating 2.0 V Video IF AGC Filter A capacitor connects from this pin to ground to control the video IF AGC rate of change with respect to a change in input signal level. An increase in input signal level causes an increase in the voltage at Pin 14 which controls the internal AGC action. Pin 14 has an unsymmetrical source and sink current of 150 µA and 8.0 µA respectively. The AGC filter voltage versus IF differential input signal level is shown in Figure 1. 6.2 k VCC 1.0 k 4.3 k RF AGC Delay From Pin 14 AGC Filter Voltage 0.01 VCC VCC Internal IF AGC RF AGC Delay A voltage applied to this input sets the video IF signal level threshold before gain reduction of the tuner begins. The threshold setting is tuner dependent but is usually in the range of 1.0 mV to 2.0 mV of signal at the antenna. Too low of a setting will cause premature tuner gain reduction and a poor picture and sound signal to noise ratio, while too high of a setting will cause tuner overload and picture distortion. The IF differential input signal level versus RF AGC takeover threshold is shown in Figure 2. 16Horizontal PLL Filter 0.05 0.68 1.5 k VCC VCC 0.4 mA 0.4 mA Horizontal PLL Filter This is a dual function pin. With the network shown, the horizontal phase–locked loop oscillator provides a keying pulse to properly gate the AGC when in PAL, SECAM, and NTSC modes. With Pin 16 grounded, both the AM and FM sound IF and detectors are inhibited. By placing Pin 3 in the Audio 2 mode, the variable audio output at Pin 27 is active and can be used to control the level of the externally processed digital sound. Refer to the description of Pin 3.

22 MOTOROLA ANALOG IC DEVICE DATA

PIN FUNCTION DESCRIPTION (continued) Pin No. DescriptionEquivalent Internal Circuit Flyback/Video Input17 0.02 VCC VCC From Negative Video Output Pin 5 Flyback/Video Input This input connects to a positive going sync source to generate an internal AGC keying pulse. An internal sync separator is provided for use in stand alone applications where a horizontal scan signal is unavailable. The sync separator allows direct use of the negative video output at Pin 5 to set the internal keying pulse. If horizontal scan circuitry is available, a positive going flyback pulse can be used instead to set the keying pulse. Lock Detector/Filter (Acquisition Circuit) VCC VCC 0.1 VCC 0 or ±80 µA 5.0 k 3.3 V 68 k Lock Detector/Filter (Acquisition Circuit) A filter capacitor for the acquisition circuit lock detector connects from this pin to ground. The capacitor voltage will vary upon signal presence and lock condition. Typical voltages are 2.7 V with the circuit unlocked and without any signal, 0.8 V to 4.3 V during signal acquisition, and 4.3 V when locked. Refer to the Acquisition Circuit Timing in Figure 25. PLL Filter (Main Loop)19 VCC VCC 3.9 V 220 0.10.01 VCC 22 k0 to ±160 µA PLL Filter (Main VCO Loop) A filter capacitor for the main phase–locked loop circuit connects from this pin to ground. The typical capacitor voltage is 3.2 V when locked and the circuit has reached the final static condition. Refer to Figure 5 for the PLL filter voltage versus carrier frequency change, and to Figure 25 for the acquisition circuit timing. 20, 21 VCC VCC C20C19 VCO CoilVCO Coil VCC 560L4 2120 4.7 k4.7 k VCO Coil These are the voltage controlled oscillator pins. Symmetrical tuning about the VCO frequency is provided by a bifiliar wound coil that resonates at one half of the desired IF frequency. The coil must be placed close to the IC pins to prevent any unwanted pickup or radiation. The printed circuit board layout must have short symmetrical traces with adequate grounding for the can shield. Capacitors C19 and C20 should not be less than 33 pF. Suggested component values for the major IF frequencies are listed in Table 3.

23MOTOROLA ANALOG IC DEVICE DATA PIN FUNCTION DESCRIPTION (continued) Pin No. DescriptionEquivalent Internal Circuit Gnd 22 Gnd This pin is the internal circuit ground. Care must be taken with the printed circuit board layout to provide a continuous sea of copper around the IC. VCC 5.5 k VCC Sound Input (AM) 23 From Ceramic Sound IF Filter at Pin 28 Sound Input (AM) This pin is the input of the AM IF. The intercarrier sound output at Pin 28 connects to this input through a ceramic bandpass filter. The AM detector is active in SECAM and NTSC modes. Refer to Table 2.

24 VCC

(Constant) 200 1.0 mA Audio Output (Constant) This is the constant audio output. The audio source is controlled by the mode selection of Pin 3. Refer to the description of Pin 3, and to Tables 1 and 2. 330 0.01 VCC 25

5.0 V VCC

This pin is the positive supply of the video/sound IF IC. The IC is functional over a minimum range of 4.75 V to 5.5 V and requires 100 mA. Operation from higher input voltages is possible with a preregulator. For optimum performance, it is recommended that circuit board layout contains dual power supply bypass capacitors with short leads connected directly to the VCC pin and ground. VCC VCC Sound Quadrature Coil (FM) 26 VCC VCC L3R28C25 Reactance Stage Representation Sound Quadrature Coil (FM) The sound quadrature tank components connect from this pin to VCC . The internal circuitry is designed to eliminate the time consuming alignment procedure by self tuning to the sound intercarrier frequency. This allows the use of economical fixed value components for a specific frequency or for a range of frequencies. The internal tuning capacitance that is placed across the tank ranges from 0.25 pF to 19 pF. Refer to Figures 9, 10, and Table 3 to select the proper component values for C25, R28, and L3.

24 MOTOROLA ANALOG IC DEVICE DATA

PIN FUNCTION DESCRIPTION (continued) Pin No. DescriptionEquivalent Internal Circuit

27 VCC

(Variable) 200 1.0 mA Audio Output (Variable) This is the variable audio output. The audio source is controlled by the mode selection of Pin 3, and audio level is controlled by a potentiometer connected to Pin 1. Refer to the description of Pin 3, Table 1, Table 2, and Figure 17.

28 VCC

1.0 mA 100 pF 2.0 k

0.001 To Sound Input

Pin 2 for FM, Pin 23 for AM Ceramic Bandpass Filter 1.0 k Intercarrier Sound Output This pin is the sound intercarrier output and is normally connected to either the AM or FM sound IF input through a bandpass filter. Because quadrature demodulation is used, the video level at this output is greatly suppressed.

Figure 28. Printed Circuit Board Evaluation Circuit

12 V R20

Table 3. Suggested Components Values for Figure 28

26 MOTOROLA ANALOG IC DEVICE DATA

Figure 29. Evaluation Circuit Board and Component Layout3.42”

27MOTOROLA ANALOG IC DEVICE DATA OUTLINE DIMENSIONS P SUFFIX PLASTIC PACKAGE CASE 710–02 ISSUE B DW SUFFIX PLASTIC PACKAGE CASE 751F–05 (SO–28L) ISSUE F NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. SEATING PLANE M A B K C N FG D H J L DIM MIN MAX MIN MAX INCHESMILLIMETERS A 36.45 37.21 1.435 1.465 B 13.72 14.22 0.540 0.560 C 3.94 5.08 0.155 0.200 D 0.36 0.56 0.014 0.022 F 1.02 1.52 0.040 0.060 G 2.54 BSC 0.100 BSC H 1.65 2.16 0.065 0.085 J 0.20 0.38 0.008 0.015 K 2.92 3.43 0.115 0.135 L 15.24 BSC 0.600 BSC M 0 15 0 15 N 0.51 1.02 0.020 0.040 /C0095/C0095/C0095/C0095 B SAM0.025 B SC M0.25 B M SEATING PLANE A NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM MIN MAX MILLIMETERS A 2.35 2.65 A1 0.13 0.29 B 0.35 0.49 C 0.23 0.32 D 17.80 18.05 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 L 0.41 0.90 /C0113 0 8 /C0095/C0095 L /C0113 C PIN 1 IDENT A B D E H e 0.10 C

28 MOTOROLA ANALOG IC DEVICE DATA

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