MC44250

MC44250 MOTOROLA | Alldatasheet

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MOTOROLA Order this document SEMICONDUCTOR TECHNICAL DATA by MC44250/0 —_ eee Advance Information Triple 8-Bit Video ADC _ a ~~ CMOS K S The MC44250 contains three independent parallel analog-to-digital flash ‘tae , <g FN SUFFIX converters (ADC). Each ADC consists of 256 latching comparators and an Nitec 44-LEAD PLCC encoder. Video may be ac or dc coupled. With ac coupling, input clamping CASE 777-02 provides for internal de restoration. The MC44250 also contains a dithering generator for video processing performance enhancements. The MC44250 is especially suitable as a front-end converter in TV-picture ORDERING INFORMATION digital processing (picture—in-picture, frame storage, etc.). The high speed MC44250FN PLCC conversion rate of the ADC is suitable for video bandwidth of well over 6 MHz. « 15 MHz Maximum Sampling Rate « Output Latching Minimizes Skew * Input Clamps Suitable for RGB and YUV Applications PIN ASSIGNMENT © Built-In Dither Generator with Subsequent Digital Correction = _ _ « Featured on the MC144000EVK PC Video Capture Evaluation Kit g A 8 = ¢ Single 5-Volt Power Supply SRBBALBAGBELS « Operating Temperature Range: - 40 to + 85°C. e7q7 . 39D lias cos 38 [] Vssir) IF CK DIAGR F ay whee SIMPLIFIED BLOCK DIAGRAM OF ONE OF THE ADCs ef 10 361] Root

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Yoo(r) Vggyp) Q 12 340 Rui G4 13 33) Rin Rrop @ [> os Q14 32] Rtop Ge 15 311] Voor) © o7 G16 30 1] VIN —> Ro (| 17 a9 Hz O72 8 72] DATA See eo$ E22 B= £ LS ¥ oT ReoT 7 Py CLOCK . ill bas ma ANALOG INPUT Lf 4 E ot tt | Hz MODE GENERATO! cs This document contains information on a new product. Specifications and information herein are subject to change without notice. OO _ le | DD & MOTOROLA © Motorola, Inc. 1995 REV1 195, Mm 6367253 0091650 cOT \\

ABSOLUTE MAXIMUM RATINGS* [Symons Vpp(A): VDD(D), | OC Supply Voltage (referenced to Vgg) -0.5t0+6.0 v Pormoge en [ese nemeewmnseyss eee a [ea [ocoupacwenrerra SCC * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the following Operating Ranges. ELECTRICAL CHARACTERISTICS (Voltages Referenced to Vgg) (VpD(R) = VoD(A) = VoD(0): Abias (Pin 39) = 5 k@2 to ground) OPERATING RANGES [smoot [ hin] Vpp(A). VD(0), | Power Supply Voltage Vv a [cow —[eaeosinmvoren a [cop [awison SSC SO a A/D CONVERTER a I TC SR SC CLOCK INPUT [spot [rn A RO i CO I 0 OR CO I i Sn [1 Jonecratine co e900, Fave MC44250 MOTOROLA ? @™ 6367253 0091651 L4b

| symoor [Characteristic | Min, Max unit | A [vu [zane tow tveivowge | || A A a * CLAMPING NETWORK (Measured on R, G, B Inputs) [| symoor | Characteristic Tin ST Max nit [sm [SarongSicurert 28 SO [Bg eenpne coronene Tt ————aicamp —[iamping eves Wax Devon Compareaiomabe | | to 188 | NOTES: 1. Unit “LSB” means ideal LSB (see definitions section). 2. “Difference” means difference between any two converters in the same package. RESISTIVE REFERENCE NETWORK es Se SO [zor [RropOupaimpemres Tm [toor [Roorountiemres OY RE MODE INPUT [symbot [Characteristic Min Max Unit a CC a CO [wiz [leoeeopertee ee a a [iz rest orenaoperuwer DATA OUTPUTS a SS [_s___[DeavronsanpieGonktovaisounnronee |e |e _*| Oe | [tor [ours Gurertavan=O4v Pe [ton [Oupusoucngcurenatvorsvoo-orv | oe [| ma | ae eh (Cy = 15 pF), Figure 1 MOTOROLA MC44250 mm 4367253 0091bS2 082 a 3

Figure 1. Clock and Output Timing

RESISTIVE REFERENCE NETWORK coincident with the horizontal syne of the composite video { Rtop (Pin 32) waveform for proper operation. Yin, Uin, and Vin may be | Rgot (Pin 34) used instead of the RGB signals. In this case the conversion Rip (Pin 36) will be a YUV analog-to-digital conversion. | Taps on the reference ladder are pinned out, providing Ibias (Pin 39) access to the bottom (RBOT). the top (RTOP), and the The comparator bias current is set by connecting an exter- middle scale points. These pins are intended for ac bypas- nal resistor between Ipiag and ground. The conversion rate is sing as ladder noise may present a problem. The value of the guaranteed for a resistor value of 5.1 kQ + 5% and will : decoupling capacitor should not exceed 47 nF Large capaci decrease logarithmically with increased resistance. The re- tance values can cause problems because of the amount o} sistor must be placed adjacent to the Ibias pin. No decoup- energy stored. When a system containing the MC-44250 is ling capacitor is allowed on this pin. rapidly powered down and up, the capacitor voltage may ex- ceed the supply voltage during the power up and cause a DIGITAL OUTPUTS latch-up condition. Failure to adequately decouple these J pins can adversely affect the conversion process. RO — R7 (Pins 17, 19-21, 24-27) { G0 — G7 (Pins 8-11, 13-16) i SUPPLY PINS BO -B7 (Pins 42-44, 1,3-5, 7) * i, These pins are the parallel output for the digital value for yooKa) tpinse. 18) the RGB signals. RO through R7 are the digital equivalent of Vv \\ ) Pin 31) the analog RED input, GO through G7 are equivalent to the | DIR) . GREEN input, and BO through B7 are equivalent to the BLUE j The three types of supply pins are analog, digital, and ref- input. If YUV analog signals have been input instead of the erence. The dc voltage applied to all four pins must be main- RGB signals the digital outputs will be YO through Y7, UO tained such that through U7 and VO through V7. : Vpp(A) = VDD(D) = VDD(R)- | Each pin must be carefully decoupled to ground as close DIGITAL INPUTS : to the package as possible, and particular care should be Clock (Pin 23) 1 taken with Vpp(R) as any noise present on this pin will ap- The analog input voltages to be converted are sensed at : pear in the output data as an equivalent input noise. This the falling edge of the clock signal and the corresponding noise will be present on the Rin, Gin and Bin input pins in a data is present on the digital outputs at the clock signal rising ratio of 1:1 to the input noise (worst case condition). Noise edge, 2.5 cycles later (see Figure 2). reduction can be improved by incorporating choke coil induc- HZ (Pin 29) tors in series with the power supply rails. This is the horizontal synchronization input, and is used to increment the dither generator. The clamp network is also ANALOG INPUTS controlled by HZ to ensure proper dc restoration for Rin, Gin Rin (Pin 33) and Bin before conversion. Gin (Pin 35) VTN (Pin 30) | Bin (Pin 37) The vertical synchronization input, VTN, resets the dither | The analog signals to be converted are input at these pins. generator after every second vertical sync pulse (after each | An on-chip clamp circuit for de restoration is available when frame). . using ac coupling. The clamp circuit operation is activated by MODE (Pin 41) the presence of the signal at the HZ input. This signal is This pin is used to select the proper clamp levels (see . derived from the composite sync information and must be Table 1). MOTOROLA MC44250 ma 4367253 009154 155 ml 5

Figure 5. Horizontal Timing tion between analog and digital forms. This method can also than a uniform luminance change. One solution is to increase the number of bits that describe rors on the screen. severity of this distortion depends on the number of digital play with less visible quantization. constant. When processing video information using 24—bits ering function is suppressed when input VTN is low. different luminance levels is reduced to 256. In cases where code may be $FE or $FF.

0.75 LSB

Figure 9. Dithering Sequence noted that the accuracy of the conversion process is re- as possible. Since the maximum value for Vop(R) is VDD. The step size is defined as SS(n) and the ideal step size is is the value that produces the greatest conversion accuracy. asow ing on the dither generator). the offset mismatch from one comparator to another and is ing on the dither generator). Since 9 is nearly independent of Vpp(R), its value will re- rect value of the input voltage. SSI = Vpp(R) x 0.6/255. saturation of about 3 V for Vpp = 5 V.

; OUTPUT ; CODE nv4 PF --- a ' | ! : n+2 pom | | i | \\ j | | i Lt ie I | | | ee | | ee ee es Vr (n) Vr (net) Vr (n42)| Vz (n43) Vin VM (n+3) : Figure 10. | © Transition Voltage: voltage at which transition from step © Step Size Ideal: 4 nto step n+1 occurs = VT(n). Vrani : ge _ 355 = SSI : * Step Size: Difference between two consecutive transition i voltages. © Differential Nonlinearity (DNL): SS(n) = Vz) — Vz(n - 1) DNL(n) = Vulr + 1) = Vil) + in tsp SSI ¢ Mid-Point Voltage: * Integral Nonlinearity (INL) and Offset: Vin) + Vzin = 1) Iyin) = M22? i ise n) + in n)=— in Vaal) = ri NL ssi Note: INL (min code) and INL (max code) is not defined. * Gain: — Gain =a in the formula Y = a e code +b Vv + Vz(max code — 1) or the slope in the curve mid-points = f(code) Vmax code) = DD(R) © M 2 * Vottset? Voffset = 6 — Vmin SSS MOTOROLA MC44250 wm 6367253 OOTLEE0 159 a "

APPLICATION INFORMATION

PCB DESIGN be superimposed on the analog signal as unwanted noise. At To maximize the performance of the MC44250, noise worst, it can render the entire circuit unusable. Even the digi- should be kept to a minimum. Good printed circuit board de- tal signal path is not immune to this type of signal. It can false sign will enhance the operation of the MC44250. Separate trigger clock circuits causing timing errors, confuse compara- analog and digital grounds will reduce noise and conversion tor type circuits, and cause digital signals to be misinter- errors. In addition, separate filters on analog Vcc and digital preted as wrong values. Vpp will also help to minimize noise and conversion errors. When laying out the PCB, use electrolytic capacitors of Sufficient decoupling and short leads will also improve per- sufficient size at the power input to the printed circuit board. : formance. Adding low ESR decoupling capacitors of about 0.1 FF ca- When designing mixed analog/digital printed circuit pacitance across Vcc and/or Vpp at each device will help boards, separate ground planes for digital ground and analog reduce noise in general and ESD susceptibility. Implementa- | ground should be employed. Large switching currents gener- tion of a good ground plane ground system can all but elimi- ‘ ated by digital circuits will be amplified by analog circuitry nate the type of noise described above. : and can quickly make a circuit unusable. Care should be tak- To summarize, use sufficient electrolytic capacitor filtering, en to ensure analog ground does not inadvertently become make separate ground planes for analog ground and digital part of the digital ground. The analog and digital grounds ground, tie these grounds together at one and only one point, should be connected together at only one point. This is usu- keep the ground planes as continuous and unbroken as pos- ally at or near where power enters the printed circuit board sible, use low ESR capacitors of about 0.1 uF capacitance ; Additionally, when interconnecting several printed circuit on Vcc and Vpp at each device, and keep all leads as short boards together, care must be taken to ensure that cabling as possible. does not interconnect digital and analog grounds together to ; produce a path for digital switching currents through analog EMI SUPRESSION ° ground. When using ICs in or near television receiver circuits, EMI i] When using any device with the performance and speed of (electromagnetic interference) and subsequent unwanted the MC44250, ground planes are essential. Loosely inter- display artifacts and distortion are probable unless adequate connected traces and/or random areas of ground strewn EMI suppression is implemented. A common misconception around the printed circuit board are inadequate for high per- is that some offending digital device is the culprit. This is er- formance circuitry. While distribution of Vpp and Vcc can roneous in that an IC itself has insufficient surface area to be done by bussing, to do so with the ground system is di- produce sufficient radiation. The device, while it is the gener- sastrous, ator of interfering signals, must be coupled to an antenna be- An inch long conductor is an 18 nH inductor. The cross fore EMI is radiated. The source for the EMI is not the IC sectional area of the conductor affects the exact value of the which generates the offending signals but rather the circuitry inductance, but for most PCB traces this is approximately which is attached to the IC. correct. If the ground system is composed of traces or Potential EMI signals are generated by al digital devices. clumps of ground loosely interconnected, it will be inductive. Whether they become a nuisance is dependent upon their The amount of inductance will be proportional to the length of frequency and whether they have a sufficient antenna. The the conductors making up the ground. This inductance can- frequency and number of these signals is affected by both not be decoupled away. It must be designed out. circuit design within the IC and the manufacturing process. ACMOS device exhibits a characteristic input capacitance Device speed is also a major contributor of potential EMI. Be- of about 10 pF. If this gate is driven by a digital signal that cause the design is determined by the anticipated applica- switches 2.5 V in a period of 5 ns, the equation for the aver- tion, the manufacturing process is fixed and the drive for age current flowing during the switching time will be: speed ever increasing, the only effective point to implement ! lay = Cavidt. EMI suppression is in the PC board design. The PC board usually is the antenna which radiates the EMI. The most effi- A voltage change of 2.5 V in 5 ns requires an average cur- cient method of minimizing EMI radiation is to minimize the rent of 5 mA. If we assume a linear ramp starting from zero, efficiency of this antenna. | the total change in current will be 10 mA. The change in cur- The most common cause of inadequate EMI suppression . rent per nanosecond per gate can be found by dividing the lies with the ground system of the suspected digital devices. | change in current by the time As pointed out previously, di/dt transitions can be significant | 10 mA/5 ns = 2 mA/ns. in digital circuits. If the di/dt transitions appear in the ground ‘ system and the ground system is inductive, the harmonics For a device with 16 outputs driving one gate for each out- present in these transtions are a source of potential EMI sig- Put, nals. The unfortunate result of putting digital devices on a di/dt = 16 x 2 mA/ns = 32 mA/ns. reactive ground system is guaranteed EMI problems. If the above 1-inch wire is in this current path, then the The area which should be addressed first as a potential voltage dropped across it can be found from the formula EMI source is the ground. Without an adequate ground sys- . tem, EMI cannot be effectively reduced by decoupling. If at V = Ldi/dt = 18 nH x 32 mA/ns = 0.576 V. all possible, the ground should be a complete unbroken If the inductor is in the ground system, it is in the signal plane. Figure 13 shows two examples of relieving ground path. The voltage generated by the switching currents around device pins. When relieving vias and plated through through this inductor will be added to the signal. At best it will holes, large areas of ground loss should be avoided. When MOTOROLA MC44250 @® =6367253 O09lbb2 T2l 8

the relief pattern is equal to half the distance between pins, rest of the ground system. Next choose a ferrite bead of the over—etching and process errors may remove ground be- appropriate value. Install this bead between the isolated tween pins. If sufficient ground around enough pins is re- ground and the ground system. Install low pass filters in all moved, the ground system can become isolated or nearly ‘suspect lines with the capacitor closest to the device pin con- isolated “patches” which will appear inductive. If ground, nected to the isolated ground in all signa! lines where EMI is such as the vicinity of an IC, must be removed, replace with suspect. Also cut the power to the device and insert a ferrite accross hatch of ground lines with the mesh as small as pos- bead as shown in Figure 14. Finally, decouple the device be- sible, tween the power pin(s) and isolated ground pin(s) using a If a single unbroken plane can be devoted to the ground low inductive/resistive capacitor of adequate value. system, EMI can usually be sufficiently suppressed by using The methods described above will work acceptably when ferrite beads on suspect EMI paths and decoupling with ade- the EMI frequency and the frequency of operation of the de- quate values of capacitors. The value of the decoupling ca- __—Vice generating the EMI differ greatly. Where the EMI is dis- pacitor depends on the frequency and amplitude of the turbing the high VHF or UHF channels and the device offending signals. Ferrite beads are available in a wide vari- generating the EMI is operating within the NTSC/PAL band- ety of shape, size and material to fit virtually any application. width, the energy contained in the harmonics generating the Choose a ferrite bead for desired impedance at the de- EMI is situated well above the operating frequency and sired frequency and construct a low pass filter using one or suppressing this type of EMI poses no great problem. How- more appropriate capacitors in a"L”, “T” or “PI” arrangement. ever, if the EMI is Present ‘on low VHF channels and/or the Use only capacitors of low inductive and resistive properties operation of the device is outside the NTSC/PAL bandwidth, such as ceramic or mica. Install filters in series with each IC -—-SUCN’ 8 a 2X pixel clock or 4xfsc oscillator, compromise be- ' ae . tween video quality and suppression complexity is usually re- pin suspected of contributing offending EMI signals and as quired to obtain an acceptable solution. For those cases close to the pin as Possible. Analysis using a spectrum ana- where the operating frequency of the device is very near the lyzer can help determine which pins are suspect. frequency of the EMI disturbance, careful attention to PCB Where PC board costs constrain the number of layers layout, multiple layer PCB and even shielding may be neces- available, and if the EMI frequencies are far removed from sary to obtain an acceptable design. the frequencies of operation, ferrite beads and decoupling capacitors may still be effective in reducing EMI emissions. APPLICATIONS CIRCUIT Where only two (or in some cases, only one!) layer is used, Figure 15 shows a typical applications circuit. This circuit the ground system is always reactive and poses an EMI will produce analog-to-digital conversion of either RGB in- problem. If the offending EMI and normal operating frequen- formation or YUV information by setting SW1. In the YUV cy differ sufficiently, filtering can still work mode, SW1 is set either to position ’1’ or to the open position An “island” is constructed in the ground system for the digi- depending on the desired clamp level (see Table 1). The tal device using ferrite beads and decoupling capacitors as RGB inputs then become YUV inputs and correspondingly, shown by the example in Figure 14. The ground must be cut the RGB outputs are YUV. For RGB operation, SW1 is set to so that the digital ground for the device is isolated from the the '0' position. MC44250 MOTOROLA 14 qm 6367253 0091663 966 mm

! fe) [| WRONG BETTER . Figure 13. r FERRITE BEAD [O [O] POWER [| [) | | [new OR (6) = FERRITE BEAD OUTPUT « /O | 0.1 pF DECOUPLING [O ol row pass | ul FILTER ! | | | [0] [O}! \\ | — GROUND (9) cuT Y FERRITE BEAD Figure 14. MOTOROLA mcaa250 @™@ = 6367253 OO9lbb4 oT mm

Figure 15. Application Circuit

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