MC44130P

Motorola, Inc

SYSTEM 4 STEREOTONE SINGLE CHIP TV SOUND CONTROL

Manufacturer: Motorola, Inc

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2 SEMICONDUCTOR See

System 4 Stereotone MC44130 Single Chip TV Sound Control P SUFFIX The Motorola MC44130 CMOS device provides, ona single chip, the sound ais vce e system of the advanced TV SYSTEM 4. It has all the necessary functions for sound control required in a TV receiver for NICAM and SECAM as wellas for - the reception of stereo sound in German TV “standard transmission mode”. tit, —< ye —<_ ai MAIN FEATURES: DAT Vy

28 Y Y

Part of Motorola System 4. 1 © Fully controlled through IIC Bus. * Accepts base band dual carrier signals or NICAM decoded signals or SECAM decoded signals. : a PIN ASSIGNMENT * “Pilot tone” demodulation and identification. ¢ Mono, Stereo and Dual Language processing. anacno 1 @ 281] voo * Maximum Stereo separation control. KeQ2 272 osc. * Volume, Treble and Bass control. «3 261) ose.c * Special effects: pseudo and extra wide stereo. wonow 25}] vss SCARTINL [] 5. 24) iser ¢ Mute and separate power-on reset mute. scart ina []6 23/] reset | * Loudspeaker, Headphone, Hifi outputs. scant our []7 22{) test © Independent left/right Volume Control on Loudspeaker and Headphone scart ourn 8 21f] pata outputs. tec 9 20] vss ter (10 19/1] cLock © Peripheral (SCART) input/output. HeIL(} 11 1efisr © Mono Recorder Drive Capability. wiFiR O12 17D ist anacno [] 13 16[) HP anavss [] 14 15[] HPL

ORDERING INFORMATION

a (SY MOTOROLA = © MOTOROLA LTD,, 1990

Baseband stereo signal decoding.
Direct Balance adjustment via software (set-up).

¢ Loudspeaker output control (tone, extra effects, independent left/right volume control). © Headphone output control (independent left/right volume control). Re-creation of MONO output on SCART for Mono recorders. Figure 1. Block diagram

Rating | Symbol | Value Unit DC supply voltage Vop 0.5 to 15 Vv Operating Temperature range Ty 0 to 70 °c Storage Temperature Tstg | -40 to +125 °c

ELECTRICAL CHARACTERISTICS

All tests used the circuit in Figure 2. The following conditions are assumed, unless stated otherwise. - 1% accuracy resistors; resonator Murata CSB437F2 (fs=427 kHz, fp=464 kHz, Cstat at 1 kHz = 630 pF, Rs= 30 Q); Vpp = 12 V, Ta = 25°C. - Va amplitude is 500 mV rms, Va frequency is 1 kHz, Vr amplitude is 400 mV pp, Vr frequency is 1 kHz, Vp frequency is 54.6875 kHz with or without amplitude modulation. — Values for subaddress, data and read bits are stated as hexadecimals. — Treble/Bass: flat = subaddress 05 data 88. - Volumes HP & LS: Maximum = subaddress 01, 02, 03, 04 data 00. - K1, K2 Set-up: Mid range = subaddress 00, 07 data 20. - Demute, matrix option 00, no special effects = subaddress 06 data 00. - When switches are not mentioned, they are considered to be OFF. ~ Pin 22 is not connected or is connected to Pin 20. 8K 330nF si 2 2 md ToF i} vpD $3 . $5 way, $6 an vp 1 x ew) 2enF I oO «= ole vR ° (se) ow tot 5k bo F 3 4 > St eda 0.01% SSK 330nF bo es Glitch vA 3 ‘=: cor Nien $2 SK 330nF 16 i CY rte 5 " 2k 43% ; 330nF ‘ »E4 5 sk “ 220, amr |e » {1 100nF a an 100nF ud = FS. Figure 2. Device under test

Left and right outputs may be balanced at any level to within half the step size by independent control of left/right attenuators. HEADPHONE (See figures 6 and 7) For these volume control tests, left and right channels are at the same setting. Subaddress 06 data 01, S2 = 4. [heretics [Svmba] Pn [Tost Condtions «(in| Typ | Mox | Unis | Step size from step 0 HPSS |5, 15, | Subaddr. 03,04 Data n — Voutin) i) 25 4.0 dB to step 25 (understood 16 | Subaddr. 03,04 Data n+1 — Vout(n+1) as decimal values) HPSS=I20 log (Vout(n)WVout(n+1))! Depth from step 0 HPDP |5, 15, | Subaddr. 03,04 Data 00 — Vout(00) 55 60 70 dB to step 25 16 | Subaddr. 03,04 Data 19 — Vout(19) HPDP=120 log (Vout(0)/Vout(19))I Depth at step 30 HPDP {5, 15, | Subaddr. 03,04 Data 1E — Vout(1E) 60 dB 16 | HPDP=120 log (Vout(0)/Vout(1E))I dB 0+3

40 PEE TITLE: erate Sect sor]

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Figure 6: HP volume control dqB 0 +4 eso SENET TTT TTT ror traric Gprions: [| [ 20 HTTPS TTT TTT 80s. 808.$04.507.$08, | oo LHITTTTNS TTT TTT fs0c.ser saz. stc st | woo HUTT PNET TT so HITT PNT co SHUT PTT TTT oo HUTT TTS eon TTT eo HTT RTT oo LUTTE TTT ign WITT] 0 5 10 15 20 25 30 35 step Figure 7: HP volume control De MOTOROLA MC44130/D

LOUDSPEAKER (see figures 8 and 9) For these volume control tests, left and right channels are at the same setting. Subaddress 06 data 01, S2 = 5. [cherectrstcn [Symbol] Fin [Tet Condhone «| Min Twp | Max | Unie | Step size from step 0 LSSS | 6, 17,] Subaddr. 01,02 Data n > Vout(n) 0 1.25 | 25 dB to step 50 (understood 18 | Subaddr. 01,02 Data n+1 —> Vout(n+1) as decimal values) LSSS=120 log (Vout(n)Voutin+1))I Depth from step 0 LSDL | 6, 17,| Subaddr. 01,02 Data 32 > Vout(32) 55 60 70 dB to step 50 18 | LSDL=I20 log (Vout(0)Wout(32))! j Depth at step 62 LSDL | 6, 17,| Subaddr. 01,02 Data 3E — Vout(3E) | 18 | LSDL=I20 log (Vout(0)Vout(3E))! 65 dB dB 045

40 PRETTY TT et ars corer |

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30 ALI 0D, S0E

vo LUTTE PTT sak sae. 40 ~s so HUTT PTT oo SHUT TST TTT vo HUTT TT eo LLU 0 10 20 30 40 50 60 70 step Figure 8: LS volume control dB 0 +5 ero FEAT TT TTT TTT Teer tate Options: | [| 20 LT TPTTTT TTT TTT |so0.s08,soc.sec. | 1)

30 LUT PWT

-60 HEHE epee oe tH 7o HUTT PSST

20 PPE EE ETT PTE

-oo LUTTE TTT [) 10 20 30 40 50 60 70 step Figure 9: LS volume control Mc44130/D MOTOROLA

K1, K2 SET-UP CONTROL (see figures 10 and 11) $2=2, S3=ON, S4=ON; Vout is measured on pins 7 and 8 for K1 and K2, respectively. This set-up control may also be used to equalise gains in dual language mode. [Gharacincs [Symbol Pn [Tet Cndios ‘(| Min [Tw | Max | Unie | Control range SUD | 2,3,7} Subaddr. 06, data: 05 8 | Subaddr. 00, 07, data: 3E, Vout(3E) Subaddr. 00, 07, data: 00, Vout(00) SUD = 120 log(Vout(3E)/Vout(00))! 3.5 45 dB | Stop size k2 SSK2 | 23 | Subaddr. 06, data: 05 Step size K1 SSK1 | 2,3 | Subadadr. 06, data: 05 | 7 | Subaddr. 00, data: 00, 02 ... 3E 0) 02 4B | Stereo separation set-up | SUSM | 2,3,7,| Subaddr. 06, data: 00 at K1/K2 mid. 8 | Subaddr. 00, 07, data: 20 VoutL on pin 7, VoutR on pin 8 | SUSM= 120 log(VoutL(20)MVoutR(20))! 20 40 dB | Stereo separation set-up | SUSO | 2,3,7,| Subaddr. 06, data: 00 optimized 8 | Subaddr. 00, data: 20 | Subaddr. 07, data: n | SUSO= 120 log(VoutL(n)/VoutR(20))! 40 50 dB dB dB 3.5 ee a a 3.5 2 3-E ki te SCART LTT} + 3 k2 to SCART R-+++ | + 4 | 2.8 © Referenced to input signal ttt 2.5 + Referenced to input signal p44 —|-| |_|

2 Matrix Option : 05+ + yet 1 1 2 Matrix Option : 08 | | +

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0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 step step Figure 10: K1 set-up control Figure 11: K2 set-up control a MOTOROLA MC44130/D

DE-EMPHASIS. De-emphasis 2,3,7| Vp=50 mV rms, S1=ON, S2=1,2, 8 | S4=ON, S5=ON. Subaddr. 06, data: 05, Vout measured on pin 7,8. DMP= 120 log (Vout(200Hz)/ Vout(1 0kHz))I 10.3*| 10.8 * Corresponding to 50ps time constant (+/-7%; 46.5ps, 53.5ys) TREBLE/BASS (See figures 12 and 13) Subaddress 06, Data = 01, S2 = 5. Flat condition definition = Subaddress 05, data = 88 — Voutf Flat condition variation BSSL From 100Hz to 10kHz 2 dB Treble & bass range Range at 100 Hz BRH | 17,18) BRH= 20 log (Vout(8E)/Vout f) - max bass +13 +16 | +19 dB | BRL | 17,18] BRL= | 20 log (Vout(81)Vout f) > min bass 19 | 16 | -13 a | Range at 10 kHz TRH | 17,18] TRH= | | 20 log (Vout(E8)/Vout f) +» max Treble | +13 | +16 | +19 dB | | TRL | 17,18] TRL= | 20 log (Vout(18)Vout f) > min Treble | -19 | -16 | -13 dB Maximum deviation DEV Treble and bass min...max 4 4 dB at 1 kHz related to | flat condition | i | Step size STZ Except for the 2 first and 2 last steps 0 - | 4 dB & Referenced to input signal & Referenced to input signal TB Matrix Option : oof fF AH LEEK Matrix Option : ooff = FTTH

10 CS i Fa io CTR 1)

5 OITA TTT Th 5 OTA TT

[CCIE SAT A are) ITS A TT o +S SSSA ee o HOTS SS ae CCT Sec — | | TTT) [TSS — | TTI

5 OSes — TT 65 OSS ee TT

Le NSS TT [NS TTT 0 +a N NES Te ao ait ANNI OT TTT AA ORAS TO [RAST ONES as Hr AAT NNT as RAAT NIN TT ee ZA om) ZA 20 +S 20 + NS a A a a -o5 LCI TTT py -o5 LCT nT py. 10 100 1000 10000 100000 10 100 1000 10000 100000 Figure 12: Treble/Bass Left Figure 13: Treble/Bass Right MC44130/D MOTOROLA

SPECIAL EFFECTS S2 = 4 PSEUDO-STEREO [‘Gharactontes [Symbol] Fin | Tost Condvone ‘| Min | Tw | Wax | Units | Frequency for 180° FREO | 5, 17,| Subaddr. 06 data 22 phase shift 18 | Input frequency Va for phase shift of 180° between Vout on pin 17,18 1.25 14 kHz respectively. Amplitude PSA | 5,18 | Subaddr. 06 Data 02 : VoutN Subaddr. 06 Data 22 : VoutPS 0.1 06 dB PSA=20 log (VoutPS/VoutN)! VARI For frequencies up to 15 kHz 3.0 dB Extra-wide Subaddr. 06 Data 00 Subaddr. 06 Data 10 *Fva=300Hz *Fva=300 Hz -$2=4 output pin 17 : V300NL -S2=4 output pin 18 : VhpLR -S2=5 output pin 18 : VZ00NR -S2=5 output pin 17 : VApRL *Fva=1kHz *Pva=1kHz -S2=4 output pin 17 : VoutNL -S2=4 output pin 17 : Vout LL -S2=5 output pin 18 : VoutNR -S2=4 output pin 18 : VoutLR -S2=5 output pin 17 : VoutRL -82=5 output pin 18 : VoutRR [Gherecternice [Symbol] Pin | Test Conditions Win | Typ | Max | Unit | Direct Gain left LLA 5,6 | LLA=(VoutLL/VoutNL)x100 110 120 | 130 % 17,18 | Direct Gain Right RRB 5,6 | RRB=(VoutRR/VoutNR)x100 110 120 | 130 % | Left to Right CC LRC 5,6 | LRC=(VoutNRxVoutLR) 48 54 60 % { 17,18} x100/(VoutNLxVoutRR) | Right to Left CC RLD 5,6 | RLD=(VoutNLxVoutRL) 48 54 60 % 17,18] x100/(VoutNRxVoutLL) High Pass filter HLPR | 5,6 | HLPR=20log((VoutLRxV300NL)/ 28 3.2 36 dB 17,18} (VoutNLxVhpLR)) High Pass filter HPRL | 5,6 | HPRL=20log((VoutRLxV300NR)/ 28 3.2 3.6 dB 17,18| (VoutNRxVhpRL)) MOTOROLA MC44130/D

Extra-wide and pseudo-stereo Fva = 1kHz; Subaddr. 06 Data 00, S2=4, output on pin 17:VspNL, $2=5, output on pin 18:VspNR Subaddr. 06 Data 30, S2=4, output on pin 17 : VspLL and output on pin 18 : VspLR $2=5, output on pin 17 : VspRL and output on pin 18 : VspRR [ Characteriics [Symbol] Pin [Test Conditions [ Min [Typ | Mx | Unit | Left to Right CC} LRBT |5,6,17,18 | LRBT=100(VspNRxVspLR)/(VspNLxVspRR) 37 42 % Right to Left CC} RLBT | 5,6,17,18 | RLBT=100(VspNLxVspRL)/(VspNRxVspLL) 37 | 42 % Insertion gain/loss LIO is defined by LIO = 20 log (VoutVin). For matrix options 00 to 04, S2=2,4,5 and S3=ON, S4=ON. For matrix options 05 to OF, S2=1,2,4,5, S4=ON. For matrix options 47 to 4F, S2=3,4,5. See also Table 1. Insertion KVK2 oe Gainfloss uo 23 (+) | Matrix options=03, 04,05,06,08. | 11,12 HIFI 4 3 | a8 | | 17,18 Ls 3 1 | @B i 15,16 HP 3 1 dB | Matrix options = 07, OF | | | i | 11,12 HIFI 2 ; 2 | 6B | 17.18 us ES lai ap | | |

15.16 HP 4 0 dB |

All matrix options (00 to OF) | |

78 SCART 3 | aB |

| AM | 4 | Mono | | | 11,12 HIFI_ (matrix option=47,4F) | 4 0 |B |

17.18 LS (matrix option=47,4F) | 7 | 3 | 0B |

| Cherecteristics [Symbol] Pin | Test Conditions | Min. Typ | Max | Units | Analog Ground VAGD | 1,13 | Vpin28=Vdd=12V | Polarisation * Vpin14=Vpin20=Vpin25=Vss=0V 5 6 7 Vv | Pin 1 and Pin 13 have to be connected | together. Input Output VPOL | 2,3,4| Force VAGD = Vdd/2 on pin 1 and pin 5 6 7 Vv j Polarisation * 5,6 | 13 and measure VPOL(n) on each | 7,8 | input and output pin. | 11,12 15,16 17,18 Input and Output Force pins 1 and 13 to VAGD = Vdd/2 Impedance * Force tested pin to VPOL(n) -0.1 V and measure the source current K(n) : IKR 2,3 | IKRin) = 0.1/K(n) 25 kQ IR 45,6] IR(n) = 0.1/Kin) 150 kQ | ors | 7.8 | ORSin)=0.1/K(n) except for matrix 03 1 Ka | and OB. | ORA | 11,12} ORA(n)=0.1/Kin) 200 Q | 15,16 “ . 200 Q | 17,18 " . 200 Q Noise NKST 7,8 | S5=ON, Bandwidth 20Hz-15 kHz 150 : uV rms 11,12] Matrix option Stereo | 15,16] Input K1 or K2 NKDM | 17,18] Matrix option Dual or Mono or Nicam 120 - pV rms stereo Input K1 or K2 NLMS Output LS 90 - | pVims Input Mono or SCART | NOMS Output SCART & Input Mono or 60, - BV rms | Output HiFi/HP & Inputs Mono/SCART | | NVCT Output LS -voletrl step 24 5 - | pVrms | Output HP volctrl step 12 PSRR PSRR |15,16,) S6=ON, Vout measured on each | | | Power Supply 17,18) output PSRR = 20 log (Vout/Vr) | Rejection 28 | For LS outputs 410 | -12 | dB - For other outputs 30 | 0 | | 4B | | * This test measurement is done directly on the device without any external wiring and hardware, apart from a short circuit between pins 1 and 13 Note: output drive capability, when using the application circuit of Figure 16, is 1Vpp on 10 kQ for all outputs. MC44130/D MOTOROLA

indicating Stereo or Dual language transmission. Figure 14. Pilot tone decoding Pins 2 and 3 are inputs for the two baseband signals K1 and K2 recovered by external demodulators. K1 contains. language for dual sound) plus pilot tone. If mono transmission occurs, it is received on K1. (typically AM for L-transmission system) directly into the switching matrix without de-emphasis. (50ps time constant) by independent networks, and fed to the switching matrix for routing.

are directly routed to the switching matrix. to one or more of the outputs. Selection is achieved by means of the IIC Bus interface. be routed to loudspeakers and/or headphones, while another SCART can record the broadcast in progress. Table 1. SWITCHING MATRIX

L &Rare the left/right channel information of a stereo transmission.

Mn signifies an amplitude modulated signal without preaccentuation.

1 If the ID. CODE is “11”, this option can also be accepted.

2 M* is the de-emphasized signal of K1, generated in this way:

in a future design, they may route K2 to all outputs.

4 Withc=d=0

Figure 15. Input/Output Combinations

Treble and bass are controlled in 14 steps from min. to max. using a 4-bit word for each. Signal alterations are identical on both channels and are realized by variable switched capacitor filters providing very low characteristic dispersion. Volume Control Volume control is realized by two independent attenuators controlled by two 6-bit words, one for the left channel and one for the right. This gives up to 50 equal control steps which is sufficiently fine to sound like a smooth continuous analog control. A balance control is easily implemented by altering, via software control, the left and right channel data. Pseudo Stereo Upon a one-bit control this function is either “on” or “off”. The effect is to create, from a mono signal, an apparent stereo effect by altering the signals. The left channel is the original mono signal, while the right channel is amono signal to which is added a frequency dependent time delay (2 poles delay with asymptotes to 627s at DC; the phase shift is nearly 180° at 1kHz) Extra-wide Stereo Upon a one-bit control this function is also either “on” or “off”. It causes an apparent increase of the stereo separation using the technique of cross coupling the left and right channels in antiphase. Since a zero separation (mono) input signal would be entirely cancelled in each channel, it is necessary to limit the percentage of cross coupling (60%) and increase the channel gain to prevent a change in volume. When sourced with pseudo-stereo operation, the cross coupling is reduced to 40%. Low frequency feedback is rolled off. HEADPHONE OUTPUT This route has independent volume controls realized in the same manner as for the loudspeaker output, but the dynamic range is performed with 31 steps (5-bit words) SCART OUTPUT Asshown in table 1, SCART output may receive left or right channel information when stereo transmission occurs, or to support mono recorders, a re-constructed de-emphasized mono signal. In dual mode transmission it can be switched to both languages. Note that the SCART input cannot be routed to the SCART output. MUTE All three input pins (K1 - K2 - mono) have muting gates which are controlled by the bus (Mute 1) (see Figure 15). All four output routes (loudspeakers, headphones, SCART, HIFI) also have muting gates (Mute 2) which are operated by the reset pin as follows: * to enable mute 2: reset the power or, during normal operation, make reset pin (23) = low. * to remove mute 2: let reset pin go high and address the chip through the bus. Demuting occurs with the first start or stop condition on the IIC Bus which follows a Chipaddress + Subaddress. Demuting should not occur until the reset pin is high, i.e. after about 100ms. We recommend addressing and loading all registers before demuting Mute 2. Note that SCART input is not muted. a MC44130/D MOTOROLA

The Stereotone I.C. is digitally controlled by using the MOTOROLA two wire serial bus (!1C compatible). A simple description is given in appendix A, with emphasis on the word structure. The MOTOROLA Bus electrical specification is given in Figure 19. Details of the Stereotone Bus operation are as follows: * The chip address is 1 000 000 Y, where Y is read/write bit (R/W). * There are 8 subaddresses available to control volumes, treble-bass, set-up and decoder- de-emphasis switching, and to select switching matrix options © Two flag bits representing the actual sound mode can be read by the master. Table 2 shows function subaddresses and data definitions. Some communication protocols to be used follow. Table 2: STEREOTONE M-Bus Protocol (Note: X = Don't care) Level Set-up K1 XXXXX000 | (Note 1) Decoder & Deemphasis switch { Level Set-up K2 XXXXX111 XX000000<= gain => XX111111 Volume, left speaker XXXXX001 XX000000<= volume =>XX111111 (Note 2) Volume, right speaker XXXXX010. XX000000<= volume =>XX111111 (Note 2) Volume, left headphone XXXXX011 | XX000000<= volume =>XX111111 (Note 2) Volume, right headphone XXXXX100 XX000000<= volume =>XX111111 (Note 2) Treble/Bass XXXXX101 | 0001 XXXX<= treble =>1110XXXX XXXX0001<= bass =>XXXX1110 Flat response 10001000 Selection matrix XXXXX110 Mute 1 : 1XXXXXXX + Special Effects | Not muted 1: OXXXXXXX Special Effects XX0OXXXX No special effect XX10XXXX Pseudo stereo XX01XXXX Extra-wide stereo XX11XXXX Both effects Matrix Select | XbxXXefgh (See Table 1) Note 1: Level set-up K1 + decoder & de-emphasis data XX12345Y, a 6-bit word. The word XX00000Y corresponds to minimum gain (0.707x). The word XX10000Y corresponds to midrange gain (1.0x) The word XX11111Y corresponds to maximum gain (1.414x) IMPORTANT: bit Y = 0 switches ON decoder & de-emphasis; bit Y = 1 switches it OFF. Note 2: Performance is guaranteed only between: XX000000 and XX110010 for LS XX000000 and XXX11001 for HP See also Figures 16 to 19. ee MOTOROLA MC44130/D

-Write one Byte STA Chip Address Ack Sub-address | Ack Data Ack sto IILIHT10 | (See Note 3) | III HE STA Note 3: The acknowledge flag is composed of one bit, and is generated by the MC44130, which pulls down the data line during one clock pulse (see Appendix A). -Write N Bytes STA | Chip addr. | Ack) Sub-addr. Ack} Data 1 Ack} Sub-addr. Ack | Data 2 Ack| STO _ HILO Ht Hitt Hutt HT STA - Read Status Byte Ack. for byte if STA | Chip addr. | Ack] Data In sTO HEE VELLEEEL | STA — With X Y 0 0 MONO 0 1. STEREO x Y 1 0 DUAL LANGUAGE APPLICATION The MC 44130 has been designed to offer many high performance features and to realize maximum component and board savings for TV receivers. The typical application circuit is very simple as per Figure 16. Software Considerations The stereotone I.C. can be driven with great flexibility. Its internal registers are purely static and therefore updating can be realized at any rate. Software Functions The balance function is easily achieved by modifying the left and right volume control registers in opposite directions. Specific total volume compensation can be realized by special software using the TV set's non-volatile memory to store normalized balance if the user’s ears are not equally sensitive. Loudness control, boosting bass and treble when volume is low can be realized, upon fixed or variable patterns, by software relationships between volume and tone control words. Pilot tone status display: as this data is permanently read by the MCU, software can easily make the latter drive the TV set's LED display; therefore there is no need for the Stereotone to drive any further LED to provide the viewer with this data. Asimple filtering program can be added to the currently used software program to improve identification when the signal delivered to inputs K1/K2 is very noisy. a MC44130/D MOTOROLA

25 Analo:

Figure 16. Typical Stereotone application

This two wire serial bus system consists of the data line (DATA) and the clock line (CLOCK).

One line is called SDA and carries the Data.
One line is called SCL and carries the clock.

drain (or collector) in order to perform the wired-AND property. a transmission, the most significant bit is transmitted first.

Start and Stop conditions

A high to low transition of the SDA line, while SCL is high, is a unique situation defined as the Start condition. A low to high transition of the SDA line, while SCL is high, is a unique situation defined as the Stop condition. Every receiver must reset its Bus logic on the reception of a Start condition. (See Figure 17). Figure 17. Start/Stop conditions

clock timing, start and stop conditions must be generated by a master, normally an MPU. Each byte is followed by one acknowledge bit. During an acknowledge bit the master lets the data line go high. that the SDA line is stable low during the high period of the acknowledge related clock pulse. to generate a Stop condition. period” which does not correspond to a bit dedicated data transmission (7th & 8th bit). Data transfer is effected in 9-bit words (see Figure 18). The Start condition can be seen first, it causes all receivers on the Bus to reset. to transmit data and “1” if it intends to receive data. The 7-bit address is a property of the slave.

1 Laas --4 '

Figure 18. Data transfer on the Bus

addressed and is ready to receive or transmit data as appropriate. Now, the address byte is followed by one or more subadress data bytes (MSB first), from the transmitting |.C. Finally the stop condition is generated by the master at the end of each data transfer. Note that a stop condition is not required to let data transmission restart. For Motorola Bus electrical specification, see figure 19. thdsta hold time start control >4us. Figure 19. BUS timing specification

ob th FH th PG GH AG FG I A AL 28 15 4 B 1 14 Pte a a L F *—_ } i +c J | | N he, seating LK rH G D PLANE | DIM | MIN" | MAX |" MIN] | MAX | NOTES: este] 372 EE EECa 1. POSITIONAL TOLERANCE OF LEADS (D) [D036 | 0.56 | 0.014 [6.022 | NEUANON TO SEATING PLANE AND [FT| t02 J 1.52 | 0.040 | 0.060 | EACHOTHER. NG PANE AND [S254 BSC [25a BSC | DIMENSION 2. DIMENSION L TO CENTER OF LEADS H 51006 58 [A | 165 72.76 | 6.065 [0.085 | WHEN FORMED PARALLEL | K [292 | 3.43 [0.115 [0.735 | MOLD FLASH. {| t_| 15.24BSC_ |" 0.600 BSC_| 4, 710-01 OBSOLETE, NEW STD 710-02 a a Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any lability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent nights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical impiant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnity and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attomey fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and ® are registered trademarks of Motorola, Inc. Motorola, Inc, is an Equal Opportunity/Affirmative Action Employer. Literature Distribution Centres: USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan. & ; “4C44130/D a4 hum n Gow Gone ny Tota Sam estar} 4800 19,79 186 ozapa7 WV i

Product Information

MC44130P specifications and overview.

Summary

SYSTEM 4 STEREOTONE SINGLE CHIP TV SOUND CONTROL

Description

SYSTEM 4 STEREOTONE SINGLE CHIP TV SOUND CONTROL

Source title MC44130P Datasheet(PDF) - Motorola, Inc

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