MC44001

MC44001 MOTOROLA | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 69

Technical content

A SC (TELECOM) BSE D MM 6367253 0086867 T23 MmenoTs 42 pucton McAA00 be TECHNICAL DATA . Chroma 4 Product Preview VIDEO PROCESSOR Chroma 4 Multistandard SILICON MONOLITHIC INTEGRATED CIRCUIT Video Processor “The MC44001 is a highly advanced circuit which performs most of the basic functions required for a color TV. All ofits advanced features are under processor control via an I2C bus, enabling potentiometer controls to be removed completely. Inthis way the component count may be reduced dramatically, allowing significant cost savings together with the possibilty of implementing sophisticated automatic test routines. Using the MC44001, TV manufacturers will be able to build a standard chassis for anywhere in the world. © Operation from a Single + 5.0 V Supply; Typical Current Consumption “o Only 120 mA : © Full PAUSECAM/NTSC capability P SUFFIX © Dual Composite Video or S-VHS Inputs PLASTIC PACKAGE © All Chroma/Luma Channel Filtering, and Luma Delay Line Are Integrated CASE 711 Using Sampled Data Filters Requiring No External Components © Filters Automatically Commutate with Change of Standard PIN CONNECTIONS © Chroma Delay Line is Realized with a 16 Pin Companion Device, the MC44140 ace [1] {20} Video 1 in © RGB Drives Incorporate Contrast and Brightness Controls and Auto Gray Video 2 [2] [30} Ose Loop Fiter Scale tet [3] [s8) ident © Switched RGB Inputs with Separate Saturation Control ae § Oo 4] [37] RY © Auxiliary Y, R-Y, B-Y Inputs | Data [5 | [36] te ” © Line Timebase Featuring H-Phase Control, Time Constant and vamp [6 | [35] Voc Em Switchable Phase Detector Gain v.owve [7] [34] Gna © Vertical Timebase Incorporating Vertical Geometry Corrections Ew pre [a] [sa] (17.7 meta) © E-W Parabola Drive Incorporating Horizontal Geometry Corrections ‘anode [9 | (14.3 MHz) or © Beam Current Monitor with Breathing Compensation DIA Output [10] [31] Sandcaste ‘SECAM Cal. Loop [11] [30] System Select H-Drve [12] [29] ¥1 Output Flyback Input [13] [28] ¥1 Clamp WeLa0p Fer ‘| a a Ir inputs MAXIMUM RATINGS (Ta = 25°C, unless otherwise noted)” ‘inal Gn [ie] fas] \\ve [Ratings | Pin Symbot | Value | unit | R( D7 [24] )R | Suppiyvotace | 8 | oo | 60 | Vie | oupas o}(ro] faa} bo ute [ croaingaroantongaaise [a5 | ta | wx | < | ols ° [‘sereoeTonpwanre | — | Tog | -esevie0 | | fect (|__|) Fetcomman [ sunetonTorporawre | | ty | t50_ | | fonven) [owe cupusexcuren || te | 20 | ma | Applied Voltage Range: Ve ORDERING INFORMATION Feedback V20 010+7.0 ‘Anode Current Vg |-2.0t0Voc * (Based on C26K, C32K, C63K and C88K geometries characterizations) MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 9-161

MOTOROLA SC (TELEC om) BSE D MM 6367253 0086868 bT mMOTS MC44001 ELECTRICAL CHARACTERISTICS (Vcc = 5.0 Vdc, Ig = 70 uA, Ta = 25°C, unless otherwise noted.) [Sapo Cis es [sof ce Tv a [Reon conc venge tf ne se |v] Paneatwenoe | | so | o | vse | BReearrawmncromons | | ww | a | ow | | (NOTES: Composite Video Input Signa! Level = 1.0 Vpp ‘Horizontal Timebase started (subaddress 00) Black-to-White = 0.7 Vp, Syn-to-Black = 0.3 Vpp- ‘Vertical Breathing contro! set to 00; V9 = 0 V_ Siew cumereteneawe esteeraremetntaes sy ae eae ‘Simplified Block Diagram Video 1 RY BY ¥t ona JAAnwm ttt men OO ---@0-O-O-O- OOO | t} ty i} | is eee ate on 15 | ai | ete 5 Fiter (nyeit- RY Sep Ka BY = a [ee vm = [rei ea Het] Ee OT =" MHIH®) Cre tS MemoryiContol Registers Fo ae I 143MH {} RGB Sat r@ Green Hs) eS) eS ee Oo Sta Fe | eee

1 Us ee eee o

Iori coe I | mle © * Ope O-OXO-ONKO-@ =F 4 +50 Pulse b ‘Anode 2c) ysov Current PC Bus MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 9-162

are interchangeable and selection is made via the I2C bus. re-enter the MC44001. Figure 1. Connection to TV Chassis

0 EE ey

MOTOROLA SC (TELECOM) bSE D MM 6367253 00664670 518 MMOTS MC44001 The next stage is called the color difference stage where a__—line. The MC44001 is a highly advanced circuit which number of control functions are carried out together with performs all the video processing, timebase and display matrixing of the components to derive RGB signals. At this _ functions needed for a modern color TV. The device employs point a number of auxiliary signals may also be switched in, analog circuitry but with the difference that all its advanced again all under MCU control. External RGB (text) and Fast features are under processor control, enabling external ‘Commutate enter here; also an external luminance (Y2) may _ filtering and potentiometer adjustments to be removed be used instead of Y1. External R-Y and B-Y are switched in completely. Sophisticated feedback control techniques have via the delay line circuit to save pins on the main device. The __been used throughout the design to ensure stable operating Y2 and External R-Y, B-Y will obviously be of considerable conditions and the absence of drift with age. benefit from the system point of view for use with either The IC described herein is one of a new generation of TV feature boxes MAC of CTI. circuits, which make use of a serial data bus to carry out “The final stage of video processing is the RGB outputs control functions. Its revolutionary design concept permits a which drive the high voltage amplifiers connected to the _level of integration and degree of flexibility never achieved tube cathodes. These outputs are controlled by a _ before. The Chroma 4 consists of a single bipolar VLSI chip sophisticated digital servo-loop which is maintained and which uses a high density, high frequency, low voltage stabilized by a sequentially sampled beam current feedback process called MOSAIC 1.5. Contained within this single 40 system. Automatic gray scale control is featured asa part of —_pin package is all the circuitry needed for the video signal this system. processing, horizontal and vertical timebases and CRT Both horizontal and vertical timebases are incorporated display control for today’s color TV. Furthermore, all the user into the MC44001 and control is via the I2C bus. The controls and manufacturer's set-up adjustments are under horizontal timebase employs adualloop system of aPLLand the control of the processor !2C bus, eliminating the need for variable phase shitter, and the vertical uses a countdown _potentiometer controls. Chroma 4 offers an enormous variety system. For the vertical, a field rate sawtooth is available of different options configurable in software, to cater to which is used to drive an external power amplifier with flyback _virtually any video standard or circumstance commonly met. generator (usually a single IC). The line output consists of a_ The decoder section offers full multistandard capability, able pulse which drives a conventional line output stage in the to handle PAL, SECAM and NTSC standards. Practically all normal way. The line flyback pulse is sensed and used by the _the filtering is carried out onboard the IC by means of second loop for horizontal phase shift. sampled data filters, and requires no extemal components or Where E-W correction is required, a parabola waveform is adjustment. available for this which, with the addition of a power amplifier, ‘can be used with a diode modulator type line output stage for Digital Interface dynamic width and E-W control. The bottom of the EHT (One of the most important features of Chroma 4 is the use ‘overwinding is returned to the MC44001 and is used for _of processor control to replace external potentiometer and ‘anode current monitoring and anti-breathing correction. filter adjustments. Great flexibility is possible using processor ‘A much more detailed description of each stage of the control, as each user can configure the software to suit their MC44001 will be found in the next section. Information on the —_individual application. The circuit operates on a bidirectional delay line is to be found in this data sheet. serial data bus, based on the well known I2C bus. This Introduction system is rapidly becoming a world standard for the control of The following information describes the basic operation of consumer equipment, the MC44001 IC together with the MC44140 chroma delay MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 9-164

circumstances. For example, channel information could be ‘simple PAL signals. is too low, or if the ACC circuit is inactive due to too low a _out by a companion device, the MC44140. Figure 4. Chroma Decoder controlled AGC amplifiers wrapped around a cloche filter the TUNING feedback from the loop-filter forming the F.L.L. filter. The center frequency of the tracking filter depends on clean DC level for clamping purposes.

active lines for FOR/FOB. difference inputs and the R,G,B (text) inputs. blanking interval, starting from field retrace and ending just Selector whichis controlled by means of 2-bits from the MCU. before the SECAM vertical ident. sequence (bottles). The From here the selected luma signal goes to the RGB matrix. calibration gate (CAL) and integrated by an external capacitor _saturation control, whose main function is described later. range most of the variations due to internal AC products and added to the three color difference signals to derive R,G,B. temperature. The R,G.B inputs may take one of two different paths. quer ao TO on Pan Gonmaten ats saturation control. The path taken is controlled in software. Saas Gay Seale ei anes: Pass difference signals ara then subjected to saturation control. output from which may be used as the primary Processed as betore. Figure 5. SECAM Decoder

2 Calibration 1 0 |

Figure 6. Color Difference Stages

feedback is used to establish a set of feedback loops to —_appropriate. respectively. The white current reference pulses are sent first, __the line flyback pulse. Figure 7. Data words from the MCU which represent the RGB this reason the free-running frequency is calibrated Latches 1,2,3 and D/A converted by DAC1.2,3 to reference —_and thence during two lines every field, the phase detector is. During Load the contents of the counter are loaded into. down; and thus closing the loop. resulting DC current is then applied as an offset to the red —_it with the incoming H-sync. If they are not in lock, a flag is. ‘common factor. A common pulse representing a white levelis switched by means of commands from the MCU. data from the appropriate latch to the Up/Down Counter, —_ by 180 degrees with a control bit set by the MCU. DC pedestal of all three drives by the same amount, anddoes —_take appropriate action. An extra loop has been included via Latch 4 and DAC 4, —_and width control (see Figure 9). compensate for cathode leakage should this be needed. pulse. Sync from any of the auxiliary inputs may also be used.

MOTOROLA SC (TELECOM) BSE D MM 6367253 0086877 972 mEMOTS MC44001 up/down counter and decoder.The counter counts up when _Vertical Countdown System sync is high, and down when syne is low. The output of the ‘The MC44001 uses a countdown system to implement decoder is compared with a threshold level, the threshold _the vertical timebase function. Initially, the vertical timebase only being reached with a high count during the broad pulses _—_ should reset to the Injection mode. This means that the in the field interval. timebase locks immediately to the first signal received, in Initially the vertical timebase operates in Injection Lock exactly the same way as an old type injection locked mode, until a standard signal is recognized (525, 625), then it _timebase. A Coincidence Detector looks for counts of the is switched to a Countdown mode. A standard recognition _right number (e.g., 625) and causes a 4-bit counter to count circuit is employed, which looks for a count of more or less__up. When there are 8 consecutive coincidences the vertical than 576; the standard recognized is then indicated to the countdown is engaged, and the MSB of the counter is MCU. Commands from the processor may be used to force brought out to the set flag. Then the Auto Coundown mode the timebase to operate only in Countdown mode at 525 or _should be set. Similarly, non-coincidences which will occur if 625 lines, or stay in Injection Locked mode. synchronizing pulses are missing or in the wrong place, or if An adjustable current source is used to charge an external there is noise on the signals, cause the counter to count capacitor at Pin 6 to generate a vertical ramp. The amplitude down. When the count goes back to zero, after 8 of the ramp is varied according to the current source (Height), non-coincidences, the timebase automatically reverts to and is automatically adapted when the 525 standard is _Injection Lock mode. recognized by multiplying by 1.2. The Linearity control is It itis known that lock will be lost (e.g., channel change), it achieved by squaring the ramp and either adding or —_is possible to jump straight into Injection Lock mode and not subtracting a portion of it to the main linear current. have to wait for the 8 consecutive non-coincidences. In this The final camp with corrections added is then passed to a_—_ way the new channet will be captured rapidly. Once locked on driver/amplifier and is output at Pin 7. The vertical ramp can to the new channel, “auto countdown” is then reselected by be used to drive a separate vertical deflection power circuit. the MCU. with local feedback control. Vertical “S” Correction will then be Under some conditions such as some VCRs in Search made using fixed components within the feedback loop of the mode, itis possible to get signals having an incorrect number power op amp. of lines, meaning that the countdown fiag will go off because The reference ramp is squared to provide a pin-cushion _of successive non-coincidences. In these circumstances, it correction parabola, developed across an external resistor at “auto countdown’ is selected, the timebase will automatically Pin 8. The parabola amplitude may be varied from zero toa _—_lock to the signal in the Injection Lock mode. The fact that the maximum level set by the external resistor. The parabola _flag is effectively saying that the vertical timebase is out of itself is squared, giving and independent fourth order term lock need not be a cause for major concern, since the (Comer Correction) whose level can also be varied; this is horizontal timebase will still be locked to the signal, and has then added as a further modifying term to the E-W output. its. own flag — “Horizontal out of Jock". The vertical This latter correction is used for obtaining good comer countdown and horizontal lock flags both perform an geometry with flat-square tubes. A variable DC current is independent test for the presence of a valid signal. A logical added to the parabola to effect a width control. Using a OR function can be performed on the two flags, such that if suitable power amplifier and a diode-modulator in the line _ either are present then by definition a valid signal is present. output stage, the parabola may be used for E-W correction The vertical oscillator has end-stops set at two line-count and dynamic width control. A further control is provided to decodes as given below: shift the center point of the parabola up and down the screen 50 x 625 / 672 = 46.5 Hz (min) (Parabola Tilt), to accommodate different CRTs. As with the 50 x 625 / 512 = 61.0 Hz (max) vertical ramp output, an EHT correction is applied ‘These figures assume that the horizontal timebase is Allof the vertical and horizontal signals are adjustable via sunning at 15,625 Hz. When the vertical timebase is in S-bit words from the MCU, and stored in latches. The Injection Lock mode the line counter reset is inhibited so that adjustment controls available are it ignores any sync pulses before a count of 512 is reached. Vertical Amplitude/Linearity/Breathing Correction This prevents any possible attempted synchronization in the Parabola (E-W) Amplitude/Horizontal Amplitude/ middle of the picture. If the count reaches 672 lines then there Corner Correction, and Parabola Tilt is an automatic reset which effectively sets the lower ‘The Anode Current Sense at Pin is also used asabeam —_requency limit. The choice of these limits is a compromise current monitor. Two thresholds may be set, by the between a wide window for rapid signal capture and a narrow manufacturer, using external components. The first threshold ___ window for good noise immunity. sets a flag to the processor it beam current becomes ltis also possibie to run the timebase in 2V mode as there excessive. The MCU could e.g. reduce brightness and/or —_ are decodes for 100 Hz (2 x 50 Hz) operation with upper and contrast to alleviate the condition. The second threshold sets _lower limits in proportion. This is, of course, intended to be a flag warning of an overload condition where the CRT —_used in conjunction with field and frame memory stores. The phosphor could be damaged. If such a condition were to _ similar decodes which would be necessary to allow 120 Hz (2 arise, the processor would be programmed to shut down x 60 Hz) operation have not, for the present, been the PSU implemented. Finally, the timebase can be forced into a count The vertical blanking period may be selected by means _of either 625 or 525 by commands from the MCU; in this of a bit from the MCU to either 22 or 11 lines. The interlace mode the input signal, if present, is ignored completely. If may also be suppressed again under the control of _thereisno signal present save for noise, then this feature can the processor. be used to obtain a stable raster. MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 9-171

Figure 7. Auto Gray Scale Control Loops

1 Feedback

162 UpiDown| mo

explanation of the external circuit component requirements _ facilitate testing and for fine tuning the performance. will be found in Figure 10. One of the primary design aims for _ single 100 nF capacitor.

MOTOROLA SC (TELECOM) 6SE D MM 6367253 0086880 4b? MEMOTS MC44001 Reference Current (Pin 3) - Master reference current used _ there is no separate ground pin available which may be throughout the IC. This is programmed by means of an —_connectednear the line O/P stage; noise could be injected into external pull-up resistor, as onboard resistors are not the signal ground on the IC. Therefore, with a transformer sufficiently accurate. The designated currentis 701A. Thispin _ driven line output stage, this output has been designed to be { should be very well decoupled to ground to avoid picking up _—_used with an extra external transistor inverter between the |C | interference from the nearby I2C bus inputs. and the line driver. 12 Clock (Pin 4)-12C bus clock input. This inputcanbetaken —_H-Flyback Input (Pin 13) - Flyback sensing input taken trom ‘Straight into the IC, but in a real TV application it may be the line output transformer. These pulses are used by the 2nd prudent to fit a series current limiting resistor nearby the pin in horizontal loop for H-phase control. A positive going pulse case of flashover. from 0 V to + 5.0 V amplitude is needed for correct operation 2 2 The internal impedance of the pin is about 50 k®2. An external 2c Data (Pin5)—I2Cdatainput. Thecommentabovetor Pin4 attenuating series resistor will also be needed. also applies to this pin. H-Loop 2 Filter (Pin 14) —A simple external filter consisting of Vertical Ramp (Pin 6)~Acurrentis usedto charge an external 400 nF capacitor for the 2nd horizontal loop. capacitor connected to this pin, developing a voltage sawtooth with a field period. H-Loop 1 Filter (Pin 15) - Horizontal PLL loop time constant. Vertical Drive (Pin 7)—The sawtooth derivedon Pinéisused "he value of RC time constant is selected aun Pears to drive an extemal power ampifier vertical output stage. The FomTpanens: 19 ave @ Smooth recovery after the fe amplitude and linearity of the output ramp are adjustable via. (terval disturbance. the MCU Signal Ground (Pin 16) Parabola (E-W) Drive (Pin 8) — A parabolic waveform derived by covery MO priv ramp ‘eased to drive an external PGB Outputs (Pin 17, 18, 19)-The R,G,B drives are current power amplifier. In sets fitted with a diode modulator ype line father than voltage due tothe limited headroom available with Sutput stage, this provides Width Control and Pin Cushion the 5.0 V supply line. The outputs themselves consist of Correction ‘The parabola is squared again to give a fourtn 0Pe"-collector transistors and these are used to drive the order correction term required for flt square tubes, The E.W _ViTual ground point ofthe high voltage cathode amplifiers. amplitude, OC level, Tit and Corner Correction are all eedpack (Pin 20) : ) - Current feedback sense derived trom the aquetabie by means of ve wee This is a owen output video output amplifiers. The currents from all three guns are oan evel inal Pulkup resistor fo develop the summed together as each is driven sequentially with known voltage waveform. current pulses during the field interval. This feedback is then ‘Anode Current (Pin 9) - Used as an anode current monitor Compared with internally set-up references. A low value (antibreathing); and also warn of excessive and overload ‘help stabilize the control loops. beam current conditions. A secondary function of this pin is for peak beam current This pin is connected via 560 k series resistorto the bottom _ limiting. When the feedback voltage during picture time of the EHT overwinding. Thus increasing beam current will becomes too great (i.2., too high beam current), a threshold pull the voltage on this pin more negative. This change is @t VCC + 2 Vbeis exceeded at which time a flag is sent to the Sensed within the chip and used to apply a correction to the -«: MCU. The MCU then has to carry out the function of peak ramp and parabola amplitudes. With large beam currents, _eam/imiter by e.g. reducing contrast until the flag goes off thresholds at +1 Vbe and - 2 Vbe set off warning flags to the ‘The threshold current is set externally with a fixed resistor MCU, which then has to take the appropriate action. The Value. anode currant Jovets at wich these Whresholds are reached Fast Commutate (Pin 21) — A very fast active high switch Pusing (transition time 10 ns). Used with text on the R,G,B inputs, for Grid 2 Control (Pin 10) - This consists of one of the MC44001 overlaying text on picture. This hardware switch may be control registers which has been D/A converted and brought enabled and disabled in software. out from the IC as a current source. The current may be varied from 0 WA 10300 HA, andmaybeusedforanumber of auxiliary __-R,G,B Inputs (Pins 22, 23, 24) These external input signals tasks, such as for Grid 2 control are AC coupled into the IC via 100 nF capacitors and are clamped. The inputs have a 1.0 kQ impedance and should be SECAM Calibration Loop (Pin 11) — A 100 nF capacitor on driven with 700 mVp-p signal levels. this pin is used for the SECAM Calibration Loop. Y2 Input (Pin 25) — Auxiliary external input to the MC44001. H-Drive (Pin 12) — Horizontal drive pulses having an The pin has a 1.0 kQ impedance and should be driven with approximately even mark-to-space ratio emerge from this pin, 700 mVp-p of luminance signal. The signal must be AC This is an open-collector output which can sink upto 10 mA. coupled via an external 100 nF coupling capacitor, and is However, taking this much current isnot recommended since clamped internally. MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 9-174

MOTOROLA SC (TELECOM) 6SE D MM 6367253 0086881 373 MEMOTS MC44001 B-Y and R-Y Inputs (Pin 26, 27) - Corrected color difference + 5.0 V Supply (Pin 35) - Supply line, nominally + 5.0 V inputs from the MC 44140. The signals are AC coupled tothe requiring about 120 mA. The actual voltage should be in the MC44001 color difference section and are clamped. The input _range of 4.75 V to 5.25 V for usable results. Itis recommended impedance is of the order of 1.0 kA. to decouple the supply line using a small ceramic capacitor mounted close to the supply and ground pins. Y1 Clamp (Pin 28) ~ External capacitor used by the circuit which clamps the Y1 signal output on Pin 29, Ground (Pin 34) Y1 Output (Pin 29) — The luminance, after passing through the filter and delay line/peaking sections, is made availableon _B-Y and R-Y Outputs (Pin 36, 37) ~ Demodulated color this pin, difference outputs. These signals are AC coupled to the MC44140 for correction and delay with PAL and SECAM, System Select (Pin 30) ~ A DC level output controlled in _respectively. Signal levels up to a maximum of 1.0 Vp-p may software. Used by the MC44140 for system selection. be expected Sandcastle (Pin 31) — A special timing pulse derived in the Ident (Pin 38) ~ External filter used by R-Y indent circuit. The MC44001 for use by the MC44140. filter normally consists of a single capacitor (47 nF) whose Crystal (Pin 32, 33) — A 14.3 MHz crystal is required at Pin 32 vauels a compromise between rapid identification and noise for NTSC decoding, and a 17.7 MHz crystal is required at Pin fection. 33 for PAL and SECAM decoding. Either crystal may be , omitted if the application does not involve the associated OSC Loop Filter (Pin 39) ~ External time constant or chroma PLL. The crystal reference oscillator is phase-locked to the signals. The appropriate crystal is selected by the MCU. Incoming beet it PAL nd NTS anon en ba The crystals are parallel-driven, and require an external Sarit, or goad ‘mnhrunty. i revmally placed ma load capacitor of 20 pF to 30 pF. Only crystals intended for @Pacitor, for good noise immunity, is normally plact . parallel with a much longer RC time constant. The PLL pull-in VCO operation should be used. The selected crystal’s duced when yhe 1 Canton the pin ig nade frequency is made available to the MC44140 by means ofthe ange Is reduced when the time constant on the pin is external eapacitor divider bigger; allowing this function to be optimized by the user. CONTROL FUNCTIONS General Description Corner Correction — An independent 4th order term which is As already related in the circuit description, the MC44001 _ subtracted from the E-W parabola to achieve correct geometry has a memory of 18 bytes. All, except Sub-address 77 and _with flat square tubes. 7E, use the 6 least significant bits (64 steps) as an analog : control register with D/A converters within the memory Horizontal Amplitude — A variable DC offset applied to the section. The remaining bits are controlled individually for E-W output parabola on Pin 8. switching of numerous functions. Table 1 gives a listing of all the memory registers and control bits. An explanation of the D/A Output variable DC curent mnder 2 bus contol function of the 16 analog control registers is given below. to drive auxiliary external circuitry under us control. , . ; Horizontal Phase Control— Applies variable phase offsetto Vertical Amplitude ~ Changes the amplitude of the vertical the horizontal drive pulse at Pin 15 providing for a picture ramp available on Pin 7. centering control Vertical Breathing Correction—Acorrectionis appliedtothe _-B, G, R Temperature - These controls set up the current vertical ramp amplitude in a sense opposite to the picture reference pulses used when sampling the beam current expansion and contraction produced by changes in beam during field interval. The data is fixed by the TV manufacturer current. This register alters the sensitivity of the beam current. _ when setting up the CRT for corract Gray Scale tracking. sensing and hence the size of correction applied for a given change in beam current. (All the above registers are for use during the test and setting up procedures; the remaining 4 registers are also user Parabola Amplitude - Changes the amplitude of the E-W —-contrals.) output parabola developed across an external pull-up resistor Contrast — During bright sample time during the field interval at Pin 8. this control varies the level of the current pulses injected into the RGB channels, th . Parabola Tilt - Shifts the point of inflection of the EW ® channels, so altering the picture contrast parabola from side to side along the time axis. Also known as Brightness — A variable current pedestal which is added to keystone correction. the three drives during active picture time. Vertical Linearity - The vertical ramp is multiplied by itselfto Saturation — A variable gain control for the two color give a squared term, a part of which is either added or _ difference signals (0 to 140%). There are two such controls subtracted to the linear ramp as determined by this register. __within the MC44001, and this control acts on them both. MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 9175

the timebase into 525 or 625 lines. ‘Some of these are used individually to control single functions which can be scanned in the nearest even or odd halt line. back to auto mode. In this way there is no delay in locking onto MC44140 is being controlled by the I2C bus via the MC44001. Figure 10. Basic Smal! Signal Circuit

Table 1. Control Data

82 Blue Temperature

6 Sse | HEN

Table 2. Control Bit Truth Tables _ - video input has a high quality syne separator which has been _accepts separate chrominance directly for the input. id used 50 Hz operation is selected. Not usable with NTSC. Either 5.5 MHz, 6.0 MHz, or 6.5 MHz center frequencies gay _ Either 22 or 11 lines may be blanked using this bit.

timebase is locked to an incoming signal quality signals. changing between 14.3 MHz and 17.7 MHz crystals. SSD ~Can be used to override SECAM mode in the delay line. Y1 EN Switches Y1 through to the color difference stage Blue color temperatures. Test — When bit is low, enables continuous sampling by the (15.750 kHz) or at doubie this rate. control is selected. Used in conjunction with SAT2 EN. memory. detector, ¢.g., when locking onto a new channel and operation control. Used in conjunction with YX EN. with VOR V1IN2 ~ To select between Video Inputs 1 and 2. Table 3. Control Bit Functions

22 Blanked Lines Selected 11 Blanked Lines Selacted

1 MC44001

l When the Address Read/Write bit is high the lasttwo bytes component network connected to beam current sensing Pin9. | these may be found in Table 4. The MC44001 is designed to _—_tothe manufacturer's set maximum level during normal usage. | the feedback mechanism which allow the MCU to interact MCU to reduce the brightness andior contrast. Table 4. Flags Returned then a 625 line system is being received. This information can = Vertical Countdown Engaged | counter is used to set this flag to the processor. Grid2 Volage Up Request ~ action in this case is therefore to shut down the set. at OK | range necessary for correct gray scale tracking.

22 Fault OK and Fault - These two flags are included asa check onthe

25 SECAM identified received is valid. the flyback transformer secondaries to Pin 13. Thisisusedfor NTSC andis also available for system identification purposes. chassis has been started upthen the MCU would haveto shut 40 off in this mode. pulse outputat Pin 1Shas been enabled. This occursaterthe __Wththe ACC fag, this is positive identification fora PAL signal. signal's being received by the MC44001, Possible action in__‘entification that SECAM is being received.

beam current which may be in only a partoof the screen. The _incorporated by the way in which the software is written. However, writing to the MC44001 must be restricted to can cause the sampling loops to become unstable. control function which is carried out with RGB sampling this time. Table 5. System Identification present wth the 14.3 MHz crystal.

1. Chroma 4 could also be used for the PAL M 8 N Standards that are used in some parts of South

Table 6. Mode Definitions “Control bts XS and NORM are always changed together.

MOTOROLA SC (TELECOM) 6S5E D MM 6367253 0086888 756 MENOTS MOTOROLA ° MC44011 SEMICONDUCTOR aaa TECHNICAL DATA a _ Advance Information BUS CONTROLLED . MULTISTANDARD B intro! us Controlled Multistandard VIDEO PROCESSOR Video Processor SILICON MONOLITHIC The Motorola MC44011, a member of the MC44000 Chroma 4 family, is INTEGRATED CIRCUIT designed to provide RGB or YUV outputs from a variety of inputs. The inputs can be composite video (two inputs), S-VHS, RGB, and color difference (R-Y, B-Y). The composite video can be PAL and/or NTSC as the MC44011 is capable of decoding both systems. Additionally, R-Y and B-Y outputs and inputs are provided for use with a delay line where needed. Sync separators are provided at all video inputs. In addition, the MC44011 provides a sampling clock output for use by a subsequenttriple A/D converter system which digitizes the RGB/YUV outputs. The sampling clock (6.0 to 40 MHz) is phase-locked to the horizontal frequency. ‘Additional outputs include composite sync, vertical sync, field identification, a luma, burst gate, and horizontal frequency. aw Control of the MC44011, and reading of status flags, is via an I2C bus. 1 * Accepts NTSC and PAL Composite Video, S-VHS, RGB, and R-Y, B-Y © Includes Luma and Chroma Filters, Luma Delay Lines, and Sound Traps FN SUFFIX © Digitally Controlled via I2C Bus PLASTIC PACKAGE. © R-Y, B-Y Inputs for Alternate Signal Source once * Line-Locked Sampling Clock for A/D Converters ‘ * Burst Gate, Composite Sync, Vertical Sync and Field Identification Outputs ¢ RGB/YUV Outputs can provide 3.0 Vp.p for A/D Inputs © Overlay Capability ORDERING INFORMATION * Single Power Supply: + 5.0 V, + 5%, 550 mW (Typical) __— | Temperature Pa @ 44 Pin PLCC Package Device_| _Renge Package

9 Simplified Block Diagram

Yoct GND1 Yi RY BY RY BY Y2 RGB Comm prrcti oF -2----- on Gr a 7on © Vie TP pt = mmr w) jo Tro Sound Taplama Fife ama Delay? |_| (| Caer biter re EL oututs comp | (Chroma FiterPAL and NTSC Decoder! az Stage au Video 2 } | Hue and Saturation Control | __ ‘ : i I Contrast, Brightness, Veca | Select ne Salucatlon Gono DACS 1 Vertical | ia =] — GNo2 Filed Decoder j Syne | | void io > 4 : ! et ‘Separator 4 20 ata sou, Tour 17.7 MHz Fenn BESET i mcaaont Regstrs SCL. seit | | fi ? | PLL #1 Horizontal PUL ee Veoo3 = 143 | puweo Pisal Clock 2 vo M2 i PLUVCO ad regime! fy _d Burst 16Fh) Fier «=H Quiot, «Fh 15k PiL Clock, To A/D Converters Gate Cgyne Switch Filer GND Ref Ret Filter a snr Frequency Divider MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 9-182

MOTOROLA SC (TELECON) BSE D MM 6367253 0086889 694 MEMOTS MC44011 é 5 2 : Bp BE nd tanh 2 Ge =}-—fa] e}] tH} —— 1b EO i oul . 4 Ca ED iy eT et a | Spe ie ioe | oF 1 ee ee Ad | EE mney) LOaViad gee “Tt fie | aH ERR | we] EP [28] Ls Vay lg u 58 | Hi [Bl E it ann | Eg ze fk i] \\ ad {eglt 13 Blot a j Bee | wl eehY gigs 3 é cca = ERLE: | = | ii = (\\Bh+) Sa] ° yr} | . 3 ide Wg | ‘i ° A it !

2 Aki ee oe Stee

et T} \\ | (eee) Bp gle-——y | exe § Li}? i! Ha Hi git TL

2 FET Ss HH i ie HI al 5

ey | By ee af 1 | OF EE = jot cee | c Bi: | ESE lly | ! | 5 5y °° 9 (5 i BESS | | 38, air a tao Py abe ltce Ei far gry dS ai) le) | rac a yy Pie] tio gets He ee ne “Fo, 3 He} fs “tit SoSH, g 3 FI i, 2 83 ° “EEA, MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 9-183

Table 1. Control Bit Test Settings

0 Composite Video input selected

$787 0 Time from beginning of Line 4 to Verical Sync’ 368. 0] Fast Commutate input ean enabe RGB inputs. $816 Yt EN t Yt luma path from PAUNTSC decoder selected. [seer |W Swicn [0 | SetHorzontal Phase Detector titer switch open.

16 FhoutputselecedatPint3 SSS ——

Vin Syne 7 ‘Composite Video inputs {Pin 1 or 3) Sync Source selected. Table 2. DAC Test Settings

MOTOROLA SC (TELECOM) bSE D MM 6367253 00466891 242 MENOTS MC44011 MAXIMUM RATINGS Power Supply Voltage Voc1 -0.5t0+6.0 Vde Veco - 0.510 +6.0 | Yoc3 -0.510+6.0 Power Supply Ditference | 405 Ve (Between any two Voc pins) Input Voltage: Video 1, 2, SCL, SDL 1 Vin -05,Vec1+0.5 | Vdc 15 kHz Return | ~0.5, Voc + 0.5 RLY, B-Y, Y2, RGB, FC. 05, Voc2 + 0.5 Junction Temperature (Storage and Operating) = 6510 +150 °C Devices should not be operated at these limits, The “Recommended Operating Conditions” table provides for actual device operation RECOMMENDED OPERATING CONDITIONS - Parareter Syme [win [te | we] om) Fava oy vag [woones | 247s [50 | vsas | ve] Input Voltage: Video 1, 2 (Sync-White) Vin o7 | 10 14 Vp-p ‘Chroma (S-VHS Mode) - | = 12 v2 07 1.0 14 RGB Os } 07 1.0 R-Y, B-Y (Pins 30, 31) Oo) = 18 15 kHz Return o | = Yocs | vdeo SCL, SDL of = Yecr | Fo o | = Vece | Burst Signal 30 | 280 560 | mVp-p Syne Amplitude 60 | 300 Voc: | mVp-p Output Load impedance to Ground: RGB (Pull-up = 390 Q) RiRGB BY, R-Y Ricp Yt Rly1 Source Impedance: Video 1, 2 Pins 26 to 31 Piel Gk Fequery (Pin 18, <0 PLL #2 Eectica Gharawiaisy |p| =| Bowes | we | [Tskienewnrusswantewtinn | ge | aa | = es [eeceereweey eo [Rewoneecurenra@ tw ‘Al mits are not necessarily functional concurrently, ELECTRICAL CHARACTERISTICS (Tq ~ + 25°C, Voc = Voce = Vocs = §.0 V, unless otherwise noted.) a POWER SUPPLIES Power Supply Current (Voc = +5.0V) Pin 40 78 5 115 mA Pin 23, 60 9.0 12 Pin 19 35 6.0 8.0 Total 85 110 135 J MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 9-185

MOTOROLA SC (TELECOM) 6SE D MM 6367253 0086892 189 MENOTS MC44011 ELECTRICAL CHARACTERISTICS (Ta = + 25°C, Voc1 = Voce = Vocs = 5.0 V, unless otherwise noted.) PALINTSC/S-VHS DECODER Video 1, 2 Inputs | Crosstalk Rejection, f = 1.0 MHz 20 40 - 8 (Measured at Y1 output, Luma Peaking = 0 dB, $77-7 = 1) | DC Level: @ Selected input - 28 — | Vdc @ Unselected Input = 07 - | Clamp Current -30 -20 10 | BA ‘Sound Trap Rejection (See Figures 14 to 23) With 17.7 MHz Crystal: @ 6.6 MHz (T1, T2 = 00) 15 30 - 0B @ 6.0 MHz (T1, T2 = 10) 15 30 - @ 55 MHz (T1, T2 = 11) 10 a — @ 5.74 MHz (Tt, T2 = 01) 18 26 - | With 14.3 MHz Crystal: @ 4.44 MHz (T1, T2= 11) - 35 - | FLY, B-Y Outputs (Pins 41, 42) | Output Amplitude (with 100% Saturated Color Bars) } Saturation (DAC 87) = 00 - <1.0 — | mpp Saturation (DAC 87) = 16 - 16 — | vpp Saturation (DAC 87) = 63 15 18 - | DC Level During Blanking - 24 - Vde Hue Control — Minimum Phase (DAC 88 - 00) -30 - — | Deg — Maximum Phase (DAC 88 = 63) +30 - - | Nominal Saturation (with respect to Y1 Output, Note 1) - 100 - | * B-Y/R-Y Ratio: Balance (DAC 78) = 63 1.35 169 206 | WV Balance (DAC 78) = 32 0.98 1.27 1.58 Balance (DAC 78) = 00 0.60 077 096 Output Amplitude Variation as Burst is varied from 80 mVp-p to 600 mVp-p - 30 - 08 Color Kill Attenuation ($7C-7, 6 and $70-6 = 011) | = 40 - B Crosstalk with respect to ¥1 Output (@ 1.0 MHz) -27 ~20 = ‘Chroma Subcarrier Residual (Measured at Y1 Output, with 17.7 MHz Crystal) = Subcarrier - 25 60 | -mVpp 2nd Harmonic Residual - 40 12 4th Harmonic Residual - 12 30 (Measured at R-Y, B-Y Outputs, with 17.7 or 14.3 MHz Crystal) f= Subcarrier } - 50 20 2nd Harmonic Residual { o- 50 20 4th Harmonic Residual {o- 18 50 Y1 Luma Output (Pin 33) | Clamp Level | 04 1 18 Vde Output Impedance - 300 - Q ‘Composite Video Mode ($77-6, 7 = 00) | Output Level versus Input Level Delay = 000, Peaking = 111, f= 100 KHz 1.0 re 12 ww Delay = Min-to-Max, Peaking = Min-to-Max - 14 _ = 3.dB Bandwidth (17.7 MHz Crystal, PAL Decoding selected, , oo 28 - MHz ‘Sound trap at 6.5 MHz, Peaking off) | Peaking Range ($7D-7, $7£-67 = 000 to 111, @ 3.0 MHz, with 17.7 MHz Crystal, 5 8 10 8 Sound trap at 6.5 MHz) ‘Overshoot with Minimum Peaking - ° - % Differential Non-linearity (Measured with Staircase) - 20 - % Delay (Pin 1 or 3 to 33) | With 14.3 MHz Crystal: Minimum _—_ 620 - ns Maximum oo 4040 - With 17.7 MHz Crystal: Minimum , - 594 - Maximum { - 876 - NOTE: 1. This spec indicates a correct output amplitude at Pins 41 and 42, with respect to Yt output. For standard color bar inputs. the output amplitude is between 1.5 and 1.7 Vp-p, with the settings in Tables 1 and 2 MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 9-186

TOROLA SC (TELECOM) BSE D MM 6367253 0086893 015 mMMOTS MC44011 ELECTRICAL CHARACTERISTICS (Tq = + 25°C. Voo1 = Voce = Veca - 5.0 V, unless othemwise noted.) { Parameter [win | typ | Max [unt | PALINTSC/S-VHS DECODER - S-VHS Mode ($77-6, 7 = 11) Output Level versus Input Level (Delay - Min-to-Max) 10 1 vw ~ 3 dB Bandwidth (17.7 MHz crystal, PAL Decoding selected, - 45 MHz ‘Sound trap at 6.5 MHz) YIG Crosstalk Rejection } 20 40 08 Delay (Luma input to Pin 33)

14.3 MHz Crystal: Minimum - 395 ns

17.7 MHz Crystal: Minimum _ 350

Maximum | =_ 632 Crystal Oscillator (Burst Level > 30 mVp-p): with 17.7 MHz Crystal | _ +350 _ Hz | with 14.3 MHz Crystal i} —_ +300 _ Afge Filter (Pin 44) DC Voltage | @ 143 MHz ~ 24 ~ | Vde No Burst present - 13 - DC Voltages Vde ‘System Select (Pin 34) | NTSC Mode (SSA= 1, SSB=0, SSC = 0, SSD = 0) | 45 175 20. | | PAL Mode (SSA=0, SSB=1, SSC =0, SSD = 0) 0 0.075 O4 1 | Color Kill Mode (SSA=1, SSB= 1, SSC = 0, SSD = 0) bad 0.075 _- i | External Mode (SSA =X, SSB = X, SSC - 1, SSD = 0) a7 40 43 | Ident Fitter (Pin 43) } NTSC Mode - 16 - | PAL Mode 12 1S 18 i} No Burst present - 02 - ACC Filter (Pin 2) No Burst present - 0.25 _ Threshold for ACC Flag an 08 12 16 Burst = 50 mVp-p - 14 - Burst = 280 mVp-p - 17 = | ‘System Select Output Impedance 40 oo | kK | COLOR DIFFERENCE SECTION _ RGB/YUV Outputs Output Swing, Black-to-White (DAC $81 = 63) 20 3.0 _ Vp-p THD (RGB Inputs to RGB Outputs @ 1.0 MHz. 0.7 Vp-p) - 05 20 % 3.dB Bandwidth - 6.0 - MHz ‘Clamp Level RGB Outputs ($7D, 7E = 00) - 14 - Vde UV Outputs ($70, 7E = 32) _ 23 baad Red, Blue Clamp Level Change (DACs $70, 7E varied tram 00 to 63) 0.85 18 24 Crosstalk Rejection Among RGB Outputs @ 1.0 MHz 20 40 Bo Yt to ¥2 | 20 40 _ From RGB Outputs to Y1 or ¥2 | 20 40 - Input Black Clamp Voltage at Y2. B-Y, R-Y. and RGB. | 24 30 36 Vde Fast Commutate Input (Pin 25) ‘Switching Threshold Voltage - os - Vde Input Current @ Vin = 0V - -75 - BA Input Current @ Vin = + 5.0 V 1 - 0 - Timing: Input Low-to-High (RGB Enable) _ 50 _ ns i Input High-to-Low (RGB Disable) - = Ea _- J MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 9-187

MOTOROLA SC (TELECOM) BSE D M@® 6367253 0086894 T5]) MBNOTS MC44011 ELECTRICAL CHARACTERISTICS (Tq = + 25°C. Voc = Voce = Ves = 5.0 V. unless otherwise noted.) _ Parameter Min Typ Max Unit : COLOR DIFFERENCE SECTION Contrast (Gain) | ww Yt to RGB (DAC $81 = 32, DAC $86 ~ 00) 18 24 30 Y2 to RGB (DAC $81 ~ 32, DAC $86 = 00) 18 23 28 Green In (Pin 27 0,Green Out (Pin 21) wih YX Enabled 18 | 23 24 ($82-6 = 1, DAC $81 and DAC $86 = 32) Red-to-Green and Blue-to-Green Gain Ratio 8 10 12 RGB Input to RGB Output with YX Not Enabled 20 26 32 (882-6 = 0, DAC $81 and DAC $86 = 32) Ratio (DAC $81 = 00 versus 32) - 02 o4 Ratio (DAC $81 = 63 versus 32) 15 20 25 Red and Blue Trim Control (DACs $80, 82 varied from 00 to 63) +5 +30 +60 % Saturation (Average of R, G, 8 saturation levels with respect to Luma) Inputs at Pins 29 to 31 (DAC $86 = 32) 50 90 130 % Ratio (DAC $86 = 00 versus 32) - - 5 Ratio (DAC $86 - 63 versus 32) 150 170 190 Inputs at Pins 26 to 28 (DAC $86 = 32, $82-6 = 1) 70 125 180 Brightness | Black Level Range (Brightness = 00 to 63 with respect to Brightness setting of 32) +03, +05 £07 Vac Red and Blue Trim Control (DACs $83, 85 varied from 00 to 63) £0.05 £03 +06 Color Coefficients ] G-Y Matrix Coefficient versus B-Y -0.21 -019 | -o17 G-Y Matrix Coetticient versus R-Y -056 | -051 0.46 YX Matrix (Inputs at Pins 26 10 28, $82-6 = 1): | Y versus 0.28 0.30 0.32 Y versus G | os7 0.59 0.61 Y versus 8 0.09 ott 0.13 HORIZONTAL TIME BASE SECTION (PLL #1) Free: Running Period (Calibration mode in effect, Bit $86-6 = 1) ] 17.7 MHz Crystal selected ($84-6 = 0) 62.5 64.0 655 Hs 9] 14.3 MHz Crystal selected ($84-6 = 1) 62.5 635 655 VCO minimum period (Pin 11 Voltage at 1.2 V) se | (585 62 us VCO maximum period (Pin 11 Voltage at 2.8 V) 66 695 72 Phase Detector Current High Gain ($83-6 = 1) 15 50 85 HA Low Gain-to-High Gain Current Ratio 032 | 0.38 0.44 WALA Noise Gate Width ($77-2 = 0, Low Gain, see Figure 26) = | 6 [| - | ws | Horizontal Fitter Switch (Pin 12) Saturation Voltage (112 = 20 yA) - 10 mv Dynamic Impendance ($84-7 = 1) — <50 Ko Parallel Resistance ($84-7 = 0) 06 10 Ma Pins 8, 13, 14 Output Level High (Io =~ 40 pA) 24 45 Voc Low (Io = + 800 HA) - 4 Burst Gate (Pin 8) Timing (See Figures 25, 27) Rising edge from Sync leading edge (Pins 1, 3) 44 56 68 Rising edge trom Syne center (Pins 26 to 29) - 25 - Pulse Width 3.0 35 40

16 Fh Output (Pin 13) Timing (Bit $85-6 = 0) (See Figures 25, 27)

Rising edge from Fh rising edge - 13 ks Duty Cycle — 50 % Composite Syne Output (Pin 13) Timing (Bit $85-6 = 1) HS Input Sync center to Output Syne center (Pins 1. 3) _ 0.95 Input Sync center to Output Sync center (Pins 26 to 29) _ - O48 MOTOROLA LINEARVINTERFACE ICs DEVICE DATA 9-188

MOTOROLA SC (TELECOM) BSE D MM 6367253 0046895 998 MNOTS MC44011 ELECTRICAL CHARACTERISTICS (Tq - + 25°C, Voc = Voc2 = Voos = 5.0 V. unless otherwise noted.) LL _ Parameter _ win Ty Tax [unit] HORIZONTAL TIME BASE SECTION (PLL #1) _ Fh Reterence (Pin 14) Timing (See Figures 25, 27) Rising edge from Syne center (Pins 1, 3) 13 - us Rising edge from Sync center (Pins 26 to 29) 650 ns Duly cycle 50 - % Sandcastle Output (Pin 35, see Figures 25, 27) Vde Output Voltage — Level 1 37 40 43 Output Voltage - Level 2 28 3.0 32 Output Vottage ~ Level 3 - 1.55 - Output Voitage - Level 4 - 0.07 = Rising edge from Syne center (Pins 1. 3) - ~26 - us Rising edge from Sync center (Pins 26 to 29) -33 - High Time - 60 - Level 2 Time = 50 - Reference Voltage @ Pin 9 (Irof = 32 uA) [10 12 14 Vde PHASE-LOCKED PIXEL CLOCK SECTION (PLL #2) _ _ VCO Frequency @ Pin 18 MHz Minimum (Pin 16 = 1.6 V, $85-7 = 1) - 20 40 Maximum (Pin 16 = 4.0 V, $85-7= 0) 30 45 60 VCO Up (Flag 19) Threshold Voltage @ Pin 16 18 17 19 Vde VCO Down (Flag 20) Threshold Voltage @ Pin 16 at 33 35 VCO Controt Voltage Range @ Pin 16 12 38 Vac VCO Control Gain factor ($7FDAG = 00, $85-7 ~ 0) 4.0 12 MHziV Charge Pump Current (Pin 16) 25 50 75 nA High Gain ($83-7 = 0) Curent Ratio 03 os 05 AA Low Gain-to-High Gain Pixel Clock Output (Pin 18) (Load = 3 FAST TTL loads + 10 pF) Qutput Voltage — High — 39 Vde Output Voltage - Low { — 0.15 Rise Time @ 50 MHz - 70 ns Rise Time @ 9.0 MHz - 7 Fall Time @ 50 MHz { — 50 Fall Time @ 8.0 MHz Lo- 80 15 kHz Return (Pin 15) | Input Threshold Voltage { - Vde Falling edge from Fh rising edge ; = ns Minimum Input Low Time | 200 VERTICAL DECODER _ — Vertical Frequency Range | 433 122 He Vertical Syne Output j Saturation Voltage (Iq = 800 A) - 08 v | Leakage Current @ 5.0 V (Output high) - 40 wa | e wowin OO | Timing from Sync polarity reversal to Pin 4 falling edge (See Figures 33, 34) } us (878-7 = 0) 32 36 0 | Vertical Sync Pulse Wiath (Pin 4, NTSC or PAL) 490 500 510 us Field Ident (Pin 7) Output Voltage — High (io = ~ 40 nA) 24 45 = Vde Output Voltage ~ Low (io = + 800 A) - 0.1 08 Timing — | Fi9.33.3¢) — HORIZONTAL SYNC SEPARATOR _ __ Syne Slicing Levels (Pins 1. 3) = 120 = mv From Black Level (Pins 26 to 29) = 150 - MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 9-189

MOTOROLA SC (TELECOM) 6SE D MM 6367253 0066896 624 MMOTS MC44011 _ _ PIN FUNCTION DESCRIPTION ee Pin No. Representative Circuitry Description 13] CT TIFT | video input 1 & 2- video 1 (Pin 1) and Video 2 (Pin3) are i or | composite video inputs. Either can be NTSC or PAL. Input Video impedances high, termination must be external. Also used Input > 335 for the luma and chroma components of an S-VHS signal ATT Som 20k Bonem ‘Selection of these inputs is done by software. External , + I an components protect against ESD Lia SS ACC Filter — A 0.1 ,.F capacitor at this pin fiters the

1 I feedback loop of the chroma automatic gain control

I amplifier. Input chroma burst amplitude can be between i 30 and 600 mVp.p | ¥ \\ Fi L==s===a a 5 10 ee Vertical Sync Output — An open collector output requiring _ an external pull-up. Output is an active low pulse, 500 us Vertical S9ne- 4 wide, occurring each field. Timing of this pulse depends | on Bit $78-7. a Cc io7 ‘SCL — Clock for the 12C bus interface. See Appendix C for From MCU > 5” a specifications. Maximum frequency is 100 kHz. Tae SDL — Bidirectional data line for the I2C bus interface. As TolFomMcu 6} oe an output, itis an open collector. (Write Address $8A,

1 Read Address $88)

7 il Field ID — TTL level output indicating Field 1 or Field 2 | Polarity depends on state of Bit $78-7 (Vert. Sync Delay). | 100k See Table 11 and Figure 33 and 34. Fit 10. Cob i ex ' itp oy L=aa aa Burst Gate - TTL love! output used for external clamps, , as well as internally. Pulse is active high, ~ 3.5 us wide, (Same as Pin 7) with the rising edge = 3.0 us after center of selected | incoming sync pulse +50 Reference Current Input Current supplied to this pin, a | typically 32 yA from + 5.0 V through a 110 ka resistor, 0k | isthe reference current for the calibration circuit. Noise 2quri) $19 + a — t | filtering should be done at the pin. Voltage at this pin is oo = | | typically 1.2V. ty 20k | | 3 8.0K | Lt - | | Quiet Ground — Ground for the horizontal PLL filter ji I is secti | MOTOROLA LINEARV/INTERFACE ICs DEVICE DATA 9-190

MOTOROLA SC (TELECOM) BSE D M@™ 6367253 0086897 760 MNOTS MC44011 PIN FUNCTION DESCRIPTION [ PinNo. | Representative Circuitry Description " eed H Filter ~ Components at this pin fter the output 1 ; | of the phase detector of PLL #1. This PLL becomes | a | phase-locked to the selected incoming horizontal sync. 1 4 | External component values are valid for NTSC and at} - PAL systems. | seo? ese a) oy au 1 fr | z £ Lz 12 ae 1 Filter Switch — An internal switch to-ground which per x mits aitering the fitering action of the components Ake . ai Pin 11 470pF == i Y ftom | Ui tee | a _ _ 1300] 16 FhiCgyn¢ — A TTL level output from PLL #1 ; This pin provides either a square wave equal to Fh x 16 (Same as Pin 7) {~ 260 kH2), or composite sync, depending on the 7 setting of Bit $85-6, _

14 Fh Reference — A TTL square wave output which is

(Same as Pin 7) phase-locked to the selected incomming horizontal sync. The rising edge occurs » 1.3 us after syne center.

18 PyosScs | 15 kHz Return ~ This TTL input receives the output

I of an external frequency divider which is par of PLL #2 | 1 (Pixel Clock PLL). This signal will be phase and een frequency-locked to the Fh signal at Pin 14. If PLL #2 19k 5, a} ook {snot used, this pin should be connected to Retun T C a+ 5.0 V supply. | 8.0 Lia So PLL #2 Filter — Components at this pin fier the | fim j ulput of the phase detector of PLL 2. This PLL becomes | ; phase-locked to the Fh signal at Pin 14. Recommended | | values for fiter components are shown. External 1 < components should be connected to ground at Pin 17. oer 16 b ; lt PLL #2 is not used, this pin should be grounded. iu ee Oo down | Gain_ us Gate L=__

7 GND 3— Ground for the high frequency PLL #2, Signals at

(See power distribution dagram at the end ofthis section.) | ine 15 9 19 should be relerenced fo ths ground 18 ne Pixel Clock Output - Sampling clock output (TTL) for 1 | 200: | external A/D converters, and for the external frequency i | ae divider. Frequency range at this pin is 6.0 to 40 MHz Piel o Crock [18 Output SO | C =: { Dee ee — —__L======se- - 19 Voe3- A + 5.0 V supply (+ 5%, for the high frequency (See power distribution diagram at the end of this section) | PLL #2. Decoupling must be provided from this pin to Pin 17. Ripple on this pin will affect pixel clock jer MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 9-191

MOTOROLA SC (TELECOM) BSE D MM 6367253 0086898 LT? MMMOTS MC44011 PIN FUNCTION DESCRIPTION Se sav FAV Output - Red (in RGB mode), or RY (in YUV mode), &Gain | 0 output from the color difference stage. A pull-up (390 2) to L* 1 * output + 5.0 V is required. Blank level is = +1.4 Vdc. Maximum oi -> 7 amplitude is = 3.0 Vp-p, black-to-white. ee | ‘ 2 G/Y Output - Green (in RGB mode), or Y (in YUV mode), (Same as Pin 20) output from the color ditterence stage (same as Pin 20). | BIU Output — Blue (in RGB mode), or B-Y (in YUV mode), | * | (Same as Pin taut tom he car arte sage cane os Pra i Veca—A+ 5.0 V supply (2 5%), for the color difference ‘GND 2 — Ground for the color difference stage. Signals at Cj FC - Fast Commutate switch. Taking this pin high (TTL | | _- level) connects the RGB inputs (Pins 26 to 28) to the RGB outputs (Pins 20 to 22), permitting an overlay function. The switch can be disabled in software (Bit $80-7).. L-==== 26, 27, 28 oe Blue (26), Green (27), Red (28) inputs — Inputs to I vet the color difference stage. Designed to accept standard L* -- analog video levels, these input pins have a clamp and RGB, 4 sync separator. They are selected with Pin 25 or in Inputs 1 == oe software (Bit $80-7). I] 100 4] __i Li a 2 Input — Luma #2/Composite sync input. This {uma in- I Veet put to the color difference stage is used in conjunction with i — auxiliary color difference inputs, and/or as a sync input. wl HA Clamp and syne separator are provided. 1 =. 9] | “ pycscccs ac B-Y (30), R-Y (31) Inputs — Inputs to the color difference | stage. Designed for standard color difference levels, these | inputs can be capacitor coupled from the color difference RYBY >| outputs, from a delay line, or an auxiliary Inputs T _ signal source. Input clamp is provided. | 100k | i | 32 es Y1 Clamp — A 0.47 uF capacitor at this pin provides } i} 7 SL ope ‘clamping for the Luma #1 output. | “ £PTSh Lo2b==s | | 3 aa Y1 Output - Luma #1 output. This output fromthe PAL | | NTSC/S-VHS decoder is the luma component of the | vt decoded composite video at Pin 1 or 3. Itis internally di- Output rected to the color difference stage. La ~~~ 34 on ee System Select — A multi-ievel OC output which indicates | -_ the color decoding system to which the PAUNTSC System detector is set by the software. This output is used by the Select M441 40 chroma delay lino, Le | MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 9-192

MOTOROLA SC (TELEC om) BSE D MM 6367253 0086899 533 MEMOTS MC44011 PIN FUNCTION DESCRIPTION [ PinNo._| Ropresentative Circuitry | Description 35 ee | Sandcastle Pulse - A multi-level timing pulse output used 1 -- by the MC44140 chroma delay line. This pulse Santaste Hh | ‘encompasses the horizontal syne and burst time. | Lt | | 36, 38 Pscscc = Xtal 2 (36), Xtal 1 (38) ~ Designed for connection of 4x. | | subcarrier color crystals. Selection is done in software.

143 Mit 204A The selected frequency is used by the PAUNTSC

i R lines; and the horizontal calibration circuit. 7M The crystal frequency should be: | | — 14.3 MHz at Pin 36 for NTSC, LI=Iaaaaa 17.7 MHz at Pin 38 for PAL. R= 400.221 Pin 38 R= 300 Qat Pin 36 {See Table 18 for crystal specs.) 37 No Connect - This pin isto be left open. 39 i Ground 1 — Ground for all sections except PLL #2 and the (See power isribuion diagram atthe endo his secon) 40 Veer ~A+ 5.0 V (1: 5%), supply to all sections except PLL (See power distribution diagram at the end of this section) | YECV A” Do Nit mon oe

4 CFS TTT | B-Y Output - Output from the PALINTSC decoder, itis

1] = | typically capacitor-coupled to a delay line or to the B-Y input. This pin is clamped, and filtered at the color By <—{ — subcarrier frequency, 2x, and 8x that frequency. | _ | : L===~ (Same as Pin 41) -Y Output — Output from the PALNTSC decoder. 43 —————— Ident Fitter ~ A 0.1 j.F capacitor fiters the system fl identification circuit in the NTSC/PAL decoder. | ot Hs _ 1 | Zs “4 | —— Crystal PLL Filter - Components at this pin fiter the PLL i t for the crystal chroma oscillator circuit am 01 i pe | = | _ ~ 2200pF \\ | Lia 10, 17, Voc Voce Vecs Power Distribution — The three Voc pins must be 19, 23, 7.0 (40) z0v (24) z0v 19) ‘extemaily connected to + 5.0 V (+ 5%) supply. The tour 24,39, 1 NER TW ™ grounds must be externally tied together, preferably toa | 40 (39, 10) a ground plane. {Dashed lines indicate substrate connection) MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 9-193

Figure 2. Comp. Video Mode Figure 3. S-VHS Mode

5 ENE = Fes a i

Figure 4. Comp. Video Mode Figure 5. S-VHS Mode

2 RACE gE EE

Figure 6. Comp. Video Mode Figure 7. S-VHS Mode

2 KH 5 ao

Figure 8. Comp. Video Mode Figure 9. S-VHS Mode

5 SY) a a

Figure 10. Comp. Video Mode Figure 11. S-VHS Mode Figure 12. (3.58 MHz) Chroma Notch Figure 13. (4.43 MHz) Chroma Notch

88 RT tat i ae

Figure 14. Comp. Video Mode Figure 15. S-VHS Mode Figure 16. Comp. Video Mode Figure 17. S-VHS Mode Figure 18. Comp. Video Mode Figure 19. S-VHS Mode

35 Peaking = 111 oS Peaking = 111

1, FREQUENCY (MHz) f, FREQUENCY (MHz).

Figure 20. Comp. Video Mode Figure 21. S-VHS Mode

5 Not Eg

Figure 22. Comp. Video Mode Figure 23. S-VHS Mode Figure 24. FC Input Current

Figure 25. Horizontal PLL1 Timing/Composite Video Inputs

16 Fh Out I

NOTE: In above wavelorms, all timing is referenced to the center ofthe incoming Sync Pulse at Pin 1 03. ‘Above timings based on a 4.6 18 wide sync pulse. Lower two levels of Sandcaste output alternate, based on video system in elfect. Figure 26. Horizontal PLL1 Noise Gate and Filter Pin

Figure 27. Horizontal PLL1 Timing/R, G, B and Y2 Inputs Lower two levels of Sancoastle output aerate, based on video system in effect.

Figure 28. System Timing/Video Inputs to RGB Outputs

Figure 30. Horizontal Outputs versus Fields (NTSC System)

Figure 31. Horizontal Outputs versus Fields (PAL System) Figure 32. Horizontal PLL2 Timing

7 Determined by

Figure 33. Vertical Timing (NTSC System)

Figure 34. Vertical Timing (PAL System)

for applications involving multimedia, picture-in-picture, and _sync and field identification (Field 1, Field 2) outputs. can be made to saturation; hue; brightness; contrast; _resistors and capacitors, and can be non-precision. (The DACs mentioned in the following description are 6-bits wide. horizontal frequency related output signals, are phase-locked —_are still in effect. Figure 35. PALINTSC/S-VHS Decoder Block Diagram

1 LT seraze6ia |

input is selected by Bit $88-7. Bits $77-6 and $77-7 must _decoding method.

1. The selected signal passes through the sound trap, Table 4. Color System Select

(Pin 34). This output is used by the MC44140 delay line. Table 3. Sound Trap Frequency The color kill setting (SSA = SSB = 1) should be used

6.0 MHz source of color difference signals are applied to the

14.32 MHz 1 The color difference signals (R-Y, B-Y) from the PALINTSC

14.32 MHe 1 [oo | 4eemHe | controls, and then through a series of notch filters before

‘ACC and PAL/NTSC Decoder nominal setting is ~1.3 Vp-p at a DAC setting of 15. of the chroma filter is sent to the ACC circuitwhich detects the _setting for this DAC is 32. for PAL, and a 14.31818 MHz crystal is required for NTSC. _is adjusted. the filter for the crystal oscillator PLL. should be >10 k&2. Sync is not present on these outputs.

internally routed to the color difference stage. Table 6. Luma Delay The inputs (on the left side of Figure 36) are analog RGB, —_and gates indicate the bits used to control those functions. of color difference signals (R-Y and B-Y) with Y1 or Y2.asthe Table 7 indicates the modes of operation.

©) In applications where the color difference inputs are the DAC operation. Table 8. DAC Operation —Color Difference Section outputs, but not the clamp level, nor the amplitude. | only, but not the clamp level, nor the amplitude. Contrast $81-0/5 | Provides gain adjustment (black-to-white) of the Provides gain adjustment of the three outputs. A Gain - Red $82-0/5 Fine tune the Red and Biue contrast levels. Fine tune of the U and V gain levels. uoc $7D-0/5 level of the U and V outputs at ~ mid-scale. Main Saturation $86-0/5 Affects color saturation, except when the RGB in- Affects color saturation levels of the UV outputs. puts bypass this section (YX EN = 0). Does not affect the Y output. Figure 36. Color Difference Stage and Outputs

on the ¥ output only (Pin 21) in the YUV mode. should be set to 32 to bias the U and V outputs to = +2.3 V. The Fast Commutate input (FC, Pin 25) is a logic level The Y output clamp will remain at = +1.4 V in the YUV mode. Commutate Timing diagram.) If Pin 25 is open, that is shown, and (usually) the transistor at Pin 12 is off. The three outputs (Pins 20 to 22) are open-collector, the + 64 is equal to the incoming horizontal frequency. mode, DACs $70 and $7E should be set to 00, which results diagram of Figures 25 and 27. Figure 38. Horizontal PLL (PLL1)

MOTOROLA SC (TELEC om) BSE D MM 6367253 OO869%b 442 MENOTS MC44011 3) Sandcastle Output (Pin 35) ~ This is a multilevel _the D-to-A converter to drive the VCO through switch Sc. The output, at the horizontal frequency, used by the resulting frequency at the output of the divide-by-64 block is MC44140 delay line. See the timing diagram of Figures _then fed to the frequency comparator to complete the loop. 25 and 27. When a sync signal is not present at Phase Detector #1, 4) 16Fh/Csyne (Pin 13) ~ This is a dual purpose output, and at the Coincidence Detector, as indicated by the TTL levels, user selectable. When Bit $85-6 is setto0, coincidence detector’s output (Flag 12), Bit $78-6 should be Pin 13 is a square wave at 16x he horizontal frequency _set to 0. This will cause the switch (Sc) to transfer to the (250 kHz for PAL, ~252 kHz for NTSC). When —_D-to-A converter for two lines (lines 4, 5) in each vertical field, Bit $85-6 is set to 1, Pin 13is negative composite sync, and will maintain the PLL at a frequency near the standard derived from the internal sync separator. See the timing __ horizontal frequency (between 14 to 16 kHz). When lock to an diagram of Figures 25 and 27. incoming sync is established, Bit $78-6 may be set to 1, The first three outputs mentioned above, and Pin 13 when _ disabling the periodic recalibration function, or it may be left set to 16 Fh, are consistent, and do not change duty cycle or set to 0. wave shape during the vertical sync interval. These four It a more accurate horizontal frequency is desired in the outputs will also be present regardless of the presence of a absence of an input signal, Bit $86-6. can be set to 1 (and video signal at the selected input. Bit $84-6 set according to Table 9). This holds the horizontal When Pin 13 is set to Cgync output, it follows the incoming frequency to ~ 15.7 kHz. In this mode, Flag 12 will stay 0, as composite sync format. If there is no video signal present at the PLL will not be able to lock-up to a newly applied external the selected input, this output will be a steady logic high. signal. To reset the system, set $86-6 to 0, write $00 to Loading on these pins should not be less than 2.0 kQ to _—_‘register $00, and then check Flag 12 to determine when the either ground or + 5.0 V. oop locks to an incoming signal Pin 11 is the filter for the PLL, and requires the components shown in Figure 38, and with the values shown in the Table 9. Calibration Loop application circuit of Figure 42. Pin 12is a switch which allows Crystal the filtering characteristics at Pin 11 to be changed. Switching ee in the additional components (set $84-7 =1) increases the presence of noisy signals. The gain of the phase detector may be set high or low, On initial power up, Bit $86-6 (PLL1 EN) is automaticall depending on the jitter content of the incoming horizontal get to 4, engaging the 900-6 (Ft oop Sontinuocaly Shi ee ee echt toe Stopes usualy condition will remain unti this bit is set to 0, and $00 is written low gain seting (S89-6 ~ 0) should be used. When the video to ragister $00, as part of the initialization routine. 9 source is, for example, a VCR, the high gain setting may be _—_- Pixel Clock PLL (PLL2) preferable to minimize instability artifacts which may show The second PLL, depicted in Figure 39, generates a high up on the screen. frequency clock which is phase-locked to the horizontal The gating function ($77-2) provides additional control frequency. where the stability of the incoming horizontal frequency is in question. With this bit set to 0, gating is in effect, causing the phase detector to not respond to the incoming sync pulses Figure 28, Pixel Clock PLL. (PLLZ) during the vertical interval. This reduces disturbances in this Votege E Fag 19,(¥00 4) PLL due to the half-line pulses and their change in polarity. Mentor _}—» Fag 20 (VCO LO} The gating may be disabled by setting this bit to 1 where the Beain CO ain timing of the incoming sync is known to be stable. The gating ftom PLLA $837 | ‘FO cannot be enabled if the phase detector gain is set high Up + | ($83-6 = 1). Fenecy (> Oharge veo [=] op Calibration Loop Comparacr jDow yj Pm |p f #7 The calibration loop (upper left portion of Figure 38) <] maintains a near correct frequency of this PLL in the absence ~<] of incoming syne signals. This feature minimizes re-adjustment and lock time when sync signals are —---ti---— ————[is}—-——— re-applied. The calibration loop is similar to the PLL function, om PLZ Filer Piel receiving one frequency from the crystal (either 4.43 MHz or (Clock

3.58 MHz) divided down to a frequency similar to the Pog

standard horizontal frequency. Bit $84-6 is used to set the bal tT Freaierey frequency divider to the correct ratio, depending on which 'S7S0H2 = Dondor crystal is selected (see Table 9). The output of the frequency comparator operates an up/down counter, which in turn sets MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 9-210

Pin 16 (which is the input to the VCO) is therefore determined temperature, supply voltage, or manutacturing distribution. with Bit $83-7. Low gain is obtained by setting this bittoa1, 1.0 k®, with 10 k@ recommended for most applications. low frequencies, so as to keep the VCO's input voltage ina _tields (CB1, CA = 11). voltage is outside this range, Flag 19 or 20 will switch high, _$77-0 and $77-1, according to Table 10. VCO, which should be done if the pixel clack is not used. When not used, Pin 18 will be at a constant low level. provides a vertical sync pulse and a field identification signal, Flag 15 should be checked after 8 fields for vertical lock-up. Figure 40. Vertical Decoder will still occur every 525 or 625 lines generated by the rasioL Field 1D + ‘Une Counter E i selected, and Flag 15 will be a steady high.

Table 11. Field ID Output ” these pins, sync may be present on any one or all three. ee | High When Y2 is selected, sync information on Pin 29 is used. Table 12. the video information. Corporation. in simple terms, I2C is a two line, multimaster functions as a master. Figure 41. 12C Bus Interface and Decoder

5 Address | Write

when applied video signals are changed. A block diagram of however, can be done anytime.

1. The first byte is always the write address for the —_ followed by an acknowledge. The third byte is the operative
2. The second byte defines the sub-address register _a third acknowledge.
3. The third byte is the data for that register. $88, and $00. 14 of the registers use Bits 0-5 to operate

and if the address is correct ($8A), an acknowledge is assignments of the registers. Table 13. Sub-Address Register Assignments Description section). Table 15 provides an explanation of the _the Applications Information section.

MOTOROLA SC (TELECOM) BSE D MM 6367253 0086920 973 MEMOTS MC44011 ___ Table 14. Control Bit Description [owe —[ ram] onston S77 S-VHS-Y | Set to 0 for normal Composite Video inputs at V1 and/or V2 (Pins 1, 3). Set to 1 for S-VHS (YC) ‘operation. When 1, the Y-input at the selected video input (V1 or V2, selected by Bit $88-7) bypasses the intial luma delay line, and associated luma/chroma filters and peaking. The signal passes through the second luma dolay, adjustable with Bits 01-03, Luma is output at Pin 33. $776 S-VHS-C | Set to 0 for normal Composite Video inputs at V1 and/or V2 (Pins 1, 3). Setto 1 for S-VHS (YC) | operation. When 1, the chroma input at the non-selected video input (V1 or V2 by Bit $88-7) is di- rected to the ACC loop and PALINTSC detector. Color difference signals are then output at Pins 41 and 42 Set to 0 for a Vertical Sync output rate of 50 Hz. Set to 1 for 100 Hz. Useablo in PAL systems only. s77-4 T2GATE | When set to 0, the pixel clock charge pump (PLL2) operation is inhibited during the Vertical Retrace to minimize momentary instabilities. When set to 1, PLL2 operation is not inhibited $773 BLCP GATE | When 0, Vertical Gating of the black level clamp pulse during the Vertical Retrace occurs to minimize momentary instabilities. The Vertical Gating can be inhibited by seting this bit to 1 372 TYGATE | When set to 0, the horizontal PLL's phase detector (PLL1) operation is inhibited during the Vertical Retrace to minimize momentary instablities. When set to 1, the phase detector is not inhibited. If PLL1 gain is high (Bit $83-6 = 1), gating cannot bo enabled €B1,CA1__| Sets the Vertical Timebase operating method according to Table 10. $787 36/68 4s ‘When 0, the time delay from the sync polarity reversal within the Composite Syne to the leading ‘edge of the Vertical Sync output (Pin 4) is 36 us. When 1, the time delay is 68 js. (See Figure 33 and 34) $786 Calkili When 0, the Horizontal Calibration Loop is enabled for two lines (lines 4 and 5) in each field When 1, the Calibration Loop is not engaged. Upon power-up, this bitis ineffective (Calibration Loop is enabled) until bit $86-6 is set to 0, and register $00 is set to $00. HI This bit is not used in the MC44011, and must be set to 1 This bit is not used in the MC44011, and must be set to 1 S7A7 Xtal | when 0, the crystal at Pin 38 (17.7 MHz) is selected. When 1, the crystal at Pin 36 (14.9 MHz) 9) Ti s7A6___| __SSD_| This bitis not used in the MC44011, and must be set 10 0. $78-7,6 Used to set the Sound Trap Notch fer frequency according to Table 3. $7C-7, 6870-6 | SSC, SSA, SSB | Sets the NTSC/PAL decoder to the correct system according to Table 4 $70-7$7E-7,6 | P1,P2,P3__| Sets the Luma Peaking in the decoder section according to Tabie 5, (See text) $7-7,6$80-6 | D3,D1,02 _ | Sets the Luma Delay in the decoder section according to Table 6. (See text) $80-7 RGBEN ‘When 0, permits the RGB inputs (Pins 26 to 28) to be selected with the Fast Commutate (FC) input (Pin 25). When 1, the FC input is disabled, preventing the RGB inputs from being selected. When the RGB inputs are selected, the Color Difference inputs (Pins 30, 31) are deselected. Y2EN When 1, the ¥2 Luma input (Pin 28) is selected. When 0, itis deselected. YreN When 1, the Y1 Luma Signal (provided by the decoder section to the color difference section) is selected. When 0, itis deselected $827 YUV EN When 0, Pins 20 to 22 provide RGB output signals. When 1, those pins provide YUV output signals $826 YXEN Effective only when the FGGB inputs are selected. When 0, the RGB inputs (Pins 26 to 28) are irected to the RGB outputs (Pins 20 to 22) via the Contrast and Brightness controls, When 1, the RGB inputs are directed through the Color Difference Matrix, allowing Saturation control in addition tothe Brightness and Contrast controls. See Figure 36. ‘When 0, the gain of the pixel clock VCO (PLL2) is high (50 WA). When 1, the gain is low (20 1A). ["se36 | LtGain | _When0, the Horizontal Phase Detector Gain (PLL1) is low. When 1, the gain is high $04.7 H Switch | When 0, Pin 12s open. When 1, Pin 12 is internally switched to ground, allowing the PLL1 fiter operation to be adjusted for noisy signals. oo SSSSSSSSSSSSSSSSSSsSSSSSSSSSSSsSssssFsssSSse MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 9-214

Table 14. Control Bit Description (continued) Calibration Loop. For NTSC systems, set to 1. For PAL systems, set to 0. $86-7 Vin Syne When 1, Composite Sync at the selected Video input (Pin 1 oF 3) is used forall internal timing. (PLL). Setting this bito a 1 will disable the Horizontal Loop, and engages the Calibration Loop. timing, When 0, the Syne source is selected by Bits $86-7 or $88-6, See Table 12. (uma) input, and Pin 1 is the chroma input. When this bits 1, Pin 1 is the luma input, and Pin 3 is. Table 15. Control DAC Description color decoding accuracy. Nominal setting is 32. $79-5/0 Used to balance out reference errors of the color subcarrier, primarily for NTSC. Nominal setting is 32. Color, similar to, but not to be confused with, hue. Used to adjust the gain of the three outputs. In RGB mode this is the Contrastcontrol. similar 0, but not to be confused with, hue. $84-510 Used to adjust the brightness of the three AGB outputs. In YUV mode this DAG atfects only Y output (Pin 21). 987-610 Used to adjust the saturation of the R-Y, 8-Y outputs (Pins 41, 42) of the Decoder section.

but may be done anytime. A flag read cycle consists of three MC44011 as two 8 bit bytes at clock cycles 10-17 and 19-26. MC44011 ($88) generate the stop bit. (address) is then entered, and if correct, an acknowledge is description of the flags. Table 16. Flag Description

10 Internally set to a Logic 1

‘er up, and will change to a 1 after initialization of control Bit $86-6 and register $00. frequency, will cause the Coincidence Detector to indicate a “not locked” condition. 525 line system (NTSC) is indicated. When low, a 625 line system (PAL) is indicated. block must be selected (set $85-7 = 1), to clear this flag. must be deselected (set $85-7 = 0) to clear this flag. This flag will be high it the VCO is off (DAC $7F = 63). 30 mVp-p, and the correct crystal selected, for lock-up to occur. PAL system identified by the decoder. indicating the decoder recognizes the line-by-line change in the burst phase. When NTSC is applied, this flag is 0.

shown in Figure 42. Except for the crystals, all the components for each pin. Figure 42. Basic Functional Circuit pins, etc.) of 4.0 to 5.0 pF be included when selecting a crystal. Table 18. Crystal Specifications coefficent can be increased if a trimmer capacitor is used for Frequency: NTSC (14.31818 MHz) the load capacitor.

• present, Pin 44 voltage will be =1.3 V.

Series Resistance: < 80.8 (nominally 108) frequency is not affected by the scope probe.

Table 17. External Components 1 PLL1 Filter The 100 KO resistor, and the 0.1 wF and 68 pF capacitors are the filter network for this PLL.

16 FiCsyne | No external components required

14 Fh Ref No external components required. Pixel Clock output to external frequency dvider and wiple A/D converter.

9 Ground ‘Ground or the Color Diference section

26,27,28 | B,G.Rin | Input signals must be capacitor-coupled. The 220 0 resistors protect the pins from ESD and RFI. Q resistor is not required by the MC44011, but depends on the signal source.

31 RY In (00 text)

‘System Sel., For use by the MC44140 delay line. No other external components required. 37 NC No external components required. 39 Ground Ground for Color Decoder section.

42 R-Y Out (see text)

43 Indent. Filter The 0.1 uF ceramic capacitor provides filtering for the Identification circuit.

Table 19. Recommended Initial Settings

78 Tat T2=1

26 to 31), and based on the applied signals at those inputs, coder, is used to help determine if the signal is PAL or NTSC. for setting modes is given in Appendix B. The “initial values” 12 above.

1. The remainder of the flow chart is a recommendation only, must be set to 1 (after Flag 12 reads 0) for this flag to indicate

crystal PLL is not locked, or ifthe horizontal PLL is not locked. from a poor quality tape, or other poor quality source.) and 24 according to Table 20.

2 SSD ($7A-6) is always Set 10. decoding. If the same single PAL video source is always used _ the internal counters. The MC44140 acts on the color difference signals before _—Figure 44 for a suggested circuit. indicate to the delay line which signals are being processed Pin 30. Figure 44. Incorporating the MC44140 Delay Line

1 Xtal 2 ct) oH 3 }Gnd BY In [14

1 RY In

Figure 45. Typical Waveforms

1 Output

Clock Generator within the MC44011 should be shut off by hence the Pixel Clock frequency. determine the need for the MC44145, to a 1, and leave open each switch corresponding to a 0. divider simply divides down the Pixel Clock Frequency so _‘requencies are required. Figure 46. Suggested Frequency Divider

1 Retum aro

1 Clock our [_] — =} SSS 1

clamps, allowing the input signals to be capacitor-coupled. _the appropriate data sheet for details. Figure 47. Connecting to a Triple A/D Converter separation of the luma and chroma components from the filters can also provide the Y and C signals in digital format. benefits are reduced dot crawl, and increased color purity. amps have an internally set gain of 2.

1 Comb Fitter -

MOTOROLA SC (TELECOM) BSE D MM@ 6367253 0086931 7549 M@enoTs MC44011 APPENDIX A Control Bit Summary a Os 1 come Pan “Sag ang Gang ot toe \\ } \\ 1 | im tock 1 | o_o L Ver Tne Covetart "= Cag as 3 corte [eta [4 [ee wo] LL _ss_| o | ciara L a [nfr[my nme | a ope} ay as ~ ‘1 = YUV Outputs oo ee oye [a] woe [se "iter Closes o} 1 |o! wo 707 (ae sane ceo. vs tne Vs Pint Input Control DACs { $78 RY/BY Gain Adjustment [ $82 [Red Contrast Trim 79_|— SsbcarerPhase $08 [le gta im $70 | Bue DC Bias ff $64 [Main Brightness | Tere [Red 0G Bias ~ If $85 [Red Brightness Tim SF Pixel Clock VCO Gain || $86 | Saturation (Color Dit. Section) ("$80 | ~~ Bue Contrast Tim || $87 | Saturation (Decoder) [sei [ Wain Cones | Flags [10 [Internally Set to 1 [| 19 | Pixel Glock VCO Gain too low W Horizontal Loop (PLL1} Enabled lf 20 [Pixel Clock VCO Gain too high [12 | Horizontaltoop nat tacked | 21 | _IntomalySettot 13. |_Internaly Setto0 || 22 | Intematy Settod | tess an 6 nes 23 ac Lopacive [1s [ 7 Werlca Decoder Engaged I| 24 | PAL Signals Detecied 16 | rteraty Settoy | @ Not Used i | Interaty Settor 26 | nterallySetto MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 9-225

| OROLA SC (TELECOM) BSE D MM 6367253 0086932 695 MBNOTS | MC44011 | APPENDIX B Suggested Mode Setting Routine (Simplified) (C Poreron_) saseo7-0 {Pin 25 must be high) Set Chroma Regstrs wth Inia Vales mL eine and Set PAL Mode with < 66 Une Bits $7C-7,6 $76 a 1 Enable Horizontal Timebase on i Sel $2660 Set Register $00 0 $00 No No\\ (Fag 11) Yes ‘NCC (Flag 23) YES Aetwe? Yes Texve Bt STAT No No 7 | » Ganone Ove Set $81.7 accordingly. BasTAT Sap Sou Selet Hotzotal Caloraton “em. Vien 9, 020-0 Froquency Bil $84.6 — SHS? ‘Check Wert. Cour down, L ” See Apo | S781 8776-0 $8470 wna | Select Y.C inputs wn Sele Vio apt wi og bse (ote SS (Flag 12) Pixel Gack No i Rogured? | (=e $8601 we ‘| Leave VCO Of } ‘Yes (S7F Register Set to 63) Close PLY = Sete Sound Wa T Set $7B4,7 | with $7F Register | ‘Select Luma Peak | ‘Output with Bit $85-7 Salat Luma Day = —— Hote, ‘Check Flags 19 & 20, Bits $86.7 87-7, $88 Fag 12) eet wee ‘Aj Cotas, Bightess, Tim, = asnecessay | Set Vert Decoder to Auto Countdown (Set $77-0, 1 = 1) ‘Monitor Flags on @ \\_coninuing ass MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 9-226

MOTOROLA SC (TELECOM) BSE D MM 6367253 0086933 52) mNOTS MC44011 APPENDIX C '2C Description Introduction The |2C system, a patented and proprietary system Data transfer is in 8-bit bytes, and can be in either direction, developed by Philips Corporation, defines a two-wire but not in both directions in one data transfer operation. ‘communication system. The number of devices inasystemis Hardware Aspects limited only by the system capacitance and data rate. Each The system bus consists of two wires, Clock and Data. All device is assigned two unique addresses —one for writingto _—_ devices must have open-collector (or open-drain) outputs. A it, and one for reading from it. Any device may act as a master single pull-up resistor is required on each line, as shown in by initiating a data transfer with any other device (the slave). Figure C1 Figure C1. Basic 12C System ne os Device 1 | Device 2 Device N i AS / a kin <J va | one va | a > Oki > > Ck Ou >— ~ | Ok Out ak OK —< chou Data in <i J oaaine-< Le d i io” > Data in Data Data Data Data Out. Data Out Date Out Devices such as the MC44011, which never act as a _ pulling Data low during this clock time. If the master does not master, need not have the output drive transistor at the Clock _receive a proper acknowledge, it can terminate the operation. pin. Nominal value for Rt and R2 is 10 kQ, but can be After the first acknowledge, the role of the two devices different to account for system capacitance at high data rates. depends on whether itis a Write or a Read operation, but the VR is a switching threshold for input signals. master always supplies the clock. The significant electrical characteristics are as follows: — Ina Write operation the master is the transmitter, and the — Maximum data rate (Clock frequency) is 100 kHz; slave is the receiver. = VoL max is 0.4 V when sinking 3.0 mA; — Ina Read operation the slave is the transmitter, and the — ViL max is 0.3 x Vp, but at least +1.5 V; master is the receiver. — ViH min is + 3.0 V for a + 5.0 V system, or 0.7 x Vp for The transmitter then sends the next 8-bit byte. At the 18th other supply voltages. Clock Pulse (and every 9th clock pulse thereafter), the = The maximum input current at Clock and Data at VoL. transmitter releases the Data line, and the receiver ‘max (when they are inputs) is -10 yA; acknowledges by pulling Data low. There is no limit to how — The maximum input current at Clock and Data at0.9xVp _— many bytes may be sent after the address. (when they are inputs) is +10 WA: When all data is transferred, the Data ine must be ~ The maximum pin capacitance is 10 pF: released by the transmitter so that the master can set the — Maximum bus capacitance is 400 pF. STOP condition. This is done by first pulling Data low (during Data Transfer clock low}, then releasing Data high while clock is high. After Prior to initiating a data transfer, both lines must be high (all this, the bus is free for any other device to initiate a new data drive transistors off). A device which initiates a data transter _ transfer. assumes the role of the master, and generates a START —_pefinitions. Condition by taking the Data line low while Clock is stil high. Master - The device which initiates a data transfer (regard- At this time, all other devices become listeners. The master —_ jess of the data direction), generates the clock, and termi- will supply the clock for the entire sequence. nates the transter. * The master then sends the 8-bit address by operating both Slave — The device addressed by the master. the clock and data lines. Data must be stable during the —_Trangmitter - The device which supplies data to the bus. clock's high time, and can change during the clock’s low time. Receiver — The device which receives data from the bus. The MSB is sent first. The address must end in a 0 if itis a Notice that the master is not necessarily the transmitter, Write operation (data transfer from master-to-slave), and it and the slave is not necessarily the receiver. must end in a 1 if it is a Read operation. Other ‘At the Sth Clock Pulse, the master must release the Data 2 line high, and the slave must provide an acknowledge bit by For additional information on the I2C bus specifications; modes of operation; arbitration; and synchronization, contact Philips Corporation. MOTOROLA LINEARVINTERFACE ICs DEVICE DATA 9-227

filter components. For a more in depth explanation, the refer and similar to a 2nd order loop. Figure 01. PLL2 Basic Configuration wi = 15750 x 2p = 98960 rad/sec (input frequency). veo | \\ R C2 margin, a reasonable value can be 15 to 20 or higher.

1572 K = Ko x Ipx Ri(2nN)

— In spite of the samples nature of the loop, a continuous calculates to 18 nF, and C2 calculates to 1.8 nF. ~ Ripple on Vo (tilter pin) is a function of loop bandwidth en = {(KoIN) x Ip/(2nC) }0-5 = 3520 rad/sec. — The loop is a type Il, 3rd order. However, since C2 is fn = 3520/2n = 560 Hz. 9 small, the pole it creates is far removed from the low @30B = 2 x an = 1120 Hz (valid if & = 0.707). be taken into account, as acquisition will be slower but always and C2. action as soon as the error reaches 2n. (3) Phaso-Locked-Loops by Roland E. Best, McGraw Hill, 1984. (4) AN-535, Phase-Locked-Loop Design Fundamentals, Motorola.

MOTOROLA SC (TELECOM) 6SE D MM 6367253 0086935 3T4 MENOTS MC44011 GLOSSARY Aspect Ratio ~ The ratio of the width of a TV screen to the ines in PAL systems. An interlaced system is typically height. In standard TVs, itis 4:3. In HDVT it will likely be 16:9. composed of two fields. Back Porch - The blanking time after the sync signal during Front Porch ~ The blanking time immediately before the which the color burst is inserted. syne signal Blank, Pedestal — The signal level which is either at black, or Horizontal Syne ~ The negative going sync pulses at the slightly more negative than black ("blacker-than-black"), and _ beginning of each line. The pulses indicate to the circuit to is used to turn off the screen dot during retrace. Also referred begin sweeping the dot across the screen. toas the pedestal. Hue — A measure of the correctness of the colors on a Brightness - A measure of the DC levels of the uma _screen. component. Changing brightness will change the minimum Interlaced System — A method of generating a picture on the and maximum luma levels together. screen whereby the even number lines are processed, and Burst - The 8 to 10 cycle sine wave which is inserted in the _then the odd number lines are processed, thereby completing back porch. It's frequency is the color subcarrier (3.58 MHz —_a full picture. or 4.43 MHz), and is used as a phase reference for the color IRE - Abbreviation for international Radio Engineers, it is the decoder. amplitude unit used to define video levels. In standard NTSC Burst Gate — A signal identifying the time during which the _ signals, blank-to-white is 100 IRE units, and blank-to-syne tip C, Chrominance - The color component of the video signal. Luma, Y ~ The brightness component of the video signal. The color is determined by the phase of the chrominance Usually abbreviated “Y", it defines the shade of gray in a component relative to the burst signal black-and-white TV set. In color systems, it is composed of Clamping - A process which establishes a fixed DC voltage 0.30 red, 0.59 green and 0.11 blue. level, usually during the back porch time. NTSC - National Television System Committee. This Color Difference Signals - B-Y, A-Y, also designated as committee set the color encoding standards and format for Uand V. television broadcast in the United States. Color Decoder — A circuit which separates composite video PAL — Phase Alternating Line. A color encoding system in into Red, Blue, and Green, luminance, and sync signals. which the burst is alternated 90° each line to help Color Encoder — A circuit which combines Red, Blue, and COMpensate for color errors which may occur during Green, luminance, and sync signals into composite video. transmission. This system is popular mainly in Europe. Comb Filter - A mult:-bandpass filter which separates the Pixel The smallest picture element, or dot, on a screen. Itis luma and chrominance components from the video signal, determined by the design of the CAT, as wall as the system without sacrificing bandwidth. bandwidth. Component Video, YUV — A format whereby the video RY, B-Y — Referred to as color difference signals. These are information is kept as separate luma, R-Y, and B-Y signals _two of the three signals of component video. When combined (YUV). Vis the same as B-Y, and V is the same as RY. with Y, the full color and luminance information is available. Composite Sync — A sync signal which combines horizontal Retrace - The rapid movement of the blanked dot from the and vertical syne information, The waveform is made up of ‘screen's right edge to the left edge so it can start scanning a regularly spaced negative going pulses for the horizontal ‘NeW line. It is also the rapid movement from the lower right sync, and then half-line pulses and polarity reversal to ofner to the upper left corner during vertical blanking indicate the vertical syne and retrace time. RGB ~ The three main colors (red, blue, green) used in the Composite Video - The video signal which consists of sync, acquiring, and subsequent display of a video signal. back porch, color burst, video information (Iluma and chroma), ‘S-VHS ~ A format whereby the video information is kept as and front porch. This is the signal normally broadcast by TV separate luma and chroma signals (Y and C). stations. Sandcastle - A signal which indicates the horizontal Contrast ~ A measure of the difference between minimum blanking time. It encompasses the front porch, sync, and and maximum luma amplitudes. Increasing contrast back porch. Two amplitudes distinguish the front porch + produces a “blacker” black and a “whiter” white. sync time from the back porch. dB - A power or voltage measurement unit, referred to Saturation ~ A measure of the intensity of the color on a another power or voltage. It is generally computed as: screen. Also related to its purity. 10x log (P1/P2) for power measurements, and Syne Separator — A circuit which will detect, and output, the 20 x log (V1/V2) for voltage measurements syne signal from a composite video waveform. Fleld ~ One of the two or more equal parts into which a frame _Vertical Syne ~ The synchronizing signal which indicates to is divided in an interlaced system. the circuitry to drive the dot to the upper left comer of the Frame — The information which makes up one complete _screen, thereby starting a new field, This signal is derived picture. It consists of 525 lines in NTSC systems, and 625 from the composite sync. MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA 9-229