MC4319

MC4316 MOTOROLA | Alldatasheet

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WC4316 © MC4016 MOTOROLA SwcAst7 ¢ der? \\MC4318" 0 M4018 — ~MC4319 © MC4019 PROGRAMMABLE MODULO-N COUNTERS PROGRAMMABLE MODULO-N oo COUNTERS The monolithic devices are programmable, cascadable, modulo-N-counters. The MC4316/4016 can be programmed to divide by any number (N) from 0 thru 9, the MC4318/4018 from O thru 15. The MC4317/4017 consists of a modulo 2 counter which can be programmed to divide by 0 or 1 and a modulo 5 counter which can be programmed to divide by any number from 0 to 4, LSUFFIX The MC4319/4019 contains two modulo 4 counters which can be (CERAMIC PACKAGE programmed to divide by any number from 0 to 3. CASE 620 ‘The parallel enable (PE) input enables the parallel data inputs D0 thru D3. All zeros are entered into the counter by applying a logic “0” level to the master reset (MR) and PE inputs. This causes the counter to stop counting (count = 0). All data inputs are independent of the logic level of the Clock. conn ence Modulo-N counters are useful in frequency synthesizers, in CASE eso phase-locked loops, and in other applications where a simple method for frequency division is needed. All Types: Input Loading Factor: Total Power Dissipation = PSUFFIX Clock, =2 250 mW typ/pkg_ PLASTIC PACKAGE D0, D1, D2, 03, Gate = 1 Propagation Delay Time: CASE G8 MR =4 Clock to Q3 = 50 ns typ Output Loading Factor = 8 Clock to Bus = 35 ns typ (MC4316/4016 (MC4317/4017 ac 161 Veo mcasie/4018 ai 169) Vcc 1Mic4319/4019 03 2 6a osj2 sae 3 14 02 Voo=Pin 16 recs ‘ape Vec=Pin 16 Gate Cha ar Gnd=Pin 8 Gate C4 13[1Clock2 © Gnd=Pin 8 bo Cs 127) Bus otis 120) Bus clock 6 nfo Clock 1 CF] 6 nfo ls | oC wh ma Macestev4018 oO? wow Gnd (Je gptjar Gnd 8 sar 3 | as [a2] a1 [a0] nacestmaots 1 via]a “ 1] 1) 0 (MC4317/4017 Mcas164016 13 rio}1 COUNT Fax | ao | Byes |2 count eristeterel | #8 [oo |e | aH 9 o}o|1 @ |ifofof: 8 rjo}o}o 8 Ojojo Z ypopryrye 7 yeyrerys [ cour Fm 6 jolilijo 6 joli}ijo COUNT [ourrar | 5 jolifol|1 5 |olifo|1 [as | a [ar | count Po Tar

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SWITCHING TIME TEST CIRCUIT AND VOLTAGE WAVEFORMS Scope and output to scope must be.

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Mc4316/4016, MC4318/4018 Operation of both counters is essentially the same. The _zero state, preset data may be changed while clocking is, MC4316/4016 has a maximum modulus of ten while the occurring. Ifit is necessary to enter a new number before MC4318/4018 is capable of dividing by up to sixteen. _the counter has reached zero this can be done by mo- Minor differences in the programming procedure will be mentarily taking PE low. Countdown will continue from covered in the discussion of cascaded stages. the new number on the next positive clock transition. Suitable connections for operating a single stage are The counters can be made to divide by 10 (MC4016) shown in Figure 1, as well as appropriate waveforms. or 16 (MC4018) by inhibiting the preset logic. This may ‘The desired modulus is applied to the data inputs D0,D1,_—_be done by either holding the gate input high or by hold- D2, and D3 in binary (MC4018) or binary coded decimal ing the bus line low. {MC4016) positive logic format. If a number greater than The normal connections for cascading stages are in- nine (BCD 1001) is applied to the MC4016, it treats the dicated in Figure 2, with the appropriate waveforms. Note most significant bit position as a zero; if for example, _that the gate input of each stage is connected to the clock; binary fourteen (1110) were applied to an MC4016, the —_—_ail bus outputs are tied to one of the internal pullup re- counter would divide by six. BCD eight is programmed —_sistors, R. The total modulus for cascaded MC4016s is in Figure 1. As PE is taken low the states on the parallel determined from Nz = No + 10Ny + 100Nz +...; NT inputs are transferred to their respective outputs. Sub- for MC4018s is given by Nt = No + 16Ny + 256N2 ‘sequent positive transitions of the input clock will dec- +... Stated another way, the BCD equivalent of each rement the counter until the all zero state is detected by decimal digit is applied to respective MC4016 stages the bus gate. The resulting positive transition of the bus while the data inputs of the MC4018 stages are treated line is internally inverted and fed backto the preset gating as part of one long binary number. The difference in circuitry but does not yet preset the counter since the programming is illustrated in Figure 2 where Ny = 245 gateclock input is still high. As the clock returns to the _is coded for both counter types. low state the counter is set to the programmed state, Cascaded operation can be further clarified by referring taking the bus line low. The net result is one positive _to the timing diagram of Figure 2. For the MC4016, count- pulse on the bus line for every N clock pulses. The output —_ing begins with the first positive clock transition after the pulse width is approximately equal to one clock pulse data has been set in. After the five clock pulses, the least- high time. significant stage has been counted down to zero. The bus Operation will continue in this fashion until the dataon _—iline does not go high at this time since the three bus the programmable inputs is changed. Since the preset _terminals are wire-ORed and the other two stages are not circuitry is inhibited except when the counter is in the _in the zero state. Since no reset occurs, the next positive FIGURE 1 — SINGLE-STAGE OPERATION fre a0 Gi a? a3, tox fin jc To esoreise | | s. 8 MA00 D102 03 0001 [+ 8 Puts ——>| fin =o ° =e co f e LP UP Lr u —U ee | ri T i Hi os n In n four fl fl 6-9

OPERATING CHARACTERISTICS: Mc4316/4016, MC4318/4018 clock edge advances the least significant stage to the nine viding by ten. Each pulse out of the second stage dec- (1001) state, causing the second stage to be decremented. rements the third until it reaches zero. At this time the The process continues in this manner with the least ‘sig- bus line goes high; it remains high until the clock goes nificant stage now dividing by ten. The second stage low, causing all three stages to be reset to the pro- eventually counts down to zero and also reverts to di- grammed count again. FIGURE 2 — CASCADED OPERATION as 8 ( e} Is 8 four = re ee | LET rs _ " =e oe TAMAMAULTAAUTALL"TALA oo PLILLAN ALAN tin Ir oe A A A Al Al r ove -— > - r [~~ r 023 — H a 30 — : a 6-10

MC4316 thru MC4319. MC4016 thru MC4019 OPERATING CHARACTERISTICS: MC4316/4016, MC4318/4018 2 [ 6p four = 2 Smamroors 12019 | S waz 071922 023" © wy 050 951 032 O33" LSD. - ae ae | WL NM-M INTUTE WULUY Y u WUUUL i er Aer on] [> ._r _| | 6 ost | || 022 (rl 6-11

OPERATING CHARACTERISTICS: Mc43164016, Mc4318/4018 Maximum operating frequency of the basic MC4016/ a count-down cycle is shown in expanded form. The 4018 counter is limited by the time required for repro- counter parallel inputs are assumed to have N = 245 ‘gramming at the end of each countdown cycle. Operation _—_applied. Timing is not shown for the third stage since it can be extended to approximately 25 MHz by adding an _—_—ihas already been counted down to the all zero state. As “early decode” feature as shown in Figure 3. The appro- _the next-to-least significant stage reaches zero, the com- priate connections for three stages are shown; however _—_—mon bus line goes high. Count down of the least signif- Up to eight stages can be satisfactorily cascaded. Note _icant stage continues until the “two” state is reached. the following differences between this and the non- This condition causes the remaining D inputs to the flip- extended method: the counter gate inputs are not con- _flop to be high. The next-to-last clock pulse of the cycle nected to the input clock; all Parallel Enables are con- ‘then triggers the flip-flop Q output high. G simultane- nected to the O output of a type D flip-flop formed by —_ously takes the parallel enable of al stages low, resetting gates G1 through G6; the bus terminal of the least sig- the programmed data to the outputs. The next input pulse nificant stage is grounded; all other bus terminals and —_—_clocks Q (foy¢) back to the zero state since the data inputs one internal resistor, R, are connected together and serve _to the flip-flop are no longer all high. The positive output 8 a data input to the flip-flop. Four additional data inputs pulse is one input clock period in duration. Note that are provided for decoding the “two” state of the least _—_ division by N equal to 1 or 2 is not available using this significant stage. Circuit operation is illustrated in the method. waveforms of Figure 3 where the timing for the end of OPERATING CHARACTERISTICS 1MC4317/4017, MC4319/4019 ‘The MC4317/4017 consists of amodulo2and.amodulo —_-must be disabled by programming it to zero (D1, D2, and 5 programmable counter, The MC4319/4019 contains two D3 grounded). Likewise, to use the device as a modulo modulo 4 programmable counters. Both parts are imple- __‘§ programmable counter the modulo 2 counter must be mented in the same manner as the MC4316/4016 and —disabled (D0 grounded). Operation of the MC4319/4019 MC4318/4018, however in these devices the output of the _is similar in that the modulo 4 counter not being used appropriate flip-flop is disconnected from the input ofthe must be disabled by programming it to zero (D0 thru D1 ‘next flip-flop. This input is then brought out asthe second ——_grounded or D2 and D3 grounded). clock input for the package (see logic diagrams on page When cascading packages for large divide ratios, the 2 of this data sheet). The resistor existing on the MC4316/ most significant Q output of the modulo counter being 4016 and MC4318/4018 is eliminated on the MC4317/4017 _—_used provides the input for the next package and all bus and MC4319/4019 in order not to exceed 16 pins. Elimi- outputs are tied together. This method of connection is nation of the resistor causes no problems because only _—the same as for the MC4316/4016 and MC4318/4018, ‘one resistor is required per divider chain and these parts The MC4317/4017 and MC4319/4019 can be made to will normally be used with the MC4316/4016 and/or —_— perform the same function as the MC4316/4016 and MC4318/4018. In applications where the parts are used MC4318/4018, respectively, by externally connecting the alone, an external resistor is connected to the bus output. _—_last Q output of one counter to the clock input of the To operate the MC4317/4017 as a modulo 2 program- other counter and programming inputs in the normal mable counter, the modulo 5 programmable counter manner. 612

Atypical system application for programmable counters In many synthesizer applications the VCO is operated is illustrated in the frequency synthesizer shown in Figure at VHF frequencies too high for direct division by TTL 4. There the counter provides a means of digitally se- counters. In these cases the VCO output is usually pre- lecting some integral multiple of a stable reference fre- _scaled by using a suitable fixed divide-by-M ECL circuit quency. The circuit phase locks the output, fyco. of 3 as shown in Figure 5. For this configuration, fyco = voltage controlled oscillator to a reference frequency, NMfref, where N is variable (programmable) and M is fref-' Circuit operation is such that fyco = Nfref. where fixed. Design of the optimum loop filter requires that the N is the divider ratio of the feedback counter, input reference frequency be as high as possible where FIGURE 4 — MTTL PHASE-LOCKED LOOP: Vee (aia! ne ! i Cr ee ar ; ne es eye. - ont Pome Uy | | vot ro ort {> ; ‘veo wemes vawcaaes =N Programmable +. ‘Gounter chain Meanie 19 FIGURE 5 — MTTL-MECL PHASE-LOCKED LOOP Vee [ ienienienienietal nz S 1 ! fret | | cee Pump Ch H ly ort—teo oF wesc LI vem Lmcaose 5 OT MC 1658

2 Programmapie M Prescaler

Mcaote—19 1 See Motorola Apolication Note AN-536 and the MC4344/4044 Date Sheet for detaled explanation of overall citcuit operation 6-13

FIGURE 6 — FEEDBACK COUNTERS WITH DUAL counter for division by Nme, and the programmable MODULUS PRESCALER counter for division by Np. The prescaler will divide by (M + 1) until the modulus contro! counter has counted down to zero; at this time, the all zero state is detected Modulus Control and causes the prescaler to divide by M until the pro- Couneer grammable counter has also counted down to zero. When t = Nee this occurs, a cycle is complete and each counter is reset a to its original modulus in readiness for the next cycle. From| +Mor (M+) For this configuration, veo Programmable t Counter . 0 Npe four fout Moc +Nmc “To Phase Detector FoF Comper” With feat Im terms of the synthesizer application, fyco = (MNpe + Nic) fref and channels can be selected every fref by the upper limit is established by the required channel letting Noe and Nmg take on suitable integer values, in- spacing. Since fyco = Nfref in the non-prescaled case, _—_cluding zero. if N is changed by one, the VCO output changes by fref, A simplified example of this technique is shown in Fig- or the synthesizer channel spacing is just equal to fref- ure 7. The MC12013 Dual Modulus Prescaler divides by When the prescaleris used asin Figure, fyco = NMfref, _ either 10 or 11 when connected as shown in Figure 7. If ‘and a change of one in N results in the VCO'changing by _—the E3 and E4 Enable inputs are high at the start of @ Mfrefs i.2., if fre is set equal to the minimum permissible prescaler cycle, division by 10 results; if the Enable inputs channel spacing as is desirable, then only every M chan- are low at the beginning of the cycle, division by 11 re- nels in a given band can be selected. One solution is to _sults. The zero detection circuitry of the MC12014 Counter ‘set fret = channel spacing/M but this leads to more strin- Control Logic is connected to monitor the outputs of the gent loop filter requirements, modulus control counter; this provides a suitable enable An alternate approach that avoids this problem is pro- ‘signal at EO as the modulus control counter reaches its vided by the counter configuration shown in Figure 6.2 terminal (zero) count. The remainder of the MC12014 is it too uses a prescaler ahead of a programmable counter, ‘connected to extend the operating frequency of the pro- however the modulus of the prescaler is now controlled grammable counter chain. by @ third counter, causing it to alternate between M and A specific example of this technique is shown in Figure 'M + 1. Operation is best explained by assuming that all 8. There the feedback divider circuitry required for gen- three counters have been set forthe beginning of acycle: _erating frequencies between 144 MHz and 178 MHz with the prescaler for division by (M + 1), the modulus control 30 kHz channel spacing is shown.2 FIGURE 7 — FREQUENCY DIVISION: f9 = fir” MNpe + Nme i os os Sxory POPT 2 Poet <, m, " Tout [HE werz01a fin Mer2014 ¢

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Figures 11A and 118 show the FM band implemented nel spacing is 2 x 10" Hz when used as a modulo 5 with MC4017 (used as a modulo 5 counter) and MC4016, Programmable counter, and 5 x 10" Hz when used as respectively. The first system has a 200 kHz reference ‘8 modulo 2 programmable counter. The MC4319/4019 is frequency, and the second system has a 100 kHz refer- for applications with a channel spacing of 2.5 x 109 Hz, ence frequency. These systems using the MC4017/19 of- The MC4316/4016 covers Phase-locked loop applications fer the same. advantages over the MC4016/18 as with the where the channel ‘spacing is 1 x 10" Hz. The MC4318/ aircraft band systems. 4018 is used when the most significant digit is between These examples illustrate the desirability of the MC4317/ 9 and 15. 4017 for phase-locked loop applications where the chan- FIGURE 11 — 88 TO 108 MHz FREQUENCY SYNTHESIZER WITH 200 kHz CHANNEL SPACING tuna ta] fret = 200 kHz a nn me ee foe Sait | a | Le a —S open ves ran ooo ove oe os souk somes wonSame tr ctnve ven ane me e cs soot et oe voting a ava uci (a frat = 100 KH vom [sa | == | L | a ie | 6 | ‘wn ‘C4016 mcaors cxenonco ss os vases ronitaame ———souPenm nian arcane n a i esse eae wou soy “8 6-18

b. are : MOTOROLA SC LoGIC LHE O | 6367252 0062450 7 | T-90-20 A letter suffix to the MECL logic function part number is used to specify the package style (see drawings below). See appropriate selector guide for specific packaging available for a given device type. L SUFFIX (LW SUFFIX L SUFFIX CERAMIC PACKAGE FOR CERAMIC PACKAGE CASE 620-09 CASE 623-05 Monae DAAAAAAL it I . PITTI | | 1 pe lalaladalad aiid — : atk r —l a , 5 t e=teal tLe YH dai | etie teeta tee sons: Persecter tira me [eT oe Tso Tote Tea | 1 aes wis ot em nant acs oF TUE Pa tiee Cise bon Tone | EADS WEN FORE Fececcettie tsar] ‘romaine ras srascnar Fetter eet] woe Fetiet retire] — Sat como Fate steer eae) MM Feta Taaat™ | 2 houie tc nstounuso yor Peper tet ge| esate Paras Trae faa Pasar] cenasac on ax cor. [et sages 1 cumasc | Poston ar SeATHG KANE Eeterter tartan] 2 ous rors crs enema Feta irra] touted Feria ere * a Pcterieteetee] | uma aTeA ” fea} PLASTIC PACKAGE ee L SUFFIX CASE 626-04 / 7 CERAMIC PACKAGE eB CASE 632-08 preorerererert—t bn} 1E vA = roe le : | i iv + (e[esnem STs] xO) [e]e2snew © T1739) Fetietisteutei| ,Wesnesaltae[sa] HEPES CHT eae Ti | + Siscne norounen rer as fp {ome Tost Tears Team | 2 OMENSONL TO CENTER OF LEADS WHEN FST ase son Tass 0200] 2 courpotinc oMMensiON: VCH. Fee Ti tase Toe |, fore maski, nowoce Foto {ow Tons Leow] x oyaenson 1 cemencr Lo unen Hieron ita tas] _saucccones, Ee ae ar et euene a Ss ae . 1-26 :

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MOTOROLA SC LOGIC 14E O | 6367252 0082853 ¢ | T-90-20 PACKAGE OUTLINE DIMENSIONS (continued) : L SUFFIX ‘P SUFFIX : CERAMIC PACKAGE PLASTIC PACKAGE . CASE 732-03 . CASE 738-03 yAn—--——"Ad = anaaanesaal } A Sooweerer 4 - * TA ae jt 1

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Le iol Le 1 « hae rey Vt a Fl dan a i Dan (aes [7125] keh, amt feb © swe Gimmape) “see he. Hee eH oes Hea ELEY “acomcsomumcomns Ts-tem {aw (oms toe | + eaosmeyarsen one on. me Foca tas Pome tear| ask [r} 14 tas | 00s | 008s | CORO A SEARENG PGR, A WoL [le to tanec" ogi sc} 2. CONTROLLING GIMENSON: INCH. [o-{~ 2maee | onmasc | MATERAL CONDON. [ce [oaa? Liar forma $ oem] 2. O:MERSION™L" TO CENTER OF LEAD WHEN Catas | iar [oem | onto | ‘2 GUL BO.CONTER OF READE WEN POR (a |" pesese [ob isc} FORMED PARALLEL [s1-om 19m | oma | oo | PAARL Fa [oaar [ema otee | coms] - 4 OMENSION “3” DOES NOT CLUDE MOLD [k-}-318 140s Tous Tere | ‘SAAR RUCEE ECR, (x [am Tass Tone Pow) PUSH, Lee P| Bs Cut ors Far [00 1 908 J Cates 101 Too | e087} D SUFFIX L SUFFIX PLASTIC SOIC PACKAGE ‘CERAMIC PACKAGE CASE 751-03 CASE 758-01 2 acm, a 7 t jit tga a ke eee ner «ht Dalle te Cy eal LES i aces ee a et ef = merits i | a a Earsiatcy ee ee HE Te] "i ncosasoreweommsno | Set let ikem rea, “musa sous Cette beatae) 'Srsaowmumsnrace epagcee ae tena! 2 postose rtenaceronutos orvees [0 Foss Toe [oom Toor} 2 owensioseya AND TOLERANCNG PER ANSE 7 of tao oats cant (olor oo SIr1A 5) [-E }-om 1 125 | cots {208 | YM, 1982. 14187 | 068-0062, 4 CT] 5 SEATING PLANE. Heir tier! Uanittnocs war. cts caine |Last en owas en [2] aie fos 1 Star Fone | DaueNSI0N “A” AND“S™ 00 NOT INCLUDE 920, 08 00m 008 “FORMED PARALLEL Hieteetesteectaa| “taomonisne Pasar Tear Ri 5 cumsorse aio reuscNs HANS tetetetemta| “Se fmomsonsrsnoains | Fy os ar same eae | A 1-29

MOTOROLA SC LOGIC ue o pusezes2 ooszas4 4 i T-90-20 nores: TY ORTUMS 4, ANO TERED ven » Fname TROPOLTUG) WHERE TO OF x0 SwOULOeS ExT PAST ) r= 00Y AT MUD PANG UNE be v Gaiam s TeoreTeus) 2. DM G TRUE POSTON To MEASURED AT OAT SEATING PUKE [= 2. DM R AND U 00 NOT INCLUDE MOLD FROTRUSON ALLORABLE MOLD PROIRUSON sSozs mara ease, i tor 4. Dahon 9 TO.EMAONG ERAN ‘YS 2. c ke $5. CONTROLUNG DaZENSON: Wok. 4 ‘ rE Hac ° i (Yanai TROFTTLOUD) warren [NGS TEAST NSTSTETG) weweo Low Fi | a (Giana © LLOaaTASTO) ufthenmis gvopers) [ean eae oe — fl Petes Toe Tons ea | Ct ae ae aa a a Eefiomerae IL. Gemmoppoxopera Crt e Tao Pose Tae] cerns {diane [rxoraltowel Fra Tae Tone [ose | FN SUFFIX zee re te Forts am | oo Las | PLASTIC PACKAGE Fac} ie f= fone} =| CASE 775-02 Car et ee} rons "DUE TO SPACE UMATATION, CASE 77-08 SHALL BE REPRESENTED BY A aise naive RATHER THAN SHOWING. qe aE onavang pan aatlon be | ETT 2 Daub hk. # xem EO { b nore Roratusonatscise rq bot ow \\* i 2 Sue Peer Be | Bonseanasee. rome nae tL 4 '$. DUENSONING AND TOUERANCNG PR ANS ¥ i Le rust, at TS Ta ewy {6 CONTROLUNG EMERSON: NOH AGRGRTTTRETNT wen ESSE i-— Tees Ted oot A A a seerieite: sri oda lel > enn -— Se bet ioe ae ws Sime ree eeg ahaha oma S ommes (acres = Pome RSS ERTS eenrtarsecsers Whxeeas TiebuteDeD a eeetberaer ent PLASTIC PACKAGE Pettitt CASE 776-02 Ge eS 1-30

. t Loic nye o feaez2s2 coaesss & Bf nes T-90-20 MECL Logic Surface Mount WHY SURFACE MOUNT? ‘Surface Mount Technology is now being utilized to _the latest EIA RS-481A specification. The antistatic offer answers to many problems that have been created embossed tape provides @ secure cavity sealed with a in the use of insertion technology. peel-back cover tape. Limitations have been reached with insertion packages ‘and PC board technology. Surface Mount Technology GENERAL INFORMATION offers the opportunity to continue to advance the State- @ Reel Size 13 inch (330 mm) Suffix: R2 ofthe-Art designs that cannot be accomplished with @ Tape Width 16 mm Insertion Technology. © Units/Reel 1000 Surface Mount Packages allow more optimum device performance with the smaller Surface Mount configu- MECHANICAL POLARIZATION ration, Internal lead lengths, parasitic capacitance and inductance that placed limitations on chip performance Typical have been reduced. The lower profile of Surface Mount Packages allows 5-~6-6-$-$-$ 9-4-4 more boards to be utilized in a given amount of space. . . They are stacked closer together and utilize less total PH eeH HeP) View from ‘volume than insertion populated PC boards. PIN’ tape si Printed circuit costs are lowered with the reduction of the number of board layers required. The elimination or reduction of the number of plated through holes in the Cineay aveation travel board, contribute significantly to lower PC board prices. inear direction of travel ‘Surface Mount assembly does not require the propa- ration of components that are common on insertiontech- ORDERING INFORMATION nology lines, Surface Mount components are sent ini Size:Dovice Type = - directly to the assembly line, eliminating an intermediate 2 Mini Rota Counts avatebin step. - a ‘@ To order devices which are to be delivered in Tape Automatic placement equipment is available that can and Reel, add the appropriate suffix to the device place Surface Mount components at the rate of 2 few number being ordered. thousand per hour to hundreds of thousands of com- ponents per hour. EXAMPLE: Surface Mount Technology is cost effective, allowing the manufacturer the opportunity to produce smaller ORDERING CODE SHIPMENT METHOD units and offer increased functions with the same size MC10100FN Magazines (Rails) product. MC10100FNR2 13 inch Tape and Reel MC10H100FN Magazines (Rails) MECL AVAILABILITY IN SURFACE MOUNT eH CON? i hale on Reel lagazit ils Motorola is now offering MECL 10K and MECL 10KH Mc12016DR2 43 moh Tape and Reel In the PLCC (Plastic Leaded Chip Carrier) packages. MECL in PLCC may be ordered in conventional plastic rails or on Tape and Reel. Refer to the Tape and Reel aN section for ordering details. eee CONVERSION DATA TAPE AND REEL The following tables give the equivalent LO pinouts of

5 Dual-In-Line (DIL) packages and Plastic Leaded Chip Car-

Motorola has now added the convenience of Tape and rier (PLCC) packages. Reel packaging for our growing family of standard Inte- Grated Circuit products. The packaging fully conforms to Conversion Tables 1-31