MC4044

MC4344 MOTOROLA | Alldatasheet

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PHASE-FREQUENCY DETECTOR PHASE-FREQUENCY DETECTOR The MC4344/4044 consists of two digital phase detectors, a charge pump, and an amplifier. In combination with a voltage controlled multivibrator (such as the MC4324/4024 or MC1648), it is useful in a broad range of phase-locked loop applications. The circuit accepts TTL waveforms at the R and V inputs and LsurFx generates an error voltage that is proportional to the frequency CERAMIC PACKAGE and/or phase difference of the input signals. Phase detector #1 CASE 632 is intended for use in systems requiring zero frequency and phase (0-116) difference at lock. Phase detector #2 is used if quadrature lock is desired. Phase detector #2 can also be used to indicate that the main loop, utilizing phase detector #1, is out of lock. Operating Frequency = 8 MHz typ PLASTIC PACKAGE Input Loading Factor: R, V = 3 CASE 646 Output Loading Factor (Pin 8) = 10 Mc4044 only Total Power Dissipation = 85 mW typ/pkg Propagation Delay Time = 9.0 ns typ (thru phase detector) LOGic DIAGRAM PIN ASSIGNMENT Pu uF A uo 40 O85

10 Phase O13

Frequency have acd) ~ 4h vec v Detector | 1 age shu 30 “ O2 ae oF vos wow 10 O eds neo v2 ampite us wo O12 nplfer Frequency of : o Oe 9 Amp in Detector | pz cn 7 2D ouput ° 06 Output Vcc=Pin 14 GND=Pin 7 PHASE DETECTOR CHARGE PUM AMPLIFIER ne Voc © Dat “1 ped Isl we Ds) < t 10k Kes vi Lio ep peed 7 : —T) tog pan Y Vax not to exceed 8.0 Vee 6-20

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Operation of the MC4344/4044 is best explained by in- FIGURE 1 — PHASE DETECTOR #1 FLOW TABLE itially considering each section separately. If phase de- tector #1 is used, loop lockup occurs when both outputs a Lous U1 and D1 remain high. This occurs only when all the Pasa. | negative transitions on R, the reference input, and V, the ons, variable or feedback input, coincide. The circuit responds ot only to transitions, hence phase error is independent of v input waveform duty cycle or amplitude variation. Phase detector #1 consists of sequential logic circuitry, there- [avTavTavpavy > fore operation prior to lockup is determined by initial [ool o1] 11] 10] conditions. m{ 2] 3fa@ When operation is initiated, by either applying power 3 | @| @| to the circuit or active input signals to R and V, the cir- ns een cuitry can be in one of several states. Given any particular 5 2 (7 | 92 ‘starting conditions, the flow table of Figure 1 can be used « fo 1, ° to determine subsequent operation. The flow table in- 8 | Se lan] aa dicates the status of U1 and D1 as the R and V inputs are varied. The numbers in the table which are in parentheses are arbitrarily assigned labels that correspond to stable Use of the table in determining circuit operation is il- ‘states that can result for each input combination. The lustrated in Figure 2. In the timing diagram, the input to numbers without parentheses refer to unstable condi- _—R is the reference frequency; the input to V is the same tions. Input changes are traced by horizontal movement frequency but lags in phase. Stable state (4) is arbitrarily in the table; after each input change, circuit operation assumed as the initial condition. From the timing diagram will settle in the numbered state indicated by moving _—_and flow table, when the circuit is in stable state (4), horizontally to the appropriate R-V column. If the number outputs U1 and D1 are "0" an "1" respectively. The next at that location is not in parentheses, move vertically to _input state is R-V = 1-1; moving horizontally from stable the number of the same value that is in parentheses. For state (4) under R-V = 1-0 to the R-V = 1-1 column, state 8. given input pair, any one of three stable states can exist. is indicated. However, this is an unstable condition and As an example, if R = 1 and V = 0, the circuit will be in the circuit will assume the state indicated by moving ver- ‘one of the stable states (4), (8), or (12). tically in the R-V = 1-1 column to stable state {3). In this FIGURE 2 — PHASE DETECTOR #1 TIMING DIAGRAM we LS US Ur LS EEL i oe ee a ee es a ee Ye] or [ef wr Yeo] mr [er[ 6) [er] 2 [ele [el or ear} es) cer] «7» fear] [eer] 7) fa] (our [eee Ol ceeneeeeees Of eee Ol een El eee Eo (8.09. nm 6 | oe oF Tr LF UF US Ur ou Ce a es es a Gn ee De Ms ne Sy tei] cr faa] er [oer] >> Jerza] er [cer] cr» foray efter] «> fra] [cer] cm [oral \\t6»| > jra (I $< oor LILI LU u ul us oe ~LEFLSELSLSILELUFDLILILrt_r Urb ov TOS wou TL LT «oC reac ooo 6-22

instance, outputs U1 and D1 remain unchanged. The in- _to the fixed phase difference case, but now the duty cycle put states next become R-V = 0-1; moving horizontally _of the U1 waveform varies at a rate proportional to the to the R-V = 0-1 column, stable state (2) is indicated. At _difference frequency of the two inputs, R and V. Itis this. this point there is still no change in U1 or D1. The next characteristic that permits the MC4344/4044 to be used input change shifts operation to the R-V = 0-0 column _as.a frequency discriminator; if the signal on R has been where unstable state § is indicated. Moving vertically to frequency modulated and if the loop bandwidth is se- stable state (5), the outputs now change state to U1-01 —_lected to pass the deviation frequency but reject R and = 1-1. The next input change, R-V = 1-0, drives the cir __V, the resulting error voltage applied to the VCO will be cuitry to stable state (8), with no change in U1 or D1. The —_the recovered modulation signal. next input, R-V = 1-1, leads to stable state (7) with no Phase detector #2 consists only of combinatorial logic, change in the outputs. The next two input state changes _therefore its characteristics can be determined from the ‘cause U1 to go low between the negative transitions of _simple truth table of Figure 3. Since circuit operation re- R and V. As the inputs continue to change, the circuitry quires that both inputs to the charge pump either be high ‘moves repeatedly through stable states (2), (5), (8), (7), or have the same duty cycle when lock occurs, using this (2), ete., as shown, and a periodic waveform is obtained phase detector leads to a quadrature relationship be- ‘on the U1 terminal while D1 remains high. tween R and V. Thisis illustrated in rows a-d of the timing A similar result is obtained if V is leading with respect _ diagram of Figure 3. Note that any deviation from a fifty to R, except that the periodic waveform now appears on _percent duty cycle on the inputs would appear as phase D1 as shown in rows e-h of the timing diagram of Figure error. 2. In each case, the average value of the resulting Waveforms showing the operation of phase detector waveform is proportional to the phase difference be- #2 when phase detector #1 is being used in a closed tween the two inputs. In a closed loop application, the loop are indicated in rows ej, When the main loop is error signal for controlling the VCO is derived by trans- _ locked, U2 remains high. If the loop drifts out of lock in lating and filtering these waveforms. either direction a negative pulse whose width is propor- The results obtained when R and V are separated by _ tional to the amount of drift appears on U2. This can be a fixed frequency difference are indicated in rows H+! of __used to generate a simple loss-of-lock indicator. the timing system. For this case, the U1 output goes low Operation of the charge pump is best explained by ‘when R goes low and stays in that state until a negative _ considering it in conjunction with the Darlington ampli- transition on V occurs. The resulting waveform is similar _fier included in the package (see Figure 4). There will be FIGURE 3 — PHASE DETECTOR #2 OPERATION v 5 ee | ° fo fo [a Tr} feta tar a R he Cates Te} ae a a SS Ss ee es ee ee ee i 71 1 CC ns A A se woe LO a2 rf 1 ro [- ov Ls SSO a Oo As cs i ma [1 m1 rc rm in ov I~ Lf SST a so 6-23

2 pulsed waveform on either PD or PU, depending on the _and down voltages have equal effects. The pump signals phase-frequency relationship of R and V. The charge _are established by Ves of transistors with milliamperes bump serves to invert one of the input waveforms (D1) _of current flowing. On the other hand, the transistors and translates the voltage levels before they are applied —_—_included for use as a filter amplifier will have very small to the loop filter. When PO is low and PU is high, Q1 will —_—_currents flowing and will have correspondingly lower be conducting in the normal direction and 2 will be off. Ves — on the order of 0.6 volt each for a threshold of Current will be flowing through Q3 and CR2; the base of ‘1.2 volts. Any displacement of the threshold from 1.5 3 will be two Vag drops above ground or approximately _—_volts causes an increase in gain in one direction and a 1.8 volts. Since both of the resistors connected to the reduction in the other. The transistor configuration pro- base of 03 are equal, the emitter of Q4 (base of Q5) will —_—_vided is hence not optimum but does allow for the use be approximately 3.0 volts. For this condition, the emitter __of an additional transistor to improve filter response. This of Q5 (DF) will be on VgE below this voltage, or about —_—_addition also results in a non-symmetrical response since 2.25 volts. The PU input to the charge pump is high _the threshold is now approximately 1.8 volts. The effec- {> 24 volts) and CR1 will be reverse biased. Therefore _tive positive swing is limited to 0.45 volt while the neg- QS will be supplying current to 6. This will tendto lower —_ ative swing below threshold can be greater than 1.0 volt. the voltage at the collector of Q7, resulting in an error This means that the loop gain when changing from a signal that lowers the VCO frequency as required by a _high frequency to a lower frequency is less than when “pump down” signal. changing in the opposite direction. For type two loops this tends to increase overshoot when going from low to high and increases damping in the other direction. FIGURE 4 — CHARGE PUMP OPERATION These problems and the selection of external filter com- Ponents are intimately related to system requirements vee Vee and are discussed in detail in the filter design section. c dr - fee 5 ie . Po Tie 4 ore At BITS RC comer FIGURE 5 — PHASE DETECTOR TEST Po" at Kno | 1 CR? pu cat UF 9 s0yee ue SAE ; a 3 OF res [oP enange ] ene 20x vTVM When PU is low and PD is high, CR1 is forward biased Fame 2| oetece [>| Pume |} ° and UF will be approximately one Vge above ground ceneraror >] #1 OTS S 320 0.018 (neglecting the VcE{sat) of the driving gate). With PD ° ivf high, Q1 conducts in the reverse direction, supplying Pulse Generator a ° base current for Q2. While Q2 is conducting, Q4 is pre- (veriabie delay) = vented from supplying base drive to Q5; with Q5 cut off H199 or Eauly and UF low there is no base current for Q6 and the voltage j-—100 ns > at the collector of Q7 moves up, resulting in an increase en rn in the VCO operating frequency as required by a “pump -oapie up” signal. (or teac) If both inputs to the charge pump are high (zero phase s__SJL— difference), both CR1 and the base-emitter junction of 05 ‘Shown for positive phase angie. Reverse ate reverse biased and there is no tendency for the error ‘And 6 tor negetive phase ange voltage to change. The output of the charge pump varies between one Vee and three Vpe as the phase difference of R and V varies from minus 27 to plus 2m. If this signal 228 isfiteredto remove the high-trequency components, the © ag [ {| Te phase detector transfer function, Kg, of approximately Fa rr | 0.12 voltiradian is obtained (see Figure 5). g 15 Cot pl Ee ‘The specified gain constant of 0.12 voltiradian may not = 180 —1 be obtained if the amplifier/filter combination is improp- 3 a ae | erly designed. As indicated previously, the charge pump 2 128) Loet + delivers pump commands of about 2.25 volts on the pos- 2 1.00. | itive swings and 0.75 volt on the negative swings for a 5 one i mean no-pump value of 1.5 volts. If the filter amplifier is & 078 > 7 rs Ta biased to threshold “on’” at 1.5 volts, then the pump up 0, PHASE DIFFERENCE (RADIANS) 6-24

FIGURE 9 — TYPE 2 SECOND ORDER STEP RESPONSE problems in linear 1oops when the system is out of lock i oa ifthe amplifier output swing is not adequately restricted | Avfoi TI since integrating operational amplifier circuits will latch "7 | [os TT | up in time and effectively open the loop. 1.6} t\\ + ry +- +S The internal amplifier included in the MC4344/4044 > 181 fe Se - +414 may be used effectively if its limits are observed. The 2 sa VX fos | | circuit configuration shown in Figure 10 illustrates the é XMos TN placement of Ry, Rz, C, and load resistor Ry (1 kM). Due 8 13) ia Siti 07 ff t to the non-infinite gain of this stage (Ay ~ 30) and other ? | RS PUT RTT non-ideal characteristics, some restraint must be placed : a PACH on passive component sslacon Foremost is tower ECTSS yo | jimit on the vatue of Rz and an upper limit on Ry. Placed B Ge Boal ee ES = in order of priority the recommendations areas follows 2 asl a5 A - 7) {a) R2 > 50 0, (b) RUR2 < 10, (c) 1k <AI< 5 KA Fo H 20 5 saa i ine t 7 FIGURE 10 — USING MC4344/4044 LOOP AMPLIFIER : | | a t Pa +sov ee! | ial im . ym a WY + Re 1 in Perit i H ca Ail Tan ro + t---js * To o a ~ Ltt] Limit (c) is the most flexible and may be violated with ent lower phase detector gain (Ry < 1 kf). If limit (b) is ex- a ceeded, loop bandwidth will be less than computed and Using relationships 7 and 8, actual resistor values may may not have any similarity to the prediction. For an be computed: accurate reproduction of calculated loop characteristics ‘one should go to an operational amplifier which has suf- Rn, ~ Roky (9) ficient gain to make limit (b) readily satisfied. Limit (a) is Nop2e very important because T; in Equation 5 is in reality com- posed of three elements: Ry = 2 (10) 1 @n Thc (G - +) (12) Although fundamentally the range of Ry and Ro may ™ be from several hundred to several thousand ohms, where gm = transconductance of the common emitter sideband considerations usually force the value of Ry to. amplifier. be set first, and then Rg and C computed. Normally gm is large and Ty nearly equals R2C, but resistance values below 50 {2 can force the phase-com- ce Ker a) Pensating “zero” to infinity or worse (into the right half 6 | Non2Ry plane) and give an unstable system. The problem can be circumvented to a large degree by buffering the feedback Calculation of passive components Rz and C (in syn- _with an emitter follower (Figure 11). Inequality (a) may thesizers) is complicated by incomplete information on _then be reduced by at least an order of magnitude (Rz N, which is variable, and the limits of wp, and ¢ during > 5 2) keeping in mind that electrolytic capacitors used that variance. Equally important are changes in Ky over the output frequency range. Minimum and maximum FIGURE 11 — AMPLIFIER CAPABLE OF HANDLING values of wr and { can be computed from Equations 4 LOWER R2 and 5 when the appropriate worst case numbers are +s0v known for all the factors. Amplifier/filter gain usually determines how much hk phase error exists between fin, and fout. and the filter Re ¢ characteristic shapes capture range and transient per- Yo formance. A relatively simple, low gain amplifier may a | fy—yt usually be used in the loop since many designs are not 1 constrained so much by phase error as by the need to t n + make fin equal foyt. Unnecessarily high gains can cause ---F 6-26

4044's transfer function linearity in the vicinity of FIGURE 24 — LOOP RESPONSE TO VCO NOISE zero phase error between the R and V inputs. . The filter amplifier ground location can be separated = o[=+ =F + FSS from the phase detector ground. 8 rt} d. An “optimum” filter amplifier input threshold of s i approximately two diode drops need not be 2 ‘ established. § || Ts a The filter discussions and relationships developed for 2 [| 7b integrator-log filter sections can be applied to the system =: a ee of Figure 22 and the previously derived equations can be € C17 t_| used to determine values for R1, R2 and C. = LY It may be desirable to split each of the R1 resistors and : wa incorporate a capacitor to ground in a manner similar to Loo prequency that shown in Figure 15. This should improve transient suppression and provide integration of the U1 and D1 signals to better enable the operational amplifier to de- Other Spurious Responses velop corrective error information from very narrow U1 and 01 pulse widths. Spurious components appearing in the output spec- Phase error for the circuit in Figure 22 will result from _twum are seldom due to reference frequency feedthrough input offset voltage in the operational amplifier, resistor _*"0ne. Modulation of any kind appearing on the VCO con- mismatch and mismatch between the phase detector ‘0! line will cause spurious sidebands and can come in output states appearing at U1 and D1. Phase error can _—‘through the loop amplifier supply, bias circuitry in the be trimmed to zero intially by adjusting either the am- control path, panier a ooh aovaitutte eo ete i rn igh sen piifler input offset or one af the RI resistors. supply variation. This should be investigated and its ef- fects considered. Problems of this nature can be mini- VCO Noise mized by operating all devices except the phase detector, oo . charge pump, and VCO from a separate and well isolated Effects of noise within the VCO itself can be evaluated supply, Acommon method uses a master supply of about by considering a closed loop situation with an external 19 or 12 volts and two regulators to produce voltages for noise source, en, introduced at the VCO(Figure 23). Re- the PLL — one for ali the logic {including the phase de- sultant modulation of the VCO by error voltage, ¢, is tector) and the other for all circuitry associated with the second order high pass function: VCO control line.

2 Sideband and noise performance is also a function of

£2. _ ¥__ good power supply and regulator layout. As mentioned en 52, STIKORY , KaKy earlier, extreme care should be exercised in isolating the T2N T2N (23) control line voltage to the VCO from influences other than s. the phase detector. This not only means good voltage = Tres tat regulation but ac bypassing and adherence to good grounding techniques as well. Figure 25 shows two sep- arate regulators and their respective loads. Resistor Rg FIGURE 23 — EFFECTS OF VCO NOISE is a small stray resistance due to a common thin ground pane return for both RLy and Riz. Any noise in Ri2 is now ry 7 reproduced (in a suppressed form) across Ri 1. Load cur- i 7 1 rent from Ri does not affect the voltage across Ri2. EE or Ne | Output Even though the regulators may be quite good, they can Lota [ sarily across the load (unless remote sensing is used). a} FIGURE 25 — LOOP VOLTAGE REGULATION ; Vino vor s. 7 fy 2s Bu S bone euisted This function has a slope of 12 dBioctave at frequencies Return © \\ less than wp (loop natural frequency), as shown in Figure 24. This means that noise components in the VCO above nq will pass unattenuated and those below will have some degree of suppression. Therefore choice of loop natural frequency may well rest on VCO noise quality. 631

culiar to loops where N is variable and greater than 1.

1. Choose input frequency. (fret = channel spacing) 8 = 40 logyg as bed
2. Compute the range of digital division. t+
3. Compute needed VCO range: Design Example (Figure 31)
4. Choose minimum ¢ from transient response plot, Lockup time between channels (to 59%) = 1.0 ms

Figure 9. A good starting point is { = 0.5, Overshoot < 20%.

1. Choose wn from needed response time (Figure 9) Minimum sideband suppression ~ -30 dB
2. Check transient response of {max for compatibility

with transient specification. ‘Thie VEO rare .

1. Compute expected sidebands: MC4324/4024 voltage controlled multivibrator.

out ret pF and the VCO gain, Ky, typically 11 x 108 radisiv. will produce a peak overshoot less than 20%.

1. If step 10 yields larger sidebands than are accept- 5. Referring to Figure 9, overshoot with ¢ = 0.8 will

1. In order to compute C, phase detector gain and R1 if desired additional sideband filtering can be ob- must be selected. Phase detector gain, Kg, for the twined as noted in steps 11 and 12. MC4344/4044 is approximately 0.1 volt/radian with Ry = 1k0. Therefore, 11. By splitting Ry and Co, further attenuation can be gained. The magnitude of C, is approximately: (0.1111 x_ 106) ¢ = ON A) = 1.8 uF 08 08 (2045 x 107110" SC ton ~ (r08)451103) 7. At this point, Rz can be computed: mi 16 Improvement in sidebands will be: Ro Ne asx tedia 10-6 7 1 — (2m x 10: N, 14 eer 8. Smax = Smin apo = 098 V"* 25145 x 1032 min 9. Figure 9 shows that ¢ = 0.98 will meet the settling Nomina! suppression is now - 63 dB. Worst-case is time requirement. 6 dB higher than nominal suppression of - 57 dB. 10. Sidebands may be computed for two cases: (1) with This is well within the - 30 dB design requirement, IL (charge pump leakage current) nominal (100 nA), step 12 is included for completeness only. and (2) with IL maximum (5.0 pA). A value of 5 uA will also be assumed for the amplifier bias current, 12. Attenuation of a second order filter is double that ip. of the single order filter section described in step11.

6 The calculations or a second order filter indicate an

sideband| _ (10 x 10°6)(200V11 x 108) _ 46. 49.3 additional - 56 dB of sideband rejection. Figures 20 fout Imax 6.28 x 108 and 21 show two second order filterconfigurations. ; IR is assigned a value of 10 kf then C may be The sideband-to-center frequency ratio nominally calculated. will be:

01 O14

c= St __94 9.0022 uF seebend = 81 x 95 x 10-3 on (48 x 103104) " fout [nom 10 = 20 log19(17.85 x 10-3) = -35 08 FIGURE 31 — CIRCUIT DIAGRAM OF TYPE 2 PHASE-LOCKED LOOP. Vee vec a < no ‘* tin eo ca | 200) c= wor | meses71 a HLA. lle Lye Qs4t Se ‘ out 12 acaans) s 11142 © 00 61 02 08 60 61 02 02 634

Glock Recovery from Phase-Encoded Data consisted only of alternating “1”s and “0s, the phase- encoded format would result in a waveform equal to one- The electro-mechanical system used for recording dig- half the original clock frequency. If this were applied di- ital data on magnetic tape often introduces random var- rectly to the loop, the VCM would of course move down iations in tape speed and data spacing. Because of this to that frequency. The encoding format insures that there and the encoding technique used, it is usually necessary will be a transition in the middle of each data time. If only to regenerate a synchronized clock from the data during these transitions are sensed they can be used to regen- this read cycle. One method for doing this is to phase- erate the clock. The schematic diagram of Figure 32in- lock @ voltage controlled multivibrator to the data as it dicates one method of accomplishing this. is read (Figure 32). The logic circuitry generates a pulse at the midpoint A typical data block using the phase encoded format of each data cell which is then applied to the reference is shown in row 1 of Figure 33.The standard format calls input of the phase detector. The loop VCM is designed for recording a preamble of forty “0s followed by a sin- to operate at some multiple of the basic clock rate. The gle 1"; this is followed by from 18 to 2048 characters CM frequency selected depends on the decoding res- of data and @ postamble consisting of a 1" followed by olution desired and other system timing requirements. forty “0"'s. The encoding format records a “0” as a tran- In this example, the VCM operates at twenty-four times sition from tow to high in the middle of a data cell. A the clock rate (Figure 33,Row 12). “1” is indicated by a transition from high to low at the Referring to Figure 32 and the timing diagram of Figure data cell midpoint. When required, phase transitions oc- 33, the phase-encoded data (Figure 33, Row 1) is com- ‘cur at the end of data cells. If a string of either consecutive bined with a delayed version of itself (output of flip-flop “0"s or consecutive “1'’s is recorded, the format dupli- A row 3) to provide a positive pulse out of G3 for every cates the original clock; the clock is easily recovered by _transition of the input signal. Portions of the data block straight forward synchronization with a phase-locked are shown expanded in row 2 of Figure 33. Flip-flop A loop. In the general case, where the data may appear in _ delays the incoming data of one-half of a VCM clock pe- any order, the phase-encoded data must be processed _riod, Gates G1, G2 and G3 implement the logicExclusive to obtain a single pulse during each data cell before it is. OR of waveforms 1 and 3 except when inhibited by applied to the phase detector. For example, if the data. DGATE (row 4) or the output of G12 (row 7). OGATE and FIGURE 32 — CLOCK RECOVERY FROM PHASE-ENCODED DATA ata} a o U—s Da fon Poe] — | sN7aLs9a dco Co La! lo: c1.a0 01 a2 a2 =e Us) | {a7 [J ae a fT [58 — eat” Vee 6 69) 001 ied Due Vee o001uF a 0.033 uF ° c passat [A na 100 oF i v fort jeu url «ee | 1 sancaoze H Lo jor mcaosa \\ Lovoar Ue mn anna mann} Timeaoze only oO a3 a0 cil, 61,62, 611,012 sn74ts20 . || SN7ALS90, Numbers in parentheses refer to [I Sravetorme of Figure 32 £ wMera7e 6-35

its complement, DGATE, serve to initialize the circuitry ‘As a rough check on acquisition time, assume that and insure that the first transition of the data block (a lockup should occur not later than half-way through @ 40- phase transition) is ignored. The MC7493 binary counter bit preample, or for twenty 8.34 us data periods. and the G5-G12 latch generate a suitable signal for gating ‘out G3 pulses caused by phase transitions at the end of wnt = (3.05)104(2018.34)10-6 = 5.1 (26) 8 data cell, such as the one shown dashed in row 6. The initial data pulse from G3 sets G12 low and is From Figure 9, the output will be within 2 to 3% of its combined with DGATE in G7 to reset the counter to its final value for wnt ~ 5 and { = 0.707. The filter compo- zero state. Subsequent VCM clock pulses now cycle the nents are calculated by: counter and approximately one-third of the way through the next data call the counter’s full state is decoded by Keky _ oo en G11, generating @ negative transition. This causes G12 Ryn ~ °"" to go high, removing the inhibit signal until it is again and reset by the next data transition. This pulse also resets KakyRo the counter, continuing the cycle and generating a pos- SAE = ion (28) itive pulse at the midpoint of each data cell as required. ¥ ‘Acquisition time is reduced if the loop is locked to a where Kg = 0.115 virad frequency approximately the same as the expected data Ky = (18.2) 108 rad/sivolt rate during inter-block gaps. inFigure 32,this is achieved N = 24 = Feedback divider ratio by operating the remaining half of the dual VCM at wp = (3.05) 104 rad/s slightly less than the data rate and applying it to the ¢= 0.707 reference input of the phase detector via the G8-G9-G10 Kgky _ (0.115)(18.2)108 of data selector. When data appears, DGATE end DGATE Naa 87200 cause the output of G3 to be selected as the reference input to the loop. From Equation 27: The loop parameters are selected as a compromise between fast acquisition and jitter-free tracking once syn- K, (8.72)104 chronization is achieved. The resulting filter component Ric = fery ¥ = iapeihigs = 9:9410-5 values indicated in Figure 32 are suitable for recovering ‘en’ ° the clock from data recorded at @ 120 kHz rate, such as . would result in a tape system operating at 75 i.p.s. with From Equation 28: 8 recording density of 1600 b.p.i. Synchronization is achieved by approximately the twenty-fourth bit time of Ra _ BunN _ 210.707N3.05N104 _ 9 ayy, the preamble. The relationship between system require- Ry Kgky (8.72)104 ments and the design procedure is illustrated by the fol- lowing sample calculation: Let Ry = 3.0 kf; then Ro = 1.5 kf and Assume a —3.0 dB loop bandwidth much less than the input data rate (~ 120 kHz), say 10 kHz. Further, assume (9.34)10-5 8 ‘a damping factor of { = 0.707. From the expression for C= “ones =~ (3.11107! loop bandwidth as a function of damping factor and un- damped natural frequency, wn, calculate wn as: or using a close standard value, use C = 0.033 uF. Now y add the additional prefiltering by splitting Ry and select- a ing a time constant for the additional section so that it 3 dB = on (1 + yet [2+ 4t2+ 4a) (24) is large with respect to R2C2. 6 | or for w_3 dp = (2n)104 rad/s and { = 0.707: OWA TICE = R2C or °n = 06 (3.05)104 rad/s co TOR, ~~ 10130103 3300 pF 6-36

FOUmE 33— THAN DIAGRAM —CLOOK RECOVERY FROM PHABE-ENCODED DATA ~ Nery te rn cme o ey nO no ee e i ec LL ere Data’ a wots (2) Data a - (3) Og | rs | S—_ (4) DGATE | — __ 1 PF (7) oz rs es es oes mae @) Gr 1 re | es | lll 1 7 r i] (11) Qg (vem +24) --SOE T7”H1WWWWTWvWW A 6-37