MC38HC705J2

HC705J2 MOTOROLA | Alldatasheet

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Rev. 1 HC05 MC68HC705J2 TECHNICAL DATA

Rev. 1 iii TABLE OF CONTENTS Section Title Page SECTION 1 INTRODUCTION SECTION 2 PIN DESCRIPTIONS 2.1 V 2.3 SECTION 3 PARALLEL I/O SECTION 4 CENTRAL PROCESSOR UNIT

iv Rev. 1 TABLE OF CONTENTS Section Title Page SECTION 5 RESETS AND INTERRUPTS SECTION 6 MEMORY SECTION 7 TIMER SECTION 8 BOOTLOADER MODE SECTION 9 MC68HC05J1 EMULATION MODE

Rev. 1 v TABLE OF CONTENTS Section Title Page 9SECTION 10 INSTRUCTION SET SECTION 11 ELECTRICAL SPECIFICATIONS

vi Rev. 1

Rev. 1 vii LIST OF FIGURES Figure Title Page

viii REV. 1.0 LIST OF FIGURES Figure Title Page

REV. 1.0 ix LIST OF TABLES Table Title Page

x Rev. 1

MC68HC705J2 INTRODUCTION MOTOROLA 1-1 SECTION 1 INTRODUCTION The MC68HC705J2 is a member of the low-cost, high-performance M68HC05 Family of 8-bit microcontroller units (MCUs). The high-density, complementary metal-oxide semiconductor (HCMOS) M68HC05 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the popular M68HC05 central processor unit (CPU) and are available with a variety of subsystems, memory sizes and types, and package types. The MC68HC705J2 is an expansion of the MC68HC05J1 design. On-chip memory is enhanced with 2 Kbytes of erasable, programmable ROM (EPROM), 112 Kbytes of RAM, and a bootloader ROM.

1.1 Features

The MCU features include the following:

• Popular M68HC05 CPU
• Memory-Mapped Input/Output (I/O) Registers
• 2064 Bytes of User EPROM Including 16 User Vector Locations
• 112 Bytes of Static RAM (SRAM)
• 14 Bidirectional I/O Pins
• Fully Static Operation With No Minimum Clock Speed
• On-Chip Oscillator With Crystal/Ceramic Resonator Connections
• 15-Bit Multifunction Timer
• Real-Time Interrupt Circuit
• Bootloader ROM
• Power-Saving STOP, WAIT, and Data Retention Modes
• MC68HC05J1 Emulation Mode
• Selectable Edge-Sensitive or Edge- and Level-Sensitive External Interrupt Trigger
• Selectable Computer Operating Properly (COP) Timer
• 8 · 8 Unsigned Multiply Instruction
• One Time Programmable 20-Pin Dual-in-Line Package (DIP)
• One Time Programmable 20-Pin Small Outline Integrated Circuit (SOIC)
• Windowed 20-Pin Cerdip

MOTOROLA INTRODUCTION MC68HC705J2 1-2

1.2 Structure

Figure 1-1 shows the organization of the MC68HC705J2 EPROM MCU. RESE T POWER OSCILLATO R SRAM — 112 BY T USER EPROM — 2064 B Y OSC 1 OSC 2 D DV SSV DATA DIRECTION A PORT A PA 5 PA 6 PA 7 PORT B PB0 PB1 PB2 PB3 PB4 PB5 DIVIDE BY 2 15-STAGE MULTIFUNCTION TIME COP TIMER AND ILLEGAL ADDRESS DE T ACCUMULAT O M68HC05 CPU fop DATA DIRECTION B RST PA 2 PA 3 PA 4 PA 0 PA 1 IRQ/VPP INDEX REGISTER STACK POINTE PROGRAM COUNT E 11 0 CONDITION CODE REGISTE 111HI N ZC 00000 0000000011 BOOTLOADER ROM — 239 B Figure 1-1. MC68HC705J2 Block Diagram

MC68HC705J2 PIN DESCRIPTIONS MOTOROLA 2-1 SECTION 2 PIN DESCRIPTIONS This section describes the function of each pin. Figure 2-1 shows the pin assignments. OSC1 1 PB5 PB4 PB3 PB2 PB1 PB 0 VD D PA 0 PA 1 PA 2 PA 3 PA 4 PA 5 PA 6 PA 7 RESE T OSC 2 VSS OSC1 PA 0 PA 1 PA 2 PA 3 PA 4 PA 5 PA 6 PA 7 PB5 PB4 PB3 PB2 PB1 PB 0 RESE T VD D OSC 2 VSS DIP/CERDI SOIC IRQ/VPP IRQ/VPP 1111 Figure 2-1. Pin Assignments

MOTOROLA PIN DESCRIPTIONS MC68HC705J2 2-2

2.1 VDD and VSS

VDD and VSS are the power supply and ground pins. The MCU operates from a single 5-V power supply. Very fast signal transitions occur on the MCU pins. The short rise and fall times place very high short-duration current demands on the power supply. To prevent noise problems, take special care to provide good power supply bypassing at the MCU. Use bypass capacitors with good high-frequency characteristics, and position them as close to the MCU as possible. Bypassing requirements vary, depending on how heavily loaded the MCU pins are.

2.2 OSC1 and OSC2

The OSC1 and OSC2 pins are the control connections for the on-chip oscillator. Connect any of the following to the OSC1 and OSC2 pins:

• A crystal (Refer to Figure 2-2.)
• A ceramic resonator (Refer to Figure 2-2.)
• An external clock signal (Refer to Figure 2-3.) The MCU divides the frequency, fosc, of the oscillator or external clock source by two to produce the internal operating frequency, fop.

2.2.1 Crystal

The circuit in Figure 2-2 shows a typical crystal oscillator circuit for a parallel resonant crystal. Follow the crystal supplier's recommendations, as the crystal parameters determine the external component values required to provide maximum stability and reliable start-up. The load capacitance values used in the oscillator circuit design should include all stray layout capacitances. Mount the crystal and components as close as possible to the pins for start-up stabilization and to minimize output distortion.

2.2.2 Ceramic Resonator

In cost-sensitive applications, use a ceramic resonator in place of the crystal. Use the circuit in Figure 2-2 for a ceramic resonator, and follow the resonator manufacturer's recommendations, as the resonator parameters determine the external component values required for maximum stability and reliable starting. The load capacitance values used in the oscillator circuit design should include all stray layout capacitances.

MC68HC705J2 PIN DESCRIPTIONS MOTOROLA 2-3 OSC2OSC1 4.7 MW 37 pF37 pF XTAL STOP Figure 2-2. Crystal/Ceramic Resonator Connections

2.2.3 External Clock

An external clock from another CMOS-compatible device can drive the OSC1 input, with the OSC2 pin not connected, as Figure 2-3 shows. OSC2OSC1 STOP NOT CONNECT E EXTERNAL CMOS CLOCK Figure 2-3. External Clock Connections

MOTOROLA PIN DESCRIPTIONS MC68HC705J2 2-4

2.3 R E S E T

A zero on the RESET pin forces the MCU to a known start-up state. See 5.1 Resets for more information.

2.4 IRQ /VPP (External Interrupt Request/Programming Voltage)

The IRQ /VPP pin has the following functions:

• Applying asynchronous external interrupt signals (See 5.2 Interrupts.)
• Applying the programming voltage for programming the EPROM (See Downloading .)

MC68HC705J2 PARALLEL I/O MOTOROLA 3-1 SECTION 3 PARALLEL I/O This section describes the two bidirectional I/O ports.

3.1 I/O Port Function

The 14 I/O pins form two I/O ports. Each I/O pin is programmable as an input or an output. The contents of a port data direction register (DDR) determine the data direction for the port. Writing a 1 to a DDR bit enables the output buffer for the associated port pin; a 0 disables the output buffer. A reset initializes all implemented DDR bits to 0, configuring all I/O pins as inputs. NOTE Connect any unused inputs and I/O pins to an appropriate logical level, either V DD or VSS . Although the I/O ports do not require termination for proper operation, termination reduces the possibility of electrostatic damage. A reset does not initialize the two port data registers. The port data registers for ports A and B are at addresses $0000 and $0001. To avoid undefined levels, write the data registers before writing the data direction registers. With an I/O port pin programmed as an output, reading the pin actually reads the value of the output data latch and not the voltage on the pin itself. When a pin is programmed as an input, reading the port bit reads the voltage level on the I/O pin. The output data latch can always be written, regardless of the state of its DDR bit. Refer to Figure 3-1 for typical port circuitry, and to Table 3-1 for a summary of I/O pin functions.

MOTOROLA PARALLEL I/O MC68HC705J2 3-2 I/O PIN DATA DIRECTIO REGISTER BIT LATCHED OUTPUT DAT A BIT CONNECTIONS TO INTERNAL DATA BUS [1] [2] [3] [1] Output buffer enables latched output to drive I/O pin when DDR bit is 1 (output mode). [2] Input buffer enabled when DDR bit is 0 (input mode). [3] Input buffer enabled when DDR bit is 1 (output mode). Figure 3-1. Parallel I/O Port Circuit Table 3-1. I/O Pin Functions R/W DDR Bit I/O Pin Function 0 0 The I/O pin is an input. Data is written into the output data latch. 0 1 Data is written into the output data latch, which drives the I/O pin. 1 0 The state of the I/O pin is read. 1 1 The I/O pin is an output. The output data latch is read. NOTE: R/W is an internal MCU signal.

MC68HC705J2 PARALLEL I/O MOTOROLA 3-3

3.2 Port A

Port A is an 8-bit general-purpose bidirectional I/O port. The contents of DDRA determine whether each pin is an input or an output. Figures 3-2 and 3-3 show the port A data register and DDRA. PORTA — Port A Data Register $0000 Bit 7 654321 Bit 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 RESET: NOT CHANGED BY RESET Figure 3-2. Port A Data Register PA7–PA0 — Port A Data Bits These read/write bits are software-programmable. Data direction of each bit is under the control of the corresponding DDRA bit. DDRA — Port A Data Direction Register $0004 Bit 7 654321 Bit 0 0 0 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 RESET: 00000000 Figure 3-3. Port A Data Direction Register DDRA7–DDRA0 — Port A Data Direction Bits These read/write bits control port A data direction. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input

MOTOROLA PARALLEL I/O MC68HC705J2 3-4

3.3 Port B

Port B is a 6-bit general-purpose bidirectional I/O port. The contents of DDRB determine whether each pin is an input or an output. Figures 3-4 and 3-5 show the port B data register and DDRB. PORTB — Port B Data Register $0001 Bit 7 654321 Bit 0 0 0 PB5 PB4 PB3 PB2 PB1 PB0 RESET: NOT CHANGED BY RESET Figure 3-4. Port B Data Register PB5–PB0 — Port B Data Bits These read/write bits are software-programmable. Data direction of each bit is under the control of the corresponding DDRA bit. DDRB — Port B Data Direction Register $0005 Bit 7 654321 Bit 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 RESET: 00000000 Figure 3-5. Port B Data Direction Register DDRB7–DDRB0 — Port B Data Direction Bits These read/write bits control port B data direction. 1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input

MC68HC705J2 CENTRAL PROCESSOR UNIT MOTOROLA 4-1 SECTION 4 CENTRAL PROCESSOR UNIT This section describes the registers, instruction set, and addressing modes of the M68HC05 central processor unit (CPU).

4.1 CPU Registers

Figure 4-1 shows the five CPU registers. These are hard-wired registers within the CPU and are not part of the memory map. A ACCUMULATOR (A) X INDEX REGISTER (X) 15 6 5 0

0000000011 S P STACK POINTER (SP)

15 12 11 * 87 0

0000 P C H P C L PROGRAM COUNTER (PC)

1 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG *Bit 11 of the program counter is fixed at 0 in MC68HC05J1 emulation mode. Figure 4-1. Programming Model

MOTOROLA CENTRAL PROCESSOR UNIT MC68HC705J2 4-2

4.1.1 Accumulator

The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and results of arithmetic and nonarithmetic operations.

4.1.2 Index Register

The 8-bit index register can perform two functions:

• Indexed addressing
• Temporary storage In indexed addressing, the CPU uses the byte in the index register to determine the conditional address of the operand. See 4.3.5 Indexed, No Offset , The index register can also serve as an auxiliary accumulator for temporary storage.

4.1.3 Stack Pointer

The stack pointer is a 16-bit register that contains the address of the next free location on the stack. During a reset or after the reset stack pointer (RSP) instruction, the stack pointer contents are preset to $00FF. The address in the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. The ten most significant bits of the stack pointer are permanently fixed at 0000000011, so the stack pointer produces addresses from $00C0 to $00FF. If subroutines and interrupts use more than 64 stack locations, the stack pointer wraps around to address $00C0 and begins writing over the previously stored data. A subroutine uses two stack locations; an interrupt uses five locations.

MC68HC705J2 CENTRAL PROCESSOR UNIT MOTOROLA 4-3

4.1.4 Program Counter

The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. The four most significant bits of the program counter are permanently fixed at 0000. In MC68HC05J1 emulation mode, the five most significant bits are fixed at 00000. Normally, the address in the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location.

4.1.5 Condition Code Register

The condition code register is an 8-bit register whose three most significant bits are permanently fixed at 111. The condition code register contains the interrupt mask and four flags that indicate the results of the instruction just executed. The following paragraphs describe the functions of the condition code register.

4.1.5.1 Half-Carry Flag

The CPU sets the half-carry flag when a carry occurs between bits 3 and 4 of the accumulator during an ADD or ADC operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations.

4.1.5.2 Interrupt Mask

Setting the interrupt mask disables interrupts. If an interrupt request occurs while the interrupt mask is zero, the CPU saves the CPU registers on the stack, sets the interrupt mask, and then fetches the interrupt vector. If an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. Normally, the CPU processes the latched interrupt as soon as the interrupt mask is cleared again. A return from interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the interrupt mask to its cleared state. After any reset, the interrupt mask is set and can be cleared only by a software instruction.

MOTOROLA CENTRAL PROCESSOR UNIT MC68HC705J2 4-4

4.1.5.3 Negative Flag

The CPU sets the negative flag when an arithmetic operation, logical operation, or data manipulation produces a negative result. Bit 7 of the negative result is automatically set, so the negative flag can be used to check an often-tested bit by assigning it to bit 7 of a register or memory location. Loading the accumulator with the contents of that register or location then sets or clears the negative flag according to the state of the tested bit.

4.1.5.4 Zero Flag

The CPU sets the zero flag when an arithmetic operation, logical operation, or data manipulation produces a $00.

4.1.5.5 Carry/Borrow Flag

The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator. Some logical operations and data manipulation instructions also clear or set the carry/borrow flag.

4.2 Arithmetic/Logic Unit (ALU)

The ALU performs the arithmetic and logical operations defined by the instruction set. The binary arithmetic circuits decode instructions and set up the ALU for the selected operation. Most binary arithmetic is based on the addition algorithm, carrying out subtraction as negative addition. Multiplication is not performed as a discrete operation but as a chain of addition and shift operations within the ALU. The multiply instruction (MUL) requires 11 internal processor cycles to complete this chain of operations.

4.3 Addressing Modes

The CPU uses eight addressing modes for flexibility in accessing data. These addressing modes define the manner in which the CPU finds the data required to execute an instruction. The eight addressing modes are as follows:

• Inherent
• Immediate
• Direct
• Extended
• Indexed, no offset
• Indexed, 8-bit offset
• Indexed, 16-bit offset
• Relative

MC68HC705J2 CENTRAL PROCESSOR UNIT MOTOROLA 4-5

4.3.1 Inherent

Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Other inherent instructions are those that act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no memory address and are one byte long. Table 4-1 lists the instructions that use the inherent addressing mode. Table 4-1. Inherent Addressing Instructions Instruction Mnemonic Arithmetic Shift Left ASLA, ASLX Arithmetic Shift Right ASRA, ASRX Clear Carry Bit CLC Clear Interrupt Mask CLI Clear CLRA, CLRX Complement COMA, COMX Decrement DECA, DECX Increment INCA, INCX Logical Shift Left LSLA, LSLX Logical Shift Right LSRA, LSRX Multiply MUL Negate NEGA, NEGX No Operation NOP Rotate Left through Carry ROLA, ROLX Rotate Right through Carry RORA, RORX Reset Stack Pointer RSP Return from Interrupt RTI Return from Subroutine RTS Set Carry Bit SEC Set Interrupt Mask SEI Enable IRQ and Stop Oscillator STOP Software Interrupt SWI Transfer Accumulator to Index Register TAX Test for Negative or Zero TSTA, TSTX Transfer Index Register to Accumulator TXA Enable Interrupt and Half Processor WAIT

MOTOROLA CENTRAL PROCESSOR UNIT MC68HC705J2 4-6

4.3.2 Immediate

Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no memory address and are two bytes long. The opcode is the first byte and the immediate data value is the second byte. Table 4-2 lists the instructions that use the immediate addressing mode. Table 4-2. Immediate Addressing Instructions Instruction Mnemonic Add with Carry ADC Add ADD Logical AND AND Bit Test Memory with Accumulator BIT Compare Accumulator with Memory CMP Compare Index Register with Memory CPX Exclusive OR Memory with Accumulator EOR Load Accumulator from Memory LDA Load Index Register from Memory LDX Inclusive OR ORA Subtract with Carry SBC Subtract SUB

4.3.3 Direct

Direct instructions can access any of the first 256 memory addresses with only two bytes. The first byte is the opcode and the second byte is the low byte of the operand's address. In the direct addressing mode, the CPU automatically uses $00 as the high byte of the operand's address. BRSET and BRCLR are three-byte instructions that use direct addressing to access the operand and relative addressing to specify a branch destination. Table 4-3 lists the instructions that use the direct addressing mode.

MC68HC705J2 CENTRAL PROCESSOR UNIT MOTOROLA 4-7 Table 4-3. Direct Addressing Instructions Instruction Mnemonic Add with Carry ADC Add ADD Logical AND AND Arithmetic Shift Left ASL Arithmetic Shift Right ASR Clear Bit in Memory BCLR Bit Test Memory with Accumulator BIT Branch if Bit n Is Clear BRCLR Branch if Bit n Is Set BRSET Set Bit in Memory BSET Clear CLR Compare Accumulator with Memory CMP Complement COM Compare Index Register with Memory CPX Decrement DEC Exclusive OR Memory with Accumulator EOR Increment INC Jump JMP Jump to Subroutine JSR Load Accumulator from Memory LDA Load Index Register from Memory LDX Logical Shift Left LSL Logical Shift Right LSR Negate NEG Inclusive OR ORA Rotate Left through Carry ROL Rotate Right through Carry ROR Subtract with Carry SBC Store Accumulator in Memory STA Store Index Register in Memory STX Subtract SUB Test for Negtative or Zero TST

MOTOROLA CENTRAL PROCESSOR UNIT MC68HC705J2 4-8

4.3.4 Extended

Extended instructions can access any address in memory with only three bytes. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand's address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction. Table 4-4 lists the instructions that use the extended addressing mode. Table 4-4. Extended Addressing Instructions Instruction Mnemonic Add with Carry ADC Add ADD Logical AND AND Bit Test Memory with Accumulator BIT Compare Accumulator with Memory CMP Compare Index Register with Memory CPX Exclusive OR Memory with Accumulator EOR Jump JMP Jump to Subroutine JSR Load Accumulator from Memory LDA Load Index Register from Memory LDX Inclusive OR ORA Subtract with Carry SBC Store Accumulator in Memory STA Store Index Register in Memory STX Subtract SUB

MC68HC705J2 CENTRAL PROCESSOR UNIT MOTOROLA 4-9

4.3.5 Indexed, No Offset

Indexed instructions with no offset are one-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the operand's conditional address. The CPU automatically uses $00 as the high byte of the operand's conditional address, so these instructions can address locations $0000–$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I/O location. Table 4-5 lists the instructions that use the indexed, no offset addressing mode.

4.3.6 Indexed, 8-Bit Offset

Indexed, 8-bit offset instructions are two-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the conditional address of the operand. These instructions can address locations $0000–$01FE. Indexed, 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value would typically be in the index register, and the address of the beginning of the table would be in the byte following the opcode. Table 4-5 lists the instructions that use the indexed, 8-bit offset addressing mode.

4.3.7 Indexed, 16-Bit Offset

Indexed, 16-bit offset instructions are three-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the conditional address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. These instructions can address any location in memory. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. Table 4-5 lists the instructions that can use the indexed, 16-bit offset addressing mode.

MOTOROLA CENTRAL PROCESSOR UNIT MC68HC705J2 4-10 Table 4-5. Indexed Addressing Instructions Instruction Mnemonic No Offset 8-Bit Offset 16-Bit Offset Add with Carry ADC ÖÖÖ Add ADD ÖÖÖ Logical AND AND ÖÖÖ Arithmetic Shift Left ASL ÖÖ Arithmetic Shift Right ASR ÖÖ Bit Test Memory with Accumulator BIT ÖÖÖ Clear CLR ÖÖ Compare Accumulator with Memory CMP ÖÖÖ Complement COM ÖÖ Compare Index Register with Memory CPX ÖÖÖ Decrement DEC ÖÖ Exclusive OR Memory with Accumulator EOR ÖÖÖ Increment INC ÖÖ Jump JMP ÖÖÖ Jump to Subroutine JSR ÖÖÖ Load Accumulator from Memory LDA ÖÖÖ Load Index Register from Memory LDX ÖÖÖ Logical Shift Left LSL ÖÖ Logical Shift Right LSR ÖÖ Negate NEG ÖÖ Inclusive OR ORA ÖÖÖ Rotate Left through Carry ROL ÖÖ Rotate Right through Carry ROR ÖÖ Subtract with Carry SBC ÖÖÖ Store Accumulator in Memory STA ÖÖÖ Store Index Register in Memory STX ÖÖÖ Subtract SUB ÖÖÖ Test for Negative or Zero TST ÖÖ

MC68HC705J2 CENTRAL PROCESSOR UNIT MOTOROLA 4-11

4.3.8 Relative

The relative addressing mode is only for branch instructions and bit test and branch instructions. The CPU finds the conditional branch destination by adding the signed byte following the opcode to the contents of the program counter if the branch condition is true. If the branch condition is not true, the CPU goes to the next instruction. To permit branching either forward or backward, the offset is a signed, two's complement byte that gives a branching range of –127 to +128 bytes from the address of the next location after the branch instruction. When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. Table 4-6 lists the instructions that use the relative addressing mode. Table 4-6. Relative Addressing Instructions Instruction Mnemonic Branch if Carry Clear BCC Branch if Carry Set BCS Branch if Equal BEQ Branch if Half-Carry Clear BHCC Branch if Half-Carry Set BHCS Branch if Higher BHI Branch if Higher or Same BHS Branch if Interrupt Line iHigh BIH Branch if Interrupt Line Low BIL Branch if Lower BLO Branch if Lower or Same BLS Branch if Interrupt Mask Clear BMC Branch if Minus BMI Branch if Interrupt Mask Set BMS Branch if Not Equal BNE Branch if Plus BPL Branch Always BRA Branch if Bit n Clear BRCLR Branch if Bit n Set BRSET Branch Never BRN Branch to Subroutine BSR

MOTOROLA CENTRAL PROCESSOR UNIT MC68HC705J2 4-12

4.4 Instruction Set

The MCU uses all the instructions available in the M146805 CMOS Family plus the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator and the index register. The CPU stores the high-order product in the index register, and the low-order product in the accumulator. The MCU instructions fall into the following five categories:

• Register/memory
• Read-modify-write
• Jump/branch
• Bit manipulation
• Control

4.4.1 Register/Memory Instructions

Most of these instructions use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory using one of the addressing modes. Most register/memory instructions use the following addressing modes:

• Immediate
• Direct
• Extended
• Indexed, no offset
• Indexed, 8-bit offset
• Indexed, 16-bit offset Table 4-7 lists the register/memory instructions.

MC68HC705J2 CENTRAL PROCESSOR UNIT MOTOROLA 4-13 Table 4-7. Register/Memory Instructions Instruction Mnemonic Load Accumulator from Memory LDA Load Index Register from Memory LDX Store Accumulator in Memory STA Store Index Register in Memory STX Add Memory to Accumulator ADD Add Memory and Carry to Accumulator ADC Subtract Memory SUB Subtract Memory from Accumulator with Borrow SBC AND Memory with Accumulator AND OR Memory with Accumulator ORA Arithmetic Compare Accumulator with Memory CMP Arithmetic Compare Index Register with Memory CPX Bit Test Memory with Accumulator (Logical Compare) BIT Multiply MUL

4.4.2 Read-Modify-Write Instructions

These instructions read a memory location or a register, modify its contents, and write the modified value back to memory or to the register. The test for negative or zero (TST) instruction is an exception to the read-modify-write sequence because it does not write a replacement value. Read-modify-write instructions use the following addressing modes:

• Inherent
• Direct
• Indexed, no offset
• Indexed, 8-bit offset Table 4-8 lists the read-modify-write instructions.

MOTOROLA CENTRAL PROCESSOR UNIT MC68HC705J2 4-14 Table 4-8. Read-Modify-Write Instructions Instruction Mnemonic Increment INC Decrement DEC Clear CLR Complement COM Negate (Two's Complement) NEG Rotate Left through Carry ROL Rotate Right through Carry ROR Logical Shift Left LSL Logical Shift Right LSR Arithmetic Shift Right ASR Test for Negative or Zero TST

4.4.3 Jump/Branch Instructions

Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand. Jump instructions use the following addressing modes:

• Direct
• Extended
• Indexed, no offset
• Indexed, 8-bit offset
• Indexed, 16-bit offset Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. All branch instructions are used in the relative addressing mode.

MC68HC705J2 CENTRAL PROCESSOR UNIT MOTOROLA 4-15 Bit test and branch instructions cause a branch based on the condition of any readable bit in the first 256 memory locations. These three-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the conditional branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from –128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. Table 4-9 lists the jump and branch instructions. Table 4-9. Jump and Branch Instructions Instruction Mnemonic Branch Always BRA Branch Never BRN Branch if Bit n of M = 0 BRCLR Branch if Bit n of M = 1 BRSET Branch if Higher BHI Branch if Lower or Same BLS Branch if Carry Clear BCC Branch if Higher or Same BHS Branch if Carry Set BCS Branch if Lower BLO Branch if Not Equal BND Branch if Equal BEQ Branch if Half-Carry Clear BHCC Branch if Half-Carry Set BHCS Branch if Plus BPL Branch if Minus BMI Branch if Interrupt Mask Clear BMC Branch if Interrupt Mask Set BMS Branch if Interrupt Line Low BIL Branch if Interrupt Line High BIH Branch to Subroutine BSR Jump Unconditional JMP Jump to Subroutine JSR

MOTOROLA CENTRAL PROCESSOR UNIT MC68HC705J2 4-16

4.4.4 Bit Manipulation Instructions

The CPU can set or clear any writable bit in the first 256 bytes of memory. Port register, port data direction registers, timer registers, and on-chip RAM locations are in the first 256 bytes of memory. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Bit manipulation instructions use the direct addressing mode. Table 4-10 lists these instructions. Table 4-10. Bit Manipulation Instructions Instruction Mnemonic Set Bit n BSET n (n = 0 . . . 7) Clear Bit n BCLR n (n = 0 . . . 7) Branch if Bit n of M = 0 BRCLR Branch if Bit n of M = 1 BRSET

4.4.5 Control Instructions

These register reference instructions control CPU operation during program execution. Control instructions, listed in Table 4-11, use the inherent addressing mode. Table 4-11. Control Instructions Instruction Mnemonic Transfer Accumulator to Index Register TAX Transfer Index Register to Accumulator TXA Set Carry Bit SEC Clear Carry Bit CLC Set Interrupt Mask SEI Clear Interrupt Mask CLI Software Interrupt SWI Return from Subroutine RTI Reset Stack Pointer RSP No Operation NOP Stop STOP Wait WAIT

Rev. 1 4-17

4.4.6 Instruction Set Summary

Table 4-12 is an alphabetical list of all M68HC05 instructions and shows the effect of each instruction on the condition code register. Table 4-12. Instruction Set Summary Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C ADC # opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X Add with Carry A ← (A) + (M) + (C) × — × × × IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff ADD # opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X Add without Carry A ← (A) + (M) × — × × × IMM DIR EXT IX2 IX1 IX AB BB CB DB EB FB ii dd hh ll ee ff ff AND # opr AND opr AN D opr AND opr,X AND opr,X AND ,X IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff ASL opr ASLA ASLX ASL opr,X ASL ,X Arithmetic Shift Left DIR INH INH IX1 IX dd ff ASR opr ASRA ASRX ASR opr,X ASR ,X Arithmetic Shift Right — — × × × DIR INH INH IX1 IX dd ff BCC rel Branch if Carry Bit Clear PC ← (PC) + 2 +rel ? C = 0 ————— R E L 2 4 r r 3 BCLR n opr Clear Bit n Mn ← 0 ————— DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd dd dd dd dd dd dd dd BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 +rel ? C = 1 ————— R E L 2 5 r r 3 BEQ rel Branch if Equal PC ← (PC) + 2 +rel ? Z = 1 ————— R E L 2 7 r r 3 BHCC rel Branch if Half-Carry Bit Clear PC ← (PC) + 2 +rel ? H = 0 ————— R E L 2 8 r r 3 C b0b7 b0b7 C

4-18 Rev. 1 BHCS rel Branch if Half-Carry Bit Set PC ← (PC) + 2 +rel ? H = 1 ————— R E L 2 9 r r 3 BHI rel Branch if Higher PC ← (PC) + 2 +rel ? C∨ Z = 0 ————— R E L 2 2 r r 3 BHS rel Branch if Higher or Same PC ← (PC) + 2 +rel ? C = 0 ————— R E L 2 4 r r 3 BIH rel Branch ifIRQ Pin High PC ← (PC) + 2 +rel ?IRQ = 1 ————— R E L 2 F r r 3 BIL rel Branch ifIRQ Pin Low PC ← (PC) + 2 +rel ?IRQ = 0 ————— R E L 2 E r r 3 BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X Bit Test Accumulator with Memory Byte IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff p BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 +rel ? C = 1 ————— R E L 2 5 r r 3 BLS rel Branch ifLower or Same PC ← (PC) + 2 +rel ? C∨ Z = 1 ————— R E L 2 3 r r 3 BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 +rel ? I = 0 ————— R E L 2 C r r 3 BMI rel Branch if Minus PC ← (PC) + 2 +rel ? N = 1 ————— R E L 2 B r r 3 BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 +rel ? I = 1 ————— R E L 2 D r r 3 BNE rel Branch if Not Equal PC ← (PC) + 2 +rel ? Z = 0 ————— R E L 2 6 r r 3 BPL rel Branch if Plus PC ← (PC) + 2 +rel ? N = 0 ————— R E L 2 A r r 3 BRA rel Branch Always PC ← (PC) + 2 +rel ? 1 = 1 ————— R E L 2 0 r r 3 BRCLR n opr relBranch if bit n clear PC ← (PC) + 2 +rel ? M n = 0 ———— × DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr BRSET n opr relBranch if Bit n Set PC ← (PC) + 2 +rel ? M n = 1 ———— × DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr BRN rel Branch Never PC ← (PC) + 2 +rel ? 1 = 0 ————— R E L 2 1 r r 3 Table 4-12. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C

Rev. 1 4-19 BSET n opr Set Bit n Mn ← 1 ————— DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) dd dd dd dd dd dd dd dd BSR rel Branch to Subroutine PC ← (PC) + 2; push (PCL) SP ← (SP) – 1; push (PCH) SP ← (SP) – 1 PC ← (PC) +rel CLC Clear Carry Bit C ← 0 ———— 0 I N H 9 8 2 CLI Clear Interrupt Mask I ← 0 — 0 — — — INH 9A 2 CLR opr CLRA CLRX CLR opr,X CLR ,X Clear Byte M ← $00 A ← $00 X ← $00 M ← $00 M ← $00 —— 0 1 — DIR INH INH IX1 IX dd ff CMP # opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X Compare Accumulator with Memory Byte IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff COM opr COMA COMX COM opr,X COM ,X Complement Byte (One’s Complement) —— × × 1 DIR INH INH IX1 IX dd ff CPX # opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X Compare Index Register with Memory Byte IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff DEC opr DECA DECX DEC opr,X DEC ,X Decrement Byte M ← (M) – 1 A ← (A) – 1 X ← (X) – 1 M ← (M) – 1 M ← (M) – 1 DIR INH INH IX1 IX dd ff EOR # opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EXCLUSIVE OR Accumulator with Memory Byte IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff Table 4-12. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C M A X M M

4-20 Rev. 1 INC opr INCA INCX INC opr,X INC ,X Increment Byte M ← (M) + 1 A ← (A) + 1 X ← (X) + 1 M ← (M) + 1 M ← (M) + 1 DIR INH INH IX1 IX dd ff JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X Unconditional Jump PC ← Jump Address ————— DIR EXT IX2 IX1 IX BC C C D C EC FC dd hh ll ee ff ff JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Jump to Subroutine PC ← (PC) + n (n = 1, 2, or 3) Push (PCL); SP← (SP) – 1 Push (PCH); SP← (SP) – 1 PC ← Conditional Address DIR EXT IX2 IX1 IX BD C D D D ED FD dd hh ll ee ff ff LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X Load Accumulator with Memory Byte A ← (M) — — × × — IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X Load Index Register with Memory Byte X ← (M) — — × × — IMM DIR EXT IX2 IX1 IX AE BE CE DE EE FE ii dd hh ll ee ff ff LSL opr LSLA LSLX LSL opr,X LSL ,X Logical Shift Left DIR INH INH IX1 IX dd ff LSR opr LSRA LSRX LSR opr,X LSR ,X Logical Shift Right — — 0 × × DIR INH INH IX1 IX dd ff MUL Unsigned Multiply X : A ← (X)× (A) 0 — — — 0 INH 42 11 NEG opr NEGA NEGX NEG opr,X NEG ,X Negate Byte (Two’s Complement) DIR INH INH IX1 IX ii ff Table 4-12. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C C b0b7 b0b7

Rev. 1 4-21 NOP No Operation ————— I N H 9 D 2 ORA # opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X Logical OR Accumulator with Memory IMM DIR EXT IX2 IX1 IX AA BA CA DA EA FA ii dd hh ll ee ff ff ROL opr ROLA ROLX ROL opr,X ROL ,X Rotate Byte Left through Carry Bit — — ××× DIR INH INH IX1 IX dd ff ROR opr RORA RORX ROR opr,X ROR ,X Rotate Byte Right through Carry Bit — — ××× DIR INH INH IX1 IX dd ff RSP Reset Stack Pointer SP ← $00FF ————— I N H 9 C 2 RTI Return from Interrupt SP ← (SP) + 1; Pull (CCR) SP ← (SP) + 1; Pull (A) SP ← (SP) + 1; Pull (X) SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL) RTS Return from Subroutine SP ← (SP) + 1; Pull (PCH) SP ← (SP) + 1; Pull (PCL) INH SBC # opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X Subtract Memory Byte and Carry Bit from Accumulator IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff SEC Set Carry Bit C ← 1 ———— 1 I N H 9 9 2 SEI Set Interrupt Mask I ← 1 — 1 — — — INH 9B 2 STA opr STA opr STA opr,X STA opr,X STA ,X Store Accumulator in DIR EXT IX2 IX1 IX dd hh ll ee ff ff STOP Stop Oscillator and Enable IRQ Pin — 0 — — — INH 8E 2 STX opr STX opr STX opr,X STX opr,X STX ,X Store Index Register In Memory M ← (X) — — × × — DIR EXT IX2 IX1 IX BF CF DF EF FF dd hh ll ee ff ff Table 4-12. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C C b0b7 b0b7 C

4-22 Rev. 1 SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X Subtract Memory Byte from Accumulator IMM DIR EXT IX2 IX1 IX ii dd hh ll ee ff ff SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte — 1 — — — INH 83 10 TAX Transfer Accumulator to Index Register TST opr TSTA TSTX TST opr,X TST ,X Test Memory Byte for Negative or Zero (M) – $00 ————— DIR INH INH IX1 IX dd ff TXA Transfer Index Register to Accumulator WAIT Stop CPU Clock and Enable Interrupts A Accumulator opr Operand (one or two bytes) C Carry/borrow flag PC Program counter CCR Condition code register PCH Program counter high byte dd Direct address of operand PCL Program counter low byte dd rr Direct address of operand and relative offset of branch instruction REL Relative addressing mode DIR Direct addressing mode rel Relative program counter offset byte ee ff High and low bytes of offset in indexed, 16-bit offset addressing rr Relative program counter offset byte EXT Extended addressing mode SP Stack pointer ff Offset byte in indexed, 8-bit offset addressing X Index register H Half-carry flag Z Zero flag hh ll High and low bytes of operand address in extended addressing # Immediate value I Interrupt mask ∧ Logical AND ii Immediate operand byte ∨ Logical OR IMM Immediate addressing mode ⊕ Logical EXCLUSIVE OR INH Inherent addressing mode ( ) Contents of IX Indexed, no offset addressing mode –( ) Negation (two’s complement) IX1 Indexed, 8-bit offset addressing mode ← Loaded with IX2 Indexed, 16-bit offset addressing mode ? If M Memory location : Concatenated with N Negative flag ↕ Set or cleared n Any bit — Not affected Table 4-12. Instruction Set Summary (Continued) Source Form Operation Description Effect on CCR Address Mode Opcode Operand CyclesHIN Z C

-23 Rev. 1.1 Table 4-13. Opcode Map Bit Manipulation Branch Read-Modify-Write Control Register/Memory DIR DIR REL DIR INH INH IX1 IX INH INH IMM DIR EXT IX2 IX1 IX 0123456789AB C D EF BRSET0

3 DIR

2 DIR

2 REL

1 INH

2 IX1

2 IMM

3 EXT

3 IX2

A BRSET5 A B BRCLR5 B C BRSET6 C D BRCLR6 D E BRSET7 E F BRCLR7 F INH = Inherent REL = Relative IMM = Immediate IX = Indexed, No Offset DIR = Direct IX1 = Indexed, 8-Bit Offset EXT = Extended IX2 = Indexed, 16-Bit Offset

0 MSB of Opcode in Hexadecimal

LSB of Opcode in Hexadecimal 0 BRSET0 Number of Bytes/Addressing Mode LSB MSB LSB MSB LSB MSB

MC68HC705J2 CENTRAL PROCESSOR UNIT MOTOROLA 4-23

4.5 Low-Power Modes

The following paragraphs describe the STOP and WAIT modes. (Refer also to 6.2Data Retention Mode .)

4.5.1 STOP Mode

The STOP instruction puts the MCU in its lowest power-consumption mode. In STOP mode, the following events occur:

• The CPU clears TOF and RTIF, the timer interrupt flags in the timer control and status register, removing any pending timer interrupts.
• The CPU clears TOIE and RTIE, the timer interrupt enable bits in the timer control and status register, disabling further timer interrupts.
• The CPU clears the divide-by-four timer prescaler.
• The CPU clears the interrupt mask in the condition code register, enabling external interrupts.
• The internal oscillator stops, halting all internal processing, including operation of the timer and the COP timer. The STOP instruction does not affect any other registers or any I/O lines. The following conditions bring the MCU out of STOP mode:
• An external interrupt. An external interrupt automatically loads the program counter with the contents of locations $0FFA and $0FFB, the locations of the vector address of the external interrupt service routine.
• A reset signal on the RESET pin. A reset automatically loads the program counter with the contents of locations $0FFE and $0FFF, the locations of the vector address of the reset service routine. Refer to Figure 10-7 in SECTION 10 ELECTRICAL SPECIFICATIONS for STOP recovery timing.

MC68HC705J2 CENTRAL PROCESSOR UNIT MOTOROLA 4-25

4.5.2 WAIT Mode

The WAIT instruction puts the MCU in an intermediate power-consumption mode. In WAIT mode, the following events occur:

• All CPU clocks stop.
• The CPU clears the interrupt mask in the condition code register, enabling external interrupts and timer interrupts. The WAIT instruction does not affect any other registers or any I/O lines. The timer and COP timer remain active in WAIT mode. The following conditions bring the MCU out of WAIT mode:
• A timer interrupt. If a real-time interrupt or a timer overflow interrupt occurs during WAIT mode, the MCU loads the program counter with the contents of locations $0FF8 and $0FF9, the locations of the vector address of the timer interrupt service routine.
• An external interrupt. An external interrupt automatically loads the program counter with the contents of locations $0FFA and $0FFB, the locations of the vector address of the external interrupt service routine.
• A COP timer reset. A timeout of the COP timer during WAIT mode resets the MCU. The programmer can enable real-time interrupts so the MCU can periodically exit WAIT mode to reset the COP timer.
• A reset signal on the RESET pin during WAIT mode resets the MCU. A COP timer reset or a reset signal on the RESET pin automatically loads the program counter with the contents of locations $0FFE and $0FFF, the locations of the vector address of the reset service routine. Figure 4-3 shows the sequence of events caused by the WAIT instruction.

MOTOROLA CENTRAL PROCESSOR UNIT MC68HC705J2 4-26 WAIT YES YES NOEXTERNAL INTERRUPT ? YES NO INTERNAL TIMER INTERRUPT ? RESTART CPU CLOCK. NO OSCILLATOR ACTIVE. TIMER CLOCKS ACTIVE. STOP CPU CLOCKS. CLEAR CCR INTERRUPT M A (1) FETCH RESET VECTOR o (2) SERVICE INTERRUPT. a. SAVE CPU REGS ON S b. SET I-BIT IN CCR. c. VECTOR TO INTERRU P SERVICE ROUTINE. RESET ? Figure 4-3. WAIT Instruction Flowchart

MC68HC705J2 RESETS AND INTERRUPTS MOTOROLA 5-1 SECTION 5 RESETS AND INTERRUPTS This section describes how resets reinitialize the MCU and how interrupts temporarily change the normal processing sequence.

5.1 Resets

A reset immediately stops the operation of the instruction being executed. A reset initializes certain control bits to known conditions and loads the program counter with a user-defined reset vector address. The following conditions produce a reset:

• Initial power-up (power-on reset)
• A logical zero applied to the RESET pin (external reset)
• Timeout of the COP timer (COP reset)
• An opcode fetch from an address not in the memory map (illegal address reset) A reset does the following things to reinitialize the MCU:
• Clears all implemented data direction register bits so that the corresponding I/O pins are inputs
• Loads the stack pointer with $FF
• Sets the interrupt mask, inhibiting interrupts
• Clears the TOFE and RTIE bits in the timer control and status register
• Clears the STOP latch, enabling the CPU clocks
• Clears the WAIT latch, waking the CPU from the WAIT mode
• Loads the program counter with the user-defined reset vector

5.1.1 Power-On Reset

A positive transition on the VDD pin generates a power-on reset. The power-on reset is strictly for power-up conditions and cannot be used to detect drops in power supply voltage.

MOTOROLA RESETS AND INTERRUPTS MC68HC705J2 5-2 A 4064 tcyc (internal clock cycle) delay after the oscillator becomes active allows the clock generator to stabilize. If the RESET pin is at a logical zero at the end of 4064 tcyc, the MCU remains in the reset condition until the signal on the RESET pin goes to a logical one.

5.1.2 External Reset

A zero applied to the RESET pin for one and one-half tcyc generates an external reset. A Schmitt trigger senses the logic level at the RESET pin.

5.1.3 Computer Operating Properly (COP) Reset

A timeout of the COP timer generates a COP reset. The COP timer is part of a software error detection system and must be cleared periodically to start a new timeout period. (See 7.3 COP Timer.) To clear the COP timer and prevent a COP reset, write a zero to bit 0 (COPR) of the COP control register at location $0FF0 before the COP timer times out. The COP control register is a write-only register that returns the contents of an EPROM location when read. See Figure 5-1. COPR — COP Control Register $0FF0 Bit 7 654321 Bit 0 Figure 5-1. COP Control Register COPR — COP Reset COPR is a write-only bit. Periodically writing a zero to COPR prevents the COP timer from resetting the MCU.

5.1.4 Illegal Address Reset

An opcode fetch from an address that is not in the EPROM (locations $0700– $0EFF), or the RAM ($0090–$00FF) generates an illegal address reset.

MC68HC705J2 RESETS AND INTERRUPTS MOTOROLA 5-3

5.2 Interrupts

An interrupt temporarily stops normal processing to process a particular event. Unlike a reset, an interrupt does not stop the operation of the instruction being executed. An interrupt takes effect when the current instruction completes its execution. An interrupt saves the CPU registers on the stack and loads the program counter with a user-defined interrupt vector address. The following conditions produce an interrupt:

• Timer overflow or real-time interrupt request (timer interrupts)
• A logical zero applied to the IRQ pin (external interrupt)
• SWI instruction (software interrupt) The CPU does the following things to begin servicing an interrupt:
• Stores the contents of the CPU registers on the stack as shown in Figure 5-2 ACCUMULATOR CONDITION CODE REGIST INDEX REGISTER PROGRAM COUNTER LOW PROGRAM COUNTER HIGH INTERRUPT RETURN TOWARD HIGHER ADDRESSES (HIGHEST STACK ADDRESS IS $0 0 TOWARD LOWER ADDRESSES (LOWEST STACK ADDRESS IS $0 UNSTAC K STACK Figure 5-2. Interrupt Stacking Order
• Sets the interrupt mask to prevent further interrupts
• Loads the program counter with the contents of the appropriate interrupt vector locations: — $0FF8 and $0FF9 (timer interrupt vector) — $0FFA and $0FFB (external interrupt vector) — $0FFC and $0FFD (software interrupt vector)

MOTOROLA RESETS AND INTERRUPTS MC68HC705J2 5-4 The return from interrupt (RTI) instruction causes the CPU to recover the CPU registers from the stack as shown in Figure 5-2.

5.2.1 Timer Interrupts

The timer generates two kinds of interrupts:

• Timer overflow interrupt
• Real-time interrupt Setting the interrupt mask in the condition code register disables timer interrupts.

5.2.1.1 Timer Overflow Interrupts

A timer overflow interrupt occurs if the timer overflow flag, TOF, becomes set while the timer overflow interrupt enable bit, TOIE, is also set. TOF and TOIE are in the timer control and status register. See 7.2 Timer Control and Status Register.

5.2.1.2 Real-Time Interrupts

A real-time interrupt occurs if the real-time interrupt flag, RTIF, becomes set while the real-time interrupt enable bit, RTIE, is also set. RTIF and RTIE are in the timer control and status register. See 7.2 Timer Control and Status Register.

5.2.2 External Interrupt

When a falling edge occurs on the IRQ pin, an external interrupt request is latched. When the CPU completes its current instruction, it tests the external interrupt latch. If the interrupt latch is set and the interrupt mask in the condition code register is reset, the CPU then begins the interrupt sequence. The CPU clears the interrupt latch while it fetches the interrupt vector, so that another external interrupt request can be latched during the interrupt service routine. As soon as the interrupt mask is cleared (usually during the return from interrupt), the CPU can recognize the new interrupt request. Figure 5-3 shows the sequence of events caused by an interrupt.

MC68HC705J2 RESETS AND INTERRUPTS MOTOROLA 5-5 EXTERNAL INTERRUPT TIMER INTERRUPT YES NO INTERRUPT MASK SET YES NO YES NO CLEAR IRQ REQUEST LATCH. STACK PCL, PCH, X, A, CCR SET INTERRUPT MASK. LOAD PC WITH VECTOR: MC68HC705J2 NATIVE MO D TIMER: $0FF8, $0FF9 EXTERNAL: $0FFA, $0FFB SOFTWARE: $0FFC, $0FFD MC68HC05J1 EMULATION M TIMER: $07F8, $07F9 EXTERNAL: $07FA, $07FB SOFTWARE: $07FC, $07FD YES NO RTI INSTRUCTION RESTORE REGISTER S FROM STACK CCR, A, X, PCH, PCL FETCH NEXT INSTRUCTION. EXECUTE INSTRUCTION. YES NO SWI INSTRUCTION FROM RESET Figure 5-3. Interrupt Flowchart

MOTOROLA RESETS AND INTERRUPTS MC68HC705J2 5-6 Either an edge-sensitive or an edge- and level-sensitive external interrupt trigger is programmable in the mask option register. Figure 5-4 shows the internal logic of this programmable option. VD D D C Q Q R EXTERNA L INTERRUPT REQUEST EXTERNAL INTERRU P BEING SERVICED (VECTOR FETCH) RESET INTERRUPT MA S LEVEL SENSITIVE TRIGG (MOR OPTI O IRQ Figure 5-4. External Interrupt Trigger Option The edge- and level-sensitive trigger option allows multiple external interrupt sources to be wire-ORed to the IRQ pin. With the level-sensitive trigger option, an external interrupt request is latched as long as any source is holding the IRQ pin low. Setting the interrupt mask in the condition code register disables external interrupts.

5.2.3 Software Interrupt

The software interrupt (SWI) instruction causes a nonmaskable interrupt.

MC68HC705J2 MEMORY MOTOROLA 6-1 SECTION 6 MEMORY This section describes the organization of the on-chip memory.

6.1 Memory Map

The CPU can address 4 Kbytes of memory space. The program counter normally advances one address at a time through the memory, reading the program instructions and data. The EPROM portion of memory holds the program instructions, fixed data, user-defined vectors, and service routines. The RAM portion of memory holds variable data. I/O registers are memory-mapped so that the CPU can access their locations in the same way that it accesses all other memory locations. Figure 6-1 is a memory map of the MCU. Figure 6-2 is a more detailed memory map of the 32-byte I/O register section.

6.1.1 Input/Output Section

The first 32 addresses of the memory space, $0000–$001F, are defined as the I/O section. These are the addresses of the I/O control registers, I/O status registers, and I/O data registers.

6.1.2 RAM

The MCU has 112 bytes of fully static read/write memory for storage of variable and temporary data during program execution. RAM addresses $00C0–$00FF serve as the stack. The CPU uses the stack to save CPU register contents before processing an interrupt or subroutine call. The stack pointer decrements during pushes and increments during pulls. NOTE Be careful if using the stack addresses ($00C0–$00FF) for data storage or as a temporary work area. The CPU may overwrite data in the stack during a subroutine or interrupt.

MOTOROLA MEMORY MC68HC705J2 6-2 PORT A DATA REGIS T TIMER INTERRUPT VECTOR (H TIMER INTERRUPT VECTOR ( EXTERNAL INTERRUPT VECTOR EXTERNAL INTERRUPT VECTO R SOFTWARE INTERRUPT VECTOR SOFTWARE INTERRUPT VECTO R RESET VECTOR (HI RESET VECTOR (L O $001C $001B $0009 $0008 $0007 $0006 $0005 $0004 $0003 $0002 $0001 $0000 $0FF7 $0FF8 $0FF9 $0FFA $0FFB $0FFC $0FFD $0FFE $0FFF PORT B DATA REGIST PORT A DATA DIRECTION REG I PORT B DATA DIRECTION REGIS UNUSE D EPROM PROGRAMMING REGIS T COP REGISTE $0FF0 WRITING 0 TO BIT 0 OF $0FF0 C COP TIMER. READING $0FF0 RE T USER EPROM DATA. UNUSED

112 BYTES

$000 $001F $0FFF I/O REGISTERS

32 BYTES

(EPROM)

16 BYTES

239 BYTES

$0FEF $06FF UNUSED

1536 BYTES

112 BYTE

TIMER CONTROL AND STATUS RE G $000AUNUSE D $070 $008F $009 $002 $00FF $010 $0FF0 USER EPRO M

2048 BYTES

8 BYTES

$0EFF $0F00 $0F0 MASK OPTION REGIST $00BF $00C STACK

64 BYTES

$001D $001E $001F Figure 6-1. Memory Map

MC68HC705J2 MEMORY MOTOROLA 6-3 Bit 7 654321 Bit 0 $0000 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PORTA $0001 0 0 PB5 PB4 PB3 PB2 PB1 PB0 PORTB $0004 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 DDRA $0005 0 0 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 DDRB $0008 TOF RTIF TOIE RTIE 0 0 RT1 RT0 TCSR $0009 Bit 7 654321 Bit 0 TCR

• •
• •
• • $001C 00000 LATCH 0 EPGM PROG $0F00 —————J 1 I R Q C O P M O R $0FF0 COPR COP Figure 6-2. I/O Registers

MOTOROLA MEMORY MC68HC705J2 6-4

6.1.3 EPROM

Two Kbytes of user EPROM for storage of program instructions and fixed data are located at addresses $0700–$0EFF. The eight addresses from $0FF8– $0FFF are EPROM locations reserved for interrupt vectors and reset vectors. Eight additional EPROM bytes are located at $0FF0–$0FF8. There are two ways to write data to the EPROM:

• The EPROM programming register contains the control bits for programming the EPROM on a byte-by-byte basis.
• The bootloader ROM contains routines to download the contents of an external memory device to the on-chip EPROM.

6.1.3.1 EPROM Programming

The EPROM programming register, shown in Figure 6-3, contains the control bits for programming the EPROM. PROG — EPROM Programming Register $001C Bit 7 654321 Bit 0

00000 LATCH 0 EPGM

Figure 6-3. EPROM Programming Register (PROG) LATCH — EPROM Bus Latch This read/write bit causes address and data buses to be latched for EPROM programming. Clearing the LATCH bit automatically clears the EPGM bit. 1 = Address and data buses configured for EPROM programming 0 = Address and data buses configured for normal operation EPGM — EPROM Programming This read/write bit applies programming power to the EPROM. To write the EPGM bit, the LATCH bit must already be set. 1 = EPROM programming power switched on 0 = EPROM programming power switched off Bits 7–3 and 1 — Not used; always read as zeros.

MC68HC705J2 MEMORY MOTOROLA 6-5 Take the following steps to program a byte of EPROM: 1. Apply 16.5 V to the IRQ /VPP pin. 2. Set the LATCH bit. 3. Write to any EPROM address. 4. Set the EPGM bit for a time tEPGM to apply the programming voltage. 5. Clear the LATCH bit.

6.1.3.2 EPROM Erasing

The erased state of an EPROM bit is zero. Erase the EPROM by exposing it to 15 Ws/cm2 of ultraviolet light with a wavelength of 2537 angstroms. Position the ultraviolet light source 1 inch from the EPROM. Do not use a shortwave filter. NOTE Windowed packages must have the window covered during programming and operation.

6.1.4 Bootloader ROM

Addresses $0F01–$0FEF contain the bootloader ROM, which can copy and verify the contents of an external EPROM to the on-chip EPROM. See SECTION 8 BOOTLOADER MODE .

MOTOROLA MEMORY MC68HC705J2 6-6

6.2 Data Retention Mode

In data retention mode, the MCU retains RAM contents and CPU register contents at VDD voltages as low as 2.0 Vdc. The data-retention feature allows the MCU to remain in a low power-consumption state during which it retains data, but the CPU cannot execute instructions. To put the MCU in data retention mode: 1. Drive the RESET pin to zero. 2. Lower the VDD voltage. The RESET line must remain low continuously during data retention mode. To take the MCU out of data retention mode: 1. Return VDD to normal operating voltage. 2. Return the RESET pin to logical one.

MC68HC705J2 TIMER MOTOROLA 7-1 SECTION 7 TIMER This section describes the operation of the timer and the COP timer. Figure 7-1 shows the organization of the timer system. INTERNAL PROCESS O CLOCK (XTAL ‚ 2) FIXED DIVIDE BY MSB LSB TCR $000TIMER COUNTER REGISTE TCSR $00 TOF TOFE RTIE RT1 RT0 LEAST SIGNIFICANT EIGHT BITS OF 15-STAGE RIPPLE MOST SIGNIFICANT SEVEN BITS OF 15-STAGE RIPPLE ‚2‚2 RTI RATE SELEC ‚2‚2‚2 CLEAR COP TIME SQ R COP TIMER RESE TIMER CONTROL AND STATUS RE G POWER-ON RESET (PO INTERRUPT CIRCU RTIF INTERRUPT REQUE S Figure 7-1. Timer

MOTOROLA TIMER MC68HC705J2 7-2

7.1 Timer Counter Register (TCR)

A 15-stage ripple counter is the core of the timer. The value of the first eight stages is readable at any time from the read-only timer counter register shown in Figure 7-2. TCR — Timer Counter Register $0009 Bit 7 654321 Bit 0 RESET 00000000 Figure 7-2. Timer Counter Register (TCR) Power-on clears the entire counter chain and begins clocking the counter. After 4064 cycles of the internal clock, the power-on reset circuit is released, clearing the counter again and allowing the MCU to come out of reset. A timer overflow function at the eighth counter stage makes timer interrupts possible every 1024 internal clock cycles.

7.2 Timer Control and Status Register (TCSR)

Timer interrupt flags, timer interrupt enable bits, and real-time interrupt rate select bits are in the read/write timer control and status register. TCSR — Timer Control and Status Register $0008 Bit 7 654321 Bit 0 TOF RTIF TOIE RTIE 0 0 RT1 RT0 RESET 00000011 Figure 7-3. Timer Control and Status Register (TCSR)

MC68HC705J2 TIMER MOTOROLA 7-3 TOF — Timer Overflow Flag This clearable, read-only bit becomes set when the first eight stages of the counter roll over from $FF to $00. TOF generates a timer overflow interrupt request if TOFE is also set. Clear TOF by writing a zero to it. Writing a one to TOF has no effect. RTIF — Real-Time Interrupt Flag This clearable, read-only bit becomes set when the selected RTI output becomes active. RTIF generates a real-time interrupt request if RTIE is also set. Clear RTIF by writing a zero to it. Writing a one to RTIF has no effect. TOIE — Timer Overflow Interrupt Enable This read/write bit enables timer overflow interrupts. 1 = Timer overflow interrupts enabled 0 = Timer overflow interrupts disabled RTIE — Real-Time Interrupt Enable This read/write bit enables real-time interrupts 1 = Real-time interrupts enabled 0 = Real-time interrupts disabled Bits 3 and 2 — Not used. Always read as zeros. RT1, RT0 — Real-Time 1 and 0 These read/write bits select one of four real-time interrupt rates. See Table 7-1. The real-time interrupt rate should be selected by reset initialization software. A reset sets both RT1 and RT0, selecting the lowest real-time interrupt rate. Changing the real-time interrupt rate near the end of the RTI period or during a cycle in which the counter is switching can produce unpredictable results. Because the selected RTI output drives the COP timer, changing the real-time interrupt rate also changes the counting rate of the COP timer. Table 7-1. Real-Time Interrupt Rate Selection RT1:RT0 RTI Rate RTI Period (fop = 2 MHz) COP Timeout Period (-0/+1 RTI Period) Minimum COP Timeout Period ( fop = 2 MHz) 0 0 fop ‚ 214 8.2 ms 7 · RTI Period 57.3 ms 0 1 fop ‚ 215 16.4 ms 7 · RTI Period 114.7 ms 1 0 fop ‚ 216 32.8 ms 7 · RTI Period 229.4 ms 1 1 fop ‚ 217 65.5 ms 7 · RTI Period 458.8 ms

MOTOROLA TIMER MC68HC705J2 7-4

7.3 COP Timer

Three counter stages at the end of the timer make up the computer operating properly (COP) timer. (See Figure 7-1.) The COP timer is a software error detection system that automatically times out and resets the MCU if not cleared periodically by a program sequence. Writing a zero to bit 0 of the COP register clears the COP timer and prevents a COP timer reset. (See Figure 7-4.) COPR — COP Register $0FF0 MC68HC05J1 Emulation Mode: $07F0 Bit 7 654321 Bit 0 Figure 7-4. COP Register (COPR) COPC — COP Clear This write-only bit resets the COP timer. Reading address $0FF0 returns the EPROM data at that address.

MC68HC705J2 BOOTLOADER MODE MOTOROLA 8-1 SECTION 8 BOOTLOADER MODE This section describes how to use the bootloader ROM to download to the on-chip EPROM.

8.1 Bootloader ROM

The bootloader ROM, located at addresses $0F01–$0FEF, contains routines for copying to the on-chip EPROM from an external EPROM or from a personal computer. In MC68HC705J2 native mode, the bootloader copies to the 2 Kbyte space located at EPROM addresses $0700–$0EFF. In MC68HC05J1 emulation mode, the bootloader copies to the 1 Kbyte space located at EPROM addresses $0300–$06FF. The addresses of the copied code must correspond to the internal addresses to which the code is copied. The bootloader ignores all other addresses. The COP timer is automatically disabled in bootloader mode.

8.1.1 External EPROM Downloading

Figure 8-1 shows the circuit used to download to the on-chip EPROM from a 2764 EPROM. The bootloader circuit includes an external 12-bit counter to address the EPROM containing the code to be copied. Operation is fastest when unused external EPROM addresses contain $00.

MOTOROLA BOOTLOADER MODE MC68HC705J2 8-2 OSC 1 OSC 2 PA 0 PA 1 PA 2 PA 3 PA 4 PA 5 PA 6 PA 7 RESE T 1 m F

4 MH z

V VDD 10 kW

2764 MC1404 0

Figure 8-1. Bootloader Circuit The bootloader function begins when a rising edge occurs on the RESET pin while the IRQ /VPP pin is at VPP , the PB1 pin is at logical one, and the PB0 pin is grounded. The PB2 pin selects the bootloader function, as the following table shows. Table 8-1. Bootloader Function Selection PB2 Bootloader Function

1 Program and Verify

0 Verify

MC68HC705J2 BOOTLOADER MODE MOTOROLA 8-3 Complete the following steps to bootload the MCU: 1. Turn off all power to the circuit. 2. Install the MCU and the EPROM. 3. Select the MCU mode: a. Install a jumper between points 2 and 3 to program the MCU as an MC68HC705J2. b. Install a jumper between points 1 and 2 to program the MCU as an MC68HC05J1. 4. Select the bootloader function: a. Open switch S2 to select the program and verify function. b. Close switch S2 to select the verify only function. 5. Close switch S1 to reset the MCU. 6. Apply V DD to the circuit. 7. Apply the EPROM programming voltage, VPP , to the circuit. 8. Open switch S1 to take the MCU out of reset. During programming the PROGRAM LED turns on. It turns off when the verification routine begins. If verification is successful, the VERIFY LED turns on. If the bootloader finds an error during verification, it puts the error address on the external address bus and stops running. 9. Close switch S1 to reset the MCU. 10. Remove the VPP voltage. 11. Remove the VDD voltage.

8.2 Host Downloading

The MC68HC05P8EVS board supports downloading user programs directly from a personal computer. Refer to MC68HC05P8EVS Customer Specified Integrated Circuit (CSIC) Evaluation System, Motorola document number BR735/D.

MOTOROLA BOOTLOADER MODE MC68HC705J2 8-4

8.3 Mask Option Register (MOR)

The mask option register is an EPROM byte that contains three bits to control the following options:

• MC68HC05J1 emulation mode
• External interrupt trigger sensitivity
• COP timer (enable/disable) The mask option register is programmable only when using the bootloader function to download to the EPROM. MOR — Mask Option Register $0F00 MC68HC05J1 Emulation Mode: $0700 Bit 7 654321 Bit 0 Figure 8-2. Mask Option Register (MOR) J1 — MC68HC05J1 Emulation Mode Select This bit can be read at any time, but can be programmed only by the bootloader. 1 = Emulation mode selected; MCU functions as MC68HC05J1 0 = (Erased state) MC68HC705J2 native mode selected IRQ — Interrupt Request This bit can be read at any time, but can be programmed only by the bootloader. 1 = IRQ trigger is both edge-sensitive and level-sensitive 0 = (Erased state) IRQ trigger is edge-sensitive only COP — COP Timer Enable This bit can be read at any time, but can be programmed only by the bootloader. 1 = COP timer enabled 0 = (Erased state) COP timer disabled

MC68HC705J2 MC68HC05J1 EMULATION MODE MOTOROLA 9-1 SECTION 9 MC68HC05J1 EMULATION MODE This section describes how to use the MC68HC05J1 emulation mode to achieve compatibility with MC68HC05J1 devices.

9.1 Bootloading

Use the bootloader function to put the MCU in MC68HC05J1 emulation mode. To activate the emulation mode: 1. Connect pin PB5 to VDD in the bootloader circuit. 2. Program the J1 bit (in the mask option register) high.

9.2 MC68HC05J1 Emulation

In MC68HC05J1 emulation mode, the MCU operates as an MC68HC05J1 with the following exceptions:

• The emulation mode does not support the RC oscillator mask option of the MC68HC05J1.
• The emulation mode does not support the STOP disable mask option of the MC68HC05J1.
• The emulation mode has no self-check function.

MOTOROLA MC68HC05J1 EMULATION MODE MC68HC705J2 9-2

9.3 Memory Map

Figure 9-1 shows the 2 Kbyte MC68HC05J1 emulation mode memory map. PORT A DATA REGIS T TIMER INTERRUPT VECTOR (H TIMER INTERRUPT VECTOR ( EXTERNAL INTERRUPT VECTOR EXTERNAL INTERRUPT VECTO R SOFTWARE INTERRUPT VECTOR SOFTWARE INTERRUPT VECTO R RESET VECTOR (HI RESET VECTOR (L O $001C $001B $0009 $0008 $0007 $0006 $0005 $0004 $0003 $0002 $0001 $0000 $07F7 $07F8 $07F9 $07FA $07FB $07FC $07FD $07FE $07FF PORT B DATA REGIST PORT A DATA DIRECTION REG I PORT B DATA DIRECTION REGIS UNUSE D EPROM PROGRAMMING REGIS T COP REGISTE $07F0 WRITING 0 TO BIT 0 OF $07F0 C COP TIMER. READING $07F0 RET USER EPROM DATA. UNUSED

160 BYTES

$000 $001F $07FF I/O REGISTERS (EPROM) $07EF $02FF UNUSED

512 BYTES

TIMER CONTROL & STATUS REG I $000AUNUSE D $030 $00BF $00C $002 $00FF $010 $07F0 USER EPRO M

1024 BYTES

$06FF $070 $070 MASK OPTION REGIST STACK RA M $001D $001E $001F Figure 9-1. MC68HC05J1 Emulation Mode Memory Map

MC68HC705J2 ELECTRICAL SPECIFICATIONS MOTOROLA 10-1 SECTION 10 ELECTRICAL SPECIFICATIONS This section contains parametric and timing information.

10.1 Maximum Ratings

The MCU contains circuitry that protects the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in Table 10-1. Keep Vin and Vout within the range VSS £ (Vin or Vout) £ VDD . Connect unused inputs to the appropriate logical voltage level, either VSS or VDD . Table 10-1. Maximum Ratings Rating Symbol Value Unit Supply Voltage V DD –0.3 to +7.0 V Input Voltage All Pins in Normal Operation IRQ /VPP Pin in Bootloader Mode Vin VSS – 0.3 to VDD + 0.3 VSS – 0.3 to 2 · VDD + 0.3 V EPROM Programming Voltage (IRQ /VPP Pin) V PP 16.75 V Current Drain Per Pin (ExcludingVDD and VSS )I 2 5 m A Operating Temperature Range MC68HC705J2P, DW (Standard) MC68HC705J2CP, CDW (Extended) MC68HC705J2VP , VDW T A 0 to +70 –40 to +85 –40 to +105 ° C Storage Temperature Range T STG –65 to +150 ° C

10.2 Thermal Characteristics

Table 10-2. Thermal Resistance Characteristic Symbol Value Unit Thermal Resistance PDIP SOIC q JA 60 °C/W

MOTOROLA ELECTRICAL SPECIFICATIONS MC68HC705J2 10-2

10.3 Power Considerations

The average chip-junction temperature, TJ, in °C, can be obtained from: TJ = TA + (PD · qJA) (1) where: TA = Ambient temperature, °C qJA = Package thermal resistance, junction to ambient, °C/W PD = PINT + PI/O PINT = IDD · VDD watts (chip internal power) PI/O = Power dissipation on input and output pins (user-determined) For most applications PI/O « PINT and can be neglected. The following is an approximate relationship between PD and TJ (neglecting PI/O ): Solving equations (1) and (2) for K gives: K = PD · (TA + 273 °C) + qJA · (PD )2 (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA.

MC68HC705J2 ELECTRICAL SPECIFICATIONS MOTOROLA 10-3 10.4 DC Electrical Characteristics (VDD = 5.0 Vdc) Table 10-3. DC Electrical Characteristics (VDD = 5.0 Vdc) Characteristic Symbol Min Typ Max Unit Output Voltage Iload = 10.0 mA Iload = –10.0 mA VOL VOH VDD – 0.1 0.1 V Output High Voltage (Iload = –0.8 mA) PA7–PA0, PB5–PB0 VOH VDD – 0.8 — — V Output Low Voltage (Iload = 1.6 mA) PA7–PA0, PB5–PB0 VOL — — 0.4 V Input High Voltage PA7–PA0, PB5–PB0, IRQ /VPP , RESET , OSC1 VIH 0.7 · VDD —V DD V Input Low Voltage PA7–PA0, PB5–PB0, IRQ /VPP , RESET , OSC1 VIL V SS — 0.2 · VDD V Supply Current (See NOTES.) Run Wait Stop 25 °C –40 to +85 °C I DD 5.0 1.3 2.0 7.0 2.5 100 mA mA mA mA I/O Ports High-Z Leakage Current PA7–PA0, PB5–PB0 IOZ —— –10 mA Input Current RESET , IRQ /VPP , OSC1 Iin —— –1 mA Capacitance Ports (as input or output) RESET , IRQ /VPP C out Cin pF Programming Voltage V PP 16.25 16.5 16.75 V Programming Current I PP —51 0 m A Programming Time/Byte t EPGM 4— — m s NOTES: 1. Typical values at midpoint of voltage range, 25 °C only. 2. Run (operating) IDD and wait IDD measured using external square wave clock source (fosc = 4.2 MHz), all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. 3. Wait IDD and Stop IDD : all ports configured as inputs; VIL = 0.2 V, VIH = VDD – 0.2 V. 4. Stop IDD measured with OSC1 = VSS . 5. Standard temperature range is 0 °C to 70 °C. 6. OSC2 capacitance linearly affects Wait IDD . 7. Programming voltage measured at IRQ/VPP pin.

MOTOROLA ELECTRICAL SPECIFICATIONS MC68HC705J2 10-4 10.5 DC Electrical Characteristics (VDD = 3.3 Vdc) Table 10-4. DC Electrical Characteristics (VDD = 3.3 Vdc) Characteristic Symbol Min Typ Max Unit Output Voltage Iload = 10.0 mA Iload = –10.0 mA VOL VOH VDD – 0.1 0.1 V Output High Voltage (Iload = –0.2 mA) PA7–PA0, PB5–PB0 VOH VDD – 0.3 — — V Output Low Voltage (Iload = 0.4 mA) PA7–PA0, PB5–PB0 VOL — — 0.3 V Input High Voltage PA7–PA0, PB5–PB0, IRQ /VPP , RESET , OSC1 VIH 0.7 · VDD —V DD V Input Low Voltage PA7–PA0, PB5–PB0, IRQ /VPP , RESET , OSC1 VIL V SS — 0.2 · VDD V Supply Current (See NOTES.) Run Wait Stop 25 °C –40 to +85 °C I DD 1.3 0.7 1.0 2.0 1.0 mA mA mA mA I/O Ports High-Z Leakage Current PA7–PA0, PB5–PB0 Ioz —— –10 mA Input Current RESET , IRQ /VPP , OSC1 Iin —— –1 mA Capacitance Ports (as input or output) RESET , IRQ /VPP C out Cin pF pF NOTES: 1. Typical values at midpoint of voltage range, 25 °C only. 2. Run (operating) IDD and Wait IDD measured using external square wave clock source (fosc = 2 MHz), all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. 3. Wait IDD and Stop IDD : all ports configured as inputs; VIL = 0.2 V, VIH = VDD – 0.2 V. 4. Stop IDD measured with OSC1 = VSS . 5. Standard temperature range is 0 °C to 70 °C. 6. OSC2 capacitance linearly affects Wait IDD . TEST POIN VD D R2 VD DPINS PA7–PA0, PB5–P 4.5 V 3.0 V 3.26 kW 10.91 kW R 2 2.38 kW 6.32 kW C 50 pF 50 pFC

MOTOROLA ELECTRICAL SPECIFICATIONS MC68HC705J2 10-8 10.6 Control Timing (VDD = 5.0 Vdc) Table 10-5. Control Timing (VDD = 5.0 Vdc) (VDD = 5.0 Vdc – 10%, VSS = 0 Vdc; TA = TL to TH ) Characteristic Symbol Min Max Unit Oscillator Frequency Crystal Option External Clock Option fosc — dc 4.2

4.2 MHz

Internal Operating Frequency Crystal (fosc ‚ 2) External Clock (fosc ‚ 2) fop — dc 2.1

2.1 MHz

Cycle Time t cyc 480 — ns RESET Pulse Width tRL 1.5 — t cyc Timer Resolution (NOTE 1) t RESL 4.0 — t cyc Interrupt Pulse Width Low (Edge-Triggered) t ILIH 125 — ns Interrupt Pulse Period t ILIL (NOTE 2) — t cyc OSC1 Pulse Width t OH , tOL 90 — ns Programming Time per Byte t EPGM 4— m s NOTES: 1. The 2-bit timer prescaler is the limiting factor in determining timer resolution. 2. The minimum period t ILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 19 tcyc. 1IRQ nIRQ IRQ (PIN IRQ (MCU ILIHt ILILt ILIHt NORMALLY USED WITH WIRED–OR CONNECTI O Edge and Level-Sensitive Trigger — If IRQ remains low after interrupt is serviced, the next interrupt is recognized. Edge-Sensitive Trigger — The minimum t is either 125 ns (V = 5 V) or 250 ns (V = 3 V). The period t should not be less than the number of t cycles it takes to execute the interrupt service routine plus 19 t cycles. ILIH D D D D ILIL cyccyc Figure 10-6. External Interrupt Timing

MC68HC705J2 ELECTRICAL SPECIFICATIONS MOTOROLA 10-9 10.7 Control Timing (VDD = 3.3 Vdc) Table 10-6. Control Timing (VDD = 3.3 Vdc) (VDD = 3.3 Vdc – 10%, VSS = 0 Vdc; TA = TL to TH ) Characteristic Symbol Min Max Unit Oscillator Frequency Crystal Option External Clock Option fosc — dc 2.0

2.0 MHz

Internal Operating Frequency Crystal (fosc ‚ 2) External Clock (fosc ‚ 2) fop — dc 1.0

1.0 MHz

Cycle Time t cyc 1000 — ns RESET Pulse Width tRL 1.5 — t cyc Timer Resolution (NOTE 1) t RESL 4.0 — t cyc Interrupt Pulse Width Low (Edge-Triggered) t ILIH 250 — ns Interrupt Pulse Period t ILIL (NOTE 2) — t cyc OSC1 Pulse Width t OH , tOL 400 — ns NOTES: 1. The 2-bit timer prescaler is the limiting factor in determining timer resolution. 2. The minimum period t ILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 19 tcyc.

MOTOROLA ELECTRICAL SPECIFICATIONS MC68HC705J2 10-10 INTERN A ADDRES S BUS OSC 1 RESE T IRQ IRQ3 tRL tILIH tILCH 4064 CYC INTERN A CLOCK FFE4 FFE4 FFE4 FFF4 NOTES: 1. Represents internal gating of OSC1 pin. 2. IRQ pin edge-sensitive mask option. 3. IRQ pin level and edge-sensitive mask option. 4. Reset vector address of MC68HC705J2 native mode shown as timing example. RESET OR INTERRU VECTOR FETCH Figure 10-7. STOP Recovery Timing