35XS3500 FREESCALE | Alldatasheet

Document overview

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Technical content

Features

  • Penta 35 mΩ high side switches
  • 16-bit SPI communication interface with daisy chain capability
  • Current sense output with SPI-programmable multiplex switch and Board Temperature Feedback
  • Digital diagnosis feature
  • PWM module with multiphase feature including prescaler
  • LEDs control including accurate current sensing and low duty- cycle capability
  • Fully protected switches
  • Over-current shutdown detection
  • Power net and reverse polarity protection
  • Low-power mode
  • Fail mode functions incl uding auto restart feature
  • External smart power switch control including current recopy
  • Lead-free packaging designated by suffix code PNA

Figure 1. 35XS3500 Simplified Application Diagram

ORDERING INFORMATION

Range (TA) Package MC35XS3500PNA -40 to 125 °C 24 PQFN PNA SUFFIX 98ART10511D 24-PIN PQFN PB FREE Bottom View MCU 35XS3500 LIMP FLASHER IGN RST CLOCK CS SI SCLK CSNS GND VCC VBAT CP OUT1 OUT2 OUT3 OUT4 OUT5 FETIN FETOUT Watchdog VBAT 12V 5.0V 12V Smart Switch STOP

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Figure 2. 35XS3500 Simplified Internal Block Diagram

Figure 3. 35XS3500 Pin Connections (Transparent Package Top View) Table 1. 35XS3500 Pin Definitions Functional descriptions these pins can be found in the Functional Description section beginning on page 18. 1 FETIN Input External FET Input This pin is the current sense recopy of the external MOSFET.

2 IGN Input Ignition Input

mode activation. This pin has a passive internal pull-down.

4 FLASHER Input Flasher Input

This input wakes the device. This pin has a passive internal pull-down. 5 CLOCK Input Clock Input This pin state depends on RST logic level. generated from this digital clock input by the PWM module. This pin has a passive internal pull-down.

6 LIMP Input Limp Home Input

internal pull-down current source.

7 STOP Input Stop Light Input

This input wakes the device. This pin has a passive internal pull-down.

8 CS Input Chip Select

this signal returns high. This pin has a passive internal pull-up resistance.

9 SCLK Input SPI Clock Input This input pin is connected to the master microcontroller providing the

internal pull-down resistance.

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a passive internal pull-down resistance. 11 VCC Input Logic Supply SPI Logic power supply. negative edge of SCLK, and when CS is high. This pin is high-impedance. 15 VBAT Input Battery Input Power supply pin.

16 CP Output Charge Pump This pin is the connection for an external tank capacitor (for internal use

Protected 35 mΩ high side power output to the load. report a voltage proportional to the temperature on the GND flag.

  1. The pins 14, 17, and 23 must be shorted on the board.

Table 1. 35XS3500 Pin Definitions (continued) Functional descriptions these pins can be found in the Functional Description section beginning on page 18.

Analog Integrated Circuit Device Data Freescale Semiconductor 5 35XS3500

ELECTRICAL CHARACTERISTICS

Table 2. Maximum Ratings permanent damage to the device.

2.0 Min @ 25 °C

  1. ESD testing is performed in accordanc e with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω) and the Charge Device
  2. Pin soldering temperature limit is for 40 seconds maximum durat ion. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device. If the qualification fails, TSOLDER will be changed for 240 °C.

  1. Typical value is guaranteed per design.

Analog Integrated Circuit Device Data

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STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions 3.0 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VBAT ≤ 20 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.

3.0 MHz SPI Communication

  1. In extended mode, the functionality is guaranteed but not the electrical parameters.
  2. Valid for RST, SI, SCLK, CLOCK, FLASHER, STOP, and LIMP pins.
  3. Valid for the following input voltage range: VCC = -0.3 to +0.3 V.
  4. Please refer to Loss of VBAT section for more details.

Analog Integrated Circuit Device Data Freescale Semiconductor 7 35XS3500 STATIC ELECTRICAL CHARACTERISTICS LOGIC INPUT/ OUTPUT (IGN, CS, CSNS, SI, SCLK, CLOCK, SO, FLASHER, RST, LIMP, STOP) (CONTINUED) CLOCK Output Voltage reporting wake-up event (ICLOCK=1.0 mA) VCLOCKH 0.8 0.95 – VCC SO Low-state Output Voltage IOL = -1.6 mA VSOL – 0.2 0.4 V SO Tri-state Leakage Current CS > 0.7 VCC ISOLEAK - 1.0 0.0 1.0 μA CSNS Tri-state Leakage Current VCC = 5.5 V, CSNS = 5.5 V VCC = 5.0 V, CSNS = 5.5 V VCC = 5.0 V, CSNS = 4.5 V ICSNSLEAK - 5.0 - 10 - 1.0 1.0 1.0 1.0 μA Current Sense Output Clamp Voltage ICSNS < 10.0 mA VCSNS 5.0 6.0 7.0 V OUTPUT (OUT 1:5) Output Leakage Current in OFF state Sleep mode, Outputs Grounded Normal mode, Outputs Grounded IOUTLEAK 2.0 μA Output Negative Clamp Voltage IOUT = -500 mA, Outputs OFF VOUT - 22 – -16 V Current Sense Output Precision(9) Full-Scale Range (FSR) for LED Control bit = 0

0.75 FSR

0.50 FSR

0.25 FSR

0.10 FSR

Full-Scale Range (FSR) for LED Control bit = 1 0.187 FSR = 0.75 FSRLED 0.125 FSR = 0.50 FSRLED 0.062 FSR = 0.25 FSRLED 0.025 FSR = 0.10 FSRLED δICS / ICS -14 -15 -17 -22 -13 -13 -20 -30 Current Sense Output Precision Over-temperature Range [-40;125 °C], VBAT Range [10 V-16 V] and FSR Range [25%-100%], calculated with one calibration point (Taken at 25 °C, VBAT = 13.5 V and 50% FSR)(11) -6.0 - 6.0 % Current Sense Output Precision with one calibration point (50% FSRLED, VBAT = 13.5 at 25 °C(11) -6.0 – 6.0 % Temperature Drift of Current Sense Output(10) VBAT = 13.5 V, IOUT = 2.8 A reference taken at TA = 25 °C ΔICS / ΔT – ± 280 ± 400 ppm/ Minimum Output Current Reported in CSNS for OUT1-5

10 V ≤ VBAT ≤ 16 V

I35MIN(CSNS) 65 – – mA Minimum Output Current Reported in CSNS for OUT[1-5] in LED Mode(12) I35MIN(CSNS) LED 40 – – mA Notes 9. 10 V < VBAT < 16 V. (δICS / ICS = (measured ICS- targeted ICS)/ targeted ICS with targeted ICS = 5.0 mA 10. Based on statistical data. Not production tested. ΔICS / ΔT = [(measured at ICS at T1 - measured at ICS at T2) measured at ICS at room]/ (T1 - T2) 11. Based on statistical analysis covering 99.74% of parts. 12. Output current value computed after leakage current removal (open load condition) Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 3.0 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VBAT ≤ 20 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data

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STATIC ELECTRICAL CHARACTERISTICS OUTPUT (OUT 1:5) (CONTINUED) Over-temperature Shutdown TOTS 155 175 195 °C Thermal Prewarning(13) TOTSWARN 110 125 140 °C Output Voltage Threshold VOUT_TH 0.475 0.5 0.525 VBAT TAIL LIGHT (OUT1) Output Drain-to-Source ON Resistance (IOUT = 2.8 A, TA = 25 °C) VBAT = 13.5 V VBAT = 7.0 V RDS(ON) mΩ Output Drain-to-Source ON Resistance (IOUT = 2.8 A, VBAT = 13.5 V, TA = 150 °C)(13) RDS(ON) – – 59.5 mΩ Reverse Output ON Resistance (IOUT = -2.8 A, VBAT = -12 V, TA = 25 °C)(14) RSD(ON) – – 70 mΩ TAIL LIGHT (OUT1) Output Drain-to-Source ON Resistance (IOUT = 1.5 A, TA = 25 °C) for LED Control = 1 VBAT = 13.5 V VBAT = 7.0 V RDS(ON)25_LED 110 mΩ Output Drain-to-Source ON Resistance (IOUT = 1.5 A, VBAT = 13.5 V, TA = 150 °C) for LED Control = 1 RDS(ON)150_LED – – 119 mΩ High Over-current Shutdown Threshold 1 VBAT = 16 V, TA = -40 °C VBAT = 16 V, TA = 25 °C VBAT = 16 V, TA = 125 °C IOCHI1 28.0 30.2 29.4 28.3 35.0 36.0 35.0 33.8 43.5 41.8 40.6 39.3 A High Over-current Shutdown Threshold 2 IOCHI2 12.3 15.4 18.5 A Low Over-current Shutdown Threshold IOCLO 5.7 7.2 8.9 A Open Load Current Threshold in ON State(15) IOL 0.05 0.2 0.5 A Open Load Current Threshold in ON State with LED(16) VOL = VBAT - 0.5 V IOLLED 4.0 10 20 mA Current Sense Full-scale Range(17) ICS FSR – 6.0 – A Current Sense Full-scale Range(13) depending on LED Control = 1 ICS FSR_LED – 1.6 – A Severe short-circuit impedance range(13) RSC1(OUT1) 350 mΩ Notes 13. Parameter guaranteed by design; however it is not production tested. 14. Source-to-Drain ON Resistance (Reverse Drain-to -Source ON Resistance) with negative polarity VBAT. 15. OLLED1, bit D0 in SI data is set to [0] 16. OLLED1, bit D0 in SI data is set to [1] 17. For a typical value of I CS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is not guaranteed. Characteristics noted under conditions 3.0 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VBAT ≤ 20 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 9 35XS3500 STATIC ELECTRICAL CHARACTERISTICS LICENSE LIGHT (OUT2) Output Drain-to-Source ON Resistance (IOUT = 2.8 A, TA = 25 °C) VBAT = 13.5 V VBAT = 7.0 V RDS(ON) mΩ Output Drain-to-Source ON Resistance (IOUT = -2.8 A, VBAT = -13.5 V, TA = 25 °C)(22) RDS(ON) – – 59.5 mΩ Reverse Output ON Resistance (IOUT = 2.8 A, VBAT = 12 V, TA = 150 °C)(18) RSD(ON) – – 70 mΩ Output Drain-to-Source ON Resistance (IOUT =1.5 A, TA = 25 °C) for LED Control = 1 VBAT = 13.5 V VBAT = 7.0 V RDS(ON)25_LED 110 mΩ Output Drain-to-Source ON Resistance (IOUT = 1.5 A, VBAT = 13.5 V, TA = 150 °C) for LED Control = 1 RDS(ON)150_LED – – 119 mΩ High Over-current Shutdown Threshold 1 VBAT = 16 V, TA = -40 °C VBAT = 16 V, TA = 25 °C VBAT = 16 V, TA = 125 °C IOCHI1 28.0 30.2 29.4 28.3 35.0 36.0 35.0 33.8 43.5 41.8 40.6 39.3 A High Over-current Shutdown Threshold 2 IOCHI2 12.3 15.4 18.5 A Low Over-current Shutdown Threshold IOCLO 5.7 7.2 8.9 A Open Load Current Threshold in ON State(19) IOL 0.05 0.2 0.5 A Open Load Current Threshold in ON State with LED(20) VOL = VBAT - 0.5 V IOLLED 4.0 10 20 mA Current Sense Full-Scale Range(21) ICS FSR – 6.0 – A Current Sense Full-Scale Range(22) depending on LED Control = 1 ICS FSR_LED – 1.6 – A Notes 18. Source-to-Drain ON Resistance (Reverse Drain-to -Source ON Resistance) with negative polarity VBAT. 19. OLLED2, bit D0 in SI data is set to [0] 20. OLLED2, bit D0 in SI data is set to [1] 21. For typical value of I CS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is not guaranteed. 22. Parameter guaranteed by design; however, it is not production tested. Characteristics noted under conditions 3.0 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VBAT ≤ 20 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data

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STATIC ELECTRICAL CHARACTERISTICS LICENSE LIGHT (OUT2) (CONTINUED) Severe short-circuit impedance range(23) RSC1(OUT2) 350 mΩ TAIL LIGHT (OUT3) Output Drain-to-Source ON Resistance (IOUT = 2.8 A, TA = 25 °C) VBAT = 13.5 V VBAT = 7.0 V RDS(ON)25 mΩ Output Drain-to-Source ON Resistance (IOUT = 2.8 A, VBAT = 13.5 V, TA = 150 °C)(23) RDS(ON)150 – – 59.5 mΩ Reverse Source-to-Drain ON Resistance (IOUT = -2.8 A, VBAT = -12 V, TA = 25 °C)(24) RSD(ON)25 – – 70 mΩ Output Drain-to-Source ON Resistance (IOUT = 1.5 A, TA = 25 °C) for LED Control = 1 VBAT = 13.5 V VBAT = 7.0 V RDS(ON)25_LED 110 mΩ Output Drain-to-Source ON Resistance (IOUT = 1.5 A, VBAT = 13.5 V, TA = 150 °C) for LED Control = 1 RDS(ON)150_LED – – 119 mΩ High Over Current Shutdown Threshold 1 VBAT = 16 V, TA = -40 °C VBAT = 16 V, TA = 25 °C VBAT = 16 V, TA = 125 °C IOCHI1 28.0 30.2 29.4 28.3 35.0 36.0 35.0 33.8 43.5 41.8 40.6 39.3 A High Over-current Shutdown Threshold 2 IOCHI2 12.3 15.4 18.5 A Low Over-current Shutdown Threshold IOCLO 5.7 7.2 8.9 A Open Load Current Threshold in ON State(25) IOL 0.05 0.2 0.5 A Open Load Current Threshold in ON State with LED(26) VOL = VBAT - 0.5 V IOLLED 4.0 10 20 mA Current Sense Full-scale Range(27) ICS FSR – 6.0 – A Current Sense Full-scale Range(22) depending on LED Control = 1 ICS FSR_LED – 1.6 – A Severe short-circuit impedance range(23) RSC1(OUT3) 350 mΩ Notes 23. Parameter guaranteed by design; however, it is not production tested. 24. Source-to-Drain ON Resistance (Reverse Drain-to -Source ON Resistance) with negative polarity VBAT. 25. OLLED3, bit D2 in SI data is set to [0] 26. OLLED3, bit D2 in SI data is set to [1] 27. For a typical value of I CS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is not guaranteed. Characteristics noted under conditions 3.0 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VBAT ≤ 20 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 11 35XS3500 STATIC ELECTRICAL CHARACTERISTICS STOP LIGHT (OUT4) Output Drain-to-Source ON Resistance (IOUT = 2.8 A, TA = 25 °C) VBAT = 13.5 V VBAT = 7.0 V RDS(ON)25 mΩ Output Drain-to-Source ON Resistance (IOUT = 2.8 A, VBAT = 13.5 V, TA = 150 °C)(28) RDS(ON)150 – – 59.5 mΩ Output Drain-to-Source ON Resistance (IOUT = 1.5 A, TA = 25 °C) for LED Control = 1 VBAT = 13.5 V VBAT = 7.0 V RDS(ON)25_LED 110 mΩ Output Drain-to-Source ON Resistance (IOUT =1.5 A, VBAT = 13.5 V, TA = 150 °C) for LED Control = 1 RDS(ON)150_LED – – 119 mΩ Reverse Source-to-Drain ON Resistance (IOUT = -2.8 A, VBAT = -12 V, TA = 25 °C)(29) RDS(ON)25 – – 70 mΩ High Over-current Shutdown Threshold 1 VBAT = 16 V, TA = -40 °C VBAT = 16 V, TA = 25 °C VBAT = 16 V, TA = 125 °C IOCHI1 28.0 30.2 29.4 28.3 35.0 36.0 35.0 33.8 43.5 41.8 40.6 39.3 A High Over-current Shutdown Threshold 2 IOCHI2 12.3 15.4 18.5 A Low Over-current Shutdown Threshold IOCLO 5.7 7.2 8.9 A Open Load Current Threshold in ON State(30) IOL 0.05 0.2 0.5 A Open Load Current Threshold in ON State with LED(31) VOL = VBAT - 0.5 V IOLLED 4.0 10 20 mA Current Sense Full-scale Range(32) ICS FSR – 6.0 – A Current Sense Full-scale Range(22) depending on LED Control = 1 ICS FSR_LED – 1.6 – A Severe short-circuit impedance range(28) RSC1(OUT4) 350 mΩ FLASHER (OUT5) Output Drain-to-Source ON Resistance (IOUT = 2.8 A, TA = 25 °C) VBAT = 13.5 V VBAT = 7.0 V RDS(ON)25 mΩ Output Drain-to-Source ON Resistance (IOUT = 2.8 A, VBAT = 13.5 V, TA = 150 °C)(28) RDS(ON)150 – – 59.5 mΩ Reverse Source-to-Drain ON Resistance (IOUT = -2.8 A, VBAT = -12 V, TA = 25 °C)(29) RSD(ON)25 – – 70 mΩ Notes 28. Parameter guaranteed by design; however, it is not production tested. 29. Source-to-Drain ON Resistance (Reverse Drain-to -Source ON Resistance) with negative polarity VBAT. 30. OLLED3, bit D2 in SI data is set to [0] 31. OLLED3, bit D2 in SI data is set to [1] 32. For a typical value of I CS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is not guaranteed. Characteristics noted under conditions 3.0 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VBAT ≤ 20 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data

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STATIC ELECTRICAL CHARACTERISTICS FLASHER (OUT5) (CONTINUED) Output Drain-to-Source ON Resistance (IOUT =1.5 A, TA = 25 °C) for LED Control = 1 VBAT = 13.5 V VBAT = 7.0 V RDS(ON)25_LED 110 mΩ Output Drain-to-Source ON Resistance (IOUT = 1.5 A, VBAT = 13.5 V, TA = 150 °C) for LED Control = 1 RDS(ON)150_LED – – 119 mΩ High Over Current Shutdown Threshold 1 VBAT = 16 V, TA = -40 °C VBAT = 16 V, TA = 25 °C VBAT = 16 V, TA = 125 °C IOCHI1 28.0 30.2 29.4 28.3 35.0 36.0 35.0 33.8 43.5 41.8 40.6 39.3 A High Over-current Shutdown Threshold 2 IOCHI2 12.3 15.4 18.5 A Low Over-current Shutdown Threshold IOCLO 5.7 7.2 8.9 A Open Load Current Threshold in ON State(34) IOL 0.05 0.2 0.5 A Open Load Current Threshold in ON State with LED(35) VOL = VBAT - 0.5 V IOLLED 4.0 10 20 mA Current Sense Full-scale Range(36) ICS FSR – 6.0 – A Current Sense Full-scale Range(22) depending on LED Control = 1 ICS FSR_LED – 1.6 – A Severe short-circuit impedance range(33) RSC1(OUT5) 350 mΩ SPARE (FETOUT , FETIN) FETOUT Output High Level @ I = 1.0 mA VH MAX 0.8 – – VCC FETOUT Output Low Level @ I = 1.0 mA VH MIN – 0.2 0.4 V FETIN Input Full Scale Range Current IFET IN – 5.0 – mA FETIN Input Clamp Voltage VCLIN 5.3 – 7.0 V Drop Voltage between FETIN and CSNS for MUX[2:0] = 110 IFET IN = 5 mA, 5.5 V > CSNS > 0.0 V VDRIN 0.0 – 0.4 V FETIN Leakage Current when external current switch sense is enabled VCC > VFET IN > 0 V, 5.5 V > VCC 4.5 V, CSNS open VCC > VFET IN > 0 V, 4.5 V > VCC > 0, CSNS open IFETINLEAK - 1.0 - 1.0 5.0 1.0 μA TEMPERATURE OF GND FLAG Analog Temperature Feedback at TA = 25 °C with 5.0 kΩ > RCSNS > 500 Ω VT_FEED 920 1025 1140 mV Analog Temperature Feedback Derating with 5.0 kΩ > RCSNS > 500 Ω(33) VDT_FEED 10.9 11.3 11.7 mV/ Analog Temperature Feedback Precision(33) VDT_ACC -15 – 15 °C Analog Temperature Feedback Precision with calibration point at 25 °C(33) VDT_ACC_CAL -5.0 – 5.0 °C Notes 33. Parameter guaranteed by design; however, it is not production tested. 34. OLLED3, bit D2 in SI data is set to [0] 35. OLLED3, bit D2 in SI data is set to [1] 36. For a typical value of I CS FSR, ICSNS = 5.0 mA. If the range is exceeded, no current clamp and the precision is not guaranteed. Characteristics noted under conditions 3.0 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VBAT ≤ 20 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 13 35XS3500 DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VBAT ≤ 20 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.

200 Hz Output PWM frequency

400 Hz Output PWM frequency

  1. The PWM ratio is measured at V OUT = 50% of VBAT in nominal range of frequency. It is possible to put the device fully on (PWM duty

Input Timing Switching Characteristics on page 16.

  1. Linear range is defined by output duty cycle to SPI duty cycle configuration +/- LSB. For values outside the linear duty cycle range, a

calibration curve is available.

  1. Full diagnostic corresponds to t he availability of the following features: output current sensing, output status and openload detection.

Analog Integrated Circuit Device Data

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DYNAMIC ELECTRICAL CHARACTERISTICS WATCHDOG TIMING Watchdog Timeout (SPI Failure) t WDTO 50 75 100 ms I /O PLAUSIBILITY CHECK TIMING Fault Shutdown Delay Time (from Over-temperature or OCHI1 or OHCI2 or OCLO Fault Detection to Output = 50% VBAT without round shaping feature for turn off) t SD – 7.0 30 μs Under-voltage Deglitch Time(41) t UV 1.5 2.5 5.0 μs High Over-current Threshold Time 1 t 1 7.0 10 13.5 ms High Over-current Threshold Time 2 t 2 52.5 75 97.5 ms Autorestart Period tAUTORST 52.5 75 97.5 ms Autorestart Over-current Shutdown Delay Time t OCSH_AUTO 3.5 5.0 6.5 ms Limp Home Input pin Deglicher Time t LIMP 7.0 10.0 13.0 ms Cyclic Open Load Detection Timing with LED(42) t OLLED 105 150 195 ms Flasher Toggle Timeout t FLASHER 1.4 2.3 3.0 s Ignition Toggle Timeout t IGNITION 1.4 2.3 3.0 s Stop Toggle Timeout tSTOP 1.4 2.3 3.0 s Clock Input Low Frequency Detection Range f LCLK DET 1.0 2.0 4.0 kHz Clock Input High Frequency Detection Range f HCLK DET 100 200 400 kHz SPI INTERFACE CHARACTERISTICS Maximum Frequency of SPI Operation f SPI – – 3.0 MHz Rising Edge of CS to Falling Edge of CS (Required Setup Time)(43) t CS – – 1.0 us Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)(43) t LEAD – – 500 ns Required High State Duration of SCLK (Required Setup Time)(43) t WSCLKH – – 167 ns Required Low State Duration of SCLK (Required Setup Time)(43) t WSCLKl – – 167 ns Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)(43) t LAG – 50 167 ns SI to Falling Edge of SCLK (Required Setup Time)(44) t SI SU – 25 83 ns Falling Edge of SCLK to SI (Required Setup Time)(44) t SI HOLD – 25 83 ns Notes 41. This time is measured from the V BAT(UV) level to the fault reporting. Parameter guaranteed in testmode. 42. OLLEDn bit (where “n” corresponds to respective outputs 1 through 5) in SI data is set to logic [1]. Refer to Table 8, Serial Input Address and Configuration Bit Map, page 25. 43. Maximum setup time required for the 35XS3500 is the minimum guaranteed time needed from the microcontroller. 44. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VBAT ≤ 20 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data Freescale Semiconductor 15 35XS3500 DYNAMIC ELECTRICAL CHARACTERISTICS SPI INTERFACE CHARACTERISTICS (CONTINUED) SO Rise Time CL = 80 pF t RSO – 25 50 ns SO Fall Time CL = 80 pF t FSO – 25 50 ns SI, CS, SCLK, Incoming Signal Rise Time(45) t RSI – – 50 ns SI, CS, SCLK, Incoming Signal Fall Time(45) t FSI – – 50 ns Time from Falling Edge of CS to SO Low-impedance(46) t SO(EN) – – 145 ns Time from Rising Edge of CS to SO High-impedance(47) t SO(DIS) – 65 145 ns Notes 45. Time required for output status data to be available for use at SO. 1.0 kΩ on pull-up on CS. 46. Time required for output status data to be terminated at SO. 1.0 kΩ on pull-up on CS. 47. Time required to obtain valid data out from SO following the rise of SCLK. Characteristics noted under conditions 4.5 V ≤ VCC ≤ 5.5 V, 7.0 V ≤ VBAT ≤ 20 V, -40 °C ≤ TA ≤ 125 °C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.

Analog Integrated Circuit Device Data

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Figure 4. Input Timing Switching Characteristics Figure 5. SCLK Waveform and Valid SO Data Delay Time

0.7 VDD

0.2 VDD

18 Freescale Semiconductor

diagnostics are accomplished using a 16-bit SPI interface. from the switching MOSFETs to the printed circuit board. This pin is the ground of the device. frequency per output, depending PR bit value. with a resolution of 7 bits of duty cycle (bits D[6:0]). The following table describes the PWM resolution. Table 5. PWM Resolution behavior of the light module. pictures illustrate the behavior. PWM sync (initialization register).

  • with the following SPI co nfiguration: D7:D0=FF.
  • In case of clock input signal failure (out of f PWM), the outputs state depends on the D7 bit value (D7=1+ON) in Normal mode. In Fail mode. The outputs state depends on the IGN, STOP and Flasher pins. If RST=0, this pin reports the wake-up event for wake=1 when VBAT and VCC are in operational voltage range. Limp Home (LIMP) The Limp Home mode of the component can be activated by this digital input port. The signal is “high active”, meaning the Fail mode can be activated by a logic high signal at the input. On/Off (Bit D7) Duty cycle (7 bits resolution) Output state

0 X OFF

Analog Integrated Circuit Device Data Freescale Semiconductor 19 35XS3500 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION Ignition Input (IGN) The Ignition input wakes the device. It also controls the Fail Home mode activation. The signal is “high active”, meaning the component is active in case of a logic high at the input. Flasher Input (FLASHER) The Flasher input wakes the device. It also controls the Fail mode activation. The signal is “high active”, meaning the component is active in case of a logic high at the input. Reset Input (RST) This input wakes the device when the RST pin is at logic [1]. It is also used to initialize the device configuration and the SPI fault registers when the signal is low. All SI/SO registers described in Table 8 and Table 11 are reset. The fault management is not affected by RST (see Figure 2). Current Sense Output (CSNS) The current sense output pin is an analog current output or a voltage proportional to the temperature on the GND flag. The routing to the common resistor is SPI programmable. This current sense monitoring may be synchronized in case of the OUT6 is not used. So, the current sense monitoring can be synchronized with a rising edge on the FETOUT pin (tCSNS(SYNC)) if CSNS sync SPI bit is set to logic [1]. Connection of the FETOUT-pin to a MCU input pin allows the MCU to sample the CSNS-pin during a valid time-slot. Since this falling edge is generated at the end of this time- slot, upon a switch-off command, this feature may be used to implement maximum current control. Charge Pump (CP) An external capacitor is connected between this pin and the VBAT pin. It is used as a tank for the internal charge pump. Its typical value is 100 nF ± 20%, 25 V maximum. FETOUT Output (FETOUT) This output pin is used to control an external MOSFET (OUT6). The high level of the FETOUT Output is VCC if VBAT and VCC are available in case of FETOUT is controlled ON. FETOUT is not protected in case of a short circuit or under- voltage on VBAT. In case of a reverse battery, OUT6 is OFF. FETIN Input (FETIN) This input pin gives the current recopy of the external MOSFET. It can be routed on the CSNS output by a SPI command. SPI Protocol Description The SPI interface has a full-duplex, three-wire synchronous data transfer with four I /O lines associated with it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO), and Chip Select (CS). The SI/SO pins of the 35XS3500 device follow a first-in, first-out (D15 to D0) protocol, with both input and output words transferring the most significant bit (MSB) first. All inputs are compatible with 5.0 V CMOS logic levels supplied by VCC. The SPI lines perform the following functions: Serial Clock (SCLK) The SCLK pin clocks the internal shift registers of the 35XS3500 device. The SI pin accepts data into the input shift register on the falling edge of the SCLK signal, while the SO pin shifts data information out of the SO line driver on the rising edge of the SCLK signal. It is important that the SCLK pin be in a logic low state whenever CS makes any transition. For this reason, it is recommended that the SCLK pin be in a logic [0] whenever the device is not accessed (CS logic [1] state). SCLK has a passive pull-down, RDWN. When CS is logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (high-impedance) (see Figure 8).

20 Freescale Semiconductor

Figure 8. Single 16-Bit Word SPI Communication The SI pin is a serial interface command data input pin. D15 to D0. SI has a passive pull-down, RDOWN. The SO data pin is a tri-state output from the shift register. component is active in case of a logic high at the input.

  1. RSTB is in a logic H state during the above operation.
  2. DO, D1, D2, ... , and D15 relate to the most recent ordered entry of program data into the LUX IC

3 OD0 OD1 OD2 and OD15 relate to the first 16 bits of ordered fault and status data out of the LUX IC

  1. D15:D0 relate to the most recent ordered entry of data into the device.
  2. OD15:OD0 relate to the first 16 bits of ordered fault and status data out of the device.

The Sleep mode is the default mode of the 35XS3500.

  • W a k e = IGN or IGN_ON or FLASHER or FLASHER_ON or STOP or STOP_ON or RST
  • F a i l = VCC fail or SPI fail or External limp Normal Mode The 35XS3500 is in Normal mode when:
  • W a k e = 1
  • F a i l = 0 In Normal operating mode the power outputs are under full control of the SPI as follows:
  • The outputs 1 to 6, including multiphase timing, and selectable slew-rate, are controlled by the programmable PWM module.
  • The output 4 is activated dire ctly by the STOP external pin in case the STOP_en bit is set to a logic [1].
  • The outputs 1 to 5 are switched OFF in case of under- voltage on VBAT.
  • The outputs 1 to 5 are protec ted by the selectable over- current double window and over-temperature shutdown circuit.
  • The digital diagnosis featur e transfers status of the smart outputs via the SPI.
  • The analog current sense output (current recopy feature) can be rerouted by the SPI.
  • The outputs can be configur ed to control LED loads: RDS(ON) is increased by a factor of 2 and the current recopy ratio is scaled by a factor of 4.
  • The SPI reports NM=1 in this mode. The following figure describes the PWM, outputs and over- current behavior in Normal mode. Fail Mode The 35XS3500 is in Fail mode when:
  • W a k e = 1
  • F a i l = 1 In Fail mode:
  • The outputs are under control of the external pins (see Table 5).
  • The outputs are fully protec ted in case of overload, over-temperature and under-voltage (on BVAT or on VCC).
  • The SPI reports continuously the content of address 11, disregard to previous requested output data word.
  • Neither digital diagnosis feature (SPI) nor analog current sense are available.
  • In case of overload (OCHI2 or OCLO) conditions or under-voltage on VBAT, the outputs are under control of the autorestart feature.
  • In case of a serious overload condition (OCHI1 or OT) the corresponding output is latched OFF until a new wake-up event (wake = 0 then 1) Over-current Output D0-D6 bits D7 bit Over-current OUT[1,2] IGN (external) IGN_ON 1.4 sec min

Table 6. Limp Home Output State

22 Freescale Semiconductor

availability of the outputs. supervising intelligence of the microcontroller is available. 9, Over-current window in case of Autorestart). tochi_Auto, then after the output is protected by OCLO. Figure 9. Over-current window in case of Autorestart OFF. After the autorestart period (75 ms) is turned ON again. The Autorestart is not limited in time. transition into Normal mode.

  • V BAT and VCC power supplies must be above their under-voltage thresholds (Sleep mode).
  • Generate a wake-up event (wake=1) from 0 to 1 on RST. The device switches to Normal mode.
  • Apply the PWM clock after a maximum of 200 μs (min. 50 μs).
  • Send a SPI command to the device status register to clear the clock fail flag and enable the PWM module to start. If the correct startup sequence is not provided, the PWM function is not guaranteed. Figure 10 describes the wake-up block diagram. POWER OFF MODE The 35XS3500 is in Power OFF mode when the battery voltage is below VBATPOR[1,2] thresholds. For more details, please refer to Loss of VBAT paragraph. Output current OCHI1 OCLO time tochi_auto Auto period OCLO or UV fault

Figure 10. Operating Modes State Machine

24 Freescale Semiconductor

Figure 11. Wake-up Block Diagram

Table 7. The 5 bits D15 : D11, called register to latch in a message that is not 16 bits will be ignored. equals 0 or fail mode (Fail=1). section. Table 8 summarizes the content of the SI registers. Table 7. SI Message Bit Assignment MSB D15 : D11 Register address bits. protection features, and SO status content. Table 8. Serial Input Address and Configuration Bit Map Note: testmode address used only by FSL is D[15:11]=01111 with RST voltage higher than 8V typ.

26 Freescale Semiconductor

and D0 determine the content of the 16 bits of SO data. D9 : D2 are described in Table 9. Table 9. Initialization Register page 25) and to active the LED Control. Two configuration registers are available at this address. Configuration SR when D9 bit is set to logic [1]. divided by 2) is activated for the dedicated output. current sense analog feedback. synchronization signal is reported on FETOUT output pin. of under-voltage fault detection. duty cycle resolution is given by bits D6 : D0. D7 (STOPen) = 0, STOP pin does not control the output 4. D7 (STOPen) = 1, STOP pin controls the output 4. Table 10. Switching Phases

D7 = 1, D6 : D0 = 7 F output continuous ON (no PWM). the SPI during normal operation. and SOA0 defined in the last SPI initialization word). feature is useful for daisy chaining devices. accept new fault status information.

  • The previous SPI communication was determined to be invalid. In this case, the status will be reported as though the invalid SPI communication never occurred.
  • Battery transients below 6. 0V, resulting in an under- voltage shutdown of the outputs, may result in incorrect data loaded into the SPI register, except the UVF fault reporting (OD13). Serial Output Bit Assignment The contents of bits OD15 : OD0 depend on bits D1: D0 from the most recent initialization command SOA[1:0] (refer to Table 8, page 25), as explained in the paragraphs that follow. The register bits are reset by a read operation and also if the fault is removed. Table 11 summarizes the SO register content. Bit OD10 reflects Normal mode (NM).

Table 11. Serial Output Bit Map Description

4 OD13 OD12 OD11 OD1

0 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0

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reflect the temperature status (Table 13). status of the 35XS3500 (Table 14). Table 12. Output Status Flag at Outputs 5 through 1, respectively. corresponds to over-temperature or OCHI or OCLO faults. A logic [1] at bits OD9:OD0 indicates a fault. If there is no fault, bits OD9:OD0 are logic [0]. Table 13. Overload Status A logic [1] at bits OD9:OD0 indicates a fault. If there is no fault, bits OD9:OD0 are logic [0]. Table 14. Device Status

status of the 35XS3500 (Table 14).

  • Protection against transients on V BAT supply line (per ISO 7637)
  • Active clamp, including protection against negative transients on output line
  • Over-temperature
  • Severe and resistive over-current
  • Open Load during ON state These protections are provided for each output (OUT1:5). Over-temperature detection The 35XS3500 provides over-temperature shutdown for each output (OUT1:OUT5 ). It can occur when the output pin is in the ON or OFF state. An over-temperature fault condition results in turning OFF the corresponding output. The fault is latched and reported via the SPI. To delatch the fault and be able to turn the outputs ON again, the failure condition must be removed (T< 175 °C typically) and:
  • if the device was in Normal mode, the output corresponding register (bit D7) must be rewritten. Application of the complete OCHI window (OCHI1+OCHI2 during t2) depends on toggling or not toggling D7 bit.
  • if the device was in Fail mode, the corresponding output is locked until device restart: wake up from Sleep mode or V BATPOR1. The SPI fault report (OTS bit) is removed after a read operation. Over-current detections The 35XS3500 provides intelligent over-current shutdown (see Figure 12) in order to protect the internal power transistors and the harness in the event of overload (fuse characteristic).

Figure 12. Double Over-current Window in Normal Mode dynamically the transient over-current profile. detection), the corresponding output is disabled immediately.

  • if the device was in No rmal mode: the output corresponding register (bit D7) must be rewritten D7=1. Application of complete OCHI window depends on toggling or not toggling D7 bit.

Table 15. Output Status

Analog Integrated Circuit Device Data

30 Freescale Semiconductor

FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS

  • if the device was in Fail mode, the failure is locked until restart of the device: wake-up from Sleep mode or V BATPOR1. For OCHI2 and OCLO:
  • if the device was in Normal mode: the output corresponding register (bit D7) must be rewritten D7=1. Application of complete OCHI window depends on toggling or not toggling D7 bit.
  • if the device was in Fail mo de, Autorestart is activated. The device Autorestart feature provides a fixed duty cycle and fixed period with OCHI1 window. Autorestart feature resets OCHI2 or OCLO fault after corresponding Autorestart period. The SPI fault reports are removed after a read operation: - OC bit=(OCHI1) or (OCHI2) fault - OVL bit=(OCHI1) or (OCHI2) or (OCLO) fault Over-voltage detection and active clamp The 35XS3500 provides an active gate clamp circuit, in order to limit the maximum drain to source voltage. In case of overload on an output, the corresponding switch (OUT[1 to 5]) is turned off which leads to a high voltage at VBAT, with an inductive VBAT line. The maximum VBAT voltage is limited at VBATCLAMP by active clamp circuitry through the load. In case of open load condition, the positive transient pulses (ISO 7637 pulse 2 and inductive battery line) shall be handled by the application. Figures 13 and 14 describe the faults management in Normal mode and Fail mode.

Analog Integrated Circuit Device Data Freescale Semiconductor 31 35XS3500 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS OFF OCHI1 OCHI2 OCLO (OCHI2=1) or (OT=1) or (UV=1) or (D7=0) (OCHI1=1) or (OT=1) or (UV=1) or (D7=0) D7=0 then 1 without fault and (NO_OCHI=0) (rewrite D7=1) and (tON<t1) without fault and (NO_OCHI=0) tON=t2 without faulttON=t1 without fault tON>t1 without fault and (rewrite D7=1) and (NO_OCHI=0) (tON>t2) and (rewrite D7=1) without fault (OCLO=1) or (OT=1) or (UV=1) or (D7=0) Note: t1 and t2 please refer to Figure 12. D7=0 then 1 without fault and (NO_OCHI=1) (NO_OCHI=1) without fault (NO_OCHI=1) without fault t1<tON<t2 and (NO_OCHI=0) without fault tON<t1 and (NO_OCHI=0) without fault

32 Freescale Semiconductor

Figure 13. Faults Management in Normal Mode (for OUT[1:5] only) Figure 14. Faults Management in Fail Mode (for OUT[1:5] only) output (OUT1:OUT5 ) when the output pin is in the ON state. OLLED in fully on state, the output must be on at least t OLLED. When an open load has been detected, the output stays ON. Power on Reset on VBAT, the fault will be reset. SPI programmable (MUX[2,0] bits). output switch without overshoot (aperiodic settling). The current recopy is not active in Fail mode. Note: * See Autorestart strategy chapter.

34 Freescale Semiconductor

without load on OUT outputs. above to VCCUV. The fault is reported to the UVF bit (OD13).

  • the bit D7 must be rewritt en to a logic [1] in Normal mode. Application of the OCHI window depends on toggling or not toggling the D7 bit. When the fault is delatched, the 35XS3500 returns to the configuration it was just before the failure.
  • if the device was in Fail mode, the fault will be delatched periodically by the Autorestart feature. In case of VBAT<VBATPOR1 (Power OFF state), the behavior depends on VCC:
  • all latched faults are reset if V CC < VCCUV,
  • all latched faults are maintained under V CC in nominal conditions. In case VBAT is disconnected, OUT[1:5] outputs are OFF. OUT6 output state depends on the previous SPI configuration. The SPI configuration, reporting, and daisy-chain features are provided for RST is set to logic [1]. The SPI pull-up and pull-down current resistors are available. This fault condition can be diagnosed with UVF fault in OD13 reporting bit. The previous device configuration is maintained. No current is conducted from V CC to VBAT. Loss of VCC (Digital Logic Supply Line) During loss a of VCC (VCC < VCCUV ) and with wake=1, the 35XS3500 is switched automatically into Fail mode (no deglich time). The external SMART MOSFET is OFF. All SPI registers are reset and must be reprogrammed when VCC goes above VCCUV. The device will transit in OFF mode if VBAT < VBATPOR2. LOSS OF VCC AND VBAT If the external VBAT and VCC supplies are disconnected (or not within specification: (VCC and VBAT) < VBATPOR1), all SPI register contents are reset with default values corresponding to all SPI bits are set to logic [0] and all latched faults are also reset. Loss of Ground (GND) During a loss of ground, the 35XS3500 cannot operate the loads (the outputs (1:5) are switched OFF), but is not destroyed by the operating condition. Current limit resistors in the digital input lines protect the digital supply against excessive current (1.0 kohm typical). The state of the external smart power switch controlled by FETOUT is not guaranteed, and the state of the external smart MOS is defined with an external termination resistor. Fatal Mistreatment of Logic I / O Pins The digital I / Os are protected against fatal mistreatment by a signal plausibility check according to Table 16. In case the LIMP input is set to a logic [1] for a delay longer than 10 ms typical, the 35XS3500 is switched into Fail mode. In case of a (PWM) Clock failure, no PWM feature is provided, and the bit D7 defines the outputs state. In case of a SPI failure, the 35XS3500 is switched into Fail mode Figure 18)

Figure 18. Watchdog window Table 16. Logic I / O Plausibility Check

Analog Integrated Circuit Device Data

36 Freescale Semiconductor

EMC & EMI PERFORMANCES The 35XS3500 will be compliant to CISPR25 Class5 in Standby mode with 22 nF decoupling capacitor on OUT[1:5].

Analog Integrated Circuit Device Data Freescale Semiconductor 37 35XS3500 PACKAGING PACKAGING DIMENSIONS PACKAGING PACKAGING DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. PNA SUFFIX 24-PIN PQFN 98ART10511D ISSUE 0

Analog Integrated Circuit Device Data

38 Freescale Semiconductor

Analog Integrated Circuit Device Data Freescale Semiconductor 39 35XS3500 PACKAGING PACKAGING DIMENSIONS PNA SUFFIX 24-PIN PQFN 98ART10511D ISSUE 0

Analog Integrated Circuit Device Data

40 Freescale Semiconductor

REVISION HISTORY

Revision Date Description of Changes 1.0 5/2010 • Initial Release 2.0 7/20101 • Changed PN to MC35XS3500PNA

  • Changed classification to Advance Information 3.0 9/2010 • Added Minimum Output Current Reported in CSNS for OUT1-5 to Table 3.
  • Added Minimum Output Current Reported in CSNS for OUT[1-5] in LED Mode(12) to Table 3.
  • Added Note: Output current value computed after leakage current removal (open load condition)to Table 3. 4.0 5/2011 • Added Under-voltage Deglitch Time parameter.

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