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MC35FS4505CAE

NXP Semiconductors

Grade 0 safety power system basis chip with CAN FD transceiver Rev. 3 - 5 August 2024

Manufacturer: NXP Semiconductors

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PDF pages: 139

Technical content

Datasheet sections

1 General description
2 Features and benefits
3 Applications
4 Simplified application diagrams
5 Ordering information
5.1 Part number definition
5.2 Part numbers list
6 Block diagram
7 Pinning information
7.1 Pinning information
7.2 Pin description
8 Maximum ratings
9 Static electrical characteristics
10 Dynamic electrical characteristics
11 Functional pin description
11.1 Introduction
11.2 Power supplies (VSUP1, VSUP2, VSUP3)
11.3 VSENSE input (VSENSE)
11.4 Pre-regulator (VPRE)
11.8 SELECT input pin
11.8.1 VCCA, VAUX voltage configuration
11.8.2 Deep fail-safe configuration
11.9 CAN_5V voltage regulator
11.10 Interrupt (INTB)
11.11 CANH, CANL, TXD, RXD
11.11.1 TXD
11.11.2 RXD
11.11.3 CANH and CANL
11.12 Multiplexer output MUX_OUT
11.13 I/O pins (I/O_0:I/O_5)
11.14 SAFE output pins (FS0B, FS1B, RSTB)
11.14.1 FS0B pin
11.14.2 FS1B pin
11.14.3 RSTB pin
11.15 VPU_FS (fail-safe pull-up)
11.16 DEBUG input (entering in debug mode)
12 Functional device operation
12.1 Mode and state description of the main
12.1.1 Buck or buck boost configuration
12.1.2 VPRE on
12.1.3 SELECT pin configuration
12.1.4 VCORE/VAUX/VCCA on
12.1.5 INIT main
12.1.6 Normal
12.1.7 Low-power mode off
12.1.7.1 LPOFF - sleep
12.1.7.2 LPOFF - auto WU
12.1.7.3 LPOFF - deep FS
12.1.7.4 Register configuration in LPOFF
12.1.7.5 ISO pulse in LPOFF
12.2 Mode and state description of fail-safe state
12.2.1 Select pin configuration
12.2.2 ABIST
12.2.2.1 ABIST1
12.2.2.2 ABIST2
12.2.3 Release RSTB
12.2.4 INIT_FS
12.2.5 Normal WD
12.2.6 Assert RSTB
12.2.7 Assert FSxB and ABIST2
12.3 Deep fail-safe state
12.4 Functional state diagram
12.5 Fail-safe machine
12.5.1 Fail-safe machine state diagram
12.5.2 Watchdog operation
12.5.2.1 Normal operation (first watchdog refresh)
12.5.2.2 Normal watchdog refresh
12.5.2.3 Watchdog in debug mode
12.5.2.4 Wrong watchdog refresh handling
12.5.2.5 Watchdog error counter
12.5.2.6 Watchdog refresh counter
12.5.3 Fault error counter
12.5.3.1 Fault error counter intermediate value
12.5.3.2 Fault error counter at start-up or resuming
12.5.4 RESET (RSTB) activation
12.5.5 Fail-safe output (FS0B) activation
12.5.6 Fail-safe output (FS1B) activation
12.5.7 Fail-safe outputs (FS0B and FS1B) release
12.5.7.1 RELEASE_FSxB register
12.5.8 SPI DED
12.6 Input voltage range
12.7 Power management operation
12.7.1 VPRE voltage pre-regulator
12.7.1.1 Power up and power down sequence
12.7.1.2 Cranking management
12.7.1.3 Light load condition
12.7.1.4 Input power feed forward condition
12.7.1.5 Overcurrent detection and current limitation
12.7.1.6 VPRE voltage monitoring
12.7.1.7 VPRE efficiency
12.7.2 VCORE voltage regulator
12.7.2.1 VCORE DC–DC converter
12.7.2.2 Light load condition
12.7.2.3 Current limitation
12.7.2.4 Voltage monitoring
12.7.2.5 VCORE efficiency
12.7.2.6 VCORE linear regulator
12.7.2.7 Current limitation
12.7.2.8 Voltage monitoring
12.7.3 Charge pump and bootstrap
12.7.4 VCCA voltage regulator
12.7.4.1 Current limitation
12.7.4.2 Voltage monitoring
12.7.5 VAUX voltage regulator

Grade 0 safety power system basis chip with CAN FD transceiver Rev. 3 — 5 August 2024 Product data sheet

1 General description

The 35FS4500/35FS6500 ASIL B SMARTMOS devices are a multi-output, power supply, integrated circuit, including CAN Flexible Data (FD) transceiver, dedicated to the automotive market. Multiple switching and linear voltage regulators, including low-power mode (32 μA) are available with various wake-up capabilities. An advanced power management scheme is implemented to maintain high efficiency over a wide range of input voltages (down to 2.7 V) and output current ranges (up to 1.5 A). The 35FS4500/35FS6500 ASIL B includes configurable fail-safe/fail silent safety behavior and features, with two fail-safe outputs, becoming a full part of a safety oriented system partitioning, to reach a high integrity safety level (up to ASIL B). The built-in CAN FD interface fulfills the ISO 11898-2(11) and -5(12) standards. High temperature capability up to TA = 150 °C and TJ = 175 °C, compliant with AEC-Q100 Grade 0 automotive qualification.

2 Features and benefits

Battery voltage sensing and MUX output pin
Highly flexible SMPS pre-regulator, allowing two topologies: non-inverting buck-boost and standard buck
Linear voltage regulator dedicated to auxiliary functions, or to sensor supply (VCCA tracker or independent), 5.0 V, or 3.3 V
Linear voltage regulator dedicated to MCU Analog/Digital (A/D) reference voltage or I/Os supply (VCCA), 5.0 V, or 3.3 V
3.3 V keep alive memory supply available in low-power mode
Long duration timer, counting up to 6 months with 1.0 s resolution
Multiple wake-up sources in low-power mode: CAN, IOs, LDT
Five configurable I/Os

3 Applications

TA up to 150 °C and TJ up to 175 °C
Drive Train Electrification (BMS, Hybrid EV and HEV, Inverter, DC-DC, Alterno Starter)
Drive Train - Chassis and Safety (Active Suspension, Steering, Safety Domain Gateway)
Power Train (EMS, TCU, Gear Box)
ADAS (LDW, Radar, Sensor Fusion Safety area)
On board charger
Motor control

4 Simplified application diagrams

Figure 1. 35FS6500C simplified application diagram - buck boost configuration - FS1B 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 2. 35FS4500C simplified application diagram - buck boost configuration - FS1B

5 Ordering information

5.1 Part number definition

5 None

6 FS1B

7 LDT

5.2 Part numbers list

Table 2. Orderable part variations [1] To order parts in tape and reel, add the R2 suffix to the part number. 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

6 Block diagram

Figure 3. 35FS4500/35FS6500 with CAN simplified internal block diagram 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

7 Pinning information

7.1 Pinning information

Figure 4. 35FS6500 pinout with CAN and FS1B Figure 5. 35FS6500 pinout without CAN 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

7.2 Pin description

A functional description of each pin can be found in the full data sheet. used for VSUP1. VSUP1 and VSUP2 must be connected together externally. reverse protection diode and the input PI filter. FS0B output terminal. Open drain structure.

6 GND_COM GROUND Dedicated ground for physical layers

7 CAN_5V A_OUT Output voltage for the embedded CAN FD interface

8 CANH A_IN/OUT CAN output high. If CAN function is not used, this pin must be left open. 9 CANL A_IN/OUT CAN output low. If CAN function is not used, this pin must be left open.

10 IO_4 D_IN

signals from another IC for safety purposes (when used with IO_5). Wake-up capability: Can be selectable to wake-up on edges or levels.

11 IO_5/VKAM A_IN

providing keep alive memory supply in low-power mode. signals from another IC for safety purposes (when used with IO_4). Wake-up capability: Can be selectable to wake-up on edges or levels.

12 IO_0 A_IN

Digital input: Pin status can be read through the SPI. Wake-up capability: Can be selectable to wake-up on edges or levels.

13 FCRBM A_IN Feedback core resistor bridge monitoring: For safety purposes, this pin is used to

connected directly to FB_CORE. when a fault condition is detected. Open drain structure. Table 3. 35FS4500/35FS6500 pin definition 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

15 DEBUG D_IN Debug mode entry input

16 AGND GROUND Analog ground connection

parameter is available at MUX-OUT through the SPI. Digital input: Pin status can be read through the SPI. Wake-up capability: Can be selectable to wake-up on edges or levels. If CAN function is not used, this pin must be left open.

21 RXD D_OUT Receiver output which reports the state of the CAN-bus to the MCU

If CAN function is not used, this pin must be left open. 23 NC N/A Not connected. Pin must be left open. external reset and fault condition. Open drain structure.

28 NCS D_IN Not chip select (active low)

duration is configurable. Internal pull-up to VDDIO. 30 VDDIO A_IN Input voltage for MISO output buffer. Allows voltage compatibility with MCU I/Os.

31 SELECT D_IN Hardware selection pin for VAUX and VCCA output voltages

32 FB_CORE A_IN VCORE voltage feedback. Input of the error amplifier.

33 COMP_

A_OUT Compensation network. Output of the error amplifier. For FS4500 series, this pin must be left open (NC).

34 VCORE_

36 BOOT_

For FS4500 series, this pin must be left open (NC).

37 VPRE A_IN VPRE input voltage sense

44 GATE_LS A_OUT Low-side MOSFET gate drive for non-inverting buck-boost configuration

45 DGND GROUND Digital ground connection

46 BOOT_PRE A_IN/OUT Bootstrap capacitor for the VPRE internal NMOS gate drive

47 SW_PRE2 A_OUT Second pre-regulator output switching point

48 SW_PRE1 A_OUT First pre-regulator output switching point

8 Maximum ratings

VSUP1, 2, 3, VSENSE, VAUX, IO_0, 4, 5, FS0B, FS1B VESD-GUN1 330 Ω/150 pF unpowered according to IEC 61000-4-2:(15) ±8.0 kV VESD-GUN2 330 Ω/150 pF unpowered according to OEM, CAN, FlexRay Conformance ±8.0 kV VESD-GUN3 2.0 kΩ/150 pF unpowered according to ISO 10605(14) ±8.0 kV VESD-GUN4 2.0 kΩ/330 pF powered according to ISO 10605(14) ±8.0 kV
CANH, CANL VESD-GUN5 330 Ω/150 pF unpowered according to IEC 61000-4-2:(15) ±15.0 kV VESD-GUN6 330 Ω/150 pF unpowered according to OEM, CAN, FlexRay Conformance ±12.0 kV VESD-GUN7 2.0 kΩ/150 pF unpowered according to ISO 10605(14) ±15.0 kV VESD-GUN8 2.0 kΩ/330 pF powered according to ISO 10605(14) ±12.0 kV Thermal ratings TA Ambient temperature –40 to 150 °C TJ Junction temperature –40 to 175 °C TSTG Storage temperature –55 to 150 °C Thermal resistance RθJA Thermal resistance junction to ambient 30 °C/W [3] RθJCTOP Thermal resistance junction to case top 23.8 °C/W [4] RθJCBOTTOM Thermal resistance junction to case bottom 0.9 °C/W [5]

Table 4. Maximum ratings ...continued [1] All VSUPS (VSUP1/2/3) must be connected to the same supply (Figure 63). [3] Per JEDEC JESD51-6(16) with the board (JESD51-7)(17) horizontal. [4] Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC - 883 Method 1012.1)(20). [5] Thermal resistance between the die and the solder pad on the bottom of the packaged based on simulation without any interface resistance. 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

9 Static electrical characteristics

Buck mode (VSUP > VSUP_UV_7) 6.25 — 6.75
Buck mode (VSUP_UV_7 ≥ VSUP ≥ 4.5 V) VPRE_ UV_4P3 VSUP – RDS(on)_ PRE * IPRE VPRE
Boost mode (VSUP ≥ 2.7 V) 6.0 — 7.0 V VPRE maximum output current capability [4]
Buck or boost with VSUP > VSUP_UV_7 2.0 — —
Buck with VSUP_UV_7 ≥ VSUP ≥ 4.5 V 0.5 2.0 —
Boost with VSUP_UV_7 ≥ VSUP ≥ 6.0 V 2.0 — —
Boost with 6.0 V ≥ VSUP ≥ 4.0 V 1.0 — — IPRE
Boost with 4.0 V ≥ VSUP ≥ 2.7 V 0.3 — — A IPRE_LIM1 SW_PRE output current limitation in buck–boost mode (VSUP ≤ 28 V) 3.5 — — A IPRE_LIM2 SW_PRE output current limitation in buck mode (VSUP ≤ 28 V) 2.5 — — A IPRE_OC SW_PRE overcurrent detection threshold in buck mode (VSUP ≤ 28 V) 4.5 — — A VPRE_UV VPRE undervoltage detection threshold (falling) 5.5 — 6.0 V VPRE_UV_HYST VPRE undervoltage hysteresis 0.05 — 0.15 V [5] VPRE_UV_4P3 VPRE shut-off threshold (falling – buck and buck/boost) 4.1 — 4.5 V

IPRE from 50 mA to 2.0 A - buck mode — 100 — mV [5] LORVPRE_BOOST VPRE load regulation for COUT_VPRE = 57 µF
IPRE from 50 mA to 2.0 A - boost mode — 500 — mV [5] VPRE_LL_H VPRE_LL_L VPRE pulse skipping thresholds — 200 180 mV TWARN_PRE VPRE thermal warning threshold — 125 — °C TSD_PRE VPRE thermal shutdown threshold 180 — — °C TSD_PRE_HYST VPRE thermal shutdown hysteresis — 10 — °C [5] VG_LS_OH LS gate driver high output voltage (IOUT = 50 mA) VPRE – 1 — VPRE V VG_LS_OL LS gate driver low level (IOUT = 50 mA) — — 0.5 V IG_LS LS gate driver current capability — 300 — mA RG_SHORT GATE_LS pin short to GND resistance to detect buck mode only — — 10 Ω Vcore voltage regulator VCORE_FB VCORE feedback input voltage 0.784 0.8 0.816 V IPD_CORE VCORE internal pull-down current (active when VCOR E is enabled) 5.0 12 25 mA ICORE VCORE output current capability in normal mode
FS450x
FS650x
FS651x 0.5 0.8 1.5 A ICORE_LIM VCORE output current limitation
FS450x
FS650x
FS651x 0.55 1.8 1.7 2.8 A RDSON_CORE VCORE pass transistor on resistance — — 200 mΩ FS65_ LORVCORE_1.2 VCORE transient load regulation – 1.2 V range COUT_VCORE = 40 µF, ICORE = 10 mA to 1.5 A, dICORE/dt ≤ 2.0 A/µs –60 — 60 mV [4] FS65_ LORVCORE_3.3 VCORE transient load regulation – 3.3 V range COUT_VCORE = 40 µF, ICORE = 10 mA to 1.5 A, dICORE/dt ≤ 2.0 A/µs –100 — 100 mV [4] FS65_ LORVCORE_5 VCORE transient load regulation – 5.0 V range COUT_VCORE = 20 µF, ICORE = 10 mA to 0.8 A, dICORE/dt ≤ 2.0 A/µs –150 — 150 mV [4] FS45_ LORVCORE_1.2 VCORE transient load regulation – 1.2 V range COUT_VCORE = 20 µF, ICORE = 10 mA to 0.2 A, dICORE/dt ≤ 0.5 A/µs –60 — 60 mV [4] FS45_ LORVCORE_3.3 VCORE transient load regulation – 3.3 V range –100 — 100 mV [4]

5.0 V configuration with Internal ballast at 100 mA
5.0 V configuration with external ballast at 200 mA
5.0 V configuration with external ballast at 300 mA
3.3 V configuration with Internal ballast at 100 mA
3.3 V configuration with external ballast at 200 mA
3.3 V configuration with external ballast at 300 mA 4.95 4.9 4.85 3.267 3.234 3.201 5.0 5.0 5.0 3.3 3.3 3.3 5.05 5.1 5.15 3.333 3.366 3.399 V [6] ICCA_IN VCCA output current (int. MOSFET) — — 100 mA ICCA_OUT VCCA output current (external PNP) — — 300 mA ICCA_LIM_INT VCCA output current limitation (int. MOSFET) 100 — 675 mA ICCA_LIM_OUT VCCA output current limitation (external PNP) 300 — 675 mA ICCA_LIM_FB VCCA output current limitation foldback 60 — 240 mA VCCA_LIM_FB VCCA output voltage foldback threshold 0.6 — 1.2 V VCCA_LIM_HYST VCCA output voltage foldback hysteresis 0.03 — 0.3 V ICCA_BASE_SC ICCA_BASE_SK VCCA base current capability — –20 –30 mA TWARN_CCA VCCA thermal warning threshold (int. MOSFET only) — 125 — °C TSDCCA VCCA thermal shutdown threshold (int. MOSFET only) 180 — — °C TSDCCA_HYST VCCA thermal shutdown hysteresis — 10 — °C [5] LORVCCA VCCA static load regulation
ICCA = 10 mA to 100 mA (internal MOSFET)
ICCA = 10 mA to 300 mA (external ballast) mV [5] LORTVCCA VCCA transient load regulation
ICCA = 10 mA to 100 mA (internal MOSFET)
ICCA = 10 mA to 300 mA (external ballast) 1.0 % [5] RPD_CCA VCCA internal pull-down resistor (active when VCCA is disabled) 50 — 170 Ω VAUX voltage regulator VAUX_5 VAUX output voltage (5.0 V configuration) 4.85 5.0 5.15 V VAUX_33 VAUX output voltage (3.3 V configuration) 3.2 3.3 3.4 V VAUX_TRK VAUX tracking error (VAUX_5 and VAUX_33) –15 — +15 mV IAUX_OUT VAUX output current — — 400 mA IAUX_LIM VAUX output current limitation 400 — 800 mA

IAUX_OUT = 10 mA to 400 mA — — 1.0 % [5] RPD_AUX VAUX internal pull-down resistor (active when VAUX is disabled) 50 — 170 Ω CAN_5V voltage regulator VCAN VCAN output voltage VSUP > 6.0 V in buck mode VSUP > VSUP_UV_L in boost mode 4.8 5.0 5.2 V ICAN_OUT VCAN output current — — 100 mA ICAN_LIM VCAN output current limitation 100 — 250 mA TSDCAN VCAN thermal shutdown threshold 180 — — °C TSDCAN_HYST VCAN thermal shutdown hysteresis — 10 — °C [5] VCAN_UV VCAN undervoltage detection threshold 4.25 — 4.8 V VCAN_UV_HYST VCAN undervoltage hysteresis 0.07 — 0.22 V VCAN_OV VCAN overvoltage detection threshold (rising) 5.2 — 5.85 V VCAN_OV_HYST VCAN overvoltage hysteresis 0.07 — 0.22 V LORVCAN VCAN transient load regulation
ICAN_OUT = 0 mA to 50 mA — 100 — mV [5] VKAM voltage regulator VKAM VKAM output voltage 3.0 3.5 4.0 V IKAM_OUT VKAM output current — — 3.0 mA IKAM_LIM VKAM output current limitation 4.0 — 10.0 mA ISUP_KAM VKAM current consumption from VSUP3
IKAM_OUT = 0 mA
IKAM_OUT < 1.0 mA
1.0 mA < IKAM_OUT < 3.0 mA 150 2.15 µA µA mA Long duration timer ILDT Timer current consumption (from VSUP3) — 5.0 10 µA Fail-safe machine voltage supervisor VPRE_OV VPRE overvoltage detection threshold 7.2 — 8.0 V VPRE_OV_HYST VPRE overvoltage hysteresis — 0.1 — V [5] VCORE_FB_UV VCORE FB undervoltage detection threshold 0.67 — 0.773 V VCORE_FB_UV_D VCORE FB undervoltage detection threshold - degraded mode 0.45 — 0.58 V VCORE_FB_UV_ VCORE FB undervoltage hysteresis 10 — 27 mV [5]

TA = –40 °C to 150 °C, unless otherwise specified. VSUP = VSUP_UV_L to 36 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 36 V, thermal dissipation must be considered (see Figure 27). 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

TX dominant state
TX recessive state 2.75 2.0 2.5 4.5 3.0 V VCANL CANL output voltage (45 Ω < RBUS < 65 Ω)
TX dominant state
TX recessive state 0.5 2.0 2.5 2.25 3.0 V VCAN_SYM CAN dominant voltage symmetry (VCANL + VCANH) 4.5 5.0 5.5 V VOH-VOL Differential output voltage
TX dominant state (45 Ω < RBUS < 65 Ω)
TX recessive state 1.5 –50 2.0 0.0 3.0 V mV ICANL-SK CANL sink current under short-circuit condition (VCANL ≤ 12 V, CANL driver ON, TXD low) 40 — 100 mA ICANH-SC CANH source current under short-circuit condition (VCANH = –2.0 V, CANH driver ON, TXD low) –100 — –40 mA VCANLP CANL, CANH output voltage in sleep modes. No termination load. –0.1 0.0 0.1 V ICAN CANH, CANL input current, device unsupplied, (VCANH, VCANL = 5.0 V)
VSUP and VCAN connected to GND
VSUP and VCAN connected to GND via 47 kΩ resistor –10 –10 µA µA [10] TOT Overtemperature detection 180 — — °C THYST Overtemperature hysteresis — — 20 °C

[1] Long duration timer and VKAM disable. [2] VSUP_UV_L_B = VPRE_UV_4P3 + RDSON_PRE × IPRE. [3] VSUP min to guarantee VKAM and main logic supply in LPOFF. [4] Guaranteed by characterization. [6] External PNP gain within 150 to 450. [8] If a higher resistor value than recommended is used, the accuracy degrades. [9] Wide range accuracy for input voltage from 9.0 V to 19 V. [10] Guaranteed by design and characterization.

10 Dynamic electrical characteristics

VDDIO = 5.0 V, CLOAD = 50 pF
VDDIO = 5.0 V, CLOAD = 150 pF 5.0 5.0 ns tCLH Minimum time SCLK = HIGH 62 — — ns

TA = –40 °C to 150 °C, unless otherwise specified. VSUP = VSUP_UV_L to 36 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 36 V, thermal dissipation must be considered (see Figure 27). Table 6. Dynamic electrical characteristics ...continued 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

TA = –40 °C to 150 °C, unless otherwise specified. VSUP = VSUP_UV_L to 36 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 36 V, thermal dissipation must be considered (see Figure 27). 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

VDDIO = 5.0 V, CMUX_OUT = 1.0 nF µs Interrupt tINTB_LG INTB pulse duration (long) 90 100 — µs tINTB_ST INTB pulse duration (short) 20 25 — µs Long duration timer CLKLDT Long duration timer oscillator 30802 32768 34734 Hz CLKLDT_% Long duration timer oscillator accuracy
from –40 °C to 150 °C
from –20 °C to 85 °C and calibration –6.0 –2.0 6.0 2.0 CAN dynamic characteristics (FD 2.0 Mbit/s) tDOUT TXD dominant state timeout 0.8 — 5.0 ms tDOM Bus dominant clamping detection 0.8 — 5.0 ms tLOOP Propagation loop delay TXD to RXD
RLOAD = 120 Ω, C between CANH and CANL = 100 pF, C at RXD < 15 pF 255 ns t1PWU First pulse wake-up time 0.5 — 3.5 µs t3PWU Second and third pulse wake-up time 0.5 — 1.0 µs t3PTO1 Multiple pulse wake-up timeout (short) 100 120 — µs

TA = –40 °C to 150 °C, unless otherwise specified. VSUP = VSUP_UV_L to 36 V, unless otherwise specified. All voltages referenced to ground. When 28 V < VSUP < 36 V, thermal dissipation must be considered (see Figure 27). [1] This timing is not guaranteed in case of fault during startup phase (after power-on reset of from LPOFF). [2] Guaranteed by characterization. [3] For proper CAN operation, TXD must be set to high level before CAN enable by the SPI, and must remain high for at least TCAN_READY. Figure 7. SPI timing diagram Figure 8. Register access restriction

11 Functional pin description

11.1 Introduction

High efficiency switching voltage regulator for MCU, and linear voltage regulators for integrated CAN FD interface.
External ICs such as sensors, accurate reference voltage for A to D converters, and keep alive memory supply in low-power mode for MCU static RAM.
Built-in CAN flexible data interface at 2.0 Mbit/s (ISO 11898-2(11) and -5(12)), with local and bus failure diagnostic, protection, and fail-safe operation mode. 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 5 August 2024 Document feedback

NXP Semiconductors 35FS4500-35FS6500-ASILB Grade 0 safety power system basis chip with CAN FD transceiver

Low-power mode, with ultra low-current consumption.
Various wake-up capabilities.
Long duration timer available in normal and low-power mode.
Enhanced safety features with multiple fail-safe outputs and a scheme to support ASIL B applications.

11.2 Power supplies (VSUP1, VSUP2, VSUP3)

VSUP1 and VSUP2 are the input pins for the internal supply dedicated to the SMPS regulators. VSUP3 is the input pin for internal voltage reference. VSUP1, 2, and 3 are robust against ISO 7637(13) pulses. VSUP1, 2, and 3 must be connected to the same supply (Figure 63).

11.3 VSENSE input (VSENSE)

This pin must be connected to the battery line (before the reverse battery protection diode), via a serial resistor. It incorporates a threshold detector to sense the battery voltage, and provide a battery early warning. It also includes a resistor divider to measure VSENSE voltage via the MUX-OUT pin. The VSENSE pin is robust against ISO 7637(13) pulses.

11.4 Pre-regulator (VPRE)

A highly flexible SMPS pre-regulator is implemented in the 35FS4500/35FS6500. It can be configured as a ’non-inverting buck-boost converter’ (Figure 29) or ’standard buck converter’ (Figure 28), depending on the external configuration (connection of pin GATE_LS). The configuration is detected automatically during start-up sequence. The SMPS pre-regulator is working in current mode control and the compensation network is fully integrated in the device. The high-side switching MOSFET is also integrated to make the current control easier. The pre- regulator delivers a typical output voltage of 6.5 V, which is used internally. Current limitation, overcurrent, overvoltage, and undervoltage detectors are provided. VPRE is enabled by default. 11.5 VCORE output (from 1.0 V to 5.0 V range) The VCORE block of the FS6500 series is an SMPS regulator. The voltage regulator is a step down DC– DC converter operating in voltage control mode. The stability of the converter is done externally, by using the COMP_CORE pin. The VCORE block of the FS4500 series is a linear regulator. In this case, BOOT_CORE and COMP_CORE pins must be left open. The output voltage of 35FS4500/35FS6500 is configurable to any voltage from a 1.0 V to 5.0 V range using an external resistor divider connected between VCORE and the feedback pin (FB_CORE) (as example in Figure 1, or Figure 63). Current limitation, overvoltage, and undervoltage detectors are provided. VCORE can be turned on or off via a SPI command, however it is not recommended to turn off VCORE with the SPI when VCORE is configured safety critical (both overvoltage and undervoltage have an impact on fail-safe outputs). VCORE overvoltage information disables VCORE. Diagnostics are reported in the dedicated register and generate an Interrupt. VCORE is enabled by default. For safety purpose, a second resistor bridge (R3/R4 duplicated) connected to FCRBM should be used to detect an external resistor drift. 11.6 VCCA output, 5.0 V, or 3.3 V selectable The VCCA voltage regulator is used to provide an accurate voltage output (5.0 V, 3.3 V) selectable through an external resistor connected to the SELECT pin. The VCCA output voltage regulator can be configured using an internal transistor delivering very good accuracy (±1.0 % for 5.0 V and 3.3 V configuration), with a limited current capability (100 mA) for an analog to digital 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 5 August 2024 Document feedback

voltage accuracy (±3.0 % for 300 mA) when using a local ECU supply. dedicated register and generate an Interrupt. VCCA is enabled by default. supply’ (external ECU supply) with the possibility to be configured as a tracking regulator following VCCA.

11.8 SELECT input pin

11.8.1 VCCA, VAUX voltage configuration

and VAUX are configured after each power-on reset, and after a wake-up event when the device is in LPOFF. dedicated register via the SPI. See Figure 65. Table 7. VCCA/VAUX voltage selection [1] If the SELECT pin is detected open, the VCCA and VAUX regulators start at their minimum output voltage 3.3 V.

11.8.2 Deep fail-safe configuration

Figure 9. Deep fail-safe enable/disable

11.9 CAN_5V voltage regulator

11.10 Interrupt (INTB)

11.11 CANH, CANL, TXD, RXD

interface is connected to the MCU via the RXD and TXD pins.

11.11.1 TXD

mode, when TXD is high or floating, the CANH and CANL drivers are off, setting the bus in a recessive state. is off, pulling this pin to GND.

11.11.2 RXD

RXD is the bus output level report pin. In the application, this pin is connected to the microcontroller receive pin. is dominant, RXD is low. In LPOFF mode, this pin is in the high-impedance state.

11.11.3 CANH and CANL

These are the CAN-bus pins. CANL is a low-side driver to GND, and CANH is a high-side driver to CAN_5V. and CANH to CAN_5V, creating a differential voltage on the CAN-bus. 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

disturbance, such as EMC and electrical transients. These pins have current limitation and thermal protection.

11.12 Multiplexer output MUX_OUT

VSENSE
VIO_0
VKAM
Internal 2.5 V reference
Internal die temperature sensor T(°C) = (VAMUX – VAMUX_TP)/VAMUX_TP_CO + 165 Voltage range at MUX_OUT is from GND to VDDIO (3.3 V or 5.0 V) aaa-037741 VSENSE IO_0 IO_5/VKAM 3.3 V Ratio #1 3.3 V Ratio #2 Same as VSENSE Same as VSENSE SPI selectionR1 R4 SPI selection 5.0 V Ratio #1 lnternal 2.5 V reference lnternal temp sensor 5.0 V Ratio #2 MUX_OUT

Figure 10. Simplified analog multiplexer block diagram

11.13 I/O pins (I/O_0:I/O_5)

(resistor and Zener diode) to be load dump proof and robust against ISO 7637(13) pulses. Table 8. I/Os configuration 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

IO_0 is selectable as follows: Analog input (load dump proof) sent to the MCU through the MUX_OUT pin. Wake-up input on the rising or falling edge or based on the previous state. Digital input (logic level) sent to the MCU through the SPI. Safety purpose: IO_0 is the only wake-up input to resume from deep fail-safe mode.
IO_2:3 are selectable as follows: Digital input (logic level) sent to the MCU through the SPI. Wake-up input on the rising or falling edge or based on the previous state.
IO_4 is selectable as follows: Digital input (logic level) sent to the MCU through the SPI. Wake-up input (load dump proof) on rising or falling edge or based on previous state. Output gate driver (from VPRE) for low-side logic level MOSFET.
IO_5 is selectable as follows: Analog input (20 V max.) sent to the MCU through the MUX_OUT pin. Digital input (logic level) sent to the MCU through the SPI. Wake-up input on rising or falling edge or based on previous state. VKAM output supply.
IO_4:5 are selectable as follows: Safety purpose: Digital input (logic level) to perform an IC error monitoring (both IO_4 AND IO_5 are used if configured as safety inputs, see Figure 11). aaa-037743 Internal IO_4 signal latched Error signal (IO_4 input) Acknowledgment counter Acknowledgement signal from MCU (IO_5 input) Filter time Reset counter Restart Acknowledgment counter FS0B RSTB The error is acknowledged by the MCU then, internal IO_4 signal is released The error is NOT acknowledged by the MCU. FS0B is activated at the end of the counter.

Figure 11. External error signal handling

11.14 SAFE output pins (FS0B, FS1B, RSTB)

11.14.1 FS0B pin

FS0B pin is the primary safe output pin. FS0B is asserted low when a fault event occurs (see Section 12.5.5). system and set the ECU in a protected and known state. 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

NXP Semiconductors 35FS4500-35FS6500-ASILB Grade 0 safety power system basis chip with CAN FD transceiver After each power-on reset or after each wake-up event (LPOFF), the FS0B pin is asserted low. The MCU can decide to release the FS0B pin, when the application is ready to start. An external pull-up circuitry is mandatory connected to VDDIO or VSUP3.

If the pull-up is connected to VDDIO, the value recommended is 5.0 kΩ, there is no current in LPOFF since VDDIO is off in LPOFF mode.
If the pull-up is connected to VSUP3, the value must be above 10 kΩ, there is a current in the pull-up resistor to consider at application level in LPOFF mode.

11.14.2 FS1B pin

FS1B pin is the secondary safe output pin. FS1B is asserted low with a configurable delay (tDELAY) or duration (tDUR) when FS0B is asserted low (see Section 12.5.6). This pin can be used to:

Open the phases of a motor after a configurable delay starting when FS0B is asserted, to demagnetize the motor coils and reduce the inductive effect when the switch is open.
Disable an external physical layer during a configurable duration starting when FS0B is asserted, to avoid miscommunication when the module is in fail mode.
Be a redundant safe output pin to FS0B when tDELAY = 0. In this case, FS1B is asserted at the same time than FS0B.
Any other use case where a second safety pin is needed. After each power-on reset or after each wake-up event (LPOFF), the FS1B pin is asserted low. Then the MCU can decide to release the FS1B pin, when the application is ready to start. An external pull-up circuitry is mandatory, connected to VPU_FS or VDDIO.

11.14.3 RSTB pin

The RSTB pin must be connected to MCU and is active low. An external pull-up resistor must be connected to VDDIO. In default configuration, the RST delay time has three possible values depending on the mode and product configuration:

The longest one is used automatically following a power-on reset or when resulting from LPOFF mode (low- power off).
The two reset durations are then available in the INIT_FSSM register, which are 1.0 ms and 10 ms. The configured duration is finally used in the normal operation when a fault occurs leading to a reset activation. The INIT_FSSM register is available (writing) in the INIT_FS phase.

11.15 VPU_FS (fail-safe pull-up)

This pin is intended to be the pull-up terminal of FS1B, internally attached to VPRE through a reverse diode protection. This independent pull-up (compared to FS0B pull-up) avoids common cause failures between the two safe outputs. When FS1B is used with tDELAY = 0 or in tDUR configuration, a pull-up to VDDIO is also possible, taking into account the common cause failure with the same pull-up as FS0B in the safety analysis.

11.16 DEBUG input (entering in debug mode)

The DEBUG pin allows the product to enter debug mode. To activate the debug mode, voltage applied to the DEBUG pin must be within the VDEBUG_IL and VDEBUG_IH range at start-up. If the voltage applied to DEBUG pin is out of these limits, during the SELECT pin configuration, the device settles into normal mode. In debug mode, the watchdog window is fully open and no watchdog refresh is required. This allows an easy debug of the hardware and software routines (i.e. SPI commands). However, the whole watchdog functionality is kept on (WD refresh counter, WD error counter,...). WD errors are detected and counted with reaction according to WD_IMPACT bit configuration. When the debug mode is activated, the fail-safe outputs (FS0B, 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 5 August 2024 Document feedback

NXP Semiconductors 35FS4500-35FS6500-ASILB Grade 0 safety power system basis chip with CAN FD transceiver FS1B) are asserted low at start-up. The release procedure and the assertion conditions are the same than in normal mode. When the Debug mode is activated, there is no deep fail-safe state. The CAN transceiver is set to normal operation mode by default allowing CAN communication without SPI configuration (FS1B_CAN_IMP bit = 0). To exit debug mode, the pin must be tied to ground through an external pull-down resistor and a power-on reset or wake-up from LPOFF occurs.

12 Functional device operation

12.1 Mode and state description of the main state machine

The device has several operation modes. The transition and conditions to enter or leave each mode are illustrated in the functional state diagram (Figure 13). Two state machines work in parallel. The main state machine controls the power management (VPRE, VCORE, VCCA, VAUX,...) and the fail-safe state machine controls all the safety aspects (WD, RSTB, FS0B, FS1B,...).

12.1.1 Buck or buck boost configuration

An external low-side logic level MOSFET (N-type) is required to operate in non-inverting buck-boost converter. The connection of the external MOSFET is detected automatically during the start-up phase (after a power-on reset or from LPOFF).

If the external low-side MOSFET is not connected (GATE_LS pin connected to PGND), the product is configured as a standard buck converter.
If the external low-side MOSFET is connected (GATE_LS pin connected to external MOSFET gate), the product is configured as a non-inverting buck-boost converter. The automatic detection is done by pushing 300 μA current on Gate_LS pin and monitoring the corresponding voltage generated. If a voltage >120 mV is detected before the 120 μs timeout, the non-inverting buck-boost configuration is locked. Otherwise, the standard buck configuration is locked. The boost driver has a current capability of ±300 mA.

12.1.2 VPRE on

Pre-regulator is an SMPS regulator. In this phase, the pre-regulator is switched on and a soft start with a specified duration tPRE_SOFT controls the VPRE output capacitor charge.

12.1.3 SELECT pin configuration

This phase detects the required voltage level on VAUX and VCCA, according to the resistor value connected between the SELECT pin and Ground or VPRE, and configures the deep fail-safe function.

12.1.4 VCORE/VAUX/VCCA on

In this stage, the three regulators VCORE, VAUX, VCCA are switched on at the same time with a specified soft start duration. The CAN_5V is also started at this time.

12.1.5 INIT main

This mode is automatically entered after the device is ’powered on’. When RSTB is released, initialization phase starts where the device can be configured via the SPI. During INIT phase, some registers can only be configured in this mode (see Table 18 and Table 19). Other registers can be written in this mode, and also in normal mode. 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 5 August 2024 Document feedback

NXP Semiconductors 35FS4500-35FS6500-ASILB Grade 0 safety power system basis chip with CAN FD transceiver Once the INIT registers configurations are complete, a last register called ’INIT_INT’ must be configured to switch to normal mode. Writing data in this register (even same default values), automatically locks the INIT registers, and the product switches automatically to normal mode in the main state machine.

12.1.6 Normal

In this mode, all device functions are available. This mode is entered by a SPI command from the INIT phase by writing in the INIT_INT register. While in normal mode, the device can be set to low-power mode (LPOFF) using secured SPI command.

12.1.7 Low-power mode off

The main state machine has three LPOFF modes with different conditions to enter and exit each LPOFF mode, as described hereafter. After wake-up from LPOFF, all the regulators are enabled by default. In LPOFF, all the regulators are switched off, except VKAM. The register configuration and the ISO pulse requirement are valid for the three LPOFF modes.

12.1.7.1 LPOFF - sleep

Entering in low-power mode LPOFF - sleep is only available if the product is in normal mode by sending a secured SPI command. In this mode, all the regulators are turned off and the MCU connected to the VCORE regulator is unsupplied. Only VKAM is available if VKAM is used (specific part number for VKAM on by default). Once the 35FS4500/35FS6500 is in LPOFF - sleep, the device monitors external events to wake-up and leave the low-power mode. The wake-up events can occur and depending on the device configuration from:

CAN Physical layer
I/O inputs
Timer When a wake-up event is detected, the device starts the main state machine again by detecting the VPRE configuration (buck or buck-boost), the wake-up source is reported to the dedicated SPI register, and the fail- safe state machine is also restarted.

12.1.7.2 LPOFF - auto WU

LPOFF - auto WU is entered when the device is in the INIT or normal mode and if the VPRE voltage level is passing the VPRE_UV_4P3 threshold (typ 4.3 V). It can be also entered by sending a secured SPI command if the product is in normal mode. It allows a POR and complete restart of the fail-safe state machine. After 1.0 ms, the device attempts to recover by switching on VPRE again.

12.1.7.3 LPOFF - deep FS

LPOFF - deep FS is entered when the device is in deep fail-safe and if the key is off (IO_0 is low). To exit this mode, a transition to high level on IO_0 is required. IO_0 is usually connected to the key on key off signal (see Section 12.3).

12.1.7.4 Register configuration in LPOFF

In LPOFF, the register settings of the main state machine are kept because the internal 2.5 V main digital regulator is available for wake-up operation. However, the register settings of the fail-safe state machine are erased because the 2.5 V fail-safe digital regulator is not available in LPOFF. As a consequence, after a wake- up event, the configuration of the fail-safe registers must be done again during initialization phase (256 ms open window). 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 5 August 2024 Document feedback

12.1.7.5 ISO pulse in LPOFF

maximum rating supported by this pin. Figure 12. Components involved under ISO pulse in LPOFF

12.2 Mode and state description of fail-safe state machine

12.2.1 Select pin configuration

12.2.2 ABIST

release. It allows the MCU diagnostic, keeping the application in safe sate.

12.2.2.1 ABIST1

Table 9. Regulators and fail-safe pins checked during ABIST1...continued

12.2.2.2 ABIST2

after each wake-up event when device is in LPOFF mode, to release the fail-safe pin FS0B. Table 10. Regulators and fail-safe pins checked during ABIST2

12.2.3 Release RSTB

In this state, the device releases the RSTB pin.

12.2.4 INIT_FS

has been executed. This INIT_FS mode starts as soon as RSTB is released.

12.2.5 Normal WD

this mode. This mode is exited if a fault occurs leading to an RSTB activation (external reset request included).

12.2.6 Assert RSTB

When the reset pin is asserted low by the device, a delay runs, to release RSTB, if there are no faults present. writing only in the INIT_FS phase.

12.2.7 Assert FSxB and ABIST2

These functions are executed in parallel to INIT_FS or normal WD states of the fail-safe state machine.

12.3 Deep fail-safe state

fail-safe state in the functional state diagram (Figure 13). INIT_FS_IMPACT. During ’normal WD’ state, the 8.0 s timer is activated at each RSTB pin assertion.

12.4 Functional state diagram

Figure 13. Simplified state diagram

12.5 Fail-safe machine

To fulfill safety critical applications, the 35FS4500/35FS6500 integrates a dedicated fail-safe machine (FSM). 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

NXP Semiconductors 35FS4500-35FS6500-ASILB Grade 0 safety power system basis chip with CAN FD transceiver (FSSM), and the fail-safe output driver (FSO).The FSM is electrically independent from the rest of the circuitry, to avoid common cause failure. For this reason, the FSM has its own voltage regulators (analog and digital), dedicated band gap, and its own oscillator. Three power supply pins (VSUP 1, 2, and 3) are used to overtake a pin lift issue. The internal voltage regulators are directly connected on VSUP (one bonding wire per pin is used). Additionally, the ground connection is redundant as well to avoid any loss of ground. All the voltages generated in the device are monitored by the voltage supervisor (under and overvoltage) owing to a dedicated internal voltage reference (different from the one used for the voltage regulators). The result is reported to the MCU through the SPI and delivered to the fail-safe state machine (FSSM) for action, in case of a fault. All the safety relevant signals feed the FSSM, which handles the error handling and controls the fail-safe outputs. There are three fail-safe outputs: RSTB (asserted low to reset the MCU), FS0B, and FS1B (asserted low to control any fail-safe circuitry). The fail-safe machine is in charge of bringing and maintaining the application in a fail-safe state. 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 5 August 2024 Document feedback

12.5.1 Fail-safe machine state diagram

NXP Semiconductors 35FS4500-35FS6500-ASILB Grade 0 safety power system basis chip with CAN FD transceiver

12.5.2 Watchdog operation

A simple windowed watchdog is implemented in the 35FS4500/35FS6500. The watchdog must be continuously triggered by the MCU in the open watchdog window, otherwise an error is generated. The error handling and watchdog operations are managed by the fail-safe state machine. For debugging purpose, this functionality can be inhibited by setting the right voltage on the DEBUG pin at start-up. The watchdog window duration is selectable through the SPI during the INIT_FS phase or in normal mode. The 64 ms, 128 ms, 256 ms, 512 ms, and 1024 ms. The watchdog can also be inhibited through the SPI register in INIT_FS phase to allow "reprogramming" (i.e. at vehicle level thru CAN). The MCU must write in the WD_ANSWER register during the OPEN watchdog window. In that case, the watchdog window is restarted. If the WD_ANSWER is accessed during the CLOSED watchdog window, the WD error counter is incremented and the watchdog window is restarted. Anything can be written in the WD_ANSWER register to refresh the watchdog, regardless of the LFSR register value.

12.5.2.1 Normal operation (first watchdog refresh)

At power up, when the RSTB is released as high (after around 16.5 ms), the INIT phase starts for a maximum duration of 256 ms and this is considered as a fully open watchdog window. During this initialization phase, the MCU can configure the product, and no WD error will be detected. When the configuration is done, the MCU accesses the WD_ANSWER SPI register to send the first WD refresh. When the watchdog is properly refreshed during the open window, the 256 ms open window is stopped and the initialization phase is finished. If the watchdog is not refreshed during this 256 ms open window (INIT_FS phase), the device asserts the RSTB, FS0B, and the fault error counter is incremented by '1'. After a good watchdog refresh, the device enters the Normal WD refresh mode, where open and closed windows are defined either by the configuration made during initialization phase in the WD_WINDOW register (Table 87), or by the default value already present in this register (3.0 ms).

12.5.2.2 Normal watchdog refresh

The watchdog must be refreshed during every open window of the window period configured in the register WD_ANSWER. Any WD refresh restarts the window. This ensures the synchronization between MCU and 35FS4500/35FS6500. The duration of the 'window' is selectable through the SPI with no access restriction, meaning the window duration can be changed in the INIT phase or normal mode. Doing the change in normal operation allows the system integrator to configure the watchdog window duration on the fly:

The new WD window duration (except after disable) is taken into account when a proper write access in the WD_ANSWER register occurs or when the previous WD window is finished without any writing (WD timeout).
The new WD window duration after disable is taken into account when the SPI command is validated. The duty cycle of the window is set to 50 % ±10 % and is not modifiable. 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 5 August 2024 Document feedback

Figure 15. Windowed watchdog with FS clock accuracy

12.5.2.3 Watchdog in debug mode

their software and ensure a good watchdog strategy in the application.

12.5.2.4 Wrong watchdog refresh handling

Error counters and strategy are implemented in the device to manage wrong watchdog refreshes from the MCU. INIT_SF_IMPACT register, Table 85).

12.5.2.5 Watchdog error counter

Figure 16. Watchdog error counter configuration (INIT_WD_CNT register, bits WD_CNT_ERR_1:0)

12.5.2.6 Watchdog refresh counter

Figure 17. Watchdog refresh counter configuration (INIT_WD_CNT register, WD_CNT_RFR_1:0) Table 11. Watchdog error table

12.5.3 Fault error counter

fault (undervoltage, overvoltage, external reset,...). reached. The fault error counter has two output values (intermediate and final).

The intermediate value can be used to force the FS0B activation or to generate a RSTB pulse depending on the FLT_ERR_IMP_1:0 bit configuration in INIT_FAULT register.
The final value is used to handle the transition to deep fail-safe when the SELECT pin is connected to Ground. If the SELECT pin is connected to VPRE, the main state machine remains in normal mode and the regulators remain on. The intermediate value of the fault error counter is configurable to ’1’ or ’3’ using the FLT_ERR_FS bit in the INIT_FAULT register (Table 82). The final value of the fault error counter is based on the intermediate configuration. This configuration must be done during the INIT_FS phase. 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 5 August 2024 Document feedback

FLT_ERR_FS = 0/Intermediate = 3; Final = 6 (Figure 18).
FLT_ERR_FS = 1/Intermediate = 1; Final = 2 (Figure 19). In any condition, if the RSTB pin is asserted low for a duration longer than eight seconds, the device goes to:
Deep fail-safe if the DFS function is enabled (SELECT pin connected to ground)
LPOFF-sleep if the DFS function is disabled (SELECT pin connected to VPRE) The following faults lead to an increment of the fault error counter and can be configured:
Watchdog error counter = max value (6 by default)
VCORE, VCCA, VAUX undervoltage
FCRBM follows VCORE configuration
IO_45 error detection (external IC error) The following faults lead to an increment of the fault error counter and cannot be configured:
VPRE overvoltage
Watchdog refresh not OK or watchdog timeout during INIT phase
SPI DED
ABIST1, ABIST2 fail
RSTB short to high (by cascaded effect of FS0B assertion)
External reset (except reset extension by MCU after reset assertion by the device) INCR INCR INCR INCR INCR WD Refresh counter = 7 if cfg WD Refresh counter = 7 if cfg WD Refresh counter = 7 if cfg WD Refresh counter = 7 if cfg WD Refresh counter = 7 if cfg aaa-039168 POR | WU from LPOFF * Assert FS0 if cfg * Assert RST if cfg Turn OFF regulators * DFS if cfg INCR = WD error counter = WD_CNT_ERR[1:0] | WD refresh NOK during INIT_FS | 45_ERR | UV/OV/FCRBM | ABIST1/2 | RSTB_short_high | SPI DED | External Reset | INCR WD Refresh counter = 7 WD Refresh counter = 7 if cfg RSTB assrted for 8 seconds if cfg * Assert RST if cfg * Assert RST if cfg

Figure 18. Fault error counter (FLT_ERR_FS = 0, WD_CNT_RFR = 6) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 19. Fault error counter (FLT_ERR_FS = 1, WD_CNT_RFR = 6)

12.5.3.1 Fault error counter intermediate value

Figure 20. Example of WD operation generating a reset (WD_CNT_ERR = 6)

#1, WD_IMPACT_1:0 = ’01’ and FLT_ERR_IMP_1:0 = ’01’: WD impact on RSTB only and FS0B is asserted low if FLT_ERR_CNT ≥ intermediate value
#2, WD_IMPACT_1:0 = ’10’ and FLT_ERR_IMP_1:0 = ’10’: WD impact on FS0B only and RSTB is asserted low if FLT_ERR_CNT ≥ intermediate value and WD error counter = WD_CNT_ERR[1:0] 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 5 August 2024 Document feedback

Figure 21. Example of RTSB and FS0B behavior when FLT_ERR_CNT ≥ intermediate value

12.5.3.2 Fault error counter at start-up or resuming from LPOFF mode

decrease the fault error counter to 0 (Figure 22). Figure 22. Example of WD operation leading a decrement of the fault error counter (WD_CNT_RFR = 6) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 23. Fault error counter and FS0B deactivation sequence (FLT_ERR_FS = 0 and WD_CNT_ERR = 6)

12.5.4 RESET (RSTB) activation

Watchdog error counter = max value (6 by default)
VCORE, VCCA, VAUX undervoltage
VCORE, VCCA, VAUX overvoltage
FCRBM follows VCORE configuration
Fault error counter level The following faults impact on RSTB activation cannot be configured:
VPRE overvoltage
Watchdog refresh not OK or watchdog timeout during INIT phase
FS0B short to high
RSTB pulse requested by SPI

12.5.5 Fail-safe output (FS0B) activation

Watchdog error counter = max value (6 by default)
VCORE, VCCA, VAUX undervoltage
VCORE, VCCA, VAUX overvoltage
FCRBM follows VCORE configuration
IO_45 error detection (external IC error)
Fault error counter level The following faults impact on FS0B activation cannot be configured:
VPRE overvoltage
Watchdog refresh not OK or watchdog timeout during INIT phase
ABIST1/2 fail
RSTB, FS1B short to high
FS0B low requested by SPI
SPI DED 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 5 August 2024 Document feedback

12.5.6 Fail-safe output (FS1B) activation

Figure 24. FS1B simplified architecture RVPU_FS. The R_FS1B resistor is needed to be robust against ISO 7637(13) pulses. programmable delay if tDELAY > 0 (Figure 25). Figure 25. tDELAY operation used as a FS1B pull-up (Figure 24). 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

the SF_OUTPUT_REQUEST register, before releasing the FS1B pin. digital duration is generated by the fail-safe logic with an accuracy of ±10 %. Figure 26. tDURATION operation

12.5.7 Fail-safe outputs (FS0B and FS1B) release

ABIST2_FS1B_OK=1 if part number with FS1B
ABIST2_VAUX_OK=1 except if VAUX_FS_OV_1:0=VAUX_FS_UV_1:0="00"
Fault is removed
Fault error counter must be at ’0’
Close the S1 switch (FS1B_DLY_DRV bit = 1)
RELEASE_FSxB register must be filled with the right value

12.5.7.1 RELEASE_FSxB register

negative operation per bit must be applied. for FS0B, and a second time for FS1B. Table 12. RELEASE_FSxB register based on LFSR value 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 12. RELEASE_FSxB register based on LFSR value...continued

12.5.8 SPI DED

circuitry is activated to protect registers content.

12.6 Input voltage range

more standard voltage range can still be covered using only the buck configuration. Figure 27. Input voltage range

VSUP > 28 V: Potential VPRE thermal limitation 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 5 August 2024 Document feedback

RDS(on), Current limitation and overcurrent detection are specified for VSUP < 28 V.

VSUP > 19 V: MUX_OUT limitation VSENSE and IO_0 maximum analog input voltage range is 19 V. Internal 2.5 V reference voltage accuracy degraded.
Buck only, VSUP < VSUP_UV_7: CAN communication is guaranteed for VSUP > 6.0 V. For VCCA and VAUX 5.0 V configuration, undervoltage triggers at low VSUP (See Section 9, VCCA_UV_5 and VAUX_UV_5).

12.7 Power management operation

VCCA, VCAN) and an associated individual thermal shutdown (TSD) protects these regulators independently. pass transistor decrease below the TSD threshold.

12.7.1 VPRE voltage pre-regulator

compensation network is fully integrated. The VPRE output voltage is regulated between 6.0 V and 7.0 V. capability in all conditions. Figure 28. Pre-regulator: buck configuration 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

12.7.1.1 Power up and power down sequence

Figure 31. Buck configuration power up and power down Figure 32. Buck boost configuration power up and power down

12.7.1.2 Cranking management

12.7.1.3 Light load condition

regulator operates in pulse skipping mode during light load conditions. VPRE_LL_H, the VPRE high-side transistor is switched on again for the next switching period (Figure 35). Figure 35. Description of light load conditions

12.7.1.4 Input power feed forward condition

between the two frequencies is transparent for the application. Figure 36. Input power feed forward principle

12.7.1.5 Overcurrent detection and current limitation

12.7.1.5.1 Overcurrent protection:

the SW_PRE pin is shorted to GND. The overcurrent works in buck mode only.

12.7.1.5.2 Current limitation:

switched on during tPRE_BLK_LIM to allow short-circuit detection on the SW_PRE pin. cases, the MOSFET is not switched on again before the next rising edge of the switching clock. limitation protects the regulator when the VPRE pin is shorted to GND. Figure 37. Overcurrent and current limitation scheme

12.7.1.6 VPRE voltage monitoring

12.7.1.7 VPRE efficiency

efficiency is calculated and has to be verified by measurement at the application level. Figure 38. VPRE efficiency

12.7.2 VCORE voltage regulator

12.7.2.1 VCORE DC–DC converter

(FB_CORE) (Figure 39). VCORE = VCORE_FB x ((R3 + R4)/R4). kΩ and adjust R3 to obtain the final VCORE voltage needed for the MCU core supply. 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 39. VCORE buck regulator

12.7.2.2 Light load condition

implementation described in detail in Section 12.7.1.3.

12.7.2.3 Current limitation

not switch off the regulator.

12.7.2.4 Voltage monitoring

into the fail-safe state, depending on the supervisor configuration (register INIT_VCORE_OVUV_IMPACT). VCORE voltage through a second resistor bridge (R3b/R4b) to detect an external resistor drift or disconnection. 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 40. Feedback core resistor bridge monitoring (FCRBM) satisfy FB_CORE = FCRBM in all conditions.

12.7.2.5 VCORE efficiency

during the recirculation phase. The lower the diode forward voltage (VF) is, the better the efficiency. Figure 41. VCORE efficiency

12.7.2.6 VCORE linear regulator

power dissipation must be taken into account at low-voltage. Figure 42. VCORE linear regulator

12.7.2.7 Current limitation

inside the device (see Section 12.7.2.3).

12.7.2.8 Voltage monitoring

The linear regulator has the same voltage monitoring than the DC–DC buck converter (see Section 12.7.2.4).

12.7.3 Charge pump and bootstrap

external capacitor minimum to operate properly.

12.7.4 VCCA voltage regulator

accuracy is ±1.0 % for 5.0 V and 3.3 V configuration with an output current capability at 100 mA. when VAUX is configured as a tracking regulator. 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

NXP Semiconductors 35FS4500-35FS6500-ASILB Grade 0 safety power system basis chip with CAN FD transceiver

12.7.4.1 Current limitation

A current limitation is implemented to avoid uncontrolled power dissipation of the internal MOSFET or external PNP transistor. By default, the current limitation threshold is selected based on the auto detection of the external PNP during start-up phase.

When the internal MOSFET transistor is used, the current is limited to ICCA_LIM_INT and the regulator is kept on
When the external PNP transistor is used, the current is limited to ICCA_LIM_OUT and the regulator is switch off after a dedicated duration tCCA_LIM_OFF under current limitation. A SPI command is needed to restart the regulator. In case of an external PNP configuration only, the lowest current limitation threshold can be selected by the SPI in the register INIT_VREG instead of the highest one. A current limitation foldback scheme is implemented to reduce the current limitation to ICCA_LIM_FB when VCCA is below VCCA_LIM_FB, limiting the power dissipation in the external PNP transistor during a short-circuit to GND of the VCCA pin.

12.7.4.2 Voltage monitoring

The overvoltage detection switches off the regulator. The regulator remains on if an undervoltage is detected. A diagnostic is reported in the dedicated register, generating an Interrupt and may bring the application into fail- safe state, depending on the supervisor configuration (register INIT_VCCA_OVUV_IMPACT).

12.7.5 VAUX voltage regulator

VAUX is a highly flexible linear voltage regulator, which can be used either as an auxiliary supply dedicated to additional device in the ECU or as a sensor supply (i.e. outside the ECU). An external PNP transistor must be used (no internal current capability). If VAUX is not used in the application, the VAUX, VAUX_E, and VAUX_B pins must be left open. It is recommended to turn the VAUX driver off and disable the VAUX safety impact by the SPI (VAUX_EN=0 in REG_MODE register and all bits of INIT_VAUX_OVUV_IMPACT register at 0). If VAUX is used as an auxiliary supply, the output voltage is selectable between 5.0 V and 3.3 V. Since this voltage rail can be used to supply MCU IOs, the selection is done with an external resistor connected between the SELECT pin and ground or VPRE. In such case, the voltage accuracy is ±3.0 %, with a maximum output current capability of 400 mA. If VAUX is used as a sensor supply rail, the output voltage is selectable between 5.0 V and 3.3 V. VCCA can be used as reference for the sensor supply used as tracker. In this case, the VAUX voltage must match VCCA, limiting the resistor configuration at the SELECT pin to 5.1 kΩ (VAUX = VCCA = 3.3 V) and 12 kΩ (VAUX = VCCA = 5.0 V). The tracker mode selection is done during the INIT phase and secured (bit VAUX_TRK_EN in the INIT_VREG register). The tracking accuracy is ±15 mV. 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 5 August 2024 Document feedback

5.0 V ref

Figure 43. Example of VAUX used in tracker mode

12.7.5.1 Current limitation

A current limitation is implemented to avoid uncontrolled power dissipation of the external PNP transistor. dissipation in the external PNP transistor during a short-circuit to GND of the VAUX pin. Figure 44. VAUX current limitation scheme with foldback mechanism 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

12.7.5.2 Voltage monitoring

The overvoltage detection switches off the regulator. The regulator remains on if an undervoltage is detected. fail-safe state, depending on the supervisor configuration (register INIT_VAUX_OVUV_Impact).

12.7.6 CAN_5V voltage regulator

overvoltage detector can be enabled by the SPI during INIT_MAIN state. is reported in the dedicated register, generating an Interrupt. The CAN_5V regulator is not a safety regulator. must be put into sleep mode without wake-up capability.

12.7.7 VKAM

versa. Depending on the part number selection (Section 5.2), VKAM can be on or off by default.

If VKAM is on by default, VKAM starts as soon as VSUP3 is > 4.5 V. VKAM can still be turned off/on by the SPI.
If VKAM is off by default, VKAM is turned on/off by the SPI. aaa-037779 VSUP VPRE VCORE RSTB VKAM Enable by default SPI enable Cranking

Figure 45. VKAM start-up strategy RAM or any other external IC which does not exceed the current capability. A current limitation is implemented. the device is in normal mode, and down to VSUP = 4.5 V when the device is in low-power mode off. 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

12.7.8 Power dissipation

VPRE (6.5 V) up to 2.0 A
VCORE (from 1.0 V to 5.0 V range) up to 1.5 A
VCCA (3.3 V or 5.0 V) up to 100 mA (with internal MOS) or up to 300 mA (with external PNP)
VAUX (3.3 V or 5.0 V) up to 400 mA (with external PNP)
VCAN (5.0 V) up to 100 mA A thermal dissipation analysis has to be performed based on the application use case to ensure the maximum silicon junction temperature does not exceed 150 °C. Two use cases covering the two main VCORE voltage configurations are provided in Figure 46.
use case 1: VCORE = 3.3 V, ICORE = 0.7 A, VCCA with int. MOS
use case 2: VCORE = 1.2 V, ICORE = 1.4 A, VCCA with ext. PNP Both use cases have a total internal power dissipation below 0.9 W. A junction to ambient thermal resistivity of 30 °C/W allows the application to work up to an ambient temperature of 150 °C. A good soldering of the package expose pad is highly recommended to achieve such thermal performance. VSUP = 14 V and 25 % of CAN traffic Regulator Voltage Current Comment Vpre Vcore Vcca Vaux 6 V 3.3 V 3.3 V 5 V 670 mA 700 mA 50 mA 200 mA int. MOS use case 1: VCORE = 3.3 V, ICORE = 0.7 A, VCCA with int. MOS 1) CAN transceiver dissipation includes CAN_5V regulator dissipation. 2) 25 % CAN traffic means the CAN bus is dominant for 25 % of time and recessive for the remaining 75 %. TOTAL PDIS = 0.765 W Vpre 25 % Vcca 21 % Vaux 5 % Main contributors to the IC's Power dissipation Vcore 33 % Internal IC 8 % CAN transceiver 8 % aaa-038699 Regulator Voltage Current Comment Vpre Vcore Vcca Vaux 6 V 3.3 V 3.3 V 5 V 800 mA 1.4 A 200 mA 200 mA ext. PNP use case 2: VCORE = 1.2 V, ICORE = 1.4 A, VCCA with ext. PNP TOTAL PDIS = 0.829 W Vpre 28 % Vcca 2 % Vaux 5 % Main contributors to the IC's Power dissipation Vcore 51 % Internal IC 7 % CAN transceiver 7 %

3.3 V and 5 V

5 V 5 V 5 V

Figure 47. Power dissipation versus ICORE, ICCA, or IPRE

12.7.9 Start-up sequence

released from LPOFF. All the different voltage rails start automatically as described in Figure 48. 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 48. Start-up scheme The final value of VAUX and VCCA depends on the hardware configuration (resistor values at the SELECT pin). ms by the MCU, if it is not ready to run after power up. See Section 12.7.7 for the VKAM start-up sequence.

12.8 Long duration timer

counting periods, as well as a calibration mechanism, for internal oscillator compensation. Hz oscillator, allowing a 1.0 s timebase. 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 49. Long duration timer block diagram

12.8.1 Timer characteristics

Table 13. Long duration timer characteristics

12.8.2 Calibration procedure

Select the timer function 1 and set the after run value to 65535 (~32 s).
Start the counter.
Read the counter when the MCU RTC reaches 20 s (must be less than 30 s with ±5.0 % oscillator accuracy).
If the oscillator period is at exact typical value (absolutely no deviation error), expected reading is 40960.
The exact reading calculates the error correction factor ECF = exact_reading/ expected_reading.
ECF < 1 if the oscillator is faster than the exact typical value.
ECF > 1 if the oscillator is slower than the exact typical value.
After calibration, the new after run or wake-up values to set the counter are after run x ECF and wake-up x ECF. 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 5 August 2024 Document feedback

12.8.3 Timer functions

Function 1: In normal mode, count and generate a flag or an Interrupt when the counter reaches the after run value.
Function 2: In normal mode, count until the counter reaches the after run value and enters into low-power mode.
Function 3: In normal mode, count until the counter reaches the after run value and enters into low-power mode. Once in low-power mode, count until the counter reaches the wake-up value and wakes up.
Function 4: In low-power mode, count until the counter reaches the wake-up value and wakes up.
Function 5: In low-power mode, count and do not wake-up unless the counter overflow occurs, or if the device wakes up by another source (CAN, IO). aaa-037784 timer counts After run value reached INTb SPI: configure timer function 1 SPI: write after run register SPI: write START INTB when after run value reached SPI: configure timer function 2 SPI: write after run register SPI: write START Entry in LPOFF after run value reached SPI: configure timer function 3 SPI: write after run register SPI: write wake-up register SPI: write START Entry in LPOFF after run value reached and wake-up when wake-up value reached SPI: configure timer function 4 SPI: write wake-up register SPI: go to LPOFF Wake-up when wake-up value reached SPI: configure timer function 5 SPI: go to LPOFF Wake-up when other wake-up event occurs (ex CAN) FUNCTIONS NORMAL MODE LOW-POWER MODE (LPOFF) timer counts After run value reached Entry in low-power mode when after run value reached Entry in low-power mode when after run value reached No entry in low-power mode controlled by LDT timer counts timer counts Wake-up value reached Wake-up value reached After run value reached Entry in init mode after wake-up by timer WAKE-UP Entry in low-power mode by SPI timer counts Entry in init mode after wake-up by timer Entry in init mode after CAN wake-up timer continues to count WAKE-UP Entry in low-power mode by SPI timer counts WAKE-UP (ex CAN) Function 1 Function 2 Function 3 Function 4 Function 5

Figure 50. Long duration timer functions

12.8.4 Timer operation

and the 24-bit wake-up value are configured and read in the corresponding registers. 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

set by SPI. The wake-up timer function starts when the device enters in LPOFF mode.

When function 1 is selected and the counter reaches the after run value (EOT), an interrupt is generated and the counter is stopped. The counter must be disabled (~ENABLE) before reading its value and enabled again.
When function 2 is selected and the counter reaches the after run value (EOT), the device goes to LPOFF mode and the counter is stopped. The counter must be disabled (~ENABLE) before reading its value and enabled again.
When function 3 is selected and the counter reaches the after run value (EOT), the device goes to LPOFF mode. The counter is reset and restart to count. When the counter reaches the wake-up value (EOT), the device wakes up and the counter is stopped. The counter must be disabled (~ENABLE) before reading its value and enabled again.
When function 4 is selected and the counter reaches the wake-up value (EOT), the device wakes up and the counter is stopped. The counter must be disabled (~ENABLE) before reading its value and enabled again.
When function 5 is selected and the counter overflows (OVRFLW), the device wakes up and the counter is stopped. The counter must be disabled (~ENABLE) before reading its value and enabled again. Overflow means counter max value is reached (all 24 bits at logic 1).
When function 5 is selected and the devices wakes up by CAN, or IO, the counter is running. The counter must be disabled (~ENABLE) before reading its value and enabled again. aaa-039994 AFTER RUN count IDLE STOP WAKE UP countF3 & EOT * F3 & EOT -> LPOFF ~ ENABLE ENABLE & (F1|F2|F3) (F1|F2) & EOT * F1 & EOT -> INTB * F2 & EOT -> LPOFF EOT: End Of Timer OVRFLW: Timer Overflow FX: Function X selected WU: Wake up ~ ENABLE ~ ENABLE POR ENABLE & LPOFF & (F4|F5) * F5 & WU by CAN, IO ((F3|F4) & EOT) | (F5 & OVRFLW) * (F3|F4) & EOT -> WU * F5 & OVRFLW -> WU

Figure 51. Long duration timer state machine

12.9 CAN transceiver

Figure 52. CAN simplified block diagram

12.9.1 Operating modes

12.9.1.1 Normal mode

TXD to the bus. TXD is maintained high by an internal pull-up resistor TXDPULL-UP connected to VDDIO. 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

0.3 VDDIO

0.7 VDDIO

Figure 53. CAN timing diagram

12.9.1.2 Sleep mode

enter LPOFF is restored (Figure 54). Figure 54. CAN transition when device goes to LPOFF

12.9.2 Fault detection

12.9.2.1 TXD permanent dominant (timeout)

permanently in case a failure sets the TXD input to a permanent low level. 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 55. TXD dominant timeout detection

12.9.2.2 RXD permanent recessive

detection is operating when the CAN transceiver is in normal mode and listen only mode.

12.9.2.3 CAN-bus short-circuits

logic. The CAN driver and receiver are not disabled. They are detected and reported to the device main logic. Figure 56. Illustration of CANL short to GND detection mechanism 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

12.9.2.4 CAN current limitation

(parameters ICANL-SK and ICANH-SC).

12.9.2.5 CAN overtemperature

CAN_OT is reported in the DIAG_CAN_2 register. normal operation and when a high level is detected on TXD. Event 1: overtemperature detection. CAN driver disable. Event 2: temperature falls below ’overtemp. threshold minus hysteresis’ => CAN driver remains disable. Event 3: temperature below ’overtemp. threshold minus hysteresis’ and TXD high to low transition ≥ CAN driver enable. Figure 57. Overtemperature behavior

12.9.2.6 Distinguish CAN diagnostics and CAN errors

the INIT_INH_INT register. The list of CAN diagnostic and CAN error bits is provided in Table 14. 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 14. CAN diagnostic and CAN error bits

12.9.3 Wake-up mechanism

depending on the SPI selection. The wake-up events are reported in the WU_SOURCE register.

12.9.3.1 Multiple pulse detection

event 3: a dominant level longer than t3PWU.

permanent wake-up situation which would prevent system to enter in low-power mode. Figure 58. Multiple pulse wake-up pattern illustration 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

NXP Semiconductors 35FS4500-35FS6500-ASILB Grade 0 safety power system basis chip with CAN FD transceiver

13 Serial peripheral interface

13.1 High-level overview

13.1.1 SPI

The device uses a 16-bit SPI, with the following arrangement: MOSI, Primary Out Secondary In bits:

Bit 15 read/write
Bit 14 main or fail-safe register target
bit 13 to 9 (A4 to A0) to select the register address. Bit 8 is a parity bit in write mode, next bit (=0) in read mode.
bit7 to 0 (D7 to D0): control bits MISO, Primary In Secondary Out bits:
bits 15 to 8 (S15 to S8) are device status bits
bits 7 to 0 (Do7 to Do0) are either extended device status bits, device internal control register content or device flags. Figure 59 is an overview of the SPI implementation.

13.1.2 Parity bit 8 calculation

The parity bit 8 is used in write mode only (bit 15 = 1). It is calculated based on the number of logic ones contained in the bit 15–9, 7–0 sequence (this is the whole 16 bits of the write command except bit 8). In read mode, the parity bit should be set to 0. Bit 8 must be set to 0 if the number of ones is odd. Bit 8 must be set to 1 if the number of ones is even.

13.1.3 Device status on MISO

When a write operation is performed to store data or a control bit in the device, the MISO pin reports a 16-bit fixed device status composed of two bytes: device fixed status (bits 15 to 8) + extended device status (bits 7 to 0). In a read operation, MISO reports the fixed device status (bits 15 to 8), and the next eight bits are content of the selected register. A standard serial peripheral interface (SPI) is integrated to allow bidirectional communication between the 35FS4500/35FS6500 and the MCU. The SPI is used for configuration and diagnostic purposes. 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 5 August 2024 Document feedback

for write commands, MOSI bits [15] = [1]. and sampled at falling edge. MSB first. Figure 59. SPI overview: SPI waveform and signals polarity previously written) is correct.

13.1.4 Register description

be done in between (Figure 8).

13.2 Detailed operation

13.2.1 SPI command organization

0 ReadR/W

1 Write

0 MainM/FS

1 Fail-safe

0 Number of ’1’ (bit 15:9 and bit 7:0) is oddP

1 Number of ’1’ (bit 15:9 and bit 7:0) is even

Table 15. MOSI bits description

13.2.2 Main logic general diagnostic

Figure 61. MISO SPI bits 15:8

0 No failure

1 Failure

0 No WU_G event

1 WU_G event

0 No event

1 CAN event

0 No IO transition

1 IO transition

1 Event occurred

Table 16. MISO bits description...continued

13.2.3 Fail-safe logic general diagnostic

Figure 62. MISO SPI bits 7:4 Description Secured SPI communication check, concerns fail-safe logic only.

0 No error

1 Error detected in the secured bits

1 Wrong number of clock cycles (<16 or >16)

1 SPI violation

0 Parity bit OK

1 Parity bit error

Table 17. MISO bits description...continued

13.2.4 Main logic register address table

Table 18 is a list of device registers and addresses coded in bits 13 to 9 in MOSI for main logic. Write description Table ref. Table 18. Register mapping of main logic 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Write description Table ref. Table 18. Register mapping of main logic ...continued

13.2.5 Fail-safe logic register address table

Write description Table ref. Table 19. Register mapping of fail-safe logic

13.2.6 Secured SPI command

Secure 3 = NOT(Bit5)
Secure 2 = NOT(Bit4)
Secure 1 = Bit7
Secure 0 = Bit6

13.3 Detail of main logic register mapping

13.3.1 INIT_VREG

0 TAUX_

Table 21. INIT_VREG register description

0 ICCA_LIM_OUT

1 ICCA_LIM_INT

0 Enabled

1 Disabled

0 Off. VCAN OV is not monitored. Flag is ignored. 1 On. VCAN OV is monitored. If OV the CAN_5V regulator is switched off. Table 22. INIT_VREG description and configuration of the bits (default value in bold) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Description Configure the current limitation duration before VAUX is switched off.

1 Tracking mode enabled and latched

0 NO POR

1 POR occurred

Table 22. INIT_VREG description and configuration of the bits (default value in bold) ...continued [1] BAT_FAIL = POR_M or VSUP_UV_L or BG_OK (reset sources of main logic). BAT_FAIL bit is cleared by a SPI read.

13.3.2 INIT_WU1

Table 23. INIT_WU1 register description

00 NO wake-up capability

01 Wake-up on rising edge - or high level

10 Wake-up on falling edge - or low level

11 Wake-up on any edge

Table 24. INIT_WU1 description and configuration of the bits (default value in bold) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 24. INIT_WU1 description and configuration of the bits (default value in bold)...continued

13.3.3 INIT_WU2

Table 25. INIT_WU2 register description Table 26. INIT_WU2 description and configuration of the bits (default value in bold) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

0 CAN in RX only mode (when FS1B_CAN_ IMPACT = 1 in INIT_FAULT

1 CAN in sleep mode (when FS1B_CAN_ IMPACT = 1 in INIT_FAULT register)

Table 26. INIT_WU2 description and configuration of the bits (default value in bold) ...continued

13.3.4 INIT_INT

0 INT_INH_

Table 27. INIT_INT register description

0 All INT sources

1 All INT inhibited

1 VSNS_UV INT inhibited

Table 28. INIT_INT description and configuration of the bits (default value in bold) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

1 VPRE status change inhibited

1 VCORE status change inhibited

1 VCCA/VAUX/VCAN status change inhibited

1 CAN error bits change inhibited

Table 28. INIT_INT description and configuration of the bits (default value in bold)...continued

13.3.5 INIT_INH_INT

Table 29. INIT_INH_INT register description

0 INT not masked

1 INT masked

Table 30. INIT IO_WU2 description and configuration of the bits (default value in bold) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 30. INIT IO_WU2 description and configuration of the bits (default value in bold)...continued

13.3.6 LONG_DURATION_TIMER

Table 31. LONG_DURATION_TIMER register description

000 Function 1: in normal mode count and generate flag or INT when

counter reaches the after run value.

001 Function 2: in normal mode count until after run value is reached, then enters

010 Function 3: in normal mode count until after run value is reached, then enters

011 Function 4: in LPOFF, count until wake-up value is reached and wake-up. Table 32. LONG_DURATION_TIMER description and configuration of the bits (default value in bold) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

0 Read programmed wake-up register

1 Read real time counter into wake-up register (after counter is stopped with

0 Calibration mode (488 µs resolution)

1 Normal mode (1 s resolution)

0 LDT counter stop

1 LDT counter start

0 Counter not running

1 Counter running

0 No INT generated

1 INT generated when counter reach after run value

Table 32. LONG_DURATION_TIMER description and configuration of the bits (default value in bold)...continued

13.3.7 HW_CONFIG

Table 33. HW_CONFIG register description

0 Buck-boost

1 Buck only

0 External PNP connected

1 Internal MOSFET

Table 34. HW_CONFIG description and configuration of the bits (default value in bold) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

0 Deep fail-safe disable

1 Deep fail-safe enable

0 Normal operation

1 Debug mode selected

Table 34. HW_CONFIG description and configuration of the bits (default value in bold)...continued

13.3.8 WU_SOURCE

Table 35. WU_SOURCE register description

0 No wake-up

1 Wake-up event detected

Table 36. WU_SOURCE description and configuration of the bits (default value in bold) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 36. WU_SOURCE description and configuration of the bits (default value in bold)...continued

13.3.9 DEVICE _ID

Table 37. DEVICE_ID register description Table 38. DEVICE_ID description and configuration of the bits (default value in bold) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

0 VKAM off by default

1 VKAM on by default

Table 38. DEVICE_ID description and configuration of the bits (default value in bold)...continued

13.3.10 IO_INPUT

Table 39. IO_INPUT register description

0 Low

1 High

Table 40. IO_INPUT description and configuration of the bits ...continued

13.3.11 DIAG_VPRE

Table 41. DIAG_VPRE register description

0 Buck

1 Boost

0 SMPS off

1 SMPS on

0 No thermal warning (TJ < TWARN_PRE)

1 Thermal warning (TJ > TWARN_PRE)

0 No TSD (TJ < TSD_PRE)

1 TSD occurred (TJ > TSD_PRE)

Table 42. DIAG_VPRE description and configuration of the bits (default value in bold) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

0 No overvoltage (VPRE < VPRE_OV)

1 Overvoltage detected (VPRE > VPRE_OV)

0 No undervoltage (VPRE > VPRE_UV)

1 Undervoltage detected (VPRE < VPRE_UV)

0 No current limitation (IPRE_PK < IPRE_LIM)

1 Current limitation (IPRE_PK > IPRE_LIM)

Table 42. DIAG_VPRE description and configuration of the bits (default value in bold)...continued

13.3.12 DIAG_VCORE

0 VCORE_

Table 43. DIAG_VCORE register description

0 No thermal warning (TJ < TWARN_CORE)

1 Thermal warning (TJ > TWARN_CORE)

0 No TSD (TJ< TSD_CORE)

1 TSD occurred (TJ > TSD_CORE)

0 No overvoltage (VCORE_FB < VCORE_FB_OV)

1 Overvoltage detected (VCORE_FB > VCORE_FB_OV)

Table 44. DIAG_VCORE description and configuration of the bits (default value in bold) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

0 No undervoltage (VCORE_FB > VCORE_FB_UV)

1 Undervoltage (VCORE_FB < VCORE_FB_UV)

Table 44. DIAG_VCORE description and configuration of the bits (default value in bold)...continued

13.3.13 DIAG_VCCA

Table 45. DIAG_VCCA register description

0 No thermal warning (TJ < TWARN_CCA)

1 Thermal warning (TJ > TWARN_CCA)

0 NO TSD (TJ < TSD_CCA)

1 TSD occurred (TJ > TSD_CCA)

0 No overvoltage (VCCA < VCCA_OV)

1 Overvoltage detected (VCCA > VCCA_OV)

0 No undervoltage (VCCA > VCCA_UV)

1 Undervoltage detected (VCCA < VCCA_UV)

0 No current limitation (ICCA < ICCA_LIM)

1 Current limitation (ICCA > ICCA_LIM)

Table 46. DIAG_VCCA description and configuration of the bits (default value in bold) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

0 T_LIMITATION < TCCA_LIM_OFF

1 T_LIMITATION >TCCA_LIM_OFF

Table 46. DIAG_VCCA description and configuration of the bits (default value in bold)...continued

13.3.14 DIAG_VAUX

Table 47. DIAG_VAUX register description

0 No TSD (TJ < TSD_AUX)

1 TSD occurred (TJ > TSD_AUX)

0 No overvoltage (VAUX < VAUX_OV)

1 Overvoltage detected (VAUX > VAUX_OV)

0 No undervoltage (VAUX > VAUX_UV)

1 Undervoltage detected (VAUX < VAUX_UV)

0 No current limitation (IAUX < IAUX_LIM)

1 Current limitation (IAUX > IAUX_LIM)

0 T_LIMITATION < TAUX_LIM_OFF

1 T_LIMITATION >TAUX_LIM_OFF

Table 48. DIAG_VAUX description and configuration of the bits (default value in bold) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

13.3.15 DIAG_VSUP_VCAN

Table 49. DIAG_VSUP_VCAN register description

0 VBAT > VSNS_UV

1 VBAT < VSNS_UV

0 VSUP > VSUP_UV_7

1 VSUP < VSUP_UV_7

1 IPFF mode activated

0 NO TSD (TJ < TSD_CAN)

1 TSD occurred (TJ > TSD_CAN)

0 No overvoltage (VCAN < VCAN_OV)

1 Overvoltage detected (VCAN > VCAN_OV)

0 No undervoltage (VCAN > VCAN_UV)

1 Undervoltage detected (VCAN < VCAN_UV)

0 No current limitation (ICAN < ICAN_LIM)

1 Current limitation (ICAN > ICAN _LIM)

Table 50. DIAG_VSUP_VCAN description and configuration of the bits (default value in bold) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

13.3.16 DIAG_CAN_1

Table 51. DIAG_CAN_1 register description

1 Failure detected

0 No failureTXD_DOM

Table 52. DIAG_CAN_1 description and configuration of the bits (default value in bold) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 52. DIAG_CAN_1 description and configuration of the bits (default value in bold)...continued

13.3.17 DIAG_CAN_2

Table 53. DIAG_CAN_2 register description Table 54. DIAG_CAN_2 description and configuration of the bits (default value in bold)

13.3.18 DIAG_SPI

Table 55. DIAG_SPI register description

1 Wrong number of clock cycles (<16 or > 16)

Table 56. DIAG_SPI description and configuration of the bits (default value in blue) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 56. DIAG_SPI description and configuration of the bits (default value in blue)...continued

13.3.19 Mode

Table 57. Mode register description

0 DISABLED

1 ENABLED

0 No action

1 Go to LPOFF mode and wait for wake-up event

Table 58. Mode description and configuration of the bits (default value in bold) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

0 No Request

1 Request for an INT pulse

0 Not in INIT mode

1 INIT mode

0 Not in normal mode

1 Normal mode

0 Not in deep fail-safe

1 Resume from deep fail-safe

0 Not in LPOFF

1 Resume from LPOFF

Table 58. Mode description and configuration of the bits (default value in bold)...continued

13.3.20 REG_MODE

Table 60. REG_MODE description and configuration of the bits (default value in bold)

13.3.21 IO_OUT_AMUX

Table 61. IO_OUT_AMUX register description

0 High-impedance (IO_4 configured as input)

1 Enabled (IO_4 configured as output gate driver)

Table 62. IO_OUT_AMUX description and configuration of the bits (default value in bold) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

000 VREF

001 VSNS wide range

010 IO_0 wide range

011 IO_5 wide range

100 VSNS tight range

101 IO_0 tight range

110 IO_5 tight range/VKAM

111 Die Temperature Sensor

Table 62. IO_OUT_AMUX description and configuration of the bits (default value in bold)...continued

13.3.22 CAN_MODE

Table 63. CAN_MODE register description

00 Sleep/no wake-up capability

01 Listen only

10 Sleep/wake-up capability

11 Normal operation mode

Table 64. CAN_MODE description and configuration of the bits (default value in bold) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

0 NO auto disable

1 Reset CAN_MODE from ’11’ to ’01’ on CAN_OT or TXD_DOM or

1 Wake-up detected

Table 64. CAN_MODE description and configuration of the bits (default value in bold)...continued device enters in LPOFF. After LPOFF, the initial CAN mode prior to enter LPOFF is restored.

13.3.23 LDT_AFTER_RUN_1

Table 65. LDT_AFTER_RUN_1 register description Table 66. LDT_AFTER_RUN_1 description and configuration of the bits (default value in bold)

13.3.24 LDT_AFTER_RUN_2

Table 68. LDT_AFTER_RUN_2 description and configuration of the bits (default value in bold)

13.3.25 LDT_WAKE_UP_1

Table 69. LDT_WAKE_UP_1 register description Table 70. LDT_WAKE_UP_1 description and configuration of the bits (default value in bold)

13.3.26 LDT_WAKE_UP_2

Table 71. LDT_WAKE_UP_2 register description Table 72. LDT_WAKE_UP_2 description and configuration of the bits (default value in bold) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

13.3.27 LDT_WAKE_UP_3

Table 73. LDT_WAKE_UP_3 register description Table 74. LDT_WAKE_UP_3 description and configuration of the bits (default value in bold)

13.4 Detail of fail-safe logic register mapping

13.4.1 INIT_FS1B_TIMING

Table 76. INIT_FS1B_TIMING. Description and configuration of the bits (Default value in bold)

13.4.2 BIST

0 Secure_3 Secure_2 Secure_1 Secure_0

1 Launch ABIST on FS1B

1 Launch ABIST on VAUX

0 FS1B ABIST fail or not executed

1 FS1B ABIST pass

0 VAUX ABIST fail or not executed

1 VAUX ABIST pass

0 ABIST1 fail

1 ABIST1 pass

Table 78. BIST description and configuration of the bits (default value in bold)

13.4.3 INIT_SUPERVISOR

1 Degraded mode, lower undervoltage detection threshold applied (VCORE_FB_

1 Degraded mode, lower undervoltage detection threshold applied (VCCA_UV_D)

1 Degraded mode; lower undervoltage detection threshold applied (VAUX_UV_5D)

Table 80. INIT_SUPERVISOR description and configuration of the bits (default value in bold)

13.4.4 INIT_FAULT

0 No effect

1 CAN in RX only or sleep mode when FS1B is asserted (depends on

00 No effect on RSTB and FS0B

01 FS0B is asserted low if FLT_ERR_CNT ≥ intermediate value

10 RSTB is asserted low if FLT_ERR_CNT ≥ intermediate value and WD error

11 FS0B is asserted low if FLT_ERR_CNT ≥ intermediate value

Table 82. INIT_FAULT description and configuration of the bits (default value in bold)

13.4.5 INIT_FSSM

0 Not safety

1 Safety critical

Table 84. INIT_FSSM description and configuration of the bits (default value in bold)

13.4.6 INIT_SF_IMPACT

Table 85. INIT_SF_IMPACT register description

0 FS1B tDELAY mode

1 FS1B tDURATION mode

Table 86. INIT_SF_IMPACT description and configuration of the bits (default value in bold) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

00 No effect on RSTB and FS0B if WD error counter = WD_CNT_ERR[1:0]

01 RSTB only is asserted low if WD error counter = WD_CNT_ERR[1:0]

10 FS0B only is asserted low if WD error counter = WD_CNT_ERR[1:0]

11 RSTB and FS0B are asserted low if WD error counter = WD_CNT_ERR[1:0]

Table 86. INIT_SF_IMPACT description and configuration of the bits (default value in bold)...continued

13.4.7 WD_WINDOW

0000 Disable (in INIT phase only)

Table 88. WD_WINDOW description and configuration of the bits (default value in bold)

13.4.8 LFSR

Table 90. LFSR description and configuration of the bits (default value in bold) [1] Value Bit7:Bit0: 1111 1111 is prohibited. [2] During a write command, MISO reports the previous register content.

13.4.9 WD_ANSWER

Table 91. WD_ANSWER register description Any value can be written to refresh the watchdog.

0 No reset

1 Reset occurred

0 No fail-safe

1 Fail-safe event occurred (default state at power up and after LPOFF as

Table 92. WD_ANSWER description and configuration of the bits (default value in bold) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

1 Error detected

0 WD timing refresh OK

1 Wrong WD timing refresh

Table 92. WD_ANSWER description and configuration of the bits (default value in bold) ...continued registers or access (read or write) WD_ANSWER register first.

13.4.10 RELEASE_FSxB

0 FS1B pad sense low

1 FS1B pad sense high

0 FS0B pad sense low

1 FS0B pad sense high

0 RSTB pad sense low

1 RSTB pad sense high

Table 94. RELEASE_FSxB description and configuration of the bits (default value in bold)

13.4.11 SF_OUTPUT_REQUEST

Table 95. SF_OUTPUT_REQUEST register description

1 Request FS1B assertion with immediate assertion, no delay

0 Close S1

1 Open S1

Table 96. SF_OUTPUT_REQUEST description and configuration of the bits (default value in bold) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

1 Request FS0B assertion

1 Request a RSTB low pulse

0 FS1B digital driver sense low

1 FS1B digital driver sense high

0 FS1B analog driver sense low

1 FS1B analog driver sense high

0 FS0B driver sense low

1 FS0B driver sense high

0 RSTB driver sense low

1 RSTB driver sense high

Table 96. SF_OUTPUT_REQUEST description and configuration of the bits (default value in bold)...continued

13.4.12 INIT_WD_CNT

Table 98. INIT_WD_CNT description and configuration of the bits (default value in bold)

13.4.13 DIAG_SF_IOs

Table 99. DIAG_SF_IOs register description

0 No external RSTB

1 External RSTB

Table 100. DIAG_SF_IOs description and configuration of the bits (default value in bold) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

1 Short-circuit high

00 No Failure

01 Short-circuit low/open load

Table 100. DIAG_SF_IOs description and configuration of the bits (default value in bold)...continued

13.4.14 WD_COUNTER

Table 101. WD_COUNTER register description Table 102. WD_COUNTER description and configuration of the bits (default value in bold) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

13.4.15 DIAG_SF_ERR

Table 103. DIAG_SF_ERR register description

0 No overvoltage (V2P5_M_A < V2P5_M_A_OV)

1 Overvoltage detected (V2P5_M_A > V2P5_M_A_OV)

0 No overvoltage (V2P5_M_D < V2P5_M_D_OV)

1 Overvoltage detected (V2P5_M_D > V2P5_M_D_OV)

0 No overvoltage (FB_Core – FCRBM < 150 mV)

1 Overvoltage detected (FB_Core – FCRBM > 150 mV)

0 No undervoltage (FB_Core – FCRBM > –150 mV)

1 Undervoltage detected (FB_Core – FCRBM < –150 mV)

Table 104. DIAG_SF_ERR description and configuration of the bits (default value in bold)

13.4.16 INIT_VCORE_OVUV_IMPACT

00 No effect of VCORE_FB_OV on RSTB and FS0B

01 VCORE_FB_OV does have an impact on RSTB only

10 VCORE_FB_OV does have an impact on FS0B only

11 VCORE_FB_OV does have an impact on RSTB and FS0B

00 No effect of VCORE_FB_UV on RSTB and FS0B

01 VCORE_FB_UV does have an impact on RSTB only

10 VCORE_FB_UV does have an impact on FS0B only

11 VCORE_FB_UV does have an impact on RSTB and FS0B

Table 106. INIT_VCORE_OVUV_IMPACT description and configuration of the bits (default value in bold)

13.4.17 INIT_VCCA_OVUV_IMPACT

00 No effect of VCCA_OV on RSTB and FS0B

01 VCCA_OV does have an impact on RSTB only

10 VCCA_OV does have an impact on FS0B only

11 VCCA_OV does have an impact on RSTB and FS0B

00 No effect of VCCA_UV on RSTB and FS0B

01 VCCA_UV does have an impact on RSTB only

10 VCCA_UV does have an impact on FS0B only

11 VCCA_UV does have an impact on RSTB and FS0B

Table 108. INIT_VCCA_OVUV_IMPACT description and configuration of the bits (default value in bold)

13.4.18 INIT_VAUX_OVUV_IMPACT

Table 109. INIT_VAUX_OVUV_IMPACT register description

00 No effect of VAUX_OV on RSTB and FS0B

01 VAUX_OV does have an impact on RSTB only

10 VAUX_OV does have an impact on FS0B only

11 VAUX_OV does have an impact on RSTB and FS0B

Table 110. INIT_VAUX_OVUV_IMPACT description and configuration of the bits (default value in bold) 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

00 No effect of VAUX_UV on RSTB and FS0B

01 VAUX_UV does have an impact on RSTB only

10 VAUX_UV does have an impact on FS0B only

11 VAUX_UV does have an impact on RSTB and FS0B

Table 110. INIT_VAUX_OVUV_IMPACT description and configuration of the bits (default value in bold)...continued

13.4.19 DEVICE_ID_FS

Table 111. DEVICE_ID_FS register description Table 112. DEVICE_ID_FS description and configuration of the bits (default value in bold)

14 List of interruptions and description

ILIM_CCA_OFF Current limitation maximum duration expiration. Only used when external PNP connected. ILIM_AUX_OFF Current limitation maximum duration expiration. Only used when external PNP connected. TSDCAN Temperature shutdown on the pass transistor. Auto restart when TJ < (TSDCAN – TSDCAN_HYST). Table 113. Interruptions list...continued 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

15 Typical applications

PCB layout performance ESR cap. Figure 63. 35FS6500 simplified application schematic with CAN, FS1B, VKAM, buck/boost VPRE configuration 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 66. VAUX not used, VCCA configuration up to 100 mA, deep fail-safe disabled Figure 67. VCCA connection, VAUX not used, deep fail-safe disabled Figure 68. VCCA connection, VAUX not used, deep fail-safe enabled

16 Packaging

16.1 Package mechanical dimensions

www.nxp.com and perform a keyword search for the drawing’s document number. 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

16.2 Package outline

17 Soldering

Figure 72. SOT1571-1 Rev. F - PCB design guidelines - solder mask opening pattern 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 73. SOT1571-1 Rev. F - PCB design guidelines - I/O pads and solderable area 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 74. SOT1571-1 Rev. F - PCB design guidelines - solder paste stencil 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

NXP Semiconductors 35FS4500-35FS6500-ASILB Grade 0 safety power system basis chip with CAN FD transceiver

18 References

Obtain additional information on related NXP products and application solutions through the documents and URLs listed below. (1) AN5238 - FS6500 and FS4500 Safe System Basis Chip Hardware Design and Product Guidelines - Application Note https://www.nxp.com/AN5238-DOWNLOAD (2) AN4388 - Quad Flat Package (QFP) https://www.nxp.com/files/analog/doc/app_note/AN4388.pdf (3) FS6500-FS4500PDTCALC - Power dissipation tool (Excel File) https://www.nxp.com/files/analog/software_tools/FS6500-FS4500-power-dissipation-calculator.xlsx (4) VCORE compensation network simulation tool (CNC)[1] (5) FMEDA - FS6500/FS4500 ASILB Grade 0 FMEDA[1] (6) UM11548 - 35FS4500/35FS6500 functional safety manual – ASIL B – Safety manual (7) KITFS4508CAEEVM - FS4508, System Basis Chip, ASIL B, Linear 0.5 A Vcore, FS1b, LDT, CAN https://www.nxp.com/KITFS4508CAEEVM (8) FS6500 product summary page - https://www.nxp.com/FS6500 (9) FS4500 product summary page - https://www.nxp.com/FS4500 (10) Analog power management homepage - https://www.nxp.com/products/power-management (11) ISO 11898-2:2003 - Road vehicles — Controller area network (CAN) — Part 2: High-speed medium access unit https://www.iso.org/standard/33423.html (12) ISO 11898-5:2007 - Road vehicles — Controller area network (CAN) — Part 5: High-speed medium access unit with low-power mode https://www.iso.org/contents/data/standard/04/12/41284.html (13) ISO 7637-2:2011 - Road vehicles — Electrical disturbances from conduction and coupling — Part 2: Electrical transient conduction along supply lines only https://www.iso.org/standard/50925.html (14) ISO 10605:2008 - Road vehicles — Test methods for electrical disturbances from electrostatic discharge https://www.iso.org/standard/41937.html (15) IEC 61000-4-2:2008 - Electromagnetic compatibility (EMC) - Part 4-2: Testing and measurement techniques - Electrostatic discharge immunity test https://webstore.iec.ch/publication/4189 (16) JESD51- 6 - INTEGRATED CIRCUIT THERMAL TEST METHOD ENVIRONMENTAL CONDITIONS - FORCED CON VECTION (MOVING AIR) (17) JESD51-7 - HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD FOR LEADED SURFACE MOUNT PAC KAGES (18) JESD22-A114F - ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING HUMAN BODY MODEL (HBM) (19) JESD22-C101F - FIELD-INDUCED CHARGED-DEVICE MODEL TEST METHOD FOR ELECTROSTATIC DIS CHARGE WITHSTAND THRESHOLDS OF MICROELECTRONIC COMPONENTS (20) MIL-STD-883-1, Method 1012.1 - TEST METHOD STANDARD MICROCIRCUITS [1] Available upon request. 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 5 August 2024 Document feedback

Supersedes 35FS4500-35FS6500-ASILB v.2.0
CIN 202407025I
Updated status from confidential to public
Updated document title from "35FS4500, 35FS6500: ASIL B" to "35 FS4500-35FS6500-ASILB"
Updated Revision history to reflect new NXP standard
Changed each instance of "master" to "primary", and each instance of "slave" to "secondary"
Revised Figure 3
In Table 4, removed references to LIN
In Section 12.1.7.2, changed VPRE_UV_L_4P3 to VPRE_UV_4P3
Updated Figure 13
Updated Figure 14
Updated Figure 16, and its title
Section 11.6: Changed "… (±1.0 % for 5.0 V configuration and ±1.5 %
Revised the last paragraph of Section 12.5.2
Revised Figure 17
Changed name of Figure 22
Revised Section 12.5.3
Changed each instance of the register name INT_WD to INT_WD_CNT
In Section 12.8.1, removed calibration example
Section 13.1.4: Correct two figure links
Added Section 12.8.2
In Section 13.1.2, revised all three paragraphs and corrected punctuation
Corrected the name of bit 4 in Figure 62
In Table 38, revised the description of the DEV_REV_2:0 bit field
Revised Figure 63
Added new disclaimer t001dis136 NXP B.V. is not an operating company. 35FS4500-35FS6500-ASILB v.2.0 09 April 2021 • Product data sheet
Supersedes 35FS4500-35FS6500-ASILB v.1.0
CIN 202104021I
Section 1: replaced "0.8 A" by "1.5 A"
Section 2: replaced "Family of devices to supply MCU core from 1.0 V to 5.0 V, with SMPS (0.8 A) or LDO (0.5 A)" to "Family of devices to supply A)"
Section 5: updated Table 1 and Table 2 (added new part numbers)
Table 5: updated ICORE and ICORE_LIM to include values for FS651x, and added parameters for FS65_LORvcore_1.2 and FS65_LORvcore_3.3
Section 12.7.8: updated description and Figure 46
Table 38: updated VCORE_1:0 description 35FS4500-35FS6500-ASILB v.1.0 01 May 2021 • Product data sheet
Initial release

NXP Semiconductors 35FS4500-35FS6500-ASILB Grade 0 safety power system basis chip with CAN FD transceiver Legal information Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL https://www.nxp.com. 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NXP Semiconductors 35FS4500-35FS6500-ASILB Grade 0 safety power system basis chip with CAN FD transceiver Tables Tab. 9. Regulators and fail-safe pins checked Tab. 10. Regulators and fail-safe pins checked Tab. 12. RELEASE_FSxB register based on LFSR Tab. 22. INIT_VREG description and configuration Tab. 24. INIT_WU1 description and configuration of Tab. 26. INIT_WU2 description and configuration of Tab. 28. INIT_INT description and configuration of Tab. 30. INIT IO_WU2 description and configuration Tab. 31. LONG_DURATION_TIMER register Tab. 32. LONG_DURATION_TIMER description and configuration of the bits (default value in Tab. 34. HW_CONFIG description and configuration Tab. 36. WU_SOURCE description and configuration of the bits (default value in Tab. 38. DEVICE_ID description and configuration Tab. 40. IO_INPUT description and configuration of Tab. 42. DIAG_VPRE description and configuration Tab. 44. DIAG_VCORE description and configuration of the bits (default value in Tab. 46. DIAG_VCCA description and configuration Tab. 48. DIAG_VAUX description and configuration Tab. 50. DIAG_VSUP_VCAN description and configuration of the bits (default value in Tab. 52. DIAG_CAN_1 description and configuration Tab. 54. DIAG_CAN_2 description and configuration Tab. 56. DIAG_SPI description and configuration of Tab. 58. Mode description and configuration of the Tab. 60. REG_MODE description and configuration Tab. 62. IO_OUT_AMUX description and configuration of the bits (default value in Tab. 64. CAN_MODE description and configuration Tab. 66. LDT_AFTER_RUN_1 description and configuration of the bits (default value in Tab. 68. LDT_AFTER_RUN_2 description and configuration of the bits (default value in Tab. 70. LDT_WAKE_UP_1 description and configuration of the bits (default value in Tab. 72. LDT_WAKE_UP_2 description and configuration of the bits (default value in 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 5 August 2024 Document feedback

NXP Semiconductors 35FS4500-35FS6500-ASILB Grade 0 safety power system basis chip with CAN FD transceiver Tab. 74. LDT_WAKE_UP_3 description and configuration of the bits (default value in Tab. 76. INIT_FS1B_TIMING. Description and configuration of the bits (Default value in Tab. 78. BIST description and configuration of the Tab. 80. INIT_SUPERVISOR description and configuration of the bits (default value in Tab. 82. INIT_FAULT description and configuration Tab. 84. INIT_FSSM description and configuration Tab. 86. INIT_SF_IMPACT description and configuration of the bits (default value in Tab. 88. WD_WINDOW description and configuration of the bits (default value in Tab. 90. LFSR description and configuration of the Tab. 92. WD_ANSWER description and configuration of the bits (default value in Tab. 94. RELEASE_FSxB description and configuration of the bits (default value in Tab. 95. SF_OUTPUT_REQUEST register Tab. 96. SF_OUTPUT_REQUEST description and configuration of the bits (default value in Tab. 98. INIT_WD_CNT description and configuration of the bits (default value in Tab. 100. DIAG_SF_IOs description and configuration of the bits (default value in Tab. 102. WD_COUNTER description and configuration of the bits (default value in Tab. 104. DIAG_SF_ERR description and configuration of the bits (default value in Tab. 105. INIT_VCORE_OVUV_IMPACT register Tab. 106. INIT_VCORE_OVUV_IMPACT description and configuration of the bits (default value Tab. 107. INIT_VCCA_OVUV_IMPACT register Tab. 108. INIT_VCCA_OVUV_IMPACT description and configuration of the bits (default value Tab. 109. INIT_VAUX_OVUV_IMPACT register Tab. 110. INIT_VAUX_OVUV_IMPACT description and configuration of the bits (default value Tab. 112. DEVICE_ID_FS description and configuration of the bits (default value in Figures Fig. 1. 35FS6500C simplified application diagram Fig. 2. 35FS4500C simplified application diagram Fig. 3. 35FS4500/35FS6500 with CAN simplified Fig. 12. Components involved under ISO pulse in Fig. 15. Windowed watchdog with FS clock Fig. 16. Watchdog error counter configuration (INIT_WD_CNT register, bits WD_CNT_ Fig. 17. Watchdog refresh counter configuration (INIT_WD_CNT register, WD_CNT_RFR_ Fig. 18. Fault error counter (FLT_ERR_FS = 0, 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 5 August 2024 Document feedback

NXP Semiconductors 35FS4500-35FS6500-ASILB Grade 0 safety power system basis chip with CAN FD transceiver Fig. 19. Fault error counter (FLT_ERR_FS = 1, Fig. 20. Example of WD operation generating a Fig. 21. Example of RTSB and FS0B behavior Fig. 22. Example of WD operation leading a decrement of the fault error counter (WD_ Fig. 23. Fault error counter and FS0B deactivation sequence (FLT_ERR_FS = 0 and WD_ Fig. 31. Buck configuration power up and power Fig. 32. Buck boost configuration power up and Fig. 33. Behavior during cranking (buck Fig. 34. Behavior during cranking (buck boost Fig. 40. Feedback core resistor bridge monitoring Fig. 44. VAUX current limitation scheme with Fig. 47. Power dissipation versus ICORE, ICCA, or Fig. 54. CAN transition when device goes to Fig. 56. Illustration of CANL short to GND detection Fig. 59. SPI overview: SPI waveform and signals Fig. 63. 35FS6500 simplified application schematic with CAN, FS1B, VKAM, buck/boost VPRE Fig. 64. 35F4500 simplified application schematic with CAN, IO_5, buck only VPRE Fig. 65. VAUX/VCCA connection, deep fail-safe Fig. 66. VAUX not used, VCCA configuration up to Fig. 67. VCCA connection, VAUX not used, deep Fig. 68. VCCA connection, VAUX not used, deep Fig. 72. SOT1571-1 Rev. F - PCB design guidelines Fig. 73. SOT1571-1 Rev. F - PCB design guidelines Fig. 74. SOT1571-1 Rev. F - PCB design guidelines 35FS4500-35FS6500-ASILB All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 3 — 5 August 2024 Document feedback

NXP Semiconductors 35FS4500-35FS6500-ASILB Grade 0 safety power system basis chip with CAN FD transceiver

12.9.2.6 Distinguish CAN diagnostics and CAN

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © 2024 NXP B.V. All rights reserved. For more information, please visit: https://www.nxp.com Document feedback Date of release: 5 August 2024 Document identifier: 35FS4500-35FS6500-ASILB

Product Information

MC35FS4505CAE specifications and overview.

Summary

Grade 0 safety power system basis chip with CAN FD transceiver Rev. 3 - 5 August 2024

Description

Grade 0 safety power system basis chip with CAN FD transceiver Rev. 3 - 5 August 2024

Source title MC35FS4505CAE Datasheet(PDF) - NXP Semiconductors

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