MC3304-BI/P

MCP3304 MICROCHIP | Alldatasheet

Document overview

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Technical content

Features

• Full Differential Inputs
• MCP3302: 2 Differential or 4 Single ended Inputs
• MCP3304: 4 Differential or 8 Single ended Inputs
• ±1 LSB max DNL
• ±1 LSB max INL (MCP3302/04-B)
• ±2 LSB max INL (MCP3302/04-C)
• Single supply operation: 2.7V to 5.5V
• 100 ksps sampling rate with 5V supply voltage
• 50 ksps sampling rate with 2.7V supply voltage
• 50 nA typical standby current, 1 µA max
• 4 5 0 µA max active current at 5V
• Industrial temp range: -40°C to +85°C
• 14 and 16-pin PDIP , SOIC and TSSOP packages
• MXDEV TM Evaluation kit available

Applications

• Remote Sensors
• Battery Operated Systems
• Transducer Interface Package Types General Description The Microchip Technology Inc. MCP3302/04 13-bit A/D converters feature full differential inputs and low power consumption in a small package that is ideal for battery powered systems and remote data acquisition applica- tions. The MCP3302 is programmable to provide two differential input pairs or four single ended inputs. The MCP3304 is programmable and provides four differen- tial input pairs or eight single ended inputs. Incorporating a successive approximation architecture with on-board sample and hold circuitry, these 13-bit A/D converters are specified to have ±1 LSB Differen- tial Nonlinearity (DNL); ±1 LSB Integral Nonlinearity (INL) for B-grade and ±2 LSB for C-grade devices. The industry-standard SPI™ serial interface enables 13-bit A/D converter capability to be added to any PICmicro microcontroller. The MCP3302/04 devices feature low current design that permits operation with typical standby and active currents of only 50 nA and 300 µA, respectively. The devices operate over a broad voltage range of 2.7V to 5.5V and are capable of conversion rates of up to 100 ksps. The reference voltage can be varied from 400 mV to 5V, yielding input-referred resolution between 98 µV and 1.22 mV. The MCP3302 is available in 14-pin PDIP , 150 mil SOIC and TSSOP packages. The MCP3304 is avail- able in 16-pin PDIP and 150 mil SOIC packages. The full differential inputs of these devices enable a wide variety of signals to be used in applications such as remote data acquisition, portable instrumentation and battery operated applications. VDD CLK DOUT MCP3302 VREF DIN CH0 CH1 CH2 CH3 CS /SHDNDGND AGND NC VDD CLK DOUT MCP3304 VREF DIN CS/SHDN DGND CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 NC AGND PDIP , SOIC, TSSOP PDIP , SOIC 13-Bit Differential Input, Low Power A/D Converter with SPI™ Serial Interface

DS21697B-page 2  2002 Microchip Technology Inc. Functional Block Diagram Comparator 13-Bit SAR CDAC Control Logic CS/SHDN VREF AGNDVDD CLK DOUT Shift Register CH0 Channel Mux InputCH1 CH7* * Channels 5-7 available on MCP3304 Only DIN & Hold Circuits Sample DGND

 2002 Microchip Technology Inc. DS21697B-page 3 MCP3302/04

1.0 ELECTRICAL

Maximum Ratings* *Notice: Stresses above those listed under “Maximum rat- ings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Expo- sure to maximum rating conditions for extended periods may affect device reliability. PIN FUNCTION TABLE Name Function CH0-CH7 Analog Inputs DGND Digital Ground CS /SHDN Chip Select / Shutdown Input DIN Serial Data In DOUT Serial Data Out CLK Serial Clock AGND Analog Ground VREF Reference Voltage Input VDD +2.7V to 5.5V Power Supply ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all parameters apply at V DD = 5V, VSS = 0V, and VREF = 5V. Full differential input configuration (Figure 3-4) with fixed common mode voltage of 2.5V. All parameters apply over temperature with TAMB = -40°C to +85°C ( Note 7). Conversion speed (FSAMPLE) is 100 ksps with FCLK = 21*FSAMPLE Parameter Symbol Min Typ Max Units Conditions Conversion Rate Maximum Sampling Frequency F SAMPLE —— 1 0 0k s p s Note 8 — — 50 ksps V DD = VREF = 2.7V, VCM =1.35V Conversion Time T CONV 13 CLK periods Acquisition Time T ACQ 1.5 CLK periods DC Accuracy Resolution 12 data bits + sign bits Integral Nonlinearity INL — ±0.5 LSB LSB MCP3302/04-B MCP3302/04-C Differential Nonlinearity DNL — ±0.5 ±1 LSB Monotonic over temperature Positive Gain Error -3 -0.75 +2 LSB Negative Gain Error -3 -0.5 +2 LSB Offset Error -3 +3 +6 LSB Note 1: This specification is established by characterization and not 100% tested. 2: See characterization graphs that relate converter performance to V REF level. 3: VIN = 0.1V to 4.9V @ 1 kHz. 4: VDD =5VP-P ±500 mV @ 1 kHz, see test circuit Figure 3-3. 5: Maximum clock frequency specification must be met. 6: VREF = 400 mV, VIN = 0.1V to 4.9V @ 1 kHz 7: TSSOP devices are only specified at 25°C and +85°C. 8: For slow sample rates, see Section 6.2.1 for limitations on clock frequency.

DS21697B-page 4  2002 Microchip Technology Inc. Dynamic Performance Total Harmonic Distortion THD — -91 — dB Note 3 Signal to Noise and Distortion SINAD — 78 — dB Note 3 Spurious Free Dynamic Range SFDR — 92 — dB Note 3 Common Mode Rejection CMRR — 79 — dB Note 6 Channel to Channel Crosstalk CT — > -110 — dB Note 6 Power Supply Rejection PSR — 74 — dB Note 4 Reference Input Voltage Range 0.4 — V DD V Note 2 Current Drain — 100 0.001 150 µA µAC S = VDD = 5V Analog Inputs Full Scale Input Span CH0 - CH7 -V REF —V REF V Leakage Current — 0.001 ±1 µA Switch Resistance R S —1 — k Ω See Figure 6-3 Sample Capacitor C SAMPLE — 25 — pF See Figure 6-3 Digital Input/Output Data Coding Format Binary Two’s Complement High Level Input Voltage V IH 0.7 VDD —— V Low Level Input Voltage V IL —— 0 . 3 V DD V High Level Output Voltage V OH 4.1 — — V I OH = -1 mA, VDD = 4.5V Low Level Output Voltage V OL —— 0 . 4 V I OL = 1 mA, VDD = 4.5V Input Leakage Current I LI -10 — 10 µAV IN = VSS or VDD Output Leakage Current I LO -10 — 10 µAV OUT = VSS or VDD Pin Capacitance C IN, COUT —— 1 0 p F T AMB = 25°C, F = 1 MHz, Note 1 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at V DD = 5V, VSS = 0V, and VREF = 5V. Full differential input configuration (Figure 3-4) with fixed common mode voltage of 2.5V. All parameters apply over temperature with TAMB = -40°C to +85°C ( Note 7). Conversion speed (FSAMPLE) is 100 ksps with FCLK = 21*FSAMPLE Parameter Symbol Min Typ Max Units Conditions Note 1: This specification is established by characterization and not 100% tested. 2: See characterization graphs that relate converter performance to V REF level. 3: VIN = 0.1V to 4.9V @ 1 kHz. 4: VDD =5VP-P ±500 mV @ 1 kHz, see test circuit Figure 3-3. 5: Maximum clock frequency specification must be met. 6: VREF = 400 mV, VIN = 0.1V to 4.9V @ 1 kHz 7: TSSOP devices are only specified at 25°C and +85°C. 8: For slow sample rates, see Section 6.2.1 for limitations on clock frequency.

 2002 Microchip Technology Inc. DS21697B-page 5 MCP3302/04 Timing Specifications: Clock Frequency (Note 8) FCLK 0.105 0.105 2.1 1.05 MHz MHz VDD = 5V, FSAMPLE = 100 ksps VDD = 2.7V, FSAMPLE = 50 ksps Clock High Time T HI 210 — — ns Note 5 Clock Low Time T LO 210 — — ns Note 5 CS Fall To First Rising CLK Edge T SUCS 100 — — ns Data In Setup time T SU 50 — — ns Data In Hold Time T HD —— 5 0 n s CLK Fall To Output Data Valid T DO —— 1 2 5 200 ns ns VDD = 5V, see Figure 3-1 VDD = 2.7V, see Figure 3-1 CLK Fall To Output Enable T EN —— 1 2 5 200 ns ns VDD = 5V, see Figure 3-1 VDD = 2.7V, see Figure 3-1 CS Rise To Output Disable T DIS — — 100 ns See test circuits, Figure 3-1 Note 1 CS Disable Time T CSH 475 — — ns DOUT Rise Time T R — — 100 ns See test circuits, Figure 3-1 Note 1 DOUT Fall Time T F — — 100 ns See test circuits, Figure 3-1 Note 1 Power Requirements: Operating Voltage V DD 2.7 — 5.5 V Operating Current I DD — 300 200 450 µAV DD, VREF = 5V, DOUT unloaded VDD, VREF = 2.7V, DOUT unloaded Standby Current I DDS —0 . 0 5 1 µAC S = VDD = 5.0V Temperature Ranges: Specified Temperature Range T A -40 — +85 °C Operating Temperature Range T A -40 — +85 °C Storage Temperature Range T A -65 — +150 °C Thermal Package Resistance: Thermal Resistance, 14L-PDIP θ JA —7 0 — ° C / W Thermal Resistance, 14L-SOIC θJA —1 0 8 — ° C / W Thermal Resistance, 14L-TSSOP θJA —1 0 0 — ° C / W Thermal Resistance, 16L-PDIP θJA —7 0 — ° C / W Thermal Resistance, 16L-SOIC θJA —9 0 — ° C / W ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at V DD = 5V, VSS = 0V, and VREF = 5V. Full differential input configuration (Figure 3-4) with fixed common mode voltage of 2.5V. All parameters apply over temperature with TAMB = -40°C to +85°C ( Note 7). Conversion speed (FSAMPLE) is 100 ksps with FCLK = 21*FSAMPLE Parameter Symbol Min Typ Max Units Conditions Note 1: This specification is established by characterization and not 100% tested. 2: See characterization graphs that relate converter performance to V REF level. 3: VIN = 0.1V to 4.9V @ 1 kHz. 4: VDD =5VP-P ±500 mV @ 1 kHz, see test circuit Figure 3-3. 5: Maximum clock frequency specification must be met. 6: VREF = 400 mV, VIN = 0.1V to 4.9V @ 1 kHz 7: TSSOP devices are only specified at 25°C and +85°C. 8: For slow sample rates, see Section 6.2.1 for limitations on clock frequency.

DS21697B-page 6  2002 Microchip Technology Inc. FIGURE 1-1: Timing Parameters CS CLK DIN MSB IN TSU THD TSUCS TCSH THI TLO DOUT TEN TDO TR LSBSign BIT TDIS Null Bit TF

 2002 Microchip Technology Inc. DS21697B-page 7 MCP3302/04

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, V DD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 21*FSAMPLE, TA = 25°C. FIGURE 2-1: Integral Nonlinearity (INL) vs. Sample Rate FIGURE 2-2: Integral Nonlinearity (INL) vs. VREF. FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part). FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V) FIGURE 2-5: Integral Nonlinearity (INL) vs. VREF (VDD = 2.7V) FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, V DD = 2.7V). Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 0 50 100 150 200 Sample Rate (ksps) INL (LSB) Positive INL Negative INL -1.5 -0.5 0.5 1.5 012345 VREF(V) INL (LSB) Positive INL Negative INL -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 -4096 -3072 -2048 -1024 0 1024 2048 3072 4096 Code INL (LSB) -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 0 1 02 03 04 05 06 07 0 Sample Rate (ksps) INL (LSB) Negative INL Positive INL VDD=VREF=2.7V -1.5 -0.5 0.5 1.5 00 . 511 . 522 . 53 VREF(V) INL(LSB) Positive INL Negative INL VDD = 2.7V -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 -4096 -3072 -2048 -1024 0 1024 2048 3072 4096 Code INL (LSB) VDD=VREF=2.7V FSAMPLE = 50 ksps

DS21697B-page 14  2002 Microchip Technology Inc.

3.0 TEST CIRCUITS

FIGURE 3-1: Load Circuit for TR, TF, TDO. FIGURE 3-2: Load circuit for TDIS and TEN. FIGURE 3-3: Power Supply Sensitivity Test Circuit (PSRR). FIGURE 3-4: Full Differential Test Configuration Example. FIGURE 3-5: Pseudo Differential Test Configuration Example. Test Point 1.4V DOUT 3k Ω CL = 100 pF MCP330X *Waveform 1 is for an output with internal con- ditions such that the output is high, unless dis- abled by the output control. †Waveform 2 is for an output with internal con- ditions such that the output is low, unless dis- abled by the output control. Test Point DOUT 3k Ω 100 pF TDIS Waveform 2 TDIS Waveform 1 TEN Waveform VDD VDD/2 VSS VIH TDIS CS DOUT Waveform 1* DOUT Waveform 2† 90% 10% Voltage Waveforms for TDIS MCP330X 2.63V 1k Ω 5V ±500 mVP-P 5VP-P 1k Ω 20 kΩ To VDD on DUT 1k Ω 1/2 MCP602 VDD = 5V 0.1 µF IN(+) IN(-) MCP330X 5VP-P VREF = 5V 5VP-P VCM = 2.5V 1µ F 0.1 µF VREF VDD VSS 0.1µF IN(+) IN(-) MCP330X VDD = 5V VCM = 2.5V 5VP-P VREF = 2.5V 1µF 0.1µF VREF VDD VSS

 2002 Microchip Technology Inc. DS21697B-page 15 MCP3302/04

4.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 4-1. TABLE 4-1: PIN FUNCTION TABLE

4.1 CH0-CH7

Analog input channels. These pins have an absolute voltage range of VSS - 0.3V to VDD + 0.3V. The full scale differential input range is defined as the absolute value of (IN+) - (IN-). This difference can not exceed the value of V REF - 1 LSB or digital code saturation will occur.

4.2 DGND

Ground connection to internal digital circuitry. T o ensure accuracy this pin must be connected to the same ground as AGND. If an analog ground plane is available, it is recommended that this device be tied to the analog ground plane in the circuit. See Section 6.6 for more information regarding circuit layout.

4.3 Chip Select /Shutdown (CS/SHDN)

The CS /SHDN pin is used to initiate communication with the device when pulled low. This pin will end a con- version and put the device in low power standby when pulled high. The CS /SHDN pin must be pulled high between conversions and cannot be tied low for multi- ple conversions. See Figure 7-2 for serial communica- tion protocol.

4.4 Serial Data Input (D IN)

The SPI port serial data input pin is used to clock in input channel configuration data. Data is latched on the rising edge of the clock. See Figure 7-2 for serial com- munication protocol.

4.5 Serial Data Output (D OUT)

The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place. See Figure 7-2 for serial communication protocol.

4.6 Serial Clock (CLK)

The SPI clock pin is used to initiate a conversion and to clock out each bit of the conversion as it takes place. See Section 6.2 for constraints on clock speed. See Figure 7-2 for serial communication protocol.

4.7 AGND

Ground connection to internal analog circuitry. To ensure accuracy, this pin must be connected to the same ground as DGND. If an analog ground plane is available, it is recommended that this device be tied to the analog ground plane in the circuit. See Section 6.6 for more information regarding circuit layout.

4.8 Voltage Reference (V REF)

This input pin provides the reference voltage for the device, which determines the maximum range of the analog input signal and the LSB size. The LSB size is determined according to the equation shown below. As the reference input is reduced, the LSB size is reduced accordingly. EQUATION When using an external voltage reference device, the system designer should always refer to the manufac- turer’s recommendations for circuit layout. Any instabil- ity in the operation of the reference device will have a direct effect on the accuracy of the ADC conversion results.

4.9 V DD

The voltage on this pin can range from 2.7 to 5.5V. To ensure accuracy, a 0.1 µF ceramic bypass capacitor should be placed as close as possible to the pin. See Section 6.6 for more information regarding circuit lay- out. Name Function CH0-CH7 Analog Inputs DGND Digital Ground CS /SHDN Chip Select / Shutdown Input DIN Serial Data In DOUT Serial Data Out CLK Serial Clock AGND Analog Ground V REF Reference Voltage Input VDD +2.7V to 5.5V Power Supply LSB Size = 2 x VREF 8192

DS21697B-page 16  2002 Microchip Technology Inc.

5.0 DEFINITION OF TERMS

Bipolar Operation - This applies to either a differential or single ended input configuration, where both positive and negative codes are output from the A/D converter. Full bipolar range includes all 8192 codes. For bipolar operation on a single ended input signal, the A/D con- verter must be configured to operate in pseudo differ- ential mode. Unipolar Operation - This applies to either a single ended or differential input signal where only one side of the device transfer is being used. This could be either the positive or negative side, depending on which input (IN+ or IN-) is being used for the DC bias. Full unipolar operation is equivalent to a 12-bit converter. Full Differential Operation - Applying a full differential signal to both the IN(+) and IN(-) inputs is referred to as full differential operation . This configuration is described in Figure 3-4. Pseudo-Differential Operation - Applying a single ended signal to only one of the input channels with a bipolar output is referred to as pseudo differential oper- ation. T o obtain a bipolar output from a single ended input signal the inverting input of the A/D converter must be biased above V SS. This operation is described in Figure 3-5. Integral Nonlinearity - The maximum deviation from a straight line passing through the endpoints of the bipo- lar transfer function is defined as the maximum integral nonlinearity error. The endpoints of the transfer func- tion are a point 1/2 LSB above the first code transition (0x1000) and 1/2 LSB below the last code transition (0x0FFF). Differential Nonlinearity - The difference between two measured adjacent code transitions and the 1 LSB ideal is defined as differential nonlinearity. Positive Gain Error - This is the deviation between the last positive code transition (0x0FFF) and the ideal volt- age level of V REF-1/2 LSB, after the bipolar offset error has been adjusted out. Negative Gain Error - This is the deviation between the last negative code transition (0X1000) and the ideal voltage level of -V REF-1/2 LSB, after the bipolar offset error has been adjusted out. Offset Error - This is the deviation between the first positive code transition (0x0001) and the ideal 1/2 LSB voltage level. Acquisition Time - The acquisition time is defined as the time during which the internal sample capacitor is charging. This occurs for 1.5 clock cycles of the exter- nal CLK as defined in Figure 7-2. Conversion Time - The conversion time occurs imme- diately after the acquisition time. During this time, suc- cessive approximation of the input signal occurs as the 13-bit result is being calculated by the internal circuitry. This occurs for 13 clock cycles of the external CLK as defined in Figure 7-2. Signal to Noise Ratio - Signal to Noise Ratio (SNR) is defined as the ratio of the signal to noise measured at the output of the converter. The signal is defined as the rms amplitude of the fundamental frequency of the input signal. The noise value is dependant on the device noise as well as the quantization error of the converter and is directly affected by the number of bits in the converter. The theoretical signal to noise ratio limit based on quantization error only for an N-bit con- verter is defined as: EQUATION For a 13-bit converter, the theoretical SNR limit is 80.02 dB. Total Harmonic Distortion - Total Harmonic Distortion (THD) is the ratio of the rms sum of the harmonics to the fundamental, measured at the output of the con- verter. For the MCP3302/04, it is defined using the first 9 harmonics, as is shown in the following equation: EQUATION Here V1 is the rms amplitude of the fundamental and V2 through V 9 are the rms amplitudes of the second through ninth harmonics. Signal to Noise plus Distortion (SINAD) - Numeri- cally defined, SINAD is the calculated combination of SNR and THD. This number represents the dynamic performance of the converter, including any harmonic distortion. EQUATION EffectIve Number of Bits - Effective Number of Bits (ENOB) states the relative performance of the ADC in terms of its resolution. This term is directly related to SINAD by the following equation: EQUATION For SINAD performance of 78 dB, the effective number of bits is 12.66. Spurious Free Dynamic Range - Spurious Free Dynamic Range (SFDR) is the ratio of the rms value of the fundamental to the next largest component in ADC’s output spectrum. This is, typically, the first har- monic, but could also be a noise peak. SNR 6.02N 1.76 +() dB= THD(-dB) 20 log– V2 2 V3 +++ ++ SINAD(dB) 20 log 10 SNR 10⁄() 10 THD 10⁄()–+= ENOB N() SINAD 1.76–

 2002 Microchip Technology Inc. DS21697B-page 17 MCP3302/04

6.0 APPLICATIONS INFORMATION

6.1 Conversion Description

The MCP3302/04 A/D converters employ a conven- tional SAR architecture. With this architecture, the potential between the IN+ and IN- inputs are simulta- neously sampled and stored with the internal sample circuits for 1.5 clock cycles. Following this sampling time, the input hold switches of the converter open and the device uses the collected charge to produce a serial 13-bit binary two’s complement output code. This conversion process is driven by the external clock and must include 13 clock cycles, one for each bit. During this process, the most significant bit (MSB) is output first. This bit is the sign bit and indicates if the IN+ or IN- input is at a higher potential. FIGURE 6-1: Simplified Block Diagram.

6.2 Driving the Analog Input

The analog input of the MCP3302/04 is easily driven, either differentially or single ended. Any signal that is common to the two input channels will be rejected by the common mode rejection of the device. During the charging time of the sample capacitor, a small charging current will be required. For low source impedances, this input can be driven directly. For larger source impedances, a larger acquisition time will be required due to the RC time constant that includes the source impedance. For the A/D Converter to meet specifica- tion, the charge holding capacitor (C SAMPLE) must be given enough time to acquire a 13-bit accurate voltage level during the 1.5 clock cycle acquisition period. An analog input model is shown in Figure 6-3. This model is accurate for an analog input, regardless if it is configured as a single ended input, or the IN+ and IN- input in differential mode. In this diagram, it is shown that the source impedance (R S) adds to the internal sampling switch (RSS) impedance, directly affecting the time that is required to charge the capacitor (CSAMPLE). Consequently, a larger source impedance with no addi- tional acquisition time increases the offset, gain and integral linearity errors of the conversion. To overcome this, a slower clock speed can be used to allow for the longer charging time. Figure 6-2 shows the maximum clock speed associated with source impedances. FIGURE 6-2: Maximum Clock Frequency vs. Source Resistance (R S) to maintain ±1 LSB INL. Comp 13-Bit SAR CDAC IN+ IN- Shift Register CSAMP Hold Hold CSAMP DOUT 0.0 0.5 1.0 1.5 2.0 2.5 100 1000 10000 100000 Source Resistance (ohms) Maximum Clock Frequency (MHz)

DS21697B-page 18  2002 Microchip Technology Inc. FIGURE 6-3: Analog Input Model.

6.2.1 MAINTAINING MINIMUM CLOCK

When the MCP3302/04 initiates, charge is stored on the sample capacitor. When the sample period is com- plete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample cap while the conversion is taking place. For the MCP330X devices, the recommended minimum clock speed dur- ing the conversion cycle (T CONV) is 105 kHz. Failure to meet this criteria may induce linearity errors into the conversion outside the rated specifications. It should be noted that during the entire conversion cycle, the A/D converter does not have requirements for clock speed or duty cycle, as long as all timing specifications are met.

6.3 Biasing Solutions

For pseudo-differential bipolar operation, the biasing circuit (shown in Figure 6-4) shows a single ended input AC coupled to the converter. This configuration will give a digital output range of -4096 to +4095. With the 2.5V reference, the LSB size equal to 610 µV. Although the ADC is not production tested with a 2.5V reference as shown, linearity will not change more than 0.1 LSB. See Figure 2-2 and Figure 2-9 for DNL and INL errors versus V REF at VDD = 5V. A trade-off exists between the high pass corner and the acquisition time. The value of C will need to be quite large in order to bring down the high pass corner. The value of R will need to be 1 kΩ , or less, since higher input impedances require additional acquisition time. Using the RC values in Figure 6-4, we have a 100 Hz corner frequency. See Figure 2-12 for relation between input impedance and acquisition time. FIGURE 6-4: Pseudo-differential biasing circuit for bipolar operation. Using an external operation amplifier on the input allows for gain and also buffers the input signal from the input to the ADC allowing for a higher source imped- ance. This circuit is shown in Figure 6-5. CPINVA RSS CHx 7p F VT = 0.6V VT = 0.6V ILEAKAGE Sampling Switch SS RS = 1 kΩ CSAMPLE = DAC capacitance VSS VDD = 25 pF±1 nA Legend VA = signal source RSS = source impedance CHx = input channel pad CPIN = input pin capacitance VT = threshold voltage ILEAKAGE = leakage current at the pin due to various junctions SS = sampling switch RS = sampling switch resistor CSAMPLE = sample/hold capacitance VDD = 5V 0.1 µF IN+ IN- VREF MCP330X 1µ F MCP1525 VINVOUT 0.1 µF 1k Ω 10 µF VIN R C

 2002 Microchip Technology Inc. DS21697B-page 19 MCP3302/04 FIGURE 6-5: Adding an amplifier allows for gain and also buffers the input from any high impedance sources. This circuit shows that some headroom w ill be lost due to the amplifier output not being able to swing all the way to the rail. An example would be for an output swing of 0V to 5V. This limitation can be overcome by supplying a V REF that is slightly less than the common mode voltage. Using a 2.048V reference for the A/D converter while biasing the input signal at 2.5V solves the problem. This circuit is shown in Figure 6-5. FIGURE 6-6: Circuit solution to overcome amplifier output swing limitation.

6.4 Common Mode Input Range

The common mode input range has no restriction and is equal to the absolute input voltage range: V SS -0.3V to VDD + 0.3V. However, for a given V REF, the common mode voltage has a limited swing, if the entire range of the A/D converter is to be used. Figure 6-7 and Figure 6-8 show the relationship between VREF and the common mode voltage swing. A smaller VREF allows for wider flexibility in a common mode voltage. VREF levels, down to 400 mv, exhibit less than 0.1 LSB change in DNL and INL. For characterization graphs that show this performance relationship, see Figure 2-9 and Figure 2-12. FIGURE 6-7: Common Mode Input Range of Full Differential Input Signal versus V REF. FIGURE 6-8: Common Mode Input Range versus VREF for Pseudo Differential Input. VDD = 5V 0.1 µF MCP6021 IN+ IN- VREF MCP330X 1 µF MCP1525 VINVOUT 1k Ω 10 kΩ 1M Ω 1 µF VIN 0.1 µF 1M Ω 2.048V VDD = 5V 0.1 µF MCP606 IN+ IN- VREF MCP330X 1µ F MCP1525 VINVOUT 0.1 µF 1k Ω 10 kΩ 1µ F VIN 10 kΩ VREF (V) 0.25 VDD = 5V 5.01.0 2.5 4.0 4.05V 2.8V 2.3V 0.95V Common Mode Range (V) VREF (V) 0.25 VDD = 5V 2.50.5 1.25 2.0 4.05V 2.8V 2.3V 0.95V Common Mode Range (V)

DS21697B-page 20  2002 Microchip Technology Inc.

6.5 Buffering/Filtering the Analog

Inaccurate conversion results may occur if the signal source for the A/D converter is not a low impedance source. Buffering the input will overcome the imped- ance issue. It is also recommended that an analog filter be used to eliminate any signals that may be aliased back into the conversion results. This is illustrated in Figure 6-9, where an op amp is used to drive the ana- log input of the MCP3302/04. This amplifier provides a low impedance source for the converter input and a low pass filter, which eliminates unwanted high frequency noise. Values shown are for a 10 Hz Butterworth Low Pass filter. Low pass (anti-aliasing) filters can be designed using Microchip’s interactive FilterLab ® software. FilterLab will calculate capacitor and resistor values, as well as determine the number of poles that are required for the application. For more information on filtering signals, see Application Note 699 “Anti-Aliasing Analog Filters for Data Acquisition Systems ”. FIGURE 6-9: The MCP601 Operational Amplifier is used to implement a 2nd order anti- aliasing filter for the signal being converted by the MCP3302/04.

6.6 Layout Considerations

When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor from V DD to ground should always be used with this device and should be placed as close as possible to the device pin. A bypass capacitor value of 0.1 µF is recommended. Digital and analog traces on the board should be sepa- rated as much as possible, with no traces running underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with high frequency signals (such as clock lines) as far as possi- ble from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing V DD connections to devices in a “star” configuration can also reduce noise by eliminating current return paths and associated errors (see Figure 6-10). For more information on lay- out tips when using the MCP3302/04, or other ADC devices, refer to Application Note 688, “Layout Tips for 12-Bit A/D Converter Applications”. FIGURE 6-10: VDD traces arranged in a ‘Star’ configuration in order to reduce errors caused by current return paths. MCP330X VDD 10 µF IN- IN+ +VIN 2.2 µF 1µ F VREF 4.096V Reference 0.1 µF 1µ F0.1 µF MCP6017.86 kΩ 14.6 kΩ MCP1541 CL VDD Connection Device 1 Device 2 Device 3 Device 4

 2002 Microchip Technology Inc. DS21697B-page 21 MCP3302/04

6.7 Utilizing the Digital and Analog

The MCP3302/04 devices provide both digital and ana- log ground connections to provide another means of noise reduction. As shown in Figure 6-11, the analog and digital circuitry are separated internal to the device. This reduces noise from the digital portion of the device being coupled into the analog portion of the device. The two grounds are connected internally through the sub- strate which has a resistance of 5 -10 Ω . If no ground plane is utilized, then both grounds must be connected to V SS on the board. If a ground plane is available, both digital and analog ground pins should be connected to the analog ground plane. If both an analog and a digital ground plane are available, both the digital and the analog ground pins should be con- nected to the analog ground plane, as shown in Figure 6-11. Following these steps will reduce the amount of digital noise from the rest of the board being coupled into the A/D Converter. FIGURE 6-11: Separation of Analog and Digital Ground Pins. MCP3302/04 Analog Ground Plane DGND AGND VDD 0.1 µF Substrate 5 - 10 Ω Digital Side -SPI Interface -Shift Register -Control Logic Analog Side -Sample Cap -Capacitor Array -Comparator

DS21697B-page 22  2002 Microchip Technology Inc.

7.0 SERIAL COMMUNICATIONS

7.1 Output Code Format

The output code format is a binary two’s complement scheme, with a leading sign bit that indicates the sign of the output. If the IN+ input is higher than the IN- input, the sign bit will be a zero. If the IN- input is higher, the sign bit will be a ‘1’. The diagram shown in Figure 7-1 shows the output code transfer function. In this diagram, the horizontal axis is the analog input voltage and the vertical axis is the output code of the ADC. It shows that when IN+ is equal to IN-, both the sign bit and the data word is zero. As IN+ gets larger with respect to IN-, the sign bit is a zero and the data word gets larger. The full scale output code is reached at +4095 when the input [(IN+) - (IN-)] reaches V REF - 1 LSB. When IN- is larger than IN+, the two’s complement output codes will be seen with the sign bit being a one. Some examples of analog input levels and corresponding output codes are shown in Table 7-1. TABLE 7-1: BINARY TWO’S COMPLEMENT OUTPUT CODE EXAMPLES. FIGURE 7-1: Output Code Transfer Function. Analog Input Levels Sign Bit Binary Data Decimal DATA Full Scale Positive (IN+)-(IN-)=VREF-1 LSB 0 1111 1111 1111+4095 (IN+)-(IN-) = VREF-2 LSB 0 1111 1111 1110+4094 IN+ = (IN-) +2 LSB 0 0000 0000 0010+2 IN+ = (IN-) +1 LSB 0 0000 0000 0001+1 IN+ = IN- 0 0000 0000 00000 IN+ = (IN-) - 1 LSB 1 1111 1111 1111-1 IN+ = (IN-) - 2 LSB 1 1111 1111 1110-2 (IN+)-(IN-) = VREF-2 LSB 1 0000 0000 0001-4095 Full Scale Negative (IN+)-(IN-) = VREF-1 LSB 1 0000 0000 0000-4096 IN+ > IN- IN+ < IN- 0 + 0000 0000 0001 (+1) 0 + 0000 0000 0010 (+2) 0 + 0000 0000 0011 (+3) 1 + 1111 1111 1101 (-3) 1 + 1111 1111 1110 (-2) 1 + 1111 1111 1111 (-1) 0 + 1111 1111 1110 (+4094) 0 + 1111 1111 1111 (+4095) 1 + 0000 0000 0000 (-4096) 1 + 0000 0000 0001 (-4095) Output Code 0 + 0000 0000 0000 (0) VREF-VREF Positive Full Scale Output = VREF -1 LSB Negative Full Scale Output = -VREF Analog Input IN+ - IN- Voltage

 2002 Microchip Technology Inc. DS21697B-page 23 MCP3302/04

7.2 Communicating with the MCP3302

Communication with the MCP3302/04 devices is done using a standard SPI-compatible serial interface. Initi- ating communication with either device is done by bringing the CS line low (see Figure 7-2). If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The first clock received with CS low and DIN high will constitute a start bit. The SGL/DIFF bit follows the start bit and will determine if the conversion will be done using single ended or differential input mode. Each channel in single ended mode will operate as a 12-bit converter with a unipolar output. No negative codes will be output in single ended mode. The next three bits (D0, D1 and D2) are used to select the input channel configuration. Table 7-2 and Table 7-3 show the configuration bits for the MCP3302 and MCP3304, respectively. The device will begin to sample the analog input on the fourth rising edge of the clock after the start bit has been received. The sample period will end on the falling edge of the fifth clock following the start bit. After the D0 bit is input, one more clock is required to complete the sample and hold period (D IN is a “don’t care” for this clock). On the falling edge of the next clock, the device will output a low null bit. The next 13 clocks will output the result of the conversion with the sign bit first, followed by the 12 remaining data bits, as shown in Figure 7-2. Note that if the device is operating in the single ended mode, the sign bit will always be transmitted as a ‘ 0’. Data is always output from the device on the falling edge of the clock. If all 13 data bits have been transmitted, and the device continues to receive clocks while the CS is held low, the device will output the conversion result, LSB, first, as shown in Figure 7-3. If more clocks are provided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. If necessary, it is possible to bring CS low and clock in leading zeros on the DIN line before the start bit. This is often done when dealing with microcontroller-based SPI ports that must send 8 bits at a time. Refer to Section 7.3 for more details on using the MCP3302/04 devices with hardware SPI ports TABLE 7-2: CONFIGURATION BITS FOR THE MCP3302 TABLE 7-3: CONFIGURATION BITS FOR THE MCP3304 Control Bit Selections Input Configuration Channel SelectionSingle /Diff D2* D1 D0

1 X 0 0 single ended CH0

1 X 0 1 single ended CH1

1 X 1 0 single ended CH2

1 X 1 1 single ended CH3

0 X 0 0 differential CH0 = IN+

CH1 = IN-

0 X 0 1 differential CH0 = IN-

CH1 = IN+

0 X 1 0 differential CH2 = IN+

CH3 = IN-

0 X 1 1 differential CH2 = IN-

CH3 = IN+ *D2 is don’t care for MCP3302 Control Bit Selections Input Configuration Channel SelectionSinglE /Diff D2 D1 D0 1 0 0 0 single ended CH0 1 0 0 1 single ended CH1 1 0 1 0 single ended CH2 1 0 1 1 single ended CH3 1 1 0 0 single ended CH4 1 1 0 1 single ended CH5 1 1 1 0 single ended CH6 1 1 1 1 single ended CH7 0 0 0 0 differential CH0 = IN+ CH1 = IN- 0 0 0 1 differential CH0 = IN- CH1 = IN+ 0 0 1 0 differential CH2 = IN+ CH3 = IN- 0 0 1 1 differential CH2 = IN- CH3 = IN+ 0 1 0 0 differential CH4 = IN+ CH5 = IN- 0 1 0 1 differential CH4 = IN- CH5 = IN+ 0 1 1 0 differential CH6 = IN+ CH7 = IN- 0 1 1 1 differential CH6 = IN- CH7 = IN+

 2002 Microchip Technology Inc. DS21697B-page 25 MCP3302/04

7.3 Using the MCP3302/04 with

Microcontroller (MCU) SPI Ports With most microcontroller SPI ports, it is required to send groups of eight bits. It is also required that the microcontroller SPI port be configured to clock out data on the falling edge of clock and latch data in on the ris- ing edge. Because communication with the MCP3302 and MCP3304 devices may not need multiples of eight clocks, it will be necessary to provide more clocks than are required. This is usually done by sending ‘leading zeros’ before the start bit. For example, Figure 7-4 and Figure 7-5 show how the MCP3302/04 devices can be interfaced to a MCU with a hardware SPI port. Figure 7-4 depicts the operation shown in SPI Mode 0,0, which requires that the SCLK from the MCU idles in the ‘low’ state, while Figure 7-5 shows the similar case of SPI Mode 1,1, where the clock idles in the ‘high’ state. As shown in Figure 7-4, the first byte transmitted to the A/D Converter contains 6 leading zeros before the start bit. Arranging the leading zeros this way produces the 13 data bits to fall in positions easily manipulated by the MCU. The sign bit is clocked out of the A/D Converter on the falling edge of clock number 11, followed by the remaining data bits (MSB first). After the second eight clocks have been sent to the device, the MCU receive buffer will contain 2 unknown bits (the output is at high impedance for the first two clocks), the null bit, the sign bit and the 4 highest order bits of the conversion. After the third byte has been sent to the device, the receive register will contain the lowest order eight bits of the conversion results. Easier manipulation of the con- verted data can be obtained by using this method. Figure 7-5 shows the same situation in SPI Mode 1,1, which requires that the clock idles in the high state. As with mode 0,0, the A/D Converter outputs data on the falling edge of the clock and the MCU latches data from the A/D Converter in on the rising edge of the clock.

DS21697B-page 26  2002 Microchip Technology Inc. FIGURE 7-4: SPI Communication with the MCP3302/04 using 8-bit segments (Mode 0,0: SCLK idles low). FIGURE 7-5: SPI Communication with the MCP3302/04 using 8-bit segments (Mode 1,1: SCLK idles high). 1 2 3 4 5 6 7 8 91 01 11 21 31 41 5 16 CS SCLK DIN X = Don’t Care Bits 17 18 19 20 21 22 23 24 DOUT NULL BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0HI-Z MCU latches data from A/D Converter Data is clocked out of A/D Converter on falling edges on rising edges of SCLK Don’t CareSGL/DIFF D0D1Start

00001 X X XXXDO XX XXXXXX

(Null) MCU Transmitted Data (Aligned with falling edge of clock) MCU Received Data (Aligned with rising edge of clock) X Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits Data stored into MCU receive register after transmission of last 8 bits X SB SB ? = Unknown Bits? = Unknown Bits 123 4 567 8 9 10 11 12 13 14 15 16 CS SCLK DIN 17 18 19 20 21 22 23 24 DOUT Don’t Care NULL BIT B11 B10 B9 B8 B6 B5 B4 B3 B2 B1 B0HI-Z

00001 XXXXX DO

MCU latches data from A/D Converter on rising edges of SCLK Data is clocked out of A/D Converter on falling edges D1D2SGL/ DIFF Start Bit (Null) D0D1Start MCU Transmitted Data (Aligned with falling edge of clock) MCU Received Data (Aligned with rising edge of clock) X Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits Data stored into MCU receive register after transmission of last 8 bits SB X SB D2 Don’t Care X = Don’t Care Bits ? = Unknown Bits

 2002 Microchip Technology Inc. DS21697B-page 27 MCP3302/04

8.0 PACKAGING INFORMATION

8.1 Package Marking Information

Legend: XX...X Customer specific information* YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. 14-Lead PDIP (300 mil) Example: 14-Lead SOIC (150 mil) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN XXXXXXXXXXX YYWWNNN MCP3302-B I/P 0125NNN XXXXXXXXXXX MCP3302-B 0YWWNNN XXXXXXXXXXX XXXXXXXX NNN YYWW 14-Lead TSSOP (4.4mm) † Example: 3302-C NNN IYWW †Please contact Microchip Factory for B-Grade TSSOP devices

DS21697B-page 28  2002 Microchip Technology Inc. Package Marking Information (Continued) 16-Lead PDIP (300 mil) (MCP3304) Example: 16-Lead SOIC (150 mil) (MCP3304) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN XXXXXXXXXXXXX YYWWNNN Legend: XX...X Customer specific information* YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard marking consists of Microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. MCP3304-B I/P YYWWNNN XXXXXXXXXXXXX MCP3304-B IYWWNNN XXXXXXXXXX

 2002 Microchip Technology Inc. DS21697B-page 29 MCP3302/04 14-Lead Plastic Dual In-line (P) – 300 mil (PDIP) n D eB β E c A B L p α Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 14 14 Pitch p .100 2.54 Base to Seating Plane A1 .015 0.38 Mold Draft Angle Top α 5 10 15 5 10 15 β 5 10 15 5 10 15 Mold Draft Angle Bottom * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 § Significant Characteristic

DS21697B-page 30  2002 Microchip Technology Inc. 14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC) Foot Angle φ 048048 1512015120βMold Draft Angle Bottom 1512015120αMold Draft Angle Top 1.27.050pPitch 1414nNumber of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units D p nB E h L c β 45° φ α A2A * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 § Significant Characteristic

 2002 Microchip Technology Inc. DS21697B-page 31 MCP3302/04 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) 840840φFoot Angle 10501050βMold Draft Angle Bottom 10501050αMold Draft Angle Top 1.10.043AOverall Height 0.65.026pPitch 1414nNumber of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERS*INCHESUnits Lβ c φ D n B p E α A2A1 A * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-087 § Significant Characteristic

DS21697B-page 32  2002 Microchip Technology Inc. 16-Lead Plastic Dual In-line (P) – 300 mil (PDIP) 1510515105βMold Draft Angle Bottom 1510515105αMold Draft Angle Top 0.38.015A1Base to Seating Plane 2.54.100pPitch 1616nNumber of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units D n c β eB E α p L B A * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-017 § Significant Characteristic

 2002 Microchip Technology Inc. DS21697B-page 33 MCP3302/04 16-Lead Plastic Small Outline (SL) – Narrow 150 mil (SOIC) Foot Angle φ 048048 1512015120βMold Draft Angle Bottom 1512015120αMold Draft Angle Top 1.27.050pPitch 1616nNumber of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units α L h nB 45° E p D φ β c A * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-108 § Significant Characteristic

DS21697B-page 34  2002 Microchip Technology Inc. NOTES:

 2002 Microchip Technology Inc. DS21697B-page 35 MCP3302/04 Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. T o view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site. Connecting to the Microchip Internet Web Site The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP ser- vice to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development T ools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A vari- ety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is:

• Latest Microchip Press Releases
• T echnical Support Section with Frequently Asked Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to Microchip Products
• Conferences for products, Development Systems, technical information and more
• Listing of seminars and events 013001

DS21697B-page 36  2002 Microchip Technology Inc. READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? To : T echnical Publications Manager RE: Reader Response Total Pages Sent From: Name Company Address City / State / ZIP / Country Application (optional): Would you like a reply? Y N Device: Literature Number: Questions: DS21697BMCP3302/04

 2002 Microchip Technology Inc. DS21697B-page37 MCP3302/04 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. T o determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. Device: MCP3302: 13-Bit Serial A/D Converter MCP3302T: 13-Bit Serial A/D Converter (Tape and Reel) MCP3304: 13-Bit Serial A/D Converter MCP3304T: 13-Bit Serial A/D Converter (Tape and Reel) Grade: B = ±1 LSB INL C= ± 2 L S B I N L Temperature Range: I = -40°C to +85°C Package: P = Plastic DIP (300 mil Body), 14-lead, 16-lead SL = Plastic SOIC (150 mil Body), 14-lead, 16-lead ST = Plastic TSSOP (4.4mm), 14-lead Examples: a) MCP3302-BI/P: ±1 LSB INL, Industrial Tem- perature, PDIP package b) MCP3302-BI/SL: ±1 LSB INL, Industrial Temperature, SOIC package c) MCP3302-CI/ST : ±2 LSB INL, Industrial Temperature, TSSOP package a) MCP3304-BI/P: ±1 LSB INL, Industrial Temperature, PDIP package b) MCP3304-BI/SL: ±1 LSB INL, Industrial Temperature, SOIC package PART NO. X /XX PackageTemperature Range Device X Grade

DS21697B-page 38  2002 Microchip Technology Inc. NOTES:

 2002 Microchip Technology Inc. DS21697B-page 39 MCP3302/04 Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical com- ponents in life support systems is not authorized except with express written approval by Microchip. No licenses are con- veyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, FilterLab, K EELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Tech- nology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP , ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and T otal Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro ® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.

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Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 Austria Microchip Technology Austria GmbH Durisolstrasse 2 A-4600 Wels Austria Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 05/16/02 WORLDWIDE SALES AND SERVICE