Power Management

MC32PF8121EUEP

NXP Semiconductors

12-channel power management integrated circuit for high performance applications Rev. 6 - 18 October 2024

Manufacturer: NXP Semiconductors

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PF8121_V01 NXP | Alldatasheet

Document overview

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PDF pages: 128

Technical content

Datasheet sections

1 Overview
2 Features and benefits
3 Simplified application diagram
4 Ordering information
5 Applications
6 Internal block diagram
7 Pinning information
7.1 Pinning
7.2 Pin description
8 Absolute maximum ratings
9 ESD ratings
10 Thermal characteristics
11 Operating conditions
12 General description
12.1 Features
12.2 Functional block diagram
12.3 Power tree summary
13 State machine
13.1 State descriptions
13.1.1 OTP/TRIM load
13.1.2 LP_Off state
13.1.3 QPU_Off state
13.1.4 Power up sequence
13.1.5 System-on states
13.1.5.1 Run state
13.1.5.2 Standby state
13.1.6 WD_Reset
13.1.7 Power down state
13.1.8 Fault transition
13.1.9 Coin cell state
14 General device operation
14.1 UVDET
14.2 VIN OVLO condition
14.3 IC startup timing with PWRON pulled up
14.4 IC startup timing with PWRON pulled low
14.5 Power up
14.5.1 Power up events
14.5.2 Power up sequencing
14.6 Power down
14.6.1 Turn off events
14.6.2 Power down sequencing
14.6.2.1 Sequential power down
14.6.2.2 Group power down
14.6.2.3 Power down delay
14.7 Fault detection
14.7.1 Fault monitoring during power up state
14.8 Interrupt management
14.9 I/O interface pins
14.9.1 PWRON
14.9.2 STANDBY
14.9.3 RESETBMCU
14.9.4 INTB
14.9.5 XINTB
14.9.6 WDI
14.9.7 EWARN
14.9.8 PGOOD
14.9.9 VSELECT
14.9.10 LDO2EN
14.9.11 FSOB (fault status output)
14.9.12 TBBEN
14.9.13 XFAILB
14.9.14 SDA and SCL (I2C bus)
14.9.14.1 I2C CRC verification
15 Functional blocks
15.1 Analog core and internal voltage references
15.2 Coin cell charger
15.3 VSNVS LDO/switch
15.4 Type 1 buck regulators (SW1 to SW6)
15.4.1 SW6 VTT operation
15.4.2 Multiphase operation
15.4.3 Electrical characteristics
15.5 Type 2 buck regulator (SW7)
15.5.1 Electrical characteristics
15.6 Linear regulators
15.6.1 LDO load switch operation
15.6.2 LDO regulator electrical characteristics
15.7 Voltage monitoring
15.7.1 OV/UV configuration
15.7.2 Output voltage monitoring with dedicated
15.7.3 Electrical characteristics
15.8 Clock management
15.8.1 Low frequency clock
15.8.2 High frequency clock
15.8.3 Manual frequency tuning
15.8.4 Spread-spectrum
15.8.5 Clock Synchronization
15.9 Thermal monitors
15.10 Analog multiplexer
15.11 Watchdog event management
15.11.1 Internal watchdog timer
15.11.2 Watchdog reset behaviors
16 I2C register map
16.1 PF8121 functional register map
16.2 PF8121 OTP mirror register map (page 1)
17 OTP/TBB and default configurations
17.1 TBB (Try Before Buy) operation
17.2 OTP fuse programming
17.3 Default hardwire configuration
18 IC level quiescent current requirements
19 Typical applications
20 Package information
20.1 Package outline for E-type HVQFN56
20.2 PCB design guidelines for E-type
20.3 Package outline for dimple WF-type
20.4 PCB design guidelines for dimple WF-type
21 Revision history

12-channel power management integrated circuit for high performance

applications

Rev. 6 — 18 October 2024 Product data sheet

1 Overview

The PF8121 is a power management integrated circuit (PMIC) designed for high performance consumer applications. It features seven high efficiency buck converters and four linear regulators for powering the processor, memory and miscellaneous peripherals. Built-in one-time programmable (OTP) memory stores key startup configurations, drastically reducing external components typically used to set output voltage and sequence of external regulators. Regulator parameters are adjustable through high-speed I2C after startup, offering flexibility for different system states.

12-channel power management integrated circuit for high performance applications

2 Features and benefits

Up to seven high-efficiency buck converters
Four linear regulators with load switch options
RTC supply and coin cell charger
Watchdog timer/monitor
Voltage and system monitoring circuits
One-time programmable (OTP) device configuration
3.4 MHz I2C communication interface
56-pin 8 x 8 QFN package PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

3 Simplified application diagram

3.3 V I/O

1.8 V I/O

2.5 V I/O

2.7 V to

4 Ordering information

Table 1. Device options Table 2. Ordering information [1] To order parts in tape and reel, add the R2 suffix to the part number. [3] The part numbers with a TS suffix are recommended for new designs. [4] Part numbers that are the same except for ES/EP or TS endings share the same OTP report. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

12-channel power management integrated circuit for high performance applications

5 Applications

IoT devices
Industrial PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

6 Internal block diagram

20 MHz Clock/Derivative

24 CHANNEL

7 Pinning information

7.1 Pinning

Figure 3. Pin configuration for HVQFN56

7.2 Pin description

1 DNC1 Do not connect — — — V

48 SYNCIN External clock input pin for

49 SYNCOUT Clock out pin for external part

57 EPAD Exposed pad

8 Absolute maximum ratings

Table 4. Absolute maximum ratings reliability impact, system must not operate above 5.5 V for more than 1800 sec over the lifetime of the device. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

9 ESD ratings

All ESD specifications are compliant with AEC-Q100 specification. Table 5. ESD ratings PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

10 Thermal characteristics

Table 6. Thermal characteristics Table 7. QFN56 thermal resistance and package dissipation ratings temperature, air flow, power dissipation of other components on the board, and board thermal resistance. [2] Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively. [3] Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively. [5] Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored. [6] Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

11 Operating conditions

12-channel power management integrated circuit for high performance applications

12 General description

12.1 Features

The PF8121 is a power management integrated circuit (PMIC) designed to be the primary power management building block for NXP high-end multimedia application processors. It is also capable of providing power solution to the high end i.MX 6 series as well as several non-NXP processors.

Buck regulators – SW1, SW2, SW3, SW4, SW5, SW6: 0.4 V to 1.8 V; 2500 mA; up to 1.5 % accuracy – SW7; 1.0 V to 4.1 V; 2500 mA; 2 % accuracy – Dynamic voltage scaling on SW1, SW2, SW3, SW4, SW5, and SW6 – SW1, SW2 configurable as a dual phase regulator – SW3, SW4 configurable as a dual phase regulator – SW5, SW6 configurable as a dual phase regulator – SW1, SW2 and SW3 configurable as a triple phase regulator with up to 7.5 A current capability – SW1, SW2, SW3 and SW4 configurable as a quad phase regulator with up to 10 A current capability – VTT termination mode on SW6 – Programmable current limit – Spread-spectrum and manual tuning of switching frequency
LDO regulators – LDO1, 1.5 V to 5.0 V, 400 mA: 3 % accuracy with optional load switch mode – LDO2, 1.5 V to 5.0 V, 400 mA; 3 % accuracy with optional load switch mode and selectable hardware/ software control – LDO3, 1.5 V to 5.0 V, 400 mA; 3 % accuracy with optional load switch mode – LDO4, 1.5 V to 5.0 V, 400 mA; 3 % accuracy with optional load switch mode
RTC LDO/Switch supply from system supply or coin cell – RTC supply VSNVS 1.8 V/3.0 V/3.3 V, 10 mA – Battery backed memory including coin cell charger with programmable charge current and voltage
System features – Fast PMIC startup – Advanced state machine for seamless processor interface – High speed I2C interface support (up to 3.4 MHz) – PGOOD monitor – User programmable standby and off modes – Programmable soft start sequence and power down sequence – Programmable regulator configuration – 24 channel analog multiplexer for smart system monitoring/diagnostic
OTP (One time programmable) memory for device configuration
Voltage and system monitoring – Independent voltage monitoring with programmable fault protection – Advance thermal monitoring and protection – External watchdog monitoring and programmable internal watchdog counter – I2C cyclic redundancy check (CRC) PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

12.2 Functional block diagram

24 CHANNEL AMUX

Figure 4. Functional block diagram

12.3 Power tree summary

The following table shows a summary of the voltage regulators in the PF8121. Table 9. Voltage supply summary PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

12-channel power management integrated circuit for high performance applications

13 State machine

The PF8121 features a state of the art state machine for seamless processor interface. The state machine handles the IC start up, provides fault monitoring and reporting, and protects the IC and the system during fault conditions. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

FAULT_CNT = FAULT_MAX_CNT

Figure 5. State diagram Table 10 lists the conditions for the different state machine transitions. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

STANDBY = 0 && STANDBYINV bit = 0
STANDBY = 1 && STANDBYINV bit = 1
STANDBY = 1 && STANDBYINV bit = 0
STANDBY = 0 && STANDBYINV bit = 1

OTP_PWRON_MODE = 0 && PWRON = 0
OTP_PWRON_MODE = 1 && (PWRON H to L && PWRON = low
PMIC_OFF = 1 && 500µs_Shutdown_Timer_Expired
VIN_OVLO_SDWN = 1 && VIN_OVLO detected for longer than
FAULT_CNT = FAULT_MAX_CNTTransition Z System on to power down (fault)
Thermal shutdown TJ > TSD
Power down sequences finished
Failure during power up sequence
Power down sequence is finished

13.1 State descriptions

13.1.1 OTP/TRIM load

the functional I2C registers if configured by the voltage on the VDDOTP pin. asserted. See Section 17 "OTP/TBB and default configurations" for details on handling fuse load errors. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

12-channel power management integrated circuit for high performance applications If no fuse load errors are present, VSNVS is configured as indicated in the OTP configuration bits, and the state machine moves to the LP_OFF state.

13.1.2 LP_Off state

The LP_Off state is a low power off mode selectable by the LPM_OFF bit during the system on modes. By default, the LPM_OFF = 0 when VIN crosses the UVDET threshold, therefore the state machine stops at the LP_Off state until a valid power up event is present. When LPM_OFF= 1, the state machine transitions automatically to the QPU_Off state if no power up event has been present and waits in the QPU_Off until a valid power up event is present. The selection of the LPM_OFF bit is based on whether prioritizing low quiescent current (stay in LP_Off) or quick power up (move to QPU_Off state). If a power up event is started in LP_Off state with LPM_OFF = 0 and a fuse loading error is detected, the PF8121 ignores the power up event and remains in the LP_Off state to avoid any potential damage to the system. To be in LP_Off state, it is necessary to have VIN present. If a valid LICELL is present, but VIN is below the UVDET, the PF8121 enters the coin cell state.

13.1.3 QPU_Off state

The QPU_Off state is a higher power consumption off mode, in which all internal circuitry required for a power on is biased and ready to start a power up sequence. If LPM_OFF = 1 and no turn on event is present, the device stops at the QPU_Off state, and waits until a valid turn on event is present. In this state, if VDDIO supply is provided externally, the device is able to communicate through I2C to access and modify the mirror registers in order to operate the device in TBB mode or to program the OTP registers as described in Section 17 "OTP/TBB and default configurations". By default, the coin cell charger is disabled during the QPU_Off state when VIN crosses the UVDET threshold, but it may be turned on or off in this state once it is programmed by COINCHG_OFF during the system-on states. If a power up event is started and any of the TRIM_NOK or OTP_NOK flags are asserted, the device ignores the power up event and remains in the QPU_Off state. See Section 17 "OTP/TBB and default configurations" for more details on debugging a fuse loading failure. Upon a power up event, the default configuration from OTP or hardwire is loaded into their corresponding I2C functional register in the transition from QPU_Off to power up state.

13.1.4 Power up sequence

During the power up sequence, the external regulators are turned on in a predefined order as programmed by the default (OTP or hardwire) sequence. If PGOOD is used as a GPO, it can also be set high as part of the power up sequence in order to allow sequencing of any external supply/device controlled by the PGOOD pin. The RESETBMCU is also programmed as part of the power up sequence, and it is used as the condition to enter system-on states. The RESETBMCU may be released in the middle of the power up sequence, in this case, the remaining supplies in the power up continues to power up as the device is in the run state. See Section 14.5.2 "Power up sequencing" for details. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

12-channel power management integrated circuit for high performance applications

13.1.5 System-on states

During the system-on states, the MCU is powered and out of reset and the system is fully operational. The system on is a virtual state composed by two modes of operations:

Run state
Standby state Register to control the regulators output voltage, regulator enable, interrupt masks, and other miscellaneous functions can be written to or read from the functional I2C register map during the system-on states.

13.1.5.1 Run state

If the power up state is successfully completed, the state machine transitions to the run state. In this state, RESETBMCU is released high, and the MCU is expected to boot up and set up specific registers on the PMIC as required during the system boot up process. The run mode is intended to be used as the normal mode of operation for the system. Each regulator has specific registers to control its output voltage, operation mode and/or enable/disable state during the run state. By default, the VSWx_RUN[7:0] / VLDOx_RUN[3:0] registers are loaded with the data stored in the OTP_VSWx[7:0] or OTP_VLDOx[3:0] bits respectively. SW7 uses only one global register to configure the output voltage during run or standby mode. Upon power up the VSW7[4:0] bits are loaded with the values of the OTP_VSW7[4:0]. Upon power up, if the switching regulator is part of the power up sequence, the SWx_RUN_MODE[1:0] bits will be loaded as needed by the system:

When OTP_SYNCIN_EN = 1, default SWx_RUN_MODE at power up is always set to PWM (0b01)
When OTP_SYNCOUT_EN = 1, default SWx_RUN_MODE at power up is always set to PWM (0b01)
When OTP_FSS_EN = 1, default SWx_RUN_MODE at power up shall always set to PWM (0b01)
If none of the above conditions are met, the default value of the SWx_RUN_MODE bits at power up will be set by the OTP_SW_MODE bits. When OTP_SW_MODE = 0, the default value of the SWx_RUN_MODE bits are set to 0b11 (autoskip). When OTP_SW_MODE = 1, the default value of the SWx_RUN_MODE bits are set to 0b01 (PWM). If the switching regulator is not part of the power up sequence, the SWx_RUN_MODE[1:0] bits are loaded with 0b00 (OFF mode). Likewise, if the LDO is part of the power up sequence, the LDOx_RUN_EN bit is set to 1 (enabled) by default. If the LDO is not selected as part of the power up sequence, the LDOx_RUN_EN bit is set to 0 (disabled) by default. In a typical system, each time the processor boots up (PMIC transitions from off mode to run state), all output voltage configurations are reset to the default OTP configuration, and the MCU should configure the PMIC to its desired usage in the application.

13.1.5.2 Standby state

The standby state is intended to be used as a low power (state retention) mode of operation. In this state, the voltage regulators can be preset to a specific low power configuration in order to reduce the power consumption during system’s sleep or state retention modes of operations. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

12-channel power management integrated circuit for high performance applications The standby state is entered when the STANDBY pin is pulled high or low as defined by the STANBYINV bit. The STANDBY pin is pulled high/low by the MCU to enter/exit system low power mode. See Section 14.9.2 "STANDBY" for detailed configuration of the STANDBY pin. Each regulator has specific registers to control its output voltage, operation mode and/or enable/disable state during the standby state. By default, the VSWx_STBY[7:0] / VLDOx_STBY[3:0] registers are loaded with the data stored in the OTP_VSWx[7:0] or OTP_VLDOx[3:0] bits respectively. Upon power up, if the switching regulator is part of the power up sequence, the SWx_STBY_MODE[1:0] bits will be loaded as needed by the system:

When OTP_SYNCIN_EN = 1, default SWx_STBY_MODE at power up is always set to PWM (0b01)
When OTP_SYNCOUT_EN = 1, default SWx_STBY_MODE at power up is always set to PWM (0b01)
When OTP_FSS_EN = 1, default SWx_STBY_MODE at power up shall always set to PWM (0b01)
If none of the conditions above are met, the default value of the SWx_STBY_MODE bits at power up will be set by the OTP_SW_MODE bits. When OTP_SW_MODE = 0, the default value of the SWx_STBY_MODE bits are set to 0b11 (autoskip). When OTP_SW_MODE = 1, the default value of the SWx_STBY_MODE bits are set to 0b01 (PWM). If the switching regulator is not part of the power up sequence, the SWx_STBY_MODE[1:0] bits are loaded with 0b00 (OFF mode). Likewise, if the LDO is part of the power up sequence, the LDOx_RUN_EN bit is set to 1 (enabled) by default. If the LDO is not selected as part of the power up sequence, the LDOx_RUN_EN bit is set to 0 (disabled) by default. Upon power up, the standby registers are loaded with the same default OTP values as the run mode. The MCU is expected to program the desired standby values during boot up. If any of the external regulators are disabled in the standby state, the power down sequencer is engaged as described in Section 14.6.2 "Power down sequencing".

13.1.6 WD_Reset

When a hard watchdog reset is present, the state machine increments the WD_EVENT_CNT[3:0] register and compares against the WD_MAX_CNT[3:0] register. If WD_EVENT_CNT[3:0] = WD_MAX_CNT[3:0], the state machine detects a cyclic watchdog failure, it powers down the external regulators and proceeds to the fault transition. If WD_EVENT_CNT[3:0] < WD_MAX_CNT[3:0], the state machine performs a hard WD reset. A hard WD reset can be generated from either a transition in the WDI pin or a WD event initiated by the internal watchdog counter as described in Section 15.11.2 "Watchdog reset behaviors".

13.1.7 Power down state

During power down state, all regulators except VSNVS are disabled as configured in the power down sequence. The power down sequence is programmable as defined in Section 14.6.2 "Power down sequencing". Two types of events may lead to the power down sequence:

Non faulty turn off events: move directly into LP_Off state as soon as power down sequence is finalized
Turn off events due to a PMIC fault: move to the fault transition as soon as the power down sequence is finalized PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

12-channel power management integrated circuit for high performance applications

13.1.8 Fault transition

The fault transition is entered if the PF8121 initiates a turn off event due to a PMIC fault. If the fault transition is entered, the PF8121 provides four FAIL bits to indicate the source of the failure:

The PU_FAIL is set to 1 when the device shuts down due to a power up failure
The WD_FAIL is set to 1 when the device shuts down due to a watchdog event counter max out
The REG_FAIL is set to 1 when the device shuts down due to a regulator failure (fault counter maxed out or fault timer expired)
The TSD_FAIL is set to 1 when the device shuts down due to a thermal shutdown The value of the FAIL bits is retained as long as VIN > UVDET. The MCU can read the FAIL bits during the system-on states in order to obtain information about the previous failure and can clear them by writing a 1 to them, provided the state machine is able to power up successfully after such failure.

13.1.9 Coin cell state

When VIN is not present and LICELL pin has a valid voltage, the device is placed into a coin cell state. In such state, only VSNVS remains on (if programmed to do so by the OTP_VSNVSVOTL[1:0] bits) and is expected to provide power to the SNVS domain on the MCU as long as the LICELL pin has a valid input suitable to supply the configured VSNVS output voltage. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

14 General device operation

14.1 UVDET

mandatory condition for OTP fuses to be loaded into the mirror registers and allows the main PF8121 operation. comparator to set the falling threshold. Table 11. UVDET threshold

14.2 VIN OVLO condition

When the VIN_OVLO_SDWN = 0, the VIN_OVLO event triggers an OVLO interrupt but does not turn off the device
When the VIN_OVLO_SDWN = 1, the VIN_OVLO event initiates a power down sequence When the VIN_OVLO_EN = 0, the OVLO monitor is disabled and when the VIN_OVLO_EN = 1, the OVLO monitor is enabled. The default configuration of the VIN_OVLO_EN bit is set by the OTP_VIN_OVLO_EN bit in OTP. Likewise, the default value of the VIN_OVLO_SDWN bit is set by the OTP_VIN_OVLO_SDWN upon power up. During a power up transition, if the OTP_VIN_OVLO_SDWN = 0 the device allows the external regulators to come up and the PF8121 announces the VIN_OVLO condition through an interrupt. If the OTP_VIN_OVLO_SDWN = 1, the device stops the power up sequence and returns to the corresponding off mode. Debounce on the VIN_OVLO comparator is programmable to 10 µs, 100 µs or 1.0 ms, by the VIN_OVLO_DBNC[1:0] bits. The default value for the VIN_OVLO debounce is set by the OTP_VIN_OVLO_DBNC[1:0] bits upon power up. VIN_OVLO_DBNC[1:0] VIN OVLO debounce value (µs) 00 10 01 100 10 1000

11 Reserved

Table 12. VIN_OVLO debounce configuration Table 13. VIN_OVLO specifications [1] Operating the device above the maximum VIN = 5.5 V for extended periods of time may degrade and cause permanent damage to the device. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

14.3 IC startup timing with PWRON pulled up

for VIN to cross the UVDET threshold in the rising edge. sequence is ensured to allow up to 1.5 ms time frame for the voltage regulators power up sequence. Timing for the external regulators to start up is programmed by default in the OTP fuses. sensitive modes after the power on event is present. VSNVS to reach regulation before the power up sequence is started. Figure 6. Startup with PWRON pulled up Table 14. Startup timing requirements (PWRON pulled up) PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 14. Startup timing requirements (PWRON pulled up) ...continued time to ensure power up within 5.0 ms.

14.4 IC startup timing with PWRON pulled low during VIN application

the self-test before starting a power up sequence. Figure 7 shows startup timing with LPM_OFF = 0. Figure 7. Startup with PWRON driven high externally and bit LPM_OFF = 0 Table 15. Startup with PWRON driven high externally and LPM_OFF = 0 PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 15. Startup with PWRON driven high externally and LPM_OFF = 0...continued [1] External regulators power up sequence time (treg2reset) is programmed by OTP and may be longer than 1.5 ms.

14.5 Power up

14.5.1 Power up events

until VIN crosses the UVDET threshold.

When OTP_PWRON_MODE = 0, PWRON pin is pulled high.
When OTP_PWRON_MODE = 1, PWRON pin experiences a high to low transition and remains low for as

long as the PWRON_DBNC timer.

VIN > UVDET
VIN < VIN_OVLO (unless the OVLO is disabled or OTP_VIN_OVLO_SDWN = 0)
Tj < thermal shutdown threshold
TRIM_NOK = 0 && OTP_NOK = 0

14.5.2 Power up sequencing

are enabled when going from the off mode into the run state. The OTP_SEQ_TBASE[1:0] bits set the default time base for the power up and power down sequencer. during run/standby transitions as well as the power down sequence. Table 16. Power up time base register

Switching regulators
LDO Regulators PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

PGOOD pin if programmed as a GPO
RESETBMCU The default sequence slot for each one of these signals is programmed via the OTP configuration registers. And they can be modified in the functional I2C register map to change the order in which the sequencer behaves during the run/standby transitions as well as the power down sequence. The _SEQ[7:0] bits set the regulator/pin sequence from 0 to 254. Sequence code 0x00 indicates that the particular output is not part of the startup sequence and remains in off (in case of a regulator) or remains low/ disabled (in case of PGOOD pin used as a GPO). OTP bits OTP_SWx_SEQ[7:0]/ OTP_LDOx_SEQ[7:0]/ OTP_PGOOD_SEQ[7:0]/ OTP_RESETBMCU_SEQ[7:0] Functional bits SWx_SEQ[7:0]/ LDOx_SEQ[7:0]/ PGOOD_SEQ[7:0]/ RESETBMCU_SEQ[7:0] Sequence slot Startup time (µs) 00000000 00000000 Off Off 00000001 00000001 0 SLOT0 (right after PWRON event is valid) 00000010 00000010 1 SEQ_TBASE x SLOT1 11111111 11111111 254 SEQ_TBASE x SLOT254

Table 17. Power up sequence registers programmed in the power up sequence. slot, it is released when the device enters the run state. working as a secondary PMIC, and supplies are meant to be enabled by the MCU during the system operation. In this scenario, if RESETBMCU is used, it is connected to the primary RESETBMCU pin. regulator in the sequence has ended. Figure 8 provides an example of the power up/down sequence coming from the off modes. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

12-channel power management integrated circuit for high performance applications

14.6 Power down

14.6.1 Turn off events

Turn off events may be requested by the MCU (non-PMIC fault related) or due to a critical failure of the PMIC (hard fault condition). The following are considered non-PMIC failure turn off events: 1. When OTP_PWRON_MODE = 0, the device starts a power down sequence when the PWRON pin is pulled low. 2. When OTP_PWRON_MODE = 1, the device starts a power down sequence when the PWRON pin sees a transition from high to low and remains low for longer than TRESET. 3. When bit PMIC_OFF is set to 1, the device starts a 500 µs shutdown timer. When the shutdown timer is started, the PF8121 sets the SDWN_I interrupt and asserts the INTB pin provided it is not masked. At this point, the MCU can read the interrupt and decide whether to continue with the turn off event or stop it in case it was sent by mistake. If the SDWN_I bit is cleared before the 500 µs shutdown timer is expired, the shutdown request is cancelled and the shutdown timer is reset; otherwise, if the shutdown timer is expired, the PF8121 starts a power down sequence. The PMIC_OFF bit self-clears after SDWN_I flag is cleared. 4. When VIN_OVLO_EN = 1 and VIN_OVLO_SDWN = 1, and a VIN_OVLO event is present. Turn off events due to a hard fault condition: 1. If an OV, UV or ILIM condition is present long enough for the fault timer to expire. 2. In the event that an OV, UV or ILIM condition appears and clears cyclically, and the FAULT_CNT[3:0] = FAULT_MAX_CNT[3:0]. 3. If the watchdog fail counter is overflown, that is WD_EVENT_CNT = WD_MAX_CNT. 4. When Tj crosses the thermal shutdown threshold as the temperature rises. When the PF8121 experiences a turn off event due to a hard fault condition, the device passes through the fault transition after regulators have been powered down.

14.6.2 Power down sequencing

During a power down sequence, output voltage regulators can be turned off in two different modes as defined by the PWRDWN_MODE bit. 1. When PWRDWN_MODE = 0, the regulators power down in sequential mode. 2. When PWRDWN_MODE = 1, the regulators power down by groups. During transition from run to standby, the power down sequencer is activated in the corresponding mode. If any of the external regulators are turned off in the standby configuration. If external regulators are not turned off during this transition, the power down sequencer is bypassed and the transition happens at once (any associated DVS transitions could still take time). The PWRDN_I interrupt is set at the end of the transition from run to standby when the last regulator has reached its final state, even if external regulators are not turned off during this transition.

14.6.2.1 Sequential power down

When the device is set to the sequential power down, it uses the same _SEQ[7:0] registers as the power up sequence to power down in reverse order. All regulators with the _SEQ[7:0] bits set to 0x00, power down immediately and the remaining regulators power down one OTP_SEQ_TBASE[1:0] delay after, in reverse order as defined in the _SEQ[7:0] bits. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

12-channel power management integrated circuit for high performance applications If PGOOD pin is used as a GPO, it is de-asserted as part of the power down sequence as indicated by the PGOOD_SEQ[7:0] bits. If the MCU requires a different power down sequence, it can change the values of the SEQ_TBASE[1:0] and the _SEQ[7:0] bits during the system-on states. When the state machine pass through any of the off modes, the contents of the SEQ_TBASE[1:0] and _SEQ[7:0] bits are reloaded with the corresponding mirror register (OTP) values before it starts the next power up sequence.

14.6.2.2 Group power down

When the device is configured to power down in groups, the regulators are assigned to a specific power down group. All regulators assigned to the same group are disabled at the same time when the corresponding group is due to be disabled. Power down groups shut down in decreasing order starting from the lowest hierarchy group with a regulator shutting down (for instance, Group 4 being the lowest hierarchy and Group 1 the highest hierarchy group). If no regulators are set to the lowest hierarchy group, the power down sequence timer starts off the next available group that contains a regulator to power down. Each regulator has its own _PDGRP[1:0] bits to set the power down group it belongs to as shown in Table 18. OTP_SWx_PDGRP[1:0] OTP_LDOx_PDGRP[1:0] OTP_PGOOD_PDGRP[1:0] OTP_RESETBMCU_PDGRP[1:0] SWx_PDGRP[1:0] LDOx_PDGRP[1:0] PGOOD_PDGRP[1:0] RESETBMCU_PDGRP[1:0]

Description

00 00 Regulator belongs to Group 4 01 01 Regulator belongs to Group 3 10 10 Regulator belongs to Group 2 11 11 Regulator belongs to Group 1 Table 18. Power down regulator group bits regulators in this group have been turned off, and the next group can start to power down. Table 19. Power down counter delay PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 20. Programmable delay after RESETBMCU is asserted at the same time RESETBMCU is asserted. Figure 10 shows an example of the power down sequence when PWRDWN_MODE = 1. Figure 10. Group power down sequence example

14.6.2.3 Power down delay

present. The power down delay time can be programed on OTP via the OTP_PD_SEQ_DLY[1:0] bits. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

00 No delay

Table 21. Power down delay selection Figure 11. Power down delay The default value of the OTP_PD_SEQ_DLY[1:0] bits on an unprogrammed OTP device shall be 00.

14.7 Fault detection

corresponding fault is not masked. configure them as required during the boot-up process via I2C commands. when the corresponding regulator experience a fault event.

0 = regulator disable upon an ILIM fault event
1 = regulator remains on upon an ILIM fault event SWx_OV_STATE / LDOx_OV_STATE
0 = regulator disable upon an OV fault event
1 = regulator remains on upon an OV fault event SWx_UV_STATE / LDOx_UV_STATE
0 = regulator disable upon an UV fault event
1 = regulator remains on upon an UV fault event PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

Table 22. Regulator control during fault event bits programed to disable upon an ILIM condition, the regulator turns off as soon as the ILIM condition is detected. fault persist for longer than 300 µs after the OV/UV fault has been detected. Figure 12. Regulator turned off with RegX_STATE = 0 and FLT_REN = 0 regulator can return to its previous configuration or remain disabled when the fault condition is cleared. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

0 = regulator remains disabled after the fault condition is cleared or no longer present
1 = regulator returns to its previous state if fault condition is cleared If a regulator is programmed to remain disabled after clearing the fault condition, the MCU can turn it back on during the system on states by toggling off and on the corresponding mode/enable bits. When the bit SWx_FLT_REN = 1, if a regulator is programmed to turn off upon an OV, UV or ILIM condition, the regulator returns to its previous state 500 µs after the fault condition is cleared. If the regulator is programmed to turn off upon an ILIM condition, the device may take up to 1.0 ms to debounce the ILIM condition removal, in addition to the 500 µs wait period to re-enable the regulator. RegX_STATE = 0 && FLT_REN = 1 ILIM fault RegX_STATE = 0 && FLT_REN = 1 OV/UV fault REGx I_REGx REGx_EN REGx REGx_EN PGOOD REGx_PG ILIM 1 ms 1.5 ms 500 µs 300 µs 500 µs 300 µs 1 ms 1.5 ms aaa-028058

Figure 13. Regulator turned off with RegX_STATE = 0 and FLT_REN = 1 regardless the state of the LDO2EN pin. details on hardware control of LDO2 regulator. equal, it increments the FAULT_CNT[3:0] and proceeds with the fault protection mechanism. FAULT_MAX_CNT[3:0] value, the state machine initiates a power down sequence. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

event of a current limit fault, or turn off the regulator in the event of an overvoltage fault. timer can be changed during the system on states by modifying the TIMER_FAULT[3:0] bits in the I2C registers. Table 23. Fault timer register configuration

0 = ILIM protection enabled
1 = ILIM fault bypassed SWx_OV_BYPASS / LDOx_OV_BYPASS
0 = OV protection enabled
1 = OV fault bypassed SWx_UV_BYPASS / LDOx_UV_BYPASS
0 = UV protection enabled
1 = UV fault bypassed Regulator Bit to bypass a current limit Bit to bypass an undervoltage Bit to bypass an overvoltage SW1 SW1_ILIM_BYPASS SW1_UV_BYPASS SW1_OV_BYPASS

Table 24. Fault bypass bits...continued by their corresponding OTP bits.

Increment the counter
Start the Fault timer
Disable the regulator if the corresponding _STATE bit is 0
OV / UV condition asserting the PGOOD pin low When a fault is bypassed, the corresponding interrupt bit is still set and the INTB pin is asserted, provided the interrupt has not been masked.

14.7.1 Fault monitoring during power up state

sequence and used as a gating condition to release the RESETBMCU or not.

When OTP_PG_CHECK = 0, the output voltage of the regulators is not checked during the power up sequence and power good indication is not required to de-assert the RESETBMCU. In this scenario, the OV/ UV monitors are masked until RESETBMCU is released; after this event, all regulators may start checking for faults after their corresponding blanking period.
When OTP_PG_CHECK = 1, the output voltage of the regulators is verified during the power up sequence and a power good condition is required to release the RESETBMCU. When OTP_PG_CHECK = 1, OV and UV faults during the power up sequence are reported based on the internal PG (Power Good) signals of the corresponding external regulator. The PGOOD pin can be used as an external indicator of an OV/UV failure when the RESETBMCU is ready to be de-asserted and it has been configured in the PGOOD mode. See Section 14.9.8 "PGOOD" for details on PGOOD pin operation and configuration. Regardless of the PGOOD pin configured as a power good indicator or not, the PF8121 masks the detection of an OV/UV failure until RESETBMCU is ready to be released, at this point the device checks for any OV/UV condition for the regulators turned on so far. If all regulators powered up before or in the same sequence slot than RESETBMCU are in regulation, RESETBMCU is de-asserted and the power up sequence can continue as shown in Figure 14. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

Figure 14. Correct power up (no fault during power up) continues where it stopped as shown in Figure 15. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 15. Power up sequencer with a temporary failure turn off all voltage regulators enabled so far as shown in Figure 16. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 16. Power up sequencer aborted as fault persists for longer than 2.0 ms Supplies enabled after RESETBMCU are checked for OV, UV and ILIM faults after each of them is enabled. upon a fault event as defined by the system. sequence as long as the RESETBMCU is released after one or more of the SW or LDO regulators. mechanism is active on an earlier regulator.

14.8 Interrupt management

The MCU is notified of any interrupt through the INTB pin and various interrupt registers.

The interrupt latch XXXX_I: this bit is set when the corresponding interrupt event occurs. It can be read at any time, and is cleared by writing a 1 to the bit.
The mask bit XXXX_M: this bit controls whether a given interrupt latch pulls the INTB pin low or not.
When the mask bit is 1, the interrupt latch does not control the INTB pin.
When the mask bit is 0, INTB pin is pulled low as long as the corresponding latch bit is set.
The sense bit XXXX_S: if available, the sense bit provides the actual status of the signal triggering the interrupt. The INTB pin is a reflection of an “OR” logic of all the interrupt status bits which control the pin. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

information about the Interrupt register that originated the interrupt event. interrupt bits of the respective interrupt registers.

STATUS1_I: this bit is set when the interrupt is generated within the INT STATUS1 register
STATUS2_I: this bit is set when the interrupt is generated within the INT STATUS2 register
MODE_I: this bit is set when the interrupt is generated within the SW MODE INT register
ILIM_I: this bit is set when the interrupt is generated within any of the SW ILIM INT or LDO ILIM INT registers
UV_I: this bit is set when the interrupt is generated within any of the SW UV INT or LDO UV INT registers
OV_I: this bit is set when the interrupt is generated within any of the SW OV INT or LDO OV INT registers
PWRON_I: this bit is set when the interrupt is generated within the PWRON INT register
EWARN_I: is set when an early warning event occurs to indicate an imminent shutdown The SYS_INT bits are set when the INTB pin is asserted by any of the second level interrupt bits that have not been masked in their corresponding mask registers. When the second level interrupt bit is cleared, the corresponding first level interrupt bit on the SYS_INT register will be cleared automatically. The INTB pin will remain asserted if any of the first level interrupt bit is set, and it will be de-asserted only when all the unmasked second level interrupts are cleared and thus all the first level interrupts are cleared as well. At second level, the remaining registers provide the exact source for the interrupt event. Table 25 shows a summary of the interrupt latch, mask and sense pins available on the PF8121. Register name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 INT STATUS1 SDWN_I FREQ_RDY_I CRC_I PWRUP_I PWRDN_I XINTB_I FSOB_I VIN_OVLO_I INT MASK1 SDWN_M FREQ_RDY_M CRC_M PWRUP_M PWRDN_M XINTB_M FSOB_M VIN_OVLO_M INT SENSE1 — — — — — XINTB_S FSOB_S VIN_OVLO_S THERM INT WDI_I FSYNC_FLT_I THERM_155_I THERM_140_I THERM_125_I THERM_110_I THERM_95_I THERM_80_I THERM MASK WDI_M FSYNC_FLT_M THERM_155_M THERM_140_M THERM_125_M THERM_110_M THERM_95_M THERM_80_M THERM SENSE WDI_S FSYNC_FLT_S THERM_155_S THERM_140_S THERM_125_S THERM_110_S THERM_95_S THERM_80_S SW MODE INT — SW7_MODE_I SW6_MODE_I SW5_MODE_I SW4_MODE_I SW3_MODE_I SW2_MODE_I SW1_MODE_I SW MODE MASK — SW7_MODE_M SW6_MODE_M SW5_MODE_M SW4_MODE_M SW3_MODE_M SW2_MODE_M SW1_MODE_M SW ILIM INT — SW7_ILIM_I SW6_ILIM_I SW5_ILIM_I SW4_ILIM_I SW3_ILIM_I SW2_ILIM_I SW1_ILIM_I SW ILIM MASK — SW7_ILIM_M SW6_ILIM_M SW5_ILIM_M SW4_ILIM_M SW3_ILIM_M SW2_ILIM_M SW1_ILIM_M SW ILIM SENSE — SW7_ILIM_S SW6_ILIM_S SW5_ILIM_S SW4_ILIM_S SW3_ILIM_S SW2_ILIM_S SW1_ILIM_S LDO ILIM INT — — — — LDO4_ILIM_I LDO3_ILIM_I LDO2_ILIM_I LDO1_ILIM_I LDO ILIM MASK — — — — LDO4_ILIM_M LDO3_ILIM_M LDO2_ILIM_M LDO1_ILIM_M LDO ILIM SENSE — — — — LDO4_ILIM_S LDO3_ILIM_S LDO2_ILIM_S LDO1_ILIM_S SW UV MASK — SW7_UV_M SW6_UV_M SW5_UV_M SW4_UV_M SW3_UV_M SW2_UV_M SW1_UV_M SW UV SENSE — SW7_UV_S SW6_UV_S SW5_UV_S SW4_UV_S SW3_UV_S SW2_UV_S SW1_UV_S SW OV MASK — SW7_OV_M SW6_OV_M SW5_OV_M SW4_OV_M SW3_OV_M SW2_OV_M SW1_OV_M SW OV SENSE — SW7_OV_S SW6_OV_S SW5_OV_S SW4_OV_S SW3_OV_S SW2_OV_S SW1_OV_S LDO UV SENSE — — — — LDO4_UV_S LDO3_UV_S LDO2_UV_S LDO1_UV_S LDO OV SENSE — — — — LDO4_OV_S LDO3_OV_S LDO2_OV_S LDO1_OV_S PWRON INT BGMON_I PWRON_8S_I PWRON_4S_I PRON_3S_I PWRON_2S_I PWRON_1S_I PWRON_REL_I PWRON_PUSH_I

Table 25. Interrupt registers...continued

14.9 I/O interface pins

Table 26. I/O electrical specifications...continued

14.9.1 PWRON

PWRON is an input signal to the IC that acts as a power up event signal in the PF8121. The PWRON pin has two modes of operations as programed by the OTP_PWRON_MODE bit. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

condition to generate a power on event. automatically with VIN application. See Section 14.5 "Power up" for details on power up requirements. used as an input from a push button connected to the PMIC. PWRON pin is at logic 0 and is low whenever the PWRON pin is at logic 1. The PWRON pin has a programmable debounce on the rising and falling edges as shown below. Table 27. PWRON debounce configuration in edge detection mode The default value for the power on debounce is set by the OTP_PWRON_DBNC[1:0] bits. interrupts which the processor may use to initiate PMIC state transitions. debounce setting, the PWRON_REL_I interrupt is generated. when the PWRON pin is held low for longer than 1, 2, 3, 4 and 8 seconds respectively. then it powers back up with the default OTP configuration. Table 28. TRESET configuration The default value of the TRESET delay is programmable through the OTP_TRESET[1:0] bits.

14.9.2 STANDBY

STANDBY can be configured as active high or active low using the STANDBYINV bit. Table 29. Standby pin polarity control

14.9.3 RESETBMCU

OTP_RESETBMCU_SEQ[7:0] bits, and it is a condition to enter the system-on states. indicated in the power down sequence, when a system power down or reset is initiated. In the application, RESETBMCU can be pulled up to VDDIO or VSNVS by a 100 kΩ external resistor.

14.9.4 INTB

that the interrupt is not masked. after the test pulse is generated. In the application, INTB can be pulled up to VDDIO with an external 100 kΩ resistor.

14.9.5 XINTB

provided the interrupt is not masked.

14.9.6 WDI

WDI is an input pin to the PF8121 and is intended to operate as an external watchdog monitor. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

watchdog event to place the PMIC outputs in a default known state. WDI pin is masked until RESETBMCU is de-asserted. The WDI can be configured to assert on the rising or the falling edge using the OTP_WDI_INV bit.

When OTP_WDI_INV = 0, the device starts a WD event on the falling edge of the WDI.
When OTP_WDI_INV = 1, the device starts a WD event on the rising edge of the WDI. A 10 µs debounce filter is implemented on either rising or falling edge detection to prevent false WDI signals to start a watchdog event. The OTP_WDI_MODE bit allows the WDI pin to react in two different ways:
When OTP_WDI_MODE = 1, a WDI asserted performs a hard WD reset.
When OTP_WDI_MODE = 0, a WDI asserted performs a soft WD reset. The WDI_STBY_ACTIVE bit allows the WDI pin to generate a watchdog event during the standby state.
When WDI_STBY_ACTIVE = 0, asserting the WDI will not generate a watchdog event during the standby state.
When WDI_STBY_ACTIVE = 1, asserting the WDI will start a watchdog event during the standby state. The OTP_WDI_STBY_ACTIVE is used to configure whether the WDI is active in the standby state or not by default upon power up. See Section 15.11 "Watchdog event management" for details on watchdog event.

14.9.7 EWARN

pulled down to GND by a 100 kΩ resistor.

Fault timer expired
FAULT_CNT = FAULT_MAX_CNT
Thermal Shutdown tJ > TSD
VIN_OVLO event when VIN_OVLO_SDWN=1 OTP_EWARN_TIME[1:0] EWARN delay time 00 100 μs 01 5.0 ms 10 20 ms 11 50 ms

Table 30. EWARN time configuration to the system of an imminent shutdown event. In the Off modes, EWARN remains de-asserted (pulled low). PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

notify to the processor that VIN may be lost and allow some time to prepare for the power loss. Table 31. Early warning threshold

14.9.8 PGOOD

PGOOD can be pulled up to VDDIO with a 100 kΩ resistor. When OTP_PG_ACTIVE = 0, the PGOOD pin is used as a general purpose output.

When RUN_PG_GPO = 1, the PGOOD pin is high
When RUN_PG_GPO = 0, the PGOOD pin is low During the standby state, the state of the pin is controlled by the STBY_PG_GPO bit in the functional I2C registers:
When STBY_PG_GPO = 1, the PGOOD pin is high
When STBY_PG_GPO = 0, the PGOOD pin is low When used as a GPO, the PGOOD pin can be enabled high as part of the power up sequence as programmed by the OTP_SEQ_TBASE[1:0] and the OTP_PGOOD_SEQ[7:0] bits. If enabled as part of the power up sequence, both the RUN_PG_GPO and STBY_PG_GPO bits are loaded with 1, otherwise they are loaded with 0 upon power up. When OTP_PG_ACTIVE = 1, the PGOOD pin is in Power good (PG) mode and it acts as a PGOOD indicator for the selected output voltages in the PF8121. There is an individual PG monitor for every regulator. Each monitor provide an internal PG signal that can be selected to control the status of the PGOOD pin upon an OV or UV condition when the corresponding SWxPG_EN / LDOxPG_EN bits are set. The status of the PGOOD pin is a logic AND function of the internal PG signals of the selected monitors.
When the PG_EN = 1, the corresponding regulator becomes part of the AND function that controls the PGOOD pin.
When the PG_EN = 0, the corresponding regulator does not control the status of the PGOOD pin. The PGOOD pin is pulled low when any of the selected regulator outputs falls above or below the programmed OV/UV thresholds and a corresponding OV/UV interrupt is generated. If the faulty condition is removed, the corresponding OV_S/UV_S bit goes low to indicate the output is back in regulation, however, the interrupt remains latched until it is cleared. The actual condition causing the interrupt (OV, UV) can be read in the fault interrupt registers. For more details on handling interrupts, see Section 14.8 "Interrupt management". When a particular regulator is disabled (via OTP, or I2C, or by change in state of PMIC such as going to standby mode), it no longer controls the PGOOD pin. In the Off mode and during the power up sequence, the PGOOD pin is held low until RESETBMCU is ready to be released, at this point, the PG monitors are unmasked and the PGOOD pin is released high if all the internal PG monitors are in regulation. In the event that one or more outputs are not in regulation by the time RESETBMCU is ready to de-assert, the PGOOD pin is held low and the PF8121 performs the corresponding fault protection mechanism as described in Section 14.7.1 "Fault monitoring during power up state". PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

14.9.9 VSELECT

VSELECT is an input pin used to select the output voltage of LDO2 when bit VSELECT_EN = 1.

When VSELECT pin is low, the LDO2 output is programmed to 3.3 V.
When VSELECT pin is high, the LDO2 output is programmed to 1.8 V. When VSELECT_EN = 0, the output of LDO2 is given by the VLDO2_RUN[3:0] bits. When the PF8121 is in the standby mode, the output voltage of LDO2 follows the configuration as selected by the VLDO2_STBY[3:0] bits, regardless of the value of VSELECT_EN bit. The default value of the VSELECT_EN bit is programmed by the OTP_VSELECT_EN bit in the OTP fuses. A read only bit is provided to monitor the actual state of the VSELECT pin. When the VSELECT pin is low, the VSELECT_S bit is 0 and when the VSELECT pin is high, the VSELECT_S bit is set to 1.

14.9.10 LDO2EN

LDO2EN is an input pin used to enable or disable LDO2 when the bit LDO2HW_EN = 1. mode or the LDO2_STBY_EN bit in the standby mode. Table 32. LDO control in run or standby mode The default controlling mode for LDO2 is programed by the OTP_LDO2HW_EN bit in the OTP fuses. LDO2EN_S bit is 0 and when the LDO2EN pin is high, the LDO2EN_S bit is set to 1.

14.9.11 FSOB (fault status output)

The FSOB pin is intended to operate in fault status mode. A bit is provided to enable the FSOB to be asserted when a regulator fault (OV, UV, ILIM) is present.

If FSOB_SOFTFAULT = 0, the FSOB pin is not asserted by any OV, UV, or ILIM fault.
If FSOB_SOFTFAULT = 1, an OV, UV, or ILIM fault on any of the regulators causes the FSOB pin to assert and remain asserted regardless of it being corrected or not, and also asserts the FSOB_SFAULT_NOK flag. A bit is provided to enable the FSOB to be asserted when a WD reset occurs due to a WDI event. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

12-channel power management integrated circuit for high performance applications

If FSOB_WDI = 0, the FSOB pin is not asserted by a WDI event.
If FSOB_WDI = 1, a WDI event causes the FSOB pin to assert and the FSOB_WDI_NOK flag to be set. A bit is provided to enable the FSOB to be asserted when a WD reset occurs due to an internal WD counter fault is present.
If FSOB_WDC = 0, the FSOB pin is not asserted by a WD reset started by the internal WD counter.
If FSOB_WDC = 1, a WD reset is started by the internal WD counter causing the FSOB pin to be asserted and the FSOB_WDC_NOK flag to be set. A bit is provided to enable the FSOB to be asserted when a hard fault shutdown has occurred.
If FSOB_HARDFAULT = 0, the FSOB pin is not asserted by a hard fault.
If FSOB_HARDFAULT = 1, any of the hard fault shutdown events cause the FSOB pin to be asserted and the FSOB_HFAULT_NOK flag to be set. Any of the following events are considered a hard fault shutdown:
Fault timer expired
FAULT_CNT = FAULT_MAX_CNT (regulator fault counter max out)
WD_EVENT_CNT = WD_MAX_CNT (watchdog event counter max out)
Power up failure
Thermal shutdown The FSOB pin is released when all the FSOB fault flags are cleared or VIN falls below the UVDET threshold. If the secure I2C write mechanism is enabled, all FSOB flags require a secure write to be cleared (write 1 to clear).

14.9.12 TBBEN

The TBBEN is an input pin provided to allow the user to program the mirror registers in order to operate the device with a custom configuration as well as programming the default values on the OTP fuses.

When TBBEN pin is pulled low to ground, the device is operating in normal mode.
When TBBEN pin is pulled high to V1P5D device enables the TBB configuration mode. See Section 17 "OTP/TBB and default configurations" for details on TBB and OTP operation. When TBBEN pin is pulled high to V1P5D the following conditions apply:
The device uses a fixed I2C device address (0x08)
Disable the watchdog operation, including WDI monitoring and internal watchdog timer
Disable the CRC and I2C secure write mechanism while no power up event is present (TBB/OTP programming mode). Disabling the watchdog operation may be required for in-line MCU programming where output voltages are required but watchdog operation should be completely disabled.

14.9.13 XFAILB

XFAILB is a bidirectional pin with an open drain output used to synchronize the power up and power down sequences of two or more PMIC's. It should be pulled up externally to V1P5A supply. The OTP_XFAILB_EN bit is used to enable or disable the XFAILB mode of operation.

When OTP_XFAILB_EN = 0, the XFAILB mode is disabled and any events on this pin are ignored
When OTP_XFAILB_EN = 1, the XFAILB mode is enabled PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

XFAILB pin is asserted low 20 µs before starting the power down sequence.

Fault timer expired
FAULT_CNT = FAULT_MAX_CNT (regulator fault counter max out)
WD_EVENT_CNT = WD_MAX_CNT (watchdog event counter max out)
Power up failure
Thermal shutdown
Hard WD event The XFAILB pin is forced low during the off mode. During the system-on states, if the XFAILB pin is externally pulled low, it will detect an XFAIL event after a 20 µs debounce. When an XFAIL event is detected, the XFAILB pin is asserted low internally and the device starts a power down sequence. If a PWRON event is present, the device starts a turn on event and proceeds to release the XFAILB pin when its ready to start the power up sequence state. If the XFAILB pin is pulled down externally during the power up event, the PF8121 will stop the power up sequence until the pin is no longer pulled down externally. This will help both PMIC's to synchronize the power up sequence allowing it to continue only when both PMIC's are ready to initiate the power up sequence. A hard WD event will set the XFAILB pin 20 µs before it starts its power down sequence. After all regulators outputs have been turned off, the device will release the XFAILB pin internally after a 30 µs delay, proceed to load the default OTP configuration and wait for the XFAILB pin to be released externally before it can restart the power up sequence. aaa-029215 bidirectional XFAILB (power up) power up sequence system onQPU_OffLP_Off self-test RESETBMCU XFAILB POWER UP sequence states PWRON

Figure 21. External XFAILB event during a power up sequence

14.9.14 SDA and SCL (I2C bus)

3.4 MHz I2C speed is required. address is set by the OTP_I2C_ADD[2:0]. Table 33. I2C address configuration communication protocol implementation. not provide an ACK bit to the MCU. To prevent a wrong I2C configuration, various protective mechanisms are implemented. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

14.9.14.1 I2C CRC verification

When this feature is enabled, a selectable CRC verification is performed on each I2C transaction.

When OTP_I2C_CRC_EN = 0, the CRC verification mechanism is disabled.
When OTP_I2C_CRC_EN = 1, the CRC verification mechanism is enabled. After each I2C transaction, the device calculates the corresponding CRC byte to ensure the configuration command has not been corrupted. When a CRC fault is detected, the PF8121 ignores the erroneous configuration command and triggers a CRC_I interrupt asserting the INTB pin, provided the interrupt is not masked. The PF8121 implements a CRC-8-SAE, per the SAE J1850 specification.
Polynomial = 0x1D
Initial value = 0xFF aaa-028696 MSB Data 6 5 4 1 03 I2C CRS Polynominal Seed: 1 1 1 1 1 1 1 1

15 Functional blocks

15.1 Analog core and internal voltage references

directly dependent on the performance of the bandgap. PF8121 to provide a reliable way to detect not only single point, but also latent faults. Table 34. Internal supplies electrical characteristics

15.2 Coin cell charger

current charger available at the LICELL pin.

When COINCHG_EN = 0 the coin cell charger is disabled in run or standby modes.
When COINCHG_EN = 1 the coin cell charger is enabled in run or standby modes. The COINCHG_EN bit is reset to 0, when VIN crosses the UVDET threshold. During the run mode, the coin cell charger utilizes a 60 µA charging current. If enabled during standby mode, the coin cell charger utilizes only a 10 µA charging current to be able to maintain low power consumption while still being able to maintain the backup battery voltage charged at all time. The COINCHG_OFF bit is used to enable or disable the coin cell charger during the QPU_Off state via I2C. In this mode, the charger utilizes a 10 µA charging current.
When COINCHG_OFF = 0 the coin cell charger is disabled in QPU_Off state.
When COINCHG_OFF = 1 the coin cell charger is enabled in QPU_Off state. If the system requires to allow charging of the coin cell during the QPU_Off, the system should enable the COINCHG_OFF bit during the run mode and the charger turns on during the QPU_Off state, if programmed to stay in this state after power down. The COINCHG_OFF bit is reset to 0, when VIN crosses the UVDET threshold. The VCOIN[3:0] bits set the target charging voltage for the LICELL pin as shown in the table below. The OTP_VCOIN[3:0] bits are used to set the default voltage for the coin cell battery charger. VCOIN[3:0] Target LICELL voltage (V) 0000 1.8

Table 35. Coin cell charger voltage level...continued are specified for TA = 25 ºC, VIN = 5.0 V, typical external components, unless otherwise noted. Table 36. Coin cell electrical characteristics

15.3 VSNVS LDO/switch

VSNVS is a 10 mA LDO/switch provided to power the RTC domain in the processor.

Coin cell was applied for the first time before VIN power up.
Coin cell is not present upon VIN power up.
Coin cell has been present after a previous power cycle.

gets loaded with the OTP fuse configuration. regulation point after OTP fuses are loaded. configuration bit, it will always be reset to the default value after a VIN power cycle. When VIN < VWARNTH, a best of supply circuit decides whether VSNVS is powered by VIN or LICELL.

When VIN is rising and VIN > UVDET, VSNVS is powered by VIN. When operating from VIN, it can regulate the output to 1.8 V, 3.0 V or 3.3 V. If the configured output voltage is higher than the input source, the VSNVS operates in dropout mode to track the input voltage.
When operating from LICELL, it regulates the output when the output voltage is selected at 1.8 V. VSNVS operates as a switch from LICELL when the output voltage setting is selected to 3.0 V or 3.3 V. The following table shows the expected operation of the VSNVS block for different voltage settings and different input voltage conditions. OTP_VSNVSVOLT[1:0] VSNVS output voltage (V) VIN Expected VSNVS output

00 Disabled Do not care VSNVS is disabled on OTP

Table 37. VSNVS operation description [1] Regulator is in drop off mode, if input is not enough to regulate to set point. Figure 23. VSNVS block diagram has been configured by the OTP_VSNVSVOLT[1:0] registers. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 38. VSNVS output voltage configuration the VSNVSVOLT[1:0] bits in the functional I2C registers. Table 39. VSNVS electrical characteristics

15.4 Type 1 buck regulators (SW1 to SW6)

Figure 24. Buck regulator block diagram sequence as well as the DVS slope during the system on. by changing the SWxDVS_RAMP bit on the I2C register map.

0 Slow DVS ramp

1 Fast DVS ramp

Table 40. DVS ramp speed configuration The DVS ramp rate is based on the internal clock configuration as shown in Table 41. All ramp rates are typical values. Clock frequency tolerance = ± 6 %. Table 41. Ramp rates PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

All ramp rates are typical values. Clock frequency tolerance = ± 6 %. Table 41. Ramp rates...continued Type 1 Buck regulators use 8 bits to set the output voltage.

The VSWx_RUN[7:0] set the output voltage during the run mode.
The VSWx_STBY[7:0] set the output voltage during the standby mode. The default output voltage configuration for the run and the standby modes is loaded from the OTP_VSWx[7:0] registers upon power up. Set point VSWx_RUN[7:0] VSWx_STBY[7:0] VSWxFB (V) 0 00000000 0.40000 1 00000001 0.40625 2 00000010 0.41250 3 00000011 0.41875 175 10101111 1.49375 176 10110000 1.50000 177 10110001 1.80000 178 to 255 10110010 to 11111111 Reserved

Table 42. Output voltage configuration Each regulator is provided with two bits to set its mode of operation.

The SWx_RUN_MODE[1:0] bits allow the user to change the mode of operation of the SWx regulators during the run state. If the regulator was programmed as part of the power up sequence, the SWx_RUN_MODE[1:0] bits are loaded with 0b11 (autoskip) by default. Otherwise, it is loaded with 0b00 (disabled).
The SWx_STBY_MODE[1:0] bits allow the user to change the mode of operation of the SWx regulators during the standby state. If the regulator was programmed as part of the power up sequence, the SWx_STBY_MODE[1:0] bits are loaded with 0b11 (autoskip) by default. Otherwise, it is loaded with 0b00 (disabled). SWx_MODE[1:0] Mode of operation

00 OFF

01 PWM mode

10 PFM mode

11 Autoskip mode

operation, provided the corresponding interrupt is not masked. regulator in PWM or autoskip mode. The type 1 buck regulators use 2 bits SWxILIM[1:0], to program the current limit detection. Table 44. SWx current limit selection where L is the inductance value and FSW is the selected switching frequency. in order to account for component tolerances, use the minimum inductor value per the inductor specification. modified during the system-on states. Table 45. SWx phase configuration corresponding block. The OTP_SWx_LSELECT[1:0] allow to choose the inductor as shown in Table 46. Table 46. SWx inductor selection bits PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 46. SWx inductor selection bits...continued

15.4.1 SW6 VTT operation

SW6 features a selectable VTT mode to create VTT termination for DDR memories. to SW5FB output through a divider by 2. regulation range at its output. required by the system. When SW6 and SW5 are enabled in the same slot, SW6 will always track the VSW5/2. voltage on the SW5 regulator by setting the OTP_VSW6 register accordingly. commands, the SW5 output will ramp-up to the corresponding voltage while SW6 is always VSW5/2. is disabled with the output in high impedance or discharged internally.

When OTP_VTT_PDOWN = 0, the output is disabled in high impedance mode.
When OTP_VTT_PDOWN = 1, the output is disabled with the internal pull down enabled. When SW6 is requested to enable back again, the SW6 will ramp-up to the voltage set on the VSW6_RUN or VSW6_STBY registers. Once it reaches the final DVS value, it will change its reference to start tracking SW5 output again. Note that VSW6_RUN(STBY) must be set to VSW5_RUN(STBY)/2 or the closest code by the MCU to ensure proper operation. When operating in VTT mode, the minimum output voltage configuration for SW5 should be 800 mV to ensure the SW6 is still within the regulation range at its output.

15.4.2 Multiphase operation

phase can be independently set via the corresponding SWxPHASE[1:0] bits. phase can be independently set via the corresponding SWxPHASE[1:0] bits. When SW1 to SW3 are configured in triple phase, the SW4 operates in single phase. phase can be independently set via the corresponding SWxPHASE[1:0] bits. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

or quad phase configuration.

00 SW1 and SW2 operate in single phase mode

01 SW1/SW2 operate in dual phase mode

10 SW1/SW2/SW3/SW4 operate in quad phase mode

11 SW1/SW2/SW3 operate in triple phase mode

Table 47. OTP_SW1CONFIG register description resulting voltage rail, however the two FB pins should be connected together. In dual phase operation, each phase can be independently set via the corresponding SWxPHASE[1:0] bits. The OTP_SW4CONFIG[1:0] bits are used to select the dual phase operation of SW3/SW4.

00 SW3 and SW4 operate in single phase mode

01 SW3/SW4 operate in dual phase mode

10 Reserved

Table 48. OTP SW4CONFIG register description the OTP_SW4CONFIG[1:0] bits. resulting voltage rail, however the two FB pins should be connected together. In dual phase operation, each phase can be independently set via the corresponding SWxPHASE[1:0] bits. The OTP_SW5CONFIG[1:0] bits are used to select single or dual phase configuration for SW5/SW6.

00 SW5 and SW6 operate in single phase mode

01 SW5/SW6 operate in dual phase mode

Figure 27. Quad phase configuration

15.4.3 Electrical characteristics

All parameters are specified at TA = −40 to 85 °C, VSWxIN = UVDET to 5.5 V, VSWxFB = 1.0 V, ISWx = 500 mA, typical external component values, fSW = 2.25 MHz, unless otherwise noted. Typical values are characterized at VSWxIN = 5.0 V, VSWxFB = 1.0 V, ISWx = 500 mA, and TA = 25 °C, unless otherwise noted. fully functional with degraded operation due to headroom limitation. on/off ramp rate to ensure the output is discharged completely when it is disabled. prevent reaching PMIC thermal shutdown during high ambient temperature conditions. efficiency percentage in PWM operation. [5] Max RDS(on) does not include bondwire resistance. Consider +50 % tolerance to account for bondwire and pin loss. Table 51. Recommended external components [1] Keep inductor DCR as low as possible to improve regulator efficiency. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

15.5 Type 2 buck regulator (SW7)

Figure 28. Type 2 buck regulator block diagram as stated in the VSW7[4:0] bits. Table 52. SW7 output voltage configuration PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 52. SW7 output voltage configuration...continued Regulator SW7 is provided with two bits to set its mode of operation.

The SW7_RUN_MODE[1:0] bits allow the user to change the mode of operation of the SW7 regulators during the run state. If the regulator was programmed as part of the power up sequence, the SW7_RUN_MODE[1:0] bits are loaded with 0b11 (autoskip) by default. Otherwise, it is loaded with 0b00 (disabled).
The SW7_STBY_MODE[1:0] bits allow the user to change the mode of operation of the SW7 regulators during the standby state. If the regulator was programmed as part of the power up sequence, the SW7_STBY_MODE[1:0] bits are loaded with 0b11 (autoskip) by default. Otherwise it is loaded with 0b00 (disabled). SW7_MODE[1:0] Mode of operation

Table 53. SW7 regulator mode configuration provided the corresponding interrupt is not masked. regulator is enabled/disabled by the corresponding SW7_RUN_MODE[1:0] or SW7_STBY_MODE[1:0] bits. The SW7ILIM [1:0] bits are used to program the current limit detection level of SW7. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 54. SW7 current limit selection where L is the inductance value and FSW is the selected switching frequency. in order to account for component tolerances, use the minimum inductor value per the inductor specification. up, the switching phase is defaulted to 0 degrees and can be modified during the system-on states. Table 55. SW7 phase configuration OTP_SW7_LSELECT[1:0] allow to choose the inductor as shown in the following table. Table 56. SW7 inductor selection bits PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

15.5.1 Electrical characteristics

Table 57. Type 2 buck regulator electrical characteristics...continued [1] VSW7IN must be connected to VIN to ensure proper operation. shutdown during high ambient temperature conditions. [3] Max RDS(on) does not include bondwire resistance. Consider +50 % tolerance to account for bondwire and pin losses. Table 58. Recommended external components [1] Keep inductor DCR as low as possible to improve regulator efficiency.

15.6 Linear regulators

400 mA current capability
Input voltage range from 2.5 V to 5.5 V
Programmable output voltage between 1.5 V and 5.0 V
Soft-start ramp control during power up (enable)
Discharge mechanism during power down (disable)
OTP programmable Load switch mode PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

Figure 29. LDOx regulator block diagram supply pin, LDO3IN and LDO4IN respectively. The four LDOs are provided with one bit to enable or disable its output during the system-on states.

When LDOx_RUN_EN = 0, the LDO is disabled during the run mode. If the regulator is part of the power up sequence, this bit is set during the power up sequence. Otherwise it is defaulted to 0.
When LDOx_STBY_EN = 0, the LDO is disabled during the standby mode. If the regulator is part of the power up sequence, this bit is set during the power up sequence. Otherwise it is defaulted to 0. The mode of operation of the LDOx is selected on OTP via the OTP_LDOxLS bit. LDOx_RUN_EN / LDOx_STBY_EN OTP_LDOxLS LDO operation mode (Run or standby mode)

0 X Disabled with output pull down active

Table 59. LDO operation description The LDOs use four bits to set the output voltage.

The VLDOx_RUN[3:0] sets the output voltage during the run mode.
The VLDOx_STBY[3:0] sets the output voltage during standby mode. The default output voltage configuration for the run and the standby mode is loaded from the OTP_VLDOx[3:0] registers on power up. Set point VLDOx_RUN[3:0] VLDOx_STBY[3 :0] VLDOx output (V) 0 0000 1.5 1 0001 1.6 2 0010 1.8 3 0011 1.85 4 0100 2.15

Table 60. LDO output voltage configuration...continued

15.6.1 LDO load switch operation

When the LDO regulator is set in Load switch mode, the LDOxEN bit is used to enable or disable the switch.

15.6.2 LDO regulator electrical characteristics

noted. Typical values are characterized at VLDOxIN = 5.5 V, VLDOx = 1.8 V, ILDOx = 100 mA, and TA = 25 °C, unless otherwise noted. Table 61. LDO regulator electrical characteristics PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

noted. Typical values are characterized at VLDOxIN = 5.5 V, VLDOx = 1.8 V, ILDOx = 100 mA, and TA = 25 °C, unless otherwise noted. Table 61. LDO regulator electrical characteristics...continued [1] Max RDS(on) does not include bondwire resistance. Consider 40 % tolerance to account for bondwire and pin loses.

15.7 Voltage monitoring

15.7.1 OV/UV configuration

SW1 to SW7
LDO1 to LDO4 A programmable UV threshold is selected via the OTP_SWxUV_TH[1:0] and OTP_LDOxUV_TH[1:0] bits. UV threshold selection represents a percentage of the nominal voltage programmed on each regulator. OTP_SWxUV_TH[1:0] OTP_LDOxUV_TH[1:0] UV threshold level 00 95 % 01 93 % 10 91 % 11 89 %

threshold selection represents a percentage of the nominal voltage programmed on each regulator. Table 63. OV threshold configuration register Two functional bits are provided to program the UV debounce time for all the voltage regulators. Table 64. UV debounce timer configuration Two functional bits to program the OV debounce time for all the voltage regulators. Table 65. OV debounce timer configuration

When the VMON_EN bit of a specific regulator is 1, the voltage monitor for that specific regulator is enabled.
When the VMON_EN bit of a specific regulator is 0, the voltage monitor for that specific regulator is disabled. By default, the VMON_EN bits are set to 1 on power up. When the I2C_SECURE_EN = 1, a secure write must be performed to set or clear the VMON_EN bits to enable or disable the voltage monitoring for a specific regulator. On enabling a regulator, the UV/OV monitor is masked until the corresponding regulator reaches the point of regulation. If a voltage monitor is disabled, the UV_S and OV_S indicators from that monitor are reset to 0.

15.7.2 Output voltage monitoring with dedicated bandgap reference

12-channel power management integrated circuit for high performance applications bandgap is performed. A 4 % to 12 % difference between the two bandgaps is an indicator of a potential regulation or monitoring fault and is considered as a critical issue. Therefore, the device prevents the switching regulators from powering up. If a drift between the two bandgaps is detected during system-on states:

with OTP_BGMON_BYPASS = 0, the power stage of the voltage regulators will be shutdown
with OTP_BGMON_BYPASS = 1, the bandgap monitor only sends an interrupt to the system to announce the bandgap failure The BGMON_I is asserted when a bandgap failure occurs, provided it is not masked. The BGMON_S bit is set to 0 when the bandgaps are within range, and set to 1 when the bandgaps are out of range. Figure 30 shows the PF8121 voltage monitoring architecture. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

15.7.3 Electrical characteristics

Regulator), 3.3 V (Type 2 Buck regulator, LDO Regulator), and TA = 25 °C, unless otherwise noted. Table 66. VMON Electrical characteristics

15.8 Clock management

Low power 100 kHz clock
Internal high frequency clock with programmable frequency
Phase Locked Loop (PLL) PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

A digital clock management interface is in charge of supporting interaction among these blocks. shifting for multiple phase operation.

1 OR 6

20 MHz ± 20 % 16 to 24 MHz

Figure 31. Clock management architecture

15.8.1 Low frequency clock

are based on this 100 kHz clock.

15.8.2 High frequency clock

programmable over a range of ±20 % via the CLK_FREQ[3:0] control bits.

15.8.3 Manual frequency tuning

CLK_FREQ [3:0] bits allow a manual frequency tuning of the high frequency clock from 16 MHz to 24 MHz. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

0101 Not used Not used

0110 Not used Not used

0111 Not used Not used

1000 Not used Not used

1101 Not used Not used

1110 Not used Not used

1111 Not used Not used

Table 67. Manual frequency tuning configuration The default switching frequency is set by the OTP_CLK_FREQ[3:0] bits. Manual tuning cannot be applied when frequency spread-spectrum or external clock synchronization is used. match the external frequency as close as possible.

15.8.4 Spread-spectrum

wide spread to help manage EMC in the automotive applications.

When the FSS_EN = 1, the frequency spread-spectrum is enabled.
When the FSS_EN = 0, the frequency spread-spectrum is disabled. The default state of the FSS_EN bit upon a power up can be configured via the OTP_FSS_EN bit. The FSS_RANGE bit is provided to select the clock frequency range.
When FSS_RANGE = 0, the maximum clock frequency range is ±5 %.
When FSS_RANGE = 1, the maximum clock frequency range is ±10 %. The default value of the FSS_RANGE bit upon a power up can be configured via the OTP_FSS_RANGE bit. The frequency spread-spectrum is performed at a 24 kHz modulation frequency when the internal high frequency clock is used to generate the switching frequency for the switching regulators. When the external clock synchronization is enabled, the spread-spectrum is disabled. Figure 32 shows implementation of spread-spectrum for the two settings. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

Figure 32. Spread-spectrum waveforms clock synchronization at all time. of the value of the FSS_EN bit.

15.8.5 Clock Synchronization

An external clock can be fed via the SYNCIN pin to synchronize the switching regulators to this external clock. the main frequency for the switching regulators. the PMIC has started, the SYNCIN pin must be maintained low until the external clock is applied. range set by the FSYNC_RANGE bit.

When the FSYNC_RANGE = 0, the input frequency range at SYNCIN pin should be between 2000 kHz and 3000 kHz. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

When the FSYNC_RANGE = 1, the input frequency range at SYNCIN pin should be between 333 kHz and 500 kHz. The OTP_FSYNC_RANGE bit is used to select the default frequency range accepted in the SYNCIN pin. The external clock duty cycle at the SYNCIN pin should be between 40 % and 60 %. An input frequency in the SYNCIN pin outside the range defined by the FSYNC_RANGE bit is detected as invalid. If the external clock is not present or invalid, the device automatically switches to the internal clock and sets the FSYNC_FLT_I interrupt, which in turn asserts the INTB pin provided it is not masked. The FSYNC_FLT_S bit is set to 1 as long as the input frequency is not preset or invalid, and it is cleared to 0 when the SYNCIN has a valid input frequency. The device switches back to the external switching frequency only when both, the FSYNC_FLT_I interrupt has been cleared and the SYNCIN pin sees a valid frequency. When the external clock is selected, the switching regulators should be set in PWM mode to ensure clock synchronization at all time. Upon an external clock failure, the MCU must proof the integrity of the external clock by implementing a three- step diagnostic strategy. 1. MCU acknowledges and finds the source of the interrupt event. 2. After deciding the interrupt is generated by the FSYNC_FLT_I event, the MCU reads the FSYNC_FLT_S bit to verify if the fault condition is persistent or not. 3. a. If FSYNC_FLT_S bit is 0, the fault condition can be considered a transient condition and the system is ready to switch over to the external clock by clearing the FSYNC_FLT_I flag. b. If the FSYNC_FLT_S bit is 1, the fault is considered a persistent fault and the MCU must take corrective action to send the system to safe operation. The system designer is responsible to define the tolerance time to allow the external frequency to be lost before taking a corrective action such as stopping the system. The SYNCOUT pin is used to synchronize an external device to the PF8121. The SYNCOUT pin outputs the main frequency used for the switching regulators in the range of 2.0 MHz to 3.0 MHz. The SYNCOUT_EN bit can be used to enable or disable the SYNCOUT feature via I2C during the system- on states.
When SYNCOUT_EN = 0, the SYNCOUT feature is disabled and the pin is internally pulled to ground.
When SYNCOUT_EN = 1, the SYNCOUT pin toggles at the base frequency used by the switching regulators. The SYNCOUT function can be enabled or disabled by default by using the OTP_SYNCOUT_EN bit. All parameters are specified at TA = −40 to 85 °C, unless otherwise noted. Typical values are characterized at VIN = 5.0 V and TA = 25 °C, unless otherwise noted. Symbol Parameter Min Typ Max Unit Low frequency clock IQ100KHz 100 kHz clock quiescent current — — 3.0 µA f100KHzACC 100 kHz clock accuracy −5.0 — 5.0 % High frequency clock f20MHz High frequency clock nominal frequency via CLK_FREQ[3:0] = 0000 MHz f20MzACC High frequency clock accuracy −6.0 — 6.0 %

Table 68. Clock management specifications...continued

15.9 Thermal monitors

Center of die 6. Vicinity of SW5
Vicinity of SW1 7. Vicinity of SW6
Vicinity of SW2 8. Vicinity of SW7
Vicinity of SW3 9. Vicinity of LDO1-2
Vicinity of SW4 10. Vicinity of LDO3-4

temperature exceeds desired limits at any point in the die. Figure 33 shows a high level block diagram of the thermal monitoring architecture in PF8121. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 33. Thermal monitoring architecture Table 69. Thermal monitor specifications on the corresponding AMUX channel. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 34. Thermal sensor voltage characteristics As the temperature crosses the thermal thresholds, the corresponding interrupts are set to notify the system. regulators, reducing load, or turning on a fan). turning back on until the 15 ºC thermal shutdown hysteresis is crossed as the device cools down. The temperature monitor can be enabled or disabled via I2C with the TMP_MON_EN bit.

When TMP_MON_EN = 0, the temperature monitor circuit is disabled.
When TMP_MON_EN = 1, the temperature monitor circuit is enabled. In the run state, the temperature sensor can operate in always on or sampling modes.
When the TMP_MON_AON = 1, the device is always on during the run mode.
When the TMP_MON_AON = 0, the device operates in sampling mode to reduce current consumption in the system. In sampling mode, the thermal monitor is turned on during 450 µs at a 3.0 ms sampling interval. In the standby mode, the thermal monitor operates only in sampling mode as long as the TMP_MON_EN = 1 Bit(s) Description THERM_80_I, THERM_80_S, THERM_80_M Interrupt, sense and mask bits for 80 ºC threshold THERM_95_I, THERM_95_S, THERM_95_M Interrupt, sense and mask bits for 95 ºC threshold THERM_110_I, THERM_110_S, THERM_110_M Interrupt, sense and mask bits for 110 ºC threshold THERM_125_I, THERM_125_S, THERM_125_M Interrupt, sense and mask bits for 125 ºC threshold THERM_140_I, THERM_140_S, THERM_140_M Interrupt, sense and mask bits for 140 ºC threshold THERM_155_I, THERM_155_S, THERM_155_M Interrupt, sense and mask bits for 155 ºC threshold TMP_MON_EN Disables temperature monitoring circuits when cleared TMP_MON_AON When set, the temperature monitoring circuit is always ON. When cleared, the temperature monitor operates in sampling mode.

15.10 Analog multiplexer

When the AMUX_EN bit is 0, the AMUX block is disabled and the output remains pulled down to ground. using the AMUX_SEL[4:0] bits.

0 X XXXX AMUX disabled and pin pulled-down to

Table 71. AMUX channel selection V, However, the AMUX pin is clamped to a maximum 2.5 V. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 72. AMUX specifications

15.11 Watchdog event management

The WDI pin toggles low due to a watchdog failure on the MCU
The internal watchdog expiration counter reach the maximum value the WD timer is allowed to expire A watchdog event initiated by the WDI pin may perform a hard WD reset or a soft WD reset as defined by the WDI_MODE bit. A watchdog event initiated by the internal watchdog always performs a hard WD reset.

15.11.1 Internal watchdog timer

The internal WD timer counts up and it expires when it reaches the value in the WD_DURATION[3:0] register. a 1 to clear the WD_CLEAR flag. RESETBMCU is deasserted in the next power up sequence. ms and 32768 ms (typical values). Table 73. Watchdog duration register PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Table 73. Watchdog duration register...continued WD_EXPIRE_CNT[2:0] is increased by 2. soon as the WD Timer expires for the first time. The OTP_WDWINDOW bit selects whether the watchdog is singled ended or window mode.

When OTP_WDWINDOW = 0, the WD_CLEAR flag can be cleared within 100 % of the watchdog timer.
When OTP_WDWINDOW = 1, the WD_CLEAR flag can only be cleared within the second half of the programmed watchdog timer. Clearing the WD_CLEAR flag within the first half of the watchdog window is interpreted as a failure to refresh the watchdog. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

Figure 35. Watchdog timer operation I2C_SECURE_EN = 1, a secure write must be performed to change the WD_EN bit.

When WD_EN = 0 the internal watchdog timer operation is disabled.
When WD_EN = 1 the internal watchdog timer operation is enabled. The OTP_WD_EN bit is used to select the default status of the watchdog counter upon power up. The watchdog function can be programmed to be enabled or disabled during the standby state by writing the WD_STBY_EN bit on the I2C register map. When the I2C_SECURE_EN = 1, a secure write must be performed to modify the WD_STBY_EN bit.
When WD_STBY_EN = 0 the internal watchdog timer operation during standby is disabled.
When WD_STBY_EN = 1 the internal watchdog timer operation during standby is enabled. The OTP_WD_STBY_EN bit selects whether the watchdog is active in standby mode by default or not.

15.11.2 Watchdog reset behaviors

Soft WD reset
Hard WD reset A soft WD reset is used as a safe way for the MCU to force the PMIC to return to a known default configuration without forcing a POR Reset on the MCU. During a soft WH reset, the RESETBMCU remains deasserted all the time. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

Upon a soft WD reset, a partial OTP register re-load is performed on the registers as shown in Table 74. Table 74. Soft WD register reset for each regulator (SWx_WDBYPASS / LDOx_WDBYPASS).

When the WDBYPASS = 0, the watchdog bypass is disabled and the output of the corresponding regulator is returned to its default OTP value during the soft WD reset.
When the WDBYPASS = 1, the watchdog bypass is enabled and the output of the corresponding regulator is not affected by the soft WD reset, keeping its current configuration. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

voltage configuration if their corresponding WDBYPASS = 0. during the power up sequence will turn off immediately. provided the WDI_I interrupt is not masked. Figure 36. Soft WD reset behavior scenario, a full OTP register reset is performed. also be disabled accordingly. sequence if the XFAILB pin is not held low externally. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 37. Hard WD reset behavior After a WD reset, the PMIC may enter the standby state depending on the status of STANDBY pin. failures, if the WD_EVENT_CNT[3:0] = WD_MAX_CNT[3:0] the state machine proceeds to the fault transition. counter has a fresh start after a device power down. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

12-channel power management integrated circuit for high performance applications

16 I2C register map

The PF8121 provides a complete set of registers for control and diagnostics of the PMIC operation. The configuration of the device is done at two different levels. At first level, the OTP Mirror registers provide the default hardware and software configuration for the PMIC upon power up. These are one time programmable and should be defined during the system development phase, and are not meant to be modified during the application. See Section 17 "OTP/TBB and default configurations" for more details on the OTP configuration feature. At a second level, the PF8121 provides a set of functional registers intended for system configuration and diagnostics during the system operation. These registers are accessible during the system-on states and can be modified at any time by the System Control Unit. The device ID register provides general information about the PMIC.

DEVICE_FAM[3:0]: indicates the PF8x00 family of devices 0100 (fixed)
DEVICE_ID[3:0]: provides the device type identifier 0010 = PF8121 Registers 0x02 and 0x03 provide a customizable program ID registers to identify the specific OTP configuration programmed in the part.
EMREV (Address 0x02): contains the MSB bits PROG_ID[8:11]
PROG_ID (Address 0x03): contains the LSB bit PROG_ID[7:0] PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

12-channel power management integrated circuit for high performance applications

16.1 PF8121 functional register map

UVDET Reset when VIN crosses UVDET threshold R Read only OFF_OTP Bits are loaded with OTP values (mirror register) R/W Read and Write OFF_TOGGLE Reset when device goes to OFF mode RW1C Read, Write a 1 to clear SC Self-clear after write R/SW Read/Secure Write NO_VSNVS Reset when BOS has no valid input VIN < UVDET and coin cell < 1.8 V (VSNVS not present) R/TW Read/Write on TBB only ADDR Register name R/W BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

00 DEVICE ID R DEVICE_FAM[3:0] DEVICE_ID[3:0]

01 REV ID R FULL_LAYER_REV[3:0] METAL_LAYER_REV[3:0]

02 EMREV R PROG_ID[11-8] — EMREV[2:0]

03 PROG ID R PROG_ID[7:0]

04 INT STATUS1 RW1C SDWN_I FREQ_RDY_I CRC_I PWRUP_I PWRDN_I XINTB_I FSOB_I VIN_OVLO_I

05 INT MASK1 R/W SDWN_M FREQ_RDY_M CRC_M PWRUP_M PWRDN_M XINTB_M FSOB_M VIN_OVLO_M

06 INT SENSE1 R — — — — — XINTB_S FSOB_S VIN_OVLO_S

07 THERM INT RW1C WDI_I FSYNC_FLT_I THERM_155_I THERM_140_I THERM_125_I THERM_110_I THERM_95_I THERM_80_I 08 THERM MASK R/W WDI_M FSYNC_FLT_M THERM_155_M THERM_140_M THERM_125_M THERM_110_M THERM_95_M THERM_80_M

09 THERM SENSE R WDI_S FSYNC_FLT_S THERM_155_S THERM_140_S THERM_125_S THERM_110_S THERM_95_S THERM_80_S

0A SW MODE INT RW1C — SW7_MODE_I SW6_MODE_I SW5_MODE_I SW4_MODE_I SW3_MODE_I SW2_MODE_I SW1_MODE_I 0B SW MODE MASK R/W — SW7_MODE_M SW6_MODE_M SW5_MODE_M SW4_MODE_M SW3_MODE_M SW2_MODE_M SW1_MODE_M

12 SW ILIM INT RW1C — SW7_ILIM_I SW6_ILIM_I SW5_ILIM_I SW4_ILIM_I SW3_ILIM_I SW2_ILIM_I SW1_ILIM_I

13 SW ILIM MASK R/W — SW7_ILIM_M SW6_ILIM_M SW5_ILIM_M SW4_ILIM_M SW3_ILIM_M SW2_ILIM_M SW1_ILIM_M

14 SW ILIM SENSE R — SW7_ILIM_S SW6_ILIM_S SW5_ILIM_S SW4_ILIM_S SW3_ILIM_S SW2_ILIM_S SW1_ILIM_S

15 LDO ILIM INT RW1C — — — — LDO4_ILIM_I LDO3_ILIM_I LDO2_ILIM_I LDO1_ILIM_I

16 LDO ILIM MASK R/W — — — — LDO4_ILIM_M LDO3_ILIM_M LDO2_ILIM_M LDO1_ILIM_M

17 LDO ILIM SENSE R — — — — LDO4_ILIM_S LDO3_ILIM_S LDO2_ILIM_S LDO1_ILIM_S

18 SW UV INT RW1C — SW7_UV_I SW6_UV_I SW5_UV_I SW4_UV_I SW3_UV_I SW2_UV_I SW1_UV_I

19 SW UV MASK R/W — SW7_UV_M SW6_UV_M SW5_UV_M SW4_UV_M SW3_UV_M SW2_UV_M SW1_UV_M

1A SW UV SENSE R — SW7_UV_S SW6_UV_S SW5_UV_S SW4_UV_S SW3_UV_S SW2_UV_S SW1_UV_S 1B SW OV INT RW1C — SW7_OV_I SW6_OV_I SW5_OV_I SW4_OV_I SW3_OV_I SW2_OV_I SW1_OV_I 1C SW OV MASK R/W — SW7_OV_M SW6_OV_M SW5_OV_M SW4_OV_M SW3_OV_M SW2_OV_M SW1_OV_M 1D SW OV SENSE R — SW7_OV_S SW6_OV_S SW5_OV_S SW4_OV_S SW3_OV_S SW2_OV_S SW1_OV_S 1E LDO UV INT RW1C — — — — LDO4_UV_I LDO3_UV_I LDO2_UV_I LDO1_UV_I 1F LDO UV MASK R/W — — — — LDO4_UV_M LDO3_UV_M LDO2_UV_M LDO1_UV_M

20 LDO UV SENSE R — — — — LDO4_UV_S LDO3_UV_S LDO2_UV_S LDO1_UV_S

21 LDO OV INT RW1C — — — — LDO4_OV_I LDO3_OV_I LDO2_OV_I LDO1_OV_I

22 LDO OV MASK R/W — — — — LDO4_OV_M LDO3_OV_M LDO2_OV_M LDO1_OV_M

23 LDO OV SENSE R — — — — LDO4_OV_S LDO3_OV_S LDO2_OV_S LDO1_OV_S

24 PWRON INT RW1C BGMON_I PWRON_8S_I PWRON_4S_I PRON_3S_I PWRON_2S_I PWRON_1S_I PWRON_REL_I PWRON_PUSH_I

25 PWRON MASK R/W BGMON_M PWRON_8S_M PWRON_4S_M PRON_3S_M PWRON_2S_M PWRON_1S_M PWRON_REL_M PWRON_PUSH_M

26 PWRON SENSE R BGMON_S —s — — — — — PWRON_S

27 SYS INT R EWARN_I PWRON_I OV_I UV_I ILIM_I MODE_I STATUS2_I STATUS1_I

29 HARD FAULT

RW1C — — — — PU_FAIL WD_FAIL REG_FAIL TSD_FAIL 2A FSOB FLAGS R/SW — — — — FSOB_SFAULT_ NOK FSOB_WDI_ NOK FSOB_WDC_ NOK FSOB_HFAULT_ NOK 2B FSOB SELECT R/W — — — — FSOB_SOFTFAULT FSOB_WDI FSOB_WDC FSOB_HARDFAULT

30 TEST FLAGS R/TW — — — LDO2EN_S VSELECT_S — TRIM_NOK OTP_NOK

35 VMONEN1 R/SW — SW7VMON_EN SW6VMON_EN SW5VMON_EN SW4VMON_EN SW3VMON_EN SW2VMON_EN SW1VMON_EN

12-channel power management integrated circuit for high performance applications ADDR Register name R/W BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

36 VMONEN2 R/SW — — — — LDO4VMON_EN LDO3VMON_EN LDO2VMON_EN LDO1VMON_EN

37 CTRL1 R/SW VIN_OVLO_EN VIN_OVLO_SDWN WDI_MODE TMP_MON_EN WD_EN WD_STBY_EN WDI_STBY_ACTIVE —

38 CTRL2 R/W VIN_OVLO_DBNC[1:0] — TMP_MON_AON LPM_OFF STANDBYINV RUN_PG_GPO STBY_PG_GPO

39 CTRL3 R/W OV_DB[1:0] UV_DB[1:0] — — PMIC_OFF INTB_TEST

3A PWRUP CTRL R/W — PWRDWN_MODE PGOOD_PDGRP[1:0] RESETBMCU_PDGRP[1:0] SEQ_TBASE[1:0] 3C RESETBMCU PWRUP R/W RESETBMCU_SEQ[7:0] 3D PGOOD PWRUP R/W PGOOD_SEQ[7:0] 3E PWRDN DLY1 R/W GRP4_DLY[1:0] GRP3_DLY[1:0] GRP2_DLY[1:0] GRP1_DLY[1:0] 3F PWRDN DLY2 R/W — — — — — — RESETBMCU_DLY[1:0]

40 FREQ CTRL R/W SYNCOUT_EN FSYNC_RANGE FSS_EN FSS_RANGE CLK_FREQ[3:0]

41 COINCELL CTRL R/W — — COINCHG_EN COINCHG_OFF VCOIN[3:0]

42 PWRON R/W — — — PWRON_DBNC [1:0] PWRON_RST_EN TRESET[1:0]

43 WD CONFIG R/W — — — — WD_DURATION[3:0]

44 WD CLEAR R/W1C — — — — — — — WD_CLEAR

45 WD EXPIRE R/W — WD_MAX_EXPIRE[2:0] — WD_EXPIRE_CNT[2:0]

46 WD COUNTER R/W WD_MAX_CNT [3:0] WD_EVENT_CNT [3:0]

47 FAULT COUNTER R/W FAULT_MAX_CNT[3:0] FAULT_CNT [3:0]

49 FAULT TIMERS R/W — — — — TIMER_FAULT[3:0]

4A AMUX R/W — — AMUX_EN AMUX_SEL [4:0] 4D SW1 CONFIG1 R/W SW1_UV_ BYPASS SW1_OV_BYPASS SW1_ILIM_BYPASS SW1_UV_STATE SW1_OV_STATE SW1_ILIM_STATE SW1_WDBYPASS SW1_PG_EN 4E SW1 CONFIG2 R/W SW1_FLT_REN — SW1DVS_RAMP SW1ILIM[1:0] SW1PHASE[2:0] 4F SW1 PWRUP R/W SW1_SEQ[7:0]

50 SW1 MODE R/W — — SW1_PDGRP[1:0] SW1_STBY_MODE[1:0] SW1_RUN_MODE[1:0]

51 SW1 RUN VOLT R/W VSW1_RUN[7:0]

52 SW1 STBY VOLT R/W VSW1_STBY[7:0]

55 SW2 CONFIG1 R/W SW2_UV_

SW2_OV_BYPASS SW2_ILIM_BYPASS SW2_UV_STATE SW2_OV_STATE SW2_ILIM_STATE SW2_WDBYPASS SW2_PG_EN

56 SW2 CONFIG2 R/W SW2_FLT_REN — SW2DVS_RAMP SW2ILIM[1:0] SW2PHASE[2:0]

57 SW2 PWRUP R/W SW2_SEQ[7:0]

58 SW2 MODE1 R/W — — SW2_PDGRP[1:0] SW2_STBY_MODE[1:0] SW2_RUN_MODE[1:0]

59 SW2 RUN VOLT R/W VSW2_RUN[7:0]

5A SW2 STBY VOLT R/W VSW2_STBY[7:0] 5D SW3 CONFIG1 R/W SW3_UV_ BYPASS SW3_OV_BYPASS SW3_ILIM_BYPASS SW3_UV_STATE SW3_OV_STATE SW3_ILIM_STATE SW3_WDBYPASS SW3_PG_EN 5E SW3 CONFIG2 R/W SW3_FLT_REN — SW3DVS_RAMP SW3ILIM[1:0] SW3PHASE[2:0] 5F SW3 PWRUP R/W SW3_SEQ[7:0]

60 SW3 MODE1 R/W — — SW3_PDGRP[1:0] SW3_STBY_MODE[1:0] SW3_RUN_MODE[1:0]

61 SW3 RUN VOLT R/W VSW3_RUN[7:0]

62 SW3 STBY VOLT R/W VSW3_STBY[7:0]

65 SW4 CONFIG1 R/W SW4_UV_

SW4_OV_BYPASS SW4_ILIM_BYPASS SW4_UV_STATE SW4_OV_STATE SW4_ILIM_STATE SW4_WDBYPASS SW4_PG_EN

66 SW4 CONFIG2 R/W SW4_FLT_REN — SW4DVS_RAMP SW4ILIM[1:0] SW4PHASE[2:0]

67 SW4 PWRUP R/W SW4_SEQ[7:0]

68 SW4 MODE1 R/W — — SW4_PDGRP[1:0] SW4_STBY_MODE[1:0] SW4_RUN_MODE[1:0]

69 SW4 RUN VOLT R/W VSW4_RUN[7:0]

6A SW4 STBY VOLT R/W VSW4_STBY[7:0] 6D SW5 CONFIG1 R/W SW5_UV_ BYPASS SW5_OV_BYPASS SW5_ILIM_BYPASS SW5_UV_STATE SW5_OV_STATE SW5_ILIM_STATE SW5_WDBYPASS SW5_PG_EN 6E SW5 CONFIG2 R/W SW5_FLT_REN — SW5DVS_RAMP SW5ILIM[1:0] SW5PHASE[2:0] 6F SW5 PWRUP R/W SW5_SEQ[7:0]

70 SW5 MODE1 R/W — — SW5_PDGRP[1:0] SW5_STBY_MODE[1:0] SW5_RUN_MODE[1:0]

71 SW5 RUN VOLT R/W VSW5_RUN[7:0]

72 SW5 STBY VOLT R/W VSW5_STBY[7:0]

12-channel power management integrated circuit for high performance applications ADDR Register name R/W BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

75 SW6 CONFIG1 R/W SW6_UV_

SW6_OV_BYPASS SW6_ILIM_BYPASS SW6_UV_STATE SW6_OV_STATE SW6_ILIM_STATE SW6_WDBYPASS SW6_PG_EN

76 SW6 CONFIG2 R/W SW6_FLT_REN SW6_VTTEN SW6DVS_RAMP SW6ILIM[1:0] SW6PHASE[2:0]

77 SW6 PWRUP R/W SW6_SEQ[7:0]

78 SW6 MODE1 R/W — — SW6_PDGRP[1:0] SW6_STBY_MODE[1:0] SW6_RUN_MODE[1:0]

79 SW6 RUN VOLT R/W VSW6_RUN[7:0]

7A SW6 STBY VOLT R/W VSW6_STBY[7:0] 7D SW7 CONFIG1 R/W SW7_UV_ BYPASS SW7_OV_BYPASS SW7_ILIM_BYPASS SW7_UV_STATE SW7_OV_STATE SW7_ILIM_STATE SW7_WDBYPASS SW7_PG_EN 7E SW7 CONFIG2 R/W SW7_FLT_REN — — SW7ILIM[1:0] SW7PHASE[2:0] 7F SW7 PWRUP R/W SW7_SEQ[7:0]

80 SW7 MODE1 R/W — — SW7_PDGRP[1:0] SW7_STBY_MODE[1:0] SW7_RUN_MODE[1:0]

81 SW7 RUN VOLT R/W — — — VSW7[4:0]

85 LDO1 CONFIG1 R/W LDO1_UV_

LDO1_OV_BYPASS LDO1_ILIM_ BYPASS LDO1_UV_STATE LDO1_OV_STATE LDO1_ILIM_STATE LDO1_WDBYPASS LDO1_PG_EN

86 LDO1 CONFIG2 R/W LDO1_FLT_

LDO1_PDGRP[1:0] — — — LDO1_RUN_EN LDO1_STBY_EN

87 LDO1 PWRUP R/W LDO1_SEQ[7:0]

88 LDO1 RUN VOLT R/W — — — — VLDO1_RUN[3:0]

89 LDO1 STBY

R/W — — — — VLDO1_STBY[3:0] 8B LDO2 CONFIG1 R/W LDO2_UV_ BYPASS LDO2_OV_BYPASS LDO2_ILIM_ BYPASS LDO2_UV_STATE LDO2_OV_STATE LDO2_ILIM_STATE LDO2_WDBYPASS LDO2_PG_EN 8C LDO2 CONFIG2 R/W LDO2_FLT_ REN LDO2_PDGRP[1:0] LDO2HW_EN VSELECT_EN — LDO2_RUN_EN LDO2_STBY_EN 8D LDO2 PWRUP R/W LDO2_SEQ[7:0] 8E LDO2 RUN VOLT R/W — — — — VLDO2_RUN[3:0] 8F LDO2 STBY VOLT R/W — — — — VLDO2_STBY[3:0]

91 LDO3 CONFIG1 R/W LDO3_UV_

LDO3_OV_BYPASS LDO3_ILIM_ BYPASS LDO3_UV_STATE LDO3_OV_STATE LDO3_ILIM_STATE LDO3_WDBYPASS LDO3_PG_EN

92 LDO3 CONFIG2 R/W LDO3_FLT_

LDO3_PDGRP[1:0] — — — LDO3_RUN_EN LDO3_STBY_EN

93 LDO3 PWRUP R/W LDO3_SEQ[7:0]

94 LDO3 RUN VOLT R/W — — — — VLDO3_RUN[3:0]

95 LDO3 STBY

R/W — — — — VLDO3_STBY[3:0]

97 LDO4 CONFIG1 R/W LDO4_UV_

LDO4_OV_BYPASS LDO4_ILIM_ BYPASS LDO4_UV_STATE LDO4_OV_STATE LDO4_ILIM_STATE LDO4_WDBYPASS LDO4_PG_EN

98 LDO4 CONFIG2 R/W LDO4_FLT_

LDO4_PDGRP[1:0] — — — LDO4_RUN_EN LDO4_STBY_EN

99 LDO4 PWRUP R/W LDO4_SEQ[7:0]

9A LDO4 RUN VOLT R/W — — — — VLDO4_RUN[3:0] 9B LDO4 STBY VOLT R/W — — — — VLDO4_STBY[3:0] 9D VSNVS CONFIG1 R/W — — — — — — VSNVSVOLT [1:0] 9F PAGE SELECT R/TW — — — — — PAGE[2:0] PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

12-channel power management integrated circuit for high performance applications

16.2 PF8121 OTP mirror register map (page 1)

OFF_OTP Register loads the OTP mirror register values during power up OTP Register available in OTP bank only, reset from fuses when VIN crosses UVDET threshold VSNVS Reset when BOS has no valid input. VIN < UVDET and coin cell < 1.8 V (VSNVS not present) ADDR Register name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 A0 OTP FSOB SELECT SOFTFAULT OTP_FSOB_WDI OTP_FSOB_WDC OTP_FSOB_ HARDFAULT A1 OTP I2C — — — — OTP_I2C_CRC_EN OTP_I2C_ADD[2:0] A2 OTP CTRL1 — — OTP_EWARN_TIME[1:0] — OTP_STANDBYINV OTP_PG_ACTIVE OTP_PG_CHECK A3 OTP CTRL2 OTP_FSS_EN OTP_FSS_RANGE — OTP_XFAILB_EN OTP_VIN_OVLO_ SDWN OTP_VIN_OVLO_EN OTP_VIN_OVLO_DBNC[1:0] A4 OTP CTRL3 OTP_VTT_PDOWN OTP_SW6_VTTEN OTP_SW5CONFIG[1:0] OTP_SW4CONFIG[1:0] OTP_SW1CONFIG[1:0] A5 OTP FREQ CTRL OTP_SW_MODE OTP_SYNCIN_EN OTP_SYNCOUT_EN OTP_FSYNC_ RANGE OTP_CLK_FREQ[3:0] A6 OTP COINCELL CTRL A7 OTP PWRON — — OTP_PWRON_ MODE OTP_PWRON_DBNC[1:0] OTP_PWRON_ RST_EN OTP_TRESET[1:0] A8 OTP WD CONFIG ACTIVE OTP_WDWINDOW A9 OTP WD EXPIRE AA OTP WD COUNTER OTP_WD_DURATION[3:0] OTP_WD_MAX_CNT [3:0] AB OTP FAULT COUNTERS AC OTP FAULT TIMERS AD OTP PWRDN DLY1 OTP_GRP4_DLY[1:0] OTP_GRP3_DLY[1:0] OTP_GRP2_DLY[1:0] OTP_GRP1_DLY[1:0] AE OTP PWRDN DLY2 OTP_PD_SEQ_DLY[1:0] — — — — OTP_RESETBMCU_DLY[1:0] AF OTP PWRUP CTRL — OTP_PWRDWN_ MODE OTP_PGOOD_PDGRP[1:0] OTP_RESETBMCU_PDGRP[1:0] OTP_SEQ_TBASE[1:0] B0 OTP RES ETBMCU PWRUP OTP_RESETBMCU_SEQ[7:0] B1 OTP PGOOD PWRUP OTP_PGOOD_SEQ[7:0] B2 OTP SW1 VOLT OTP_VSW1[7:0] B3 OTP SW1 PWRUP OTP_SW1_SEQ[7:0] B4 OTP SW1 CONFIG1 OTP_SW1UV_TH[1:0] OTP_SW1OV_TH[1:0] OTP_SW1_PDGRP[1:0] OTP_SW1ILIM[1:0] B5 OTP SW1 CONFIG2 OTP_SW1_LSELECT[1:0] OTP_SW1PHASE[2:0] OTP_SW1DVS_RAMP OTP_SW1_PG_EN OTP_SW1_WDBYPASS B6 OTP SW2 VOLT OTP_VSW2[7:0] B7 OTP SW2 PWRUP OTP_SW2_SEQ[7:0] B8 OTP SW2 CONFIG1 OTP_SW2UV_TH[1:0] OTP_SW2OV_TH[1:0] OTP_SW2_PDGRP[1:0] OTP_SW2ILIM[1:0] B9 OTP SW2 CONFIG2 OTP_SW2_LSELECT[1:0] OTP_SW2PHASE[2:0] OTP_SW2DVS_RAMP OTP_SW2_PG_EN OTP_SW2_WDBYPASS BA OTP SW3_ VOLT OTP_VSW3[7:0] BB OTP SW3 PWRUP OTP_SW3_SEQ[7:0] PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

12-channel power management integrated circuit for high performance applications ADDR Register name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 BC OTP SW3 CONFIG1 OTP_SW3UV_TH[1:0] OTP_SW3OV_TH[1:0] OTP_SW3_PDGRP[1:0] OTP_SW3ILIM[1:0] BD OTP SW3 CONFIG2 OTP_SW3_LSELECT[1:0] OTP_SW3PHASE[2:0] OTP_SW3DVS_RAMP OTP_SW3_PG_EN OTP_SW3_WDBYPASS BE OTP SW4 VOLT OTP_VSW4[7:0] BF OTP SW4 PWRUP OTP_SW4_SEQ[7:0] C0 OTP SW4 CONFIG1 OTP_SW4UV_TH[1:0] OTP_SW4OV_TH[1:0] OTP_SW4_PDGRP[1:0] OTP_SW4ILIM[1:0] C1 OTP SW4 CONFIG2 OTP_SW4_LSELECT[1:0] OTP_SW4PHASE[2:0] OTP_SW4DVS_RAMP OTP_SW4_PG_EN OTP_SW4_WDBYPASS C2 OTP SW5 VOLT OTP_VSW5[7:0] C3 OTP SW5 PWRUP OTP_SW5_SEQ[7:0] C4 OTP SW5 CONFIG1 OTP_SW5UV_TH[1:0] OTP_SW5OV_TH[1:0] OTP_SW5_PDGRP[1:0] OTP_SW5ILIM[1:0] C5 OTP SW5 CONFIG2 OTP_SW5_LSELECT[1:0] OTP_SW5PHASE[2:0] OTP_SW5DVS_RAMP OTP_SW5_PG_EN OTP_SW5_WDBYPASS C6 OTP SW6 VOLT OTP_VSW6[7:0] C7 OTP SW6 PWRUP OTP_SW6_SEQ[7:0] C8 OTP SW6 CONFIG1 OTP_SW6UV_TH[1:0] OTP_SW6OV_TH[1:0] OTP_SW6_PDGRP[1:0] OTP_SW6ILIM[1:0] C9 OTP SW6 CONFIG2 OTP_SW6_LSELECT[1:0] OTP_SW6PHASE[2:0] OTP_SW6DVS_RAMP OTP_SW6_PG_EN OTP_SW6_WDBYPASS CA OTP SW7 VOLT — — — OTP_VSW7[4:0] CB OTP SW7 PWRUP OTP_SW7_SEQ[7:0] CC OTP SW7 CONFIG1 OTP_SW7UV_TH[1:0] OTP_SW7OV_TH[1:0] OTP_SW7_PDGRP[1:0] OTP_SW7ILIM[1:0] CD OTP SW7 CONFIG2 OTP_SW7_LSELECT[1:0] OTP_SW7PHASE[2:0] — OTP_SW7_PG_EN OTP_SW7_WDBYPASS CE OTP LDO1 VOLT OTP_LDO1UV_TH[1:0] OTP_LDO1OV_TH[1:0] OTP_VLDO1[3:0] CF OTP LDO1 PWRUP OTP_LDO1_SEQ[7:0] D0 OTP LDO1 CONFIG OTP_LDO1_PDGRP[1:0] — — — OTP_LDO1_PG_EN OTP_LDO1_ WDBYPASS OTP_LDO1LS D1 OTP LDO2 VOLT OTP_LDO2UV_TH[1:0] OTP_LDO2OV_TH[1:0] OTP_VLDO2[3:0] D2 OTP LDO2 PWRUP OTP_LDO2_SEQ[7:0] D3 OTP LDO2 CONFIG OTP_LDO2_PDGRP[1:0] OTP_VSELECT_EN OTP_LDO2HW_EN — OTP_LDO2_PG_EN OTP_LDO2_ WDBYPASS OTP_LDO2LS D4 OTP LDO3 VOLT OTP_LDO3UV_TH[1:0] OTP_LDO3OV_TH[1:0] OTP_VLDO3[3:0] D5 OTP LDO3 PWRUP OTP_LDO3_SEQ[7:0] D6 OTP LDO3 CONFIG OTP_LDO3_PDGRP[1:0] — — — OTP_LDO3_PG_EN OTP_LDO3_ WDBYPASS OTP_LDO3LS D7 OTP LDO4 VOLT OTP_LDO4UV_TH[1:0] OTP_LDO4OV_TH[1:0] OTP_VLDO4[3:0] D8 OTP LDO4 PWRUP OTP_LDO4_SEQ[7:0] D9 OTP LDO4 CONFIG OTP_LDO4_PDGRP[1:0] — — — OTP_LDO4_PG_EN OTP_LDO4_ WDBYPASS OTP_LDO4LS DA OTP VSNVS CONFIG DB OTP_OV_ BYPASS1 — OTP_SW7_ OVBYPASS OTP_SW6_ OVBYPASS OTP_SW5_ OVBYPASS OTP_SW4_ OVBYPASS OTP_SW3_ OVBYPASS OTP_SW2_ OVBYPASS OTP_SW1_OVBYPASS DC OTP_OV_ BYPASS2 OVBYPASS OTP_LDO3_ OVBYPASS OTP_LDO2_ OVBYPASS OTP_LDO1_ OVBYPASS PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

12-channel power management integrated circuit for high performance applications ADDR Register name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 DD OTP_UV_ BYPASS1 — OTP_SW7_ UVBYPASS OTP_SW6_ UVBYPASS OTP_SW5_ UVBYPASS OTP_SW4_ UVBYPASS OTP_SW3_ UVBYPASS OTP_SW2_ UVBYPASS OTP_SW1_UVBYPASS DE OTP_UV_ BYPASS2 UVBYPASS OTP_LDO3_ UVBYPASS OTP_LDO2_ UVBYPASS OTP_LDO1_UVBYPASS DF OTP_ILIM_ BYPASS1 — OTP_SW7_ ILIMBYPASS OTP_SW6_ ILIMBYPASS OTP_SW5_ ILIMBYPASS OTP_SW4_ ILIMBYPASS OTP_SW3_ ILIMBYPASS OTP_SW2_ ILIMBYPASS OTP_SW1_ ILIMBYPASS E0 OTP_ILIM_ BYPASS2 ILIMBYPASS OTP_LDO3_ ILIMBYPASS OTP_LDO2_ ILIMBYPASS OTP_LDO1_ ILIMBYPASS E3 OTP DEBUG1 — — — — — — — BGMOM_BYPASS PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

12-channel power management integrated circuit for high performance applications

17 OTP/TBB and default configurations

The PF8121 supports OTP fuse bank configuration and a predefined hardwire configurations to select the default power up configuration via the VDDOTP pin. The default power up configuration is loaded into the functional I2C registers based on the voltage on VDDOTP pin on register loading. When OTP configuration is selected, the register loading occurs in two stages:

In the first stage, the fuses are loaded in the OTP Mirror registers every time VIN crosses the UVDET threshold in the rising edge.
At the second stage, data from the mirror registers are loaded into the functional I2C registers for device operation. When VDDOTP = GND, the mirror registers hold the default configuration to be used on a power-on event. The mirror registers can be modified during the TBB mode in order to test a custom power up configuration and/or burn the configuration into the OTP fuses to generate a customized default power up configuration. When VDDOTP = V1P5D, the I2C functional register will always be loaded from the hardwire configuration every time a default loading is required. Therefore, no TBB operation is possible in this configuration. In the event of a TRIM/OTP loading failure or a self-test failure, the corresponding fault flag is set and any PWRUP event is ignored until the flags are cleared by writing a 1 during the QPU_OFF state. The TRIM_NOK, OTP_NOK flags can only be written when the TBBEN is set high (in TBB Mode). In normal operation, the TRIM_NOK, OTP_NOK flags can only be read, but not cleared.

17.1 TBB (Try Before Buy) operation

The PF8121 allows temporary configuration (TBB) to debug or test a customized power up configuration in the system. In order to access the TBB mode, the TBBEN pin should be set high . In this mode of operation, the device ignores the default value of the LPM_OFF bit and moves into the QPU_Off. In the TBB mode, the following conditions are valid:

I2C communication uses standard communication with no CRC and secure write disabled.
Default I2C address is 0x08 regardless of the address configured by OTP.
Watchdog monitoring is disabled (including WDI and internal watchdog timer).
The PF8121 can communicate through I2C as long as VDDIO is provided to the PMIC externally. The PAGE[2:0] bits are provided to grant access to the mirror registers and other OTP dedicated bits. When device is in the TBB mode, it can access the mirror registers in the extended register Page 1. With the TBBEN pin pulled low, access to the extended register pages is not allowed. The mirror registers are preloaded with the values form the OTP configuration. These may be modified to set the proper power up configuration during TBB operation. If a power up event is present with the TBBEN pin set high, device will power up with the proper configuration but limited functionality. Limited functionality includes:
Default I2C address = 0x08
CRC and secure write disabled
Watchdog operation/monitoring disable PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

Figure 39. TBB operation diagram

17.2 OTP fuse programming

12-channel power management integrated circuit for high performance applications

17.3 Default hardwire configuration

If VDDOTP = V1P5D, the device loads the configuration from the default hardwire configuration directly into the corresponding I2C functional registers every time the registers need to be reloaded. When using the hardwire configuration, the TRIM values are still loaded from the OTP fuses. In the event of a TRIM loading failure, the corresponding fault flag is set to 1. When the hardwire configuration is used, the PF8121 does not allow TBB mode operation. When TBBEN = V1P5D, the device enters a debug mode. In this mode of operation, the device ignores the default value of the LPM_OFF bit and moves into the QPU_Off. During hardwire configuration, the OTP_NOK flag is always set to 0. When any of the TRIM_NOK, OTP_NOK flag is set, any PWRUP event is ignored until the flags are cleared by writing a 0. These flags can only be written when the system is in the debug mode, (TBBEN = V1P5D). In normal operation, the TRIM_NOK, OTP_NOK flags are read only. PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

WDI disabled
Watchdog Disabled
l2C CRC disabled
l2C Address = 0x08
Access Miscellaneous Debug flags VDDOTP = V1P5D I2C Register Map I2C Register Map Mirror Registers Mirror Registers

Figure 40. Hardwire operation diagram Table 75. Default hardwire configuration PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

18 IC level quiescent current requirements

19 Typical applications

3.0 V coin cell

20.1 Package outline for E-type HVQFN56

20.2 PCB design guidelines for E-type HVQFN56

20.3 Package outline for dimple WF-type HVQFN56 (automotive/industrial grade)

Figure 48. Package outline for dimple WF-type HVQFN56 (automotive/industrial grade) PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 49. Package outline detail for dimple WF-type HVQFN56 (automotive/industrial grade) PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

Figure 50. Package outline notes for for dimple WF-type HVQFN56 (automotive/industrial grade) PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved.

20.4 PCB design guidelines for dimple WF-type HVQFN56

Product data sheet
Global: replaced master with primary and slave with secondary
Updated title of Section 2
Updated Figure 1
Updated Table 1
Updated Table 2
Added Section 20.3
Added Section 20.4
Updated legal information PF8121 v.5.0 24 Feb 2021 • CIN 202102036
Product data sheet
Table 6: updated storage temperature (replaced −40 by −55)
Table 50: changed output accuracy from ± 2.0 % to ± 1.5 % for VSWxACC (0.8 V ≤ VSWxFB ≤ 1.0 V)
Section 14.9.13: updated Figure 21 PF8121 v.4.0 5 Oct 2020 • CIN 202010004
Product data sheet
Table 3: added note for pins SW1LX, SW2LX, SW3LX, SW4LX, SW5LX, SW6LX, and SW7LX (additional note added to clarify that the SWxLX pins are tolerant to negative transient spike during the dead band time with expectable fast transients as low as −3.0 V)
Table 10: added new transitions to the State machine transition definition table in order to clarify missing conditions related to the XFAILB during power up and power down events
Section 15.4, Section 15.5: added a section for current limit specification (The current limit specification is given with respect to the inductor …...)
Section 15.4.3 (ISWx, ISWx_DP): added note "The Type 1 buck regulator in single or dual phase configuration is capable of providing output current above the nominal max current specification as long as it does not reach the current limitation. However, if operating above the nominal maximum current, overall thermal considerations must be taken to prevent reaching PMIC thermal shutdown during high ambient temperature conditions"
Section 15.4.3: updated VSWxACC values and conditions
Section 15.5.1 (ISW7): added note "The Type 2 buck regulator is capable of providing output current above the nominal max current specification as long as it does not reach the current limitation. However, if operating above the nominal maximum current, overall thermal considerations must be taken to prevent reaching PMIC thermal shutdown during high ambient temperature conditions"
Section 15.8.5 PF8121 v.3.0 23 Mar 2020 • CIN 202003030
Product data sheet
Table 2: corrected comments / nomenclature for MC32PF8121EUEP part (replaced BUCK7 by SW7, and BUCK3 by SW4) and added MC32PF8121G5EP part number PF8121 v.2.0 29 Apr 2019 • Product data sheet
Global: changed document status from Preliminary to Product PF8121 v.1.0 19 Apr 2019 • Preliminary data sheet

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Product data sheet Rev. 6 — 18 October 2024 Document feedback

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12-channel power management integrated circuit for high performance applications Tables Tab. 7. QFN56 thermal resistance and package Tab. 14. Startup timing requirements (PWRON Tab. 15. Startup with PWRON driven high externally Tab. 20. Programmable delay after RESETBMCU is Tab. 27. PWRON debounce configuration in edge Tab. 50. Type 1 buck regulator electrical Tab. 57. Type 2 buck regulator electrical PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

12-channel power management integrated circuit for high performance applications Figures Fig. 7. Startup with PWRON driven high externally Fig. 8. Power up/down sequence between off and Fig. 9. Power up/down sequence between run and Fig. 12. Regulator turned off with RegX_STATE = 0 Fig. 13. Regulator turned off with RegX_STATE = 0 Fig. 14. Correct power up (no fault during power Fig. 15. Power up sequencer with a temporary Fig. 16. Power up sequencer aborted as fault Fig. 18. XFAILB behavior during a power up Fig. 19. XFAILB behavior during a power down Fig. 21. External XFAILB event during a power up Fig. 43. Package outline detail for E-type HVQFN56 . 112 Fig. 44. Package outline notes for E-type Fig. 48. Package outline for dimple WF-type Fig. 49. Package outline detail for dimple WF-type Fig. 50. Package outline notes for for dimple WF-type HVQFN56 (automotive/industrial Fig. 51. PCB design guidelines - solder mask Fig. 52. PCB design guidelines - I/O pads and Fig. 53. PCB design guidelines - Solder paste PF8121 All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 6 — 18 October 2024 Document feedback

12-channel power management integrated circuit for high performance applications Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © 2024 NXP B.V. All rights reserved. For more information, please visit: https://www.nxp.com Document feedback Date of release: 18 October 2024 Document identifier: PF8121

Product Information

MC32PF8121EUEP specifications and overview.

Summary

12-channel power management integrated circuit for high performance applications Rev. 6 - 18 October 2024

Description

12-channel power management integrated circuit for high performance applications Rev. 6 - 18 October 2024

Source title MC32PF8121EUEP Datasheet(PDF) - NXP Semiconductors

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