MC32PF1550A8EP

PF1550 NXP | Alldatasheet

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 150

Technical content

Datasheet sections

• 1 General description
• 1.1 Features and benefits
• 1.2 Applications
• 2 Application diagram
• 2.1 Functional block diagram
• 2.2 Internal block diagram
• 3 Orderable parts
• 4 Pinning information
• 4.1 Pinning
• 4.2 Pin definitions
• 5 General product characteristics
• 5.1 Thermal characteristics
• 5.2 Absolute maximum ratings
• 5.3 Electrical characteristics
• 5.3.1 Electrical characteristics – Battery charger
• 5.3.2 Electrical characteristics – SW1 and SW2
• 5.3.3 Electrical characteristics – SW3
• 5.3.4 Electrical characteristics – LDO1
• 5.3.5 Electrical characteristics – LDO2
• 5.3.6 Electrical characteristics – LDO3
• 5.3.7 Electrical characteristics – VREFDDR
• 5.3.8 Electrical characteristics – VSNVS
• 5.3.9 Electrical characteristics – IC level bias
• 6 Detailed description
• 6.1 Buck regulators
• 6.2 SW1 and SW2 detailed description
• 6.2.1 SWx dynamic voltage scaling description
• 6.2.2 SWx DVS and non-DVS operation
• 6.2.3 Regulator control
• 6.2.4 Current limit protection
• 6.2.5 Output voltage setting in SWx
• 6.2.6 SWx external components
• 6.3 SW3 detailed description
• 6.3.1 Regulator control
• 6.3.2 Current limit protection
• 6.3.3 Output voltage setting in SW3
• 6.3.4 SW3 external components
• 7 Low dropout linear regulators, VREFDDR
• 7.1 General description
• 7.2 LDO1 and LDO3 detailed description
• 7.2.1 Features summary
• 7.2.2 LDOy block diagram
• 7.2.3 LDOy external components
• 7.2.4 LDOy output voltage setting
• 7.2.5 LDOy low-power mode operation
• 7.2.6 LDOy current limit protection
• 7.2.7 LDOy load switch mode
• 7.3 LDO2 detailed description
• 7.3.1 LDO2 features summary
• 7.3.2 LDO2 block diagram
• 7.3.3 LDO2 external components
• 7.3.4 LDO2 output voltage setting
• 7.3.5 LDO2 Low-power mode operation
• 7.3.6 LDO2 current limit protection
• 7.4 VREFDDR reference
• 7.5 VSNVS LDO/switch
• 8 Battery charger description
• 8.1 Operating modes and behavioral description
• 8.2 Charger input source detection
• 8.3 Input self-discharge for reliable charger input
• 8.4 Charger state diagram
• 8.5 Charging profile
• 8.5.1 Precharge state
• 8.5.2 Fast charge constant current state
• 8.5.3 Fast charge constant voltage state
• 8.5.4 End-of-charge state
• 8.5.5 Done state
• 8.6 Battery supplement mode
• 8.7 Power path features
• 8.7.1 VSYS regulation
• 8.7.2 Input current limit
• 8.7.3 Battery thermistor
• 8.7.4 BATFET soft start
• 8.8 Thermal
• 8.8.1 Thermal regulation
• 8.8.2 Thermal foldback
• 8.8.3 Input voltage regulation mode
• 8.8.4 JEITA thermal control
• 8.9 Fault states
• 8.9.1 Timer fault state
• 8.9.2 Watchdog timer state
• 8.9.3 Thermal shutdown state
• 8.9.4 Battery overvoltage state
• 8.9.5 Charger fault priority
• 8.9.6 Battery overcurrent limit
• 8.10 LED indicator
• 9 Control and interface signals
• 9.1 PWRON
• 9.2 STANDBY
• 9.3 RESETBMCU
• 9.4 INTB
• 9.5 WDI
• 9.6 ONKEY
• 9.7 Control interface I2C block description
• 9.7.1 I2C device ID
• 9.7.2 I2C operation
• 10 PF1550 state machine
• 10.1 System ON states
• 10.1.1 Run state
• 10.1.2 STANDBY state
• 10.1.3 SLEEP state
• 10.2 System OFF states
• 10.2.1 REGS_DISABLE
• 10.2.2 CORE_OFF
• 10.2.3 SHIP
• 10.3 Turn on events
• 10.4 Turn off events
• 10.5 State diagram and transition conditions
• 10.6 Regulator power-up sequencer

Power management integrated circuit (PMIC) for low power application processors Rev. 5 — 10 June 2019 Product data sheet

1 General description

The PF1550 is a power management integrated circuit (PMIC) designed specifically for use with i.MX processors on low-power portable, smart wearable and Internet-of-Things (IoT) applications. It is also capable of providing full power solution to i.MX 7ULP, i.MX 6SL, 6UL, 6ULL, and 6SX processors. With three high-efficiency buck converter, three linear regulators, RTC supply, and battery linear charger, the PF1550 can provide power for a complete battery-powered system, including application processors, memory, and system peripherals.

1.1 Features and benefits

This section summarizes the PF1550 features:

• Input voltage range to PMIC VBUSIN pin via USB bus or AC adapter: 4.1 V to 6.0 V
• Buck converters: – SW3, 1.0 A; 1.8 V to 3.3 V in 100 mV steps – Soft start – Quiescent current 1.0 μA in ULP mode with light load – Peak efficiency > 90 % – Dynamic voltage scaling on SW1 and SW2 – Modes: forced PWM quasi-fixed frequency mode, adaptive variable-frequency mode – Programmable output voltage, current limit, and soft start
• LDO regulators – LDO1, 0.75 V to 1.5 V/1.8 to 3.3 V, 300 mA with load switch mode – LDO2, 1.8 V to 3.3 V, 400 mA – LDO3, 0.75 V to 1.5 V/1.8 V to 3.3 V, 300 mA with load switch mode – Quiescent current < 1.5 μA in Low-power mode – Programmable output voltage – Soft start and ramp – Current limit protection
• Battery charger – Supports single-cell Lithium Ion/Lithium Polymer batteries – Linear charging (10 mA to 1500 mA input limit) – Up to 6.5 V input operating range – VSYS regulator can withstand transient and DC inputs from 0 V up to +22 V – Programmable charge voltage (3.5 V to 4.44 V) – Programmable charge current (100 mA to 1000 mA) – Programmable charge termination current (5.0 mA to 50 mA)

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 – Integrated 50 mΩ battery isolation MOSFET for operation with no/low battery – Battery supplement mode – Battery discharge overcurrent protection, up to 3.0 A – USB_PHY low dropout linear regulator – Programmable LED driver (status indicator) – JEITA-compliant battery temp sensing and charger control – Key charging parameters can be configured and permanently stored in OTP – I2C Control Interface permitting processor control and event detection

• LDO/switch supply – RTC supply VSNVS 3.0 V, 2.0 mA – Battery backed memory including coin cell charger
• DDR memory reference voltage, VREFDDR, 0.5 V to 0.9 V, 10 mA
• OTP (One time programmable) memory for device configuration – User programmable start-up sequence, timing, soft-start, and power-down sequence – Programmable regulator output voltages and charger parameters
• I2C interface
• User programmable Standby, Sleep/Low-power, and Off (REGS_DISABLE) modes
• Ambient temperature range −40 °C to 105 °C

1.2 Applications

• Smart mobile/wearable devices
• Low-power IoT applications
• Wireless game controllers
• Embedded monitoring systems
• Home automation
• POS
• E-Read

2 Application diagram

Figure 1. Application diagram

2.1 Functional block diagram

Figure 2. Functional block diagram

2.2 Internal block diagram

16 MHz clock

16 MHz clock / derivative

Figure 3. Internal block diagram

3 Orderable parts

device can be found in Table 85.

Table 1. Orderable part variations [1] For tape and reel, add an R2 suffix to the part number.

4 Pinning information

4.1 Pinning

Figure 4. Pinout diagram

4.2 Pin definitions

Table 2. Pin description

1 WDI Watchdog input from processor

2 SDA SDA when used in I2C mode

3 SCL SCL when used in I2C mode

4 VDDIO

5 VDDOTP VDDOTP Connect to ground in application

6 PWRON PWRON input

7 STANDBY STANDBY input

8 ONKEY ONKEY push-button input

9 INTB INTB open-drain output

10 RESETBMCU

11 VLDO3IN LDO3 input supply

12 VLDO3

13 SW3LX Buck 3 switching node

14 SW3IN Buck 3 input supply

15 SW3FB

16 SW2FB Buck 2 output voltage feedback

17 SW2IN Buck 2 input supply

18 SW2LX

19 VLDO2 LDO2 output

20 VLDO2IN

21 VREFDDR VREFDDR output

22 VINREFDDR

23 VDIG VDIG regulator output (used within PF1550)

24 VCORE

25 SW1LX Buck 1 switching node

26 SW1IN Buck 1 input supply

27 SW1FB

28 VLDO1IN LDO1 input supply

29 VLDO1

30 VSNVS VSNVS regulator output

31 LICELL

32 THM Thermistor connection

37 VBUSIN Charger input

38 INT2P7 INT2P7 regulator output (used within PF1550 and as thermistor bias)

39 USBPHY USBPHY regulator output

40 CHGB

41 EPAD EPAD Exposed pad

5 General product characteristics

5.1 Thermal characteristics

Table 3. Thermal ratings Thresholds for thermal protection features. malfunction or permanent damage to the device. temperature, air flow, power dissipation of other components on the board, and board thermal resistance. [5] The Board uses the JEDEC specifications for thermal testing (and simulation) JESD51-7 and JESD51-5. [6] Per JEDEC JESD51-6 with the board horizontal. [8] Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). [9] Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

5.2 Absolute maximum ratings

Table 4. Maximum ratings

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 Symbol Description (Rating) Min Max Unit LICELL Coin cell input −0.3 3.6 V CHARGER VBATT Battery input −0.3 4.8 V INT2P7 INT2P7 regulator output (used within PF1550 and as thermistor bias) −0.3 3.6 V THM Thermistor connection. Connect thermistor to ground from this pin. −0.3 3.6 V VBUSIN Charger input −0.3 24 V USBPHY USBPHY regulator output −0.3 5.5 V CHGB Charger LED input connection. Connect LED from VSYS to this pin. −0.3 4.8 V INPUT/OUTPUT SUPPLY VINREFDDR VREFDDR input supply −0.3 3.6 V VREFDDR VREFDDR output −0.3 3.6 V IC CORE VSYS Main input voltage to PMIC and output of charger −0.3 4.8 V VDIG VCOREDIG regulator output (used within PF1550) −0.3 1.65 VCORE VCORE regulator output (used within PF1550) −0.3 1.65 V ELECTRICAL RATINGS VESD ESD ratings Human body model Charge device model (corner pins) Charge device model (all other pins) [1] ±2000 ±750 ±500 V [1] Testing is performed in accordance with the human body model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the charge device model (CDM), Robotic (CZAP = 4.0 pF).

5.3 Electrical characteristics

5.3.1 Electrical characteristics – Battery charger

characterized at VBUSIN = 5.0 V, VSYS = 3.7 V and 25 °C, unless otherwise noted. Table 5. Global conditions Table 6. Input currents

BATFET closed, VBUSIN = 0 V. Table 7. Internal 2.7 V Regulator (INT2P7) Table 8. Switch impedances and leakage currents

Table 9. Linear transients Table 10. Charger characteristics

Table 11. Power-path management Table 12. Watchdog timer Table 13. Charger timer Table 14. Battery overcurrent protection

Table 15. Thermal regulation Table 16. Battery thermistor monitor Table 17. USBPHY LDO

Table 18. LED characteristics

5.3.2 Electrical characteristics – SW1 and SW2

1.1 V, ISWx = 100 mA, and 25 °C, unless otherwise noted. Table 19. SW1 and SW2 electrical characteristics

5.3.3 Electrical characteristics – SW3

1.8 V, ISW3 = 200 mA, and 25 °C, unless otherwise noted. Table 20. SW3 electrical characteristics

5.3.4 Electrical characteristics – LDO1

VLDO1[4:0] = 11111, ILDO1 = 10 mA, and 25 °C, unless otherwise noted. Table 21. LDO1 electrical characteristics

5.3.5 Electrical characteristics – LDO2

1111, ILDO2 = 10 mA, and 25 °C, unless otherwise noted. Table 22. LDO2 electrical characteristics

5.3.6 Electrical characteristics – LDO3

VLDO3[4:0] = 11111, ILDO3 = 10 mA, and 25 °C, unless otherwise noted. Table 23. LDO3 electrical characteristics

5.3.7 Electrical characteristics – VREFDDR

Table 24. VREFDDR electrical characteristics

5.3.8 Electrical characteristics – VSNVS

Table 25. VSNVS electrical characteristics

5.3.9 Electrical characteristics – IC level bias currents

3.6 V, VSNVS = 3.0 V, and 25 °C, unless otherwise noted. Table 26. IC level electrical characteristics

6 Detailed description

processor and peripheral devices.

supply rail adjustments for the processor cores for power optimization. camera, Bluetooth, Wireless LAN. (Secure Non-Volatile Storage) /RTC (Real Time Clock) circuitry on the processor. VSNVS is powered from VSYS or from a coin cell. through the power path circuit. Table 27. Voltage regulators

6.1 Buck regulators

The PF1550 features three high-efficiency buck regulators with internal compensation. operating conditions. It also provides immediate response to dynamic load changes.

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 pulse-skip switching mode takes place automatically according to the load current to maintain optimum power efficiency. Additionally, further power savings through cutting the buck circuitry quiescent current can be achieved by activating a Low-power mode upon entering either STANDBY or SLEEP PMIC power mode or as commanded via I2C control bits. In SW1 and SW2. An OTP option enables or disables DVS in the regulators. When DVS is disabled and the low-power bit is set, the regulator enters an Ultra Low Power (ULP) mode that cuts the operating quiescent current even, in order to reach extremely low standby power levels needed for ultra low power processors such as that from Kinetis K and L series. As indicated above, the buck controller supports PWM (Pulse Width Modulation) mode for medium and high load conditions and low-power variable-frequency pulse skip mode at light loads. During high current mode, it operates in continuous conduction and the switching frequency is up to 2.0 MHz with a controlled on-time variation depending on the input voltage and output voltage. If the load current decreases, the converter seamlessly enters the pulse-skip mode to cut the operating quiescent current and maintain high efficiency down to very light loads. In pulse-skip mode, the switching frequency varies linearly with the load current. Since the controller supports both power modes within one single building block, the transition from normal power mode to lower power pulse-skip mode and vice versa is seamless without dramatic effects on the output voltage. In the adopted pulse-skip scheme, the device generates a single switching pulse to ramp up the inductor current and recharge the output capacitor, followed by a non-switching (pause) period where most of the internal circuits are shut down to achieve a lowest quiescent current. During this time, the load current is supported by the output capacitor. The duration of the pause period depends on the load current and the inductor peak current.

6.2 SW1 and SW2 detailed description

SW1 and SW2 are identical buck regulators designed to carry a nominal load current of 1.0 A. Detailed characteristics and features of SW1 and SW2 are described in this section. Being identical, reference is made only to SWx though the same specifications apply to SW1 and SW2.

6.2.1 SWx dynamic voltage scaling description

SWx integrates an optional DVS circuit that is enabled via OTP. To reduce overall power consumption, when DVS is enabled SWx output voltage can be varied depending on the mode or activity level of the processor.

• Normal operation: The output voltage is selected by I2C bits SWx_VOLT[5:0]. A voltage transition initiated by I2C is governed by the SWx_DVSSPEED I2C bit as shown in Table 28.
• Standby mode: The output voltage can be selected by I2C bits SWx_STBY_VOLT[5:0]. Voltage transitions initiated by a Standby event are governed by the SWx_DVSSPEED I2C bit as shown in Table 28. This applies only when DVS is enabled.
• Sleep mode: The output voltage can be higher or lower than in normal operation, but is typically selected to be the lowest state retention voltage of a given processor; it is selected by I2C bits SWx_SLP_VOLT[5:0]. Voltage transitions initiated by a turn off event are governed by the SWx_DVSSPEED I2C bit for SWx as shown in Table 28. This applies only when DVS is enabled.

Table 28. SWx DVS setting selection Figure 5. SWx DVS transitions

6.2.2 SWx DVS and non-DVS operation

• DVS enabled: a DVS reference is activated and output accuracy of the regulator is tight at the cost of slightly higher quiescent current. See Section 5.3 "Electrical characteristics" for details. In Figure 6, DVS FB and DVS REF are enabled via OTP for this mode of operation.
• DVS disabled: the regulator operates as a traditional buck converter with a fixed reference and soft-start. The quiescent current in this mode is lower at the cost of output accuracy and transient response. See Section 5.3 "Electrical characteristics" for details. In Figure 6, VREF FB and VREF are enabled via OTP for this mode of operation.

Figure 6. SWx DVS and non-DVS selection

6.2.3 Regulator control

entering the Standby mode, exiting/entering Sleep/ Low-power mode. Table 29. Buck regulator operating modes OFF The regulator is switched off and the output voltage is discharged using an internal resistor. load for optimized efficiency. F-PWM In this mode, the regulator is always in PWM mode operation regardless of load conditions. Sleep) with the proper I2C setting. See Table 30. The following table shows actions to control different bits for SW1 and SW2. Table 30. Buck mode control

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 PMIC state SWx_EN SWx_STBY SWx_OMODE SWx_LPWR SWx_FPWM SWx operating mode Run 1 X X 0 1 SW enabled. Forced PWM mode Run 1 X X 1 0 SW Enabled. Does not operate in Low- power mode. Run 1 X X 1 1 SW enabled. Forced PWM mode – not Low-power mode. Standby 1 0 X X X SW disabled Standby 1 1 X 0 0 SW enabled. Operates in DCM at light loads. Standby 1 1 X 0 1 SW enabled. Forced PWM mode. Standby 1 1 X 1 0 SW enabled. Operates in Low-power mode. Standby 1 1 X 1 1 SW enabled. Forced PWM mode – not Low-power mode. Sleep 1 X 0 X X SW disabled Sleep 1 X 1 0 0 SW enabled. Operates in DCM at light loads. Sleep 1 X 1 0 1 SW enabled. Forced PWM mode. Sleep 1 X 1 1 0 SW enabled. Operates in Low-power mode. Sleep 1 X 1 1 1 SW enabled. Forced PWM mode – not Low-power mode.

6.2.4 Current limit protection

SWx features high and low-side FET current limit. When current through the FETs go above their respective thresholds, the FET is turned-off to prevent further increase in current. The protection is enabled in a cycle-by-cycle mode. Hitting either current limit sets the corresponding interrupt sense bits. If the faults persist for longer than the 8.0 ms debounce time, the interrupt status bit is set.

6.2.5 Output voltage setting in SWx

Output voltage of SWx is programmable via OTP. During startup (REGS_DISABLE mode to RUN mode), contents of the OTP_SWx_VOLT[5:0] are mapped into the SWx_VOLT[5:0], SWx_STBY_VOLT[5:0], and SWx_SLP_VOLT[5:0] register which set the regulator output voltage during Run, Standby, and Sleep modes respectively. In the DVS enabled mode (OTP_SWx_DVS_SEL = 0), values of SWx_VOLT[5:0], SWx_STBY[VOLT[5:0], and SWx_SLP_VOLT[5:0] can be changed via I2C after the PMIC starts up (RESETBMCU is released). In the DVS disabled mode (OTP_SWx_DVS_SEL = 1), value of SWx_VOLT[5:0], SWx_STBY[VOLT[5:0], and SWx_SLP_VOLT[5:0] are read-only and must not be written to.

Table 31. SW1 and SW2 output voltage setting

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 Set point SWx_VOLT[5:0] SWx_STBY_VOLT[5:0] SWx_SLP_VOLT[5:0] Output voltage with DVS enabled OTP_SWx_DVS_SEL = 0 Output voltage with DVS disabled OTP_SWx_DVS_SEL = 1 35 100011 1.0375 3.30 36 100100 1.0500 3.30 37 100101 1.0625 3.30 38 100110 1.0750 3.30 39 100111 1.0875 3.30 40 101000 1.1000 3.30 41 101001 1.1125 3.30 42 101010 1.125 3.30 43 101011 1.1375 3.30 44 101100 1.1500 3.30 45 101101 1.1625 3.30 46 101110 1.1750 3.30 47 101111 1.1875 3.30 48 110000 1.2000 3.30 49 110001 1.2125 3.30 50 110010 1.2250 3.30 51 110011 1.2375 3.30 52 110100 1.2500 3.30 53 110101 1.2625 3.30 54 110110 1.2750 3.30 55 110111 1.2875 3.30 56 111000 1.3000 3.30 57 111001 1.3125 3.30 58 111010 1.3250 3.30 59 111011 1.3375 3.30 60 111100 1.3500 3.30 61 111101 1.3625 3.30 62 111110 1.3750 3.30 63 111111 1.3875 3.30

6.2.6 SWx external components

The design is optimized for a 1.0 µH inductor. Table 32. Acceptable inductance and capacitance values Table 33 and Table 34 show example inductor and capacitor part numbers respectively. Table 33. Example inductor part numbers Table 34. Example capacitor part numbers

6.3 SW3 detailed description

not supported in this regulator. Figure 7. SW3 block diagram

6.3.1 Regulator control

Available modes for buck regulators are presented in Table 35 . on the PMIC operating state. Table 35. SW3 buck regulator operating modes OFF The regulator is switched off and the output voltage is discharged using an internal resistor. skip (variable switching frequency) scheme at light load for optimized efficiency. F-PWM In this mode, the regulator is always in PWM mode operation regardless of load conditions. Table 36. SW3 buck mode control

0 X X X X SW disabled

6.3.2 Current limit protection

debounce time, the interrupt status bit is set.

6.3.3 Output voltage setting in SW3

the regulator output voltage during Run, Standby, and Sleep modes respectively. only and cannot be written to. Table 37. SW3 output voltage setting

6.3.4 SW3 external components

Table 38. Acceptable inductance and capacitance values Table 39 and Table 40 show example inductor and capacitor part numbers respectively. Table 39. Example inductor part numbers Table 40. Example capacitor part numbers

7 Low dropout linear regulators, VREFDDR and VSNVS

7.1 General description

When a regulator is disabled, the output is discharged by an internal pulldown. Switch enable bit OTP_VLDOx_LS.

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 shutdown, and processor interrupt generation, to contain failures and minimize the chance of product damage. If a short-circuit condition is detected and REGSCPEN bit is set, the LDO is disabled by resetting its VLDOxEN bit, while at the same time, an interrupt VLDOxFAULTI is generated to flag the fault to the system processor. The VLDOxFAULTI interrupt is maskable through the VLDOxFAULTM mask bit. The SCP feature is enabled by setting the REGSCPEN bit. If this bit is not set, the regulators are not automatically be disabled upon a short-circuit detection. However, the current limiter continues to limit the output current of the regulator. By default, the REGSCPEN is not set; therefore, at start-up none of the regulators are disabled if an overloaded condition occurs. A fault interrupt, VLDOxFAULTI is generated in an overload condition regardless of the state of the REGSCPEN bit. Each LDO features a Low-power mode where the quiescent current consumed is significantly lower than in regulator operation. In the Low-power mode, load current of each regulator is limited to 10 mA.

7.2 LDO1 and LDO3 detailed description

LDO1 and LDO3 are identical 300 mA low dropout (LDO) regulators that provide output voltage with high accuracy and are programmable through I2C interface bits. Being identical, reference is made to these LDOs as LDOy. To support this wide input range, LDOy circuit incorporates a PMOS pass FET as well as an NMOS pass FET. The LDO uses the main band gap as its reference. The regulator incorporates a soft-start circuit that ramps the internal reference in order to provide smooth output waveform with minimal overshooting during power-up. When the regulator is disabled, the output is discharged by an internal pulldown resistor. Additionally, the LDO can be used as a load switch by setting the corresponding Load Switch enable bit OTP_LDOy_LS. Moreover, LDOy includes current limit protection with the option to turn off the LDO when an overcurrent is detected.

7.2.1 Features summary

• Input range LDO from 1.0 V to 4.5 V
• Programmable output voltage between 0.75 V to 1.5 V (uses NMOS) or 1.8 V and

3.3 V (uses PMOS) with 2 % accuracy

• Soft-start ramp control during power-up and discharge mechanism during power-down
• Low quiescent current (~ 2.5 µA) at Low-power mode
• Current limit protection
• Configurable into load switch via OTP bit

7.2.2 LDOy block diagram

Figure 8. LDOy Block Diagram

7.2.3 LDOy external components

times the nominal output voltage.

7.2.4 LDOy output voltage setting

LDOy output voltage is programmed by setting the LDOy[4:0] bits as shown in Table 41. Table 41. LDOy output voltage setting

7.2.5 LDOy low-power mode operation

Table 42. LDOy control bits

7.2.6 LDOy current limit protection

mode that limits the available output current.

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 up none of the regulators will be disabled if an overloaded condition occurs. A fault interrupt, LDOy_FAULTI, is generated in an overload condition regardless of the state of the REGSCPEN bit. Current limit is not active when LDOy is operated in the load switch mode.

7.2.7 LDOy load switch mode

The LDOy path can be turned into a switch by setting the OTP_LDOy_LS bit. Setting this bit fully turns on the LDO pass FET. This could be useful if power domain partitioning or additional isolation is needed on the system application. Soft-start is engaged during start-up of the load switch to reduce inrush currents.

7.3 LDO2 detailed description

LDO2 is a 400 mA low dropout (LDO) regulator that provides output voltage with high accuracy and programmable through I2C/ interface bits. To support this wide input range, the LDO circuit incorporates a PMOS pass FET. The LDO uses the main bandgap as its reference. The regulator incorporates a soft-start circuit that ramps the internal reference in order to provide smooth output waveform with minimal overshooting during power-up. When the regulator is disabled, the output is discharged by an internal pull-down resistor. The pulldown is also activated when RESETBMCU is low. Moreover, LDO2 includes current limit protection with option to turn off the LDO when an overcurrent is detected.

7.3.1 LDO2 features summary

• Input range LDO from 2.8 V to 4.5 V
• Programmable output voltage between 1.8 V and 3.3 V with 2 % accuracy
• Soft-start ramp control during power-up and discharge mechanism during power-down
• Low quiescent current (~ 1.5 µA) at Low-power mode
• Current limit protection

7.3.2 LDO2 block diagram

Figure 9. LDO2 block diagram

7.3.3 LDO2 external components

times the nominal output voltage.

7.3.4 LDO2 output voltage setting

Table 43. LDO2 output voltage setting

7.3.5 LDO2 Low-power mode operation

Table 44. LDO2 control bits

7.3.6 LDO2 current limit protection

mode limiting the available output current.

7.4 VREFDDR reference

reference voltage for DDR memories. utilizes a voltage follower to drive the load.

Figure 10. VREFDDR block diagram

7.5 VSNVS LDO/switch

is simply the coin cell voltage minus the voltage drop across the switch. configuration from an LDO to a switch. Figure 11. VSNVS block diagram

8 Battery charger description

or current sense resistors are required. thermistor monitor and thermal regulation. powered from the VSYS node in the PF1550.

2 SDA

6.5 V LDO 5

6 CV_CHARGE

10 K thermistor

Figure 12. Battery charger internal block diagram

8.1 Operating modes and behavioral description

Figure 13. Charger low battery (Startup sequence, USB insert, VBATT = 0 V)

Figure 14. Charger healthy battery (Startup sequence, USB insert, VBATT = 3.8 V) Table 45. Battery regulation voltage register The VSYSMIN value is programmable via OTP as per the following table.

Table 46. VSYSMIN setting

11 Reserved

(PMIC undervoltage detection, 2.9 V typ.). current to lower the VSYS threshold, thus reducing the headroom. Typically, the VSYS output range can go as low as 300 mV below the VSYSMIN setting.

8.2 Charger input source detection

• VBUS must be above VUVLO (4.2 V max.) to be valid
• VBUS must be below its overvoltage lockout threshold (VOVLO (6.0 V min.))
• VBUS must be above the system voltage by VIN2SYS (50 mV / 175 mV programmable via OTP) The VBUS input generates an input interrupt when its status changes. The input status can be read with VBUS_OK and VBUS_SNS registers. Interrupts can be masked with VBUS_M register. Note: Adaptor removal is defined as VBUS < VUVLO. VBUS_xx VBUS_xx SYS VVBUS_xx_OVLO VIN2SYS VVBUS_xx_UVLO VBUS_UVLO VBUS_xx_INVLDVBUS_xx_OVLO LIN2SYS VBUS_INVLD aaa-025038

Figure 15. Input source detection delay

8.3 Input self-discharge for reliable charger input interrupt

threshold in a reasonable time.

8.4 Charger state diagram

Figure 16. Charger state diagram

8.5 Charging profile

modes (Trickle and Linear constant current mode).

• Linear control of BATFET – Trickle (programmable from 55 mA/100 mA based on battery voltage) – Linear constant current mode from 100 mA to 1000 mA
• Constant current (CC)
• Constant voltage (CV) aaa-023884 VBATREG VRESTART VLOW_BATT ICHARGE_CC IPRECHARGE IEOC State Battery current Battery voltage Low battery recovery Battery disconnected Fast charge constant voltage (CV) Fast charge constant current (CC) Time Time End-of-charge (EOC) End-of-charge (EOC) DONE (VSYS loaded) Restart fast charge (CV) VSYS VBATT (> 0 V) IBAT (0 A)

Figure 17. Charging profile

8.5.1 Precharge state

state, the charge current into the battery is equal or lower than IPRECHG.LB (45 mA typ).

1. When the main battery voltage rises above VPRECHG.LB, the charger enters the next

state in the charging cycle: “Fast-Charge Constant Current" state.

1. If the battery charger remains in this state for longer than tPRECHG, the charger state

machine transitions to the “Timer Fault” state.

1. If the watchdog timer is not serviced, the charger state machine transitions to the

Note: The precharge state works with battery voltages down to 0 V.

internal pack protection switch to reconnect the Lithium-ion cell.

8.5.2 Fast charge constant current state

is less than or equal to IFC (excluding accuracy IFCACC).

• The charger input is in input current limit
• The charger input voltage is low
• The system load is consuming adapter current. When the voltage drop between VBUS and VSYS is below the VIN2SYS threshold, charging stops and charge current drops down to 0 A. Note: The system load always gets priority over the battery charge current. The system load always gets priority over the battery charge current. The following events cause the state machine to exit this state:
• When the main battery voltage rises above VBATREG, the charger enters the next state in the charging cycle: "Fast Charge (CV)".
• If the battery charger remains in this state for longer than tFC, the charger state machine transitions to the "Timer Fault" state.
• If the watchdog timer is not serviced, the charger state machine transitions to the "Watchdog Suspend" state. The battery charger dissipates the most power in the fast-charge constant current state. This power dissipation causes the internal die temperature to rise. If the die temperature exceeds the threshold set by REGTEMP[1:0], IFC is reduced. This is covered in Section 8.8.1 "Thermal regulation".

Table 47. Charger current control register The fast charge current is programmable via I2C using the bits in Table 48. Table 48. Constant current charge settings

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 CHG_CC[4:0] setting IFC current (mA) 00010 200 00011 250 00100 300 00101 350 00110 400 00111 450 01000 500 01001 550 01010 600 01011 650 01100 700 01101 750 01110 800 01111 850 10000 900 10001 950 10010 1000 10011 1050 (Reserved) 10100 1100 (Reserved) 10101 1150 (Reserved) 10110 1200 (Reserved) 10111 1250 (Reserved) 11000 1300 (Reserved) 11001 1350 (Reserved) 11010 1400 (Reserved) 11011 1450 (Reserved) 11100 1500 (Reserved) 11101 1550 (Reserved) 11110 1600 (Reserved) 11111 1650 (Reserved) To insure proper operation, the maximum CC current selected must be one setting below input current limit (in charger normal mode). In normal mode, when VSYS < VSYSMINLOOPx (VSYSMINLOOPx = VSYSMINx − 300 mV), digital logic automatically controls maximum CC current (one setting lower than charger input current limit ILIM setting). If 100 mA input current limit is selected, the charge current is forced to 50 mA to allow enough current for VSYS. The Charger Low-power mode (CLPM) is entered automatically when the 50 mA input current limit setting, or lower, is selected and when VBATT > 2.8 V.

8.5.3 Fast charge constant voltage state

VBATREG from the fast-charge CC state. exponentially in this state as the battery becomes fully charged.

• The charger input is in input current limit
• The charger input voltage is low
• The system load is consuming adapter current. The system load always gets priority over the battery charge current. The following events cause the state machine to exit this state:
• When the charger current is below IEOC for tSCIDG, the charger enters the next state in the charging cycle: “End-of-Charge”.
• If the battery charger remains in this state for longer than tFC, the charger state machine transitions to the “Timer Fault” state.
• If the watchdog timer is not serviced, the charger state machine transitions to the “Watchdog Suspend” state. Note: During the CC to CV transition, the charge current can be momentarily higher than IFC. This current is safe and does not result in over charging the battery. After this transition, the charge current decays and is less than or equal to IFC.

Table 49. Battery regulation voltage register The CV setting is programmable via I2C using the bits in Table 50. Table 50. CV settings

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 CHGCV[5:0] Output voltage (V) 001011 3.56 001100 3.58 001101 3.60 001110 3.62 001111 3.64 010000 3.66 010001 3.68 010010 3.70 010011 3.72 010100 3.74 010101 3.76 010110 3.78 010111 3.80 011000 3.82 011001 3.84 011010 3.86 011011 3.88 011100 3.90 011101 3.92 011110 3.94 011111 3.96 100000 3.98 100001 4.00 100010 4.02 100011 4.04 100100 4.06 100101 4.08 100110 4.10 100111 4.12 101000 4.14 101001 4.16 101010 4.18 101011 [1] 4.20 101100 4.22 101101 4.24 101110 4.26 101111 4.28 110000 4.30 110001 4.32 110010 4.34 110011 4.36

Table 51. Charger timers register Table 52. Fast charge timer settings

000 Disable

(via CHG_OPER), or accept it as an actual timer fault.

8.5.4 End-of-charge state

typically the charge current is less than or equal to IEOC.

• The charger input is in input current limit
• The charger input voltage is low
• The system load is consuming adapter current. The system load always gets priority over the battery charge current. The following events cause the state machine to exit this state:
• After being in this state for the end-of-charge time (tEOC), the charger enters the next state in the charging cycle: “DONE”.
• If VBATT < VBATREG – VRESTART, the charger goes back to the “FAST CHARGE (CC)” state.
• If the watchdog timer is not serviced, the charger state machine transitions to the “Watchdog Suspend” state.

Table 53. Charger EOC configuration register Table 54. EOC current thresholds

101 Reserved

110 Reserved

111 Reserved

Table 55. Charger timers register Table 56. EOC state timer settings

8.5.5 Done state

CHG_OK is cleared and CHG_SNS = 0x04.

• If VBATT < VBATREG – VRESTART, the charger goes back to the "FAST CHARGE (CC)" state
• If the watchdog timer is not serviced, the charger state machine transitions to the "Watchdog Suspend" state In the done state, the charge current into the battery (ICHG) is 0 A. In the done state, the charger presents a very light load to the battery. If the system load presented to the battery is low (<<100 µA), then a typical system can remain in the done state for many days. If left in the done state long enough, the battery voltage decays below the restart threshold (VRESTART) and the charger state machine transitions back into the fast-charge CC state. There is no soft start (di/dt limiting) during the done state to fast-charge state transition. In the done state, the BATFET is fully closed. The correct way to trigger restart feature is to pull loading from VSYS, in order to discharge VBATT.

8.6 Battery supplement mode

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 battery capacity can be chosen to handle periods of peak loading, which may be currents higher than supported by the VBUS supply. If the system load current exceeds the VBUS input current limit, the VSYS supply current is no longer be able to support the load demand and the VSYS output voltage decreases. When VSYS falls below VBATT, the PF1550 suspends charging and enters the Battery supplement mode. In this mode, the battery provides current to support the VSYS load demand. If the load demand on VSYS now decreases, the VSYS output voltage recovers, and begins to rise. When VSYS rises above VBATT, the PF1550 exits the Battery supplement mode and resumes charging the battery in the CC charging phase. When VBATT decreases lower than the restart threshold, the part enters CC state from DONE. Then if the loading on VSYS decreases and VSYS > VBATT, charger starts to charge from the CC state.

8.7 Power path features

8.7.1 VSYS regulation

In the case of a low battery, the LDO path regulates VSYS to either 3.5 V, 3.7 V, or 4.3 V. This allows the system to power up with a low battery while the battery gets charged. See Table 46.

8.7.2 Input current limit

The default settings of the VBUSIN and CHG_OPER control bits are such that when a charge source is applied to VBUSIN, the PF1550 turns on its linear regulator in LINEAR- ON or CHARGE-ON (via OTP), and limits the charge current to 100 mA (via OTP). See Section 12 "Register map" for the default values for specific registers/bits. The input current limit works by monitoring the current being drawn from the input and comparing it to the programmed current limit. The current limit should be set based on the current-handling capability of the input adapter. Generally, this limit is chosen to optimally fulfill the system-power requirements while achieving a satisfactory charging time for the batteries. If the adapter current exceeds its output capability, the charger responds by reducing the charger current, thus keeping the current drawn from the adapter within its capability. There is a precision current sense circuitry that monitors the input current whenever internal INT_2P7 is asserted. The input current limit logic signal is used to reduce quiescent current when the charger is not plugged in by turning off the current sense amplifier. The input current limit should include current consumed by the charger block. There is a low-power mode for the linear regulator where it consumes less than 2.5 mA bias current at 25 °C. This is useful for the 10 mA to 50 mA input current limit settings. The input current limit also includes a second control which is voltage-based. When it drops below the desired input, it generates an interrupt to decrease the fast-charge current. This is further covered in input voltage regulation mode.

Table 57. VBUS input current limit register The table below shows valid input current limit settings. Table 58. Input current limit settings

11110 Reserved

11111 Reserved

8.7.3 Battery thermistor

hysteresis. There are I2C selections for the THOT and TCOLD temperature threshold.

8.7.4 BATFET soft start

that prevents high inrush currents into the capacitors at the VSYS node. to cover this in production as there are no critical pass/fail criteria for this feature.

8.8 Thermal

8.8.1 Thermal regulation

Figure 18. Thermal regulation Table 59. Thermal regulation

11 N/A N/A N/A 125 °C

As shown in the following figure, a hysteresis mechanism is implemented.

Figure 19. Thermal regulation (Current versus Temp, example with REGTEMP[1:0] = 00 and arrows represent when the CHG_I interrupt is generated. Figure 20. Thermal regulation (Current, Temp versus Time, example with REGTEMP[1:0] =

8.8.2 Thermal foldback

is reduced to 25 % of the final CC charging current value. is reduced to 12.5 % of the final CC charging current value. If the charger temperature reaches 125 °C, charging current is reduced to 100 mA. The thermal foldback function is not available for LPM. current min. out of the fold back function is clamped at 100 mA. Table 60. Temperature regulation control register Table 61. Thermal regulation settings

8.8.3 Input voltage regulation mode

generated after the debounce time to notify the processor of the DPM event. In the following figure, VBUS starts to drop as the charging current increases. Figure 21. Response to input voltage droop during charging The following figure describes a more stringent event.

Figure 22. DPM function comparator. The incrementing continues only if it is. Table 62. VBUS linear dynamic input voltage register Table 63. Input voltage regulation thresholds

8.8.4 JEITA thermal control

Table 64. JEITA thermal control Regulation and Control Register 0x92. Table 65. Temperature regulation control register

Figure 23. CC charge current and CV charge voltage adjustment TWARM thresholds are crossed. CC_ADJ[1:0]. CV voltage is not changed. This feature can be disabled if THM_CNFG[1:0] is set to 0x01. TWARM threshold when THM_CNFG[1:0] = 0x01. The charger parameters must not be locked by OTP to use this software function. If the thermistor functionality is not needed, THM_CNFG[1:0] can be set 0x00. Table 66. JEITA temperature control register

Table 67. CV voltage adjustment settings Table 68. CC current adjustment settings

8.9 Fault states

8.9.1 Timer fault state

charger is allowed to remain in each of its pre-qualification states is tPRECHG. which is programmable with FCHGTIME. is generated without a delay, CHG_OK is cleared and CHG_SNS = 0x06. VSYS should continue to regulate while in the Timer fault state.

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019

8.9.2 Watchdog timer state

The battery charger provides both a charge timer and a watchdog timer to ensure safe charging. The watchdog timer protects the battery from charging indefinitely in the event that the host hangs or otherwise cannot communicate correctly. The watchdog timer is disabled by default with WDTEN = 0. To use the watchdog timer feature, enable the feature by setting WDTEN. While enabled, the system controller must reset the watchdog timer within the timer period (tWD) for the charger to operate normally. Reset the watchdog timer by programming WDTCLR = 0x01. As long as WDTEN = 1, the timer continues to run and the processor continues to clear the register before the timer expires. The system processor clears the WDTEN bit to stop the timer. If the watchdog timer expires while the charger is in precharge mode, fast charge CC or CV, end-of-charge, done, or timer fault, the charging stops, a CHG_I interrupt is generated without a delay, CHG_OK is cleared, and CHG_SNS = 0x0B and indicates that the charger is off because the watchdog timer has expired. Once the watchdog timer has expired, the charger is restarted by programming WDTCLR=0x01. The VSYS node is supported by the battery and/or the adapter through the Linear regulator while the watchdog timer is expired.

8.9.3 Thermal shutdown state

The thermal shutdown state occurs when the battery charger is in any state and the junction temperature (TJ) exceeds the device’s thermal shutdown threshold (TSHDN), typical 140 °C. When TJ is close to TSHDN the charger folds back the charging current to 0 A, so the charger is effectively off. Upon entering this state, CHG_I interrupt is generated without a delay, CHG_OK is cleared. In the thermal shutdown state, the charger is off and timers are suspended. CHG_SNS = 0x0A and CHG_OK = 0 in the thermal shutdown state. The charger exits the temperature suspend state and returns to the state it came from once the die temperature has cooled. The timers resume once the charger exits this state. VSYS continues to regulate while in the thermal shutdown state.

8.9.4 Battery overvoltage state

A battery overvoltage fault occurs in any state when the battery voltage exceeds to VBATOV threshold. In this state, BAT_SNS = 0x09 and BAT_OK = 0. A BATT_I interrupt is generated in this state. In the event of a battery overvoltage state, the BATFET is opened and VSYS is regulated using the linear path. Once the battery overvoltage condition clears, the charger exits the battery overvoltage state and returns to the state it came from.

8.9.5 Charger fault priority

Some of the charger fault states occur at the same time. For example, battery overvoltage and thermal shutdown occur at the same time. In this section, which failure states take priority is discussed.

8.9.6 Battery overcurrent limit

the signal to the PMIC on/off controller. mechanical failure that causes a short-circuit. The battery overcurrent protection feature is enabled with BATFET_OC[1:0] bit. bit) to either disable the BATFET after completion of housekeeping routine or remain on. Figure 24. Response to battery overcurrent Table 69. Battery overcurrent thresholds

00 Disabled

8.10 LED indicator

automatically when charging is started and remain under control of the state machine. 32/32 takes 500 ms whereas going to from 8/32 to 16/32 takes 125 ms. Table 70. LED modes Table 71. LED enable conditions

1 On 1

0 Off 1

Table 72. LED frequency setting

9 Control and interface signals

9.1 PWRON

= 0), or as an edge sensitive input (OTP_PWRON_CFG = 1). turns off the part, or puts it into Sleep mode. seconds, the part turns off or enters Sleep mode. Table 73. PWRON pin OTP configuration options

0 PWRON pin HIGH = ON

1 PWRON pin pulled LOW momentarily = ON

Table 74. PWRON pin logic level momentarily while in RUN or STANDBY modes. Only an interrupt is generated. See Section 10 "PF1550 state machine" for detailed description.

interrupt is cleared by software, or when cycling through the REGS_DISABLE mode. Table 75. PWRONDBNC settings

9.2 STANDBY

active high or active low using the STANDBYINV bit. Table 76. Standby pin polarity control Table 77. STANDBY pin logic level made for three additional 32 kHz cycles required to synchronize the Standby event.

9.3 RESETBMCU

supplies have been enabled; it is only asserted during a turn off event.

occurs and persists for 1.8 ms typically, RESETBMCU is asserted low. signal restarts the part, if the fault persists, the sequence described above is repeated. To enter the fault mode, set bit OTP_PWRGD_EN to 1. deasserted is programmable between 2.0 ms and 1024 ms via OTP_POR_DLY[2:0] bits. Table 78. RESETBMCU pin logic level

9.4 INTB

which requires writing a “1” to the interrupt bit. polling for status from the IC. Table 79. INTB pin logic level

9.5 WDI

Table 80. WDI pin logic level

9.6 ONKEY

Table 81. ONKEY pin logic level Table 82. ONKEYDBNC settings keypress. The interrupt is generated during the rising edge of the ONKEY pin. See Section 12 "Register map" for detailed description of the ONKEY interrupt registers.

9.7 Control interface I2C block description

controlled. The registers also provide status information about how the IC is operating.

9.7.1 I2C device ID

bus. The PF1550 I2C device address is 0x08.

9.7.2 I2C operation

or NACK is received prior to completion. Figure 25. I2C sequence

10 PF1550 state machine

The PMIC part of the PF1550 can operate in a number of states as shown in Figure 26.

1. “System On” that includes the RUN, STANDBY, and SLEEP modes
2. “System Off” that includes the REGS_DISABLE, CORE_OFF, and SHIP modes

Figure 26. PMIC state machine general the system processor is powered. the Run mode requires a Turn On event. See Section 10.3 "Turn on events". Transition from any of the “System On” modes to the REGS_DISABLE state is allowed. This transition is referred to as a Turn Off event. See Section 10.4 "Turn off events".

10.1 System ON states

10.1.1 Run state

In this state, the PMIC regulators are enabled and the system is powered up. RESETBMCU is de-asserted in this state.

1. From REGS_DISABLE through a Turn On Event: During this transition, the PMIC

regulators are powered, the RESETBMCU pin is de-asserted.

1. From STANDBY by using the STANDBY pin
2. From SLEEP mode by using the PWRON pin: Typically, some of the regulators are

time slot. RESETBMCU is de-asserted through this state transition.

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019

10.1.2 STANDBY state

This state is entered by controlling the logic level of the STANDBY pin. It can be entered only from the RUN mode. The STANDBY pin polarity is programmable through the STANDBYINV I2C bit. By default, STANDBYINV = 0 and a logic high on the STANDBY pin moves the state machine from the RUN state to the STANDBY state. When STANDBYINV = 1, a logic low moves the state machine from the RUN state to the STANDBY state. Regulator output voltage may be changed, or regulator outputs could be disabled while entering the STANDBY state and vice versa. For details on the power-down sequence, see Section 10.7 "Regulator power-down sequencer". While exiting STANDBY state into the RUN mode, regulator output voltage changes and regulator enables follow the power-up sequence. It is possible to exit STANDBY state and enter the SLEEP state. SLEEP state is generally a lower power system state compared to the STANDBY state. Exiting STANDBY into the SLEEP state follows the power-down sequence. RESETBMCU is de-asserted in the STANDBY state.

10.1.3 SLEEP state

This state is entered from either the RUN state or the STANDBY state by controlling the PWRON pin. The exact condition required for this transition depends on the OTP configuration of the PWRON pin. For details see Section 9.1 "PWRON". The power-down sequence is followed while entering this state and the power-up sequence is followed while exiting this state into the RUN state. RESETBMCU is de-asserted in the SLEEP state.

10.2 System OFF states

RESETBMCU is asserted (low) in all the System Off states.

10.2.1 REGS_DISABLE

This state can be considered the ‘home state’ for the state machine. In this state, the state machine waits for appropriate commands to proceed to other states. REGS_DISABLE can be entered from one of the “System On” state through a turn off event. REGS_DISABLE can be entered from the CORE_OFF and SHIP mode by a charger attach event. In the REGS_DISABLE state, the PMIC core circuitry is active. VSNVS is a best-of- supply output of VSYS and LICELL.

10.2.2 CORE_OFF

This state is entered in two ways: 1. From the REGS_DISABLE mode by pressing and holding the ON_KEY button low > Tgreset 2. From the REGS_DISABLE mode if the GOTO_CORE_OFF bit is set

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 This state cannot be entered if a charger is plugged in. In this state, the internal core of the PMIC is turned off to reduce quiescent current. VSNVS is the only regulator that is supplied to external loads.

10.2.3 SHIP

In this mode, the MBATT switch between VSYS and VBATT is opened. All the PMIC supplies including VSNVS are turned off. The SHIP mode is entered if the GOTO_SHIP bit is set in the REGS_DISABLE state. The only way to exit from this mode is by a charger attach event. The state machine exits to the REGS_DISABLE state when this happens. A battery reattach can also be used to exit SHIP mode.

10.3 Turn on events

A turn on event takes the PMIC from the REGS_DISABLE state to the RUN state (transition H in Figure 26). The turn on events are: 1. PWRON logic high with PWRON_CFG = 0 2. PWRON H -> L with PWRON_CFG = 1 VSYS > UVDETrising and TJ < TSHDN_fall are preconditions for a turn on event to occur. The turn on is to be completed after the RESETBMCU pin is deasserted. The WDI pin is masked till the RESETBMCU pin is deasserted.

10.4 Turn off events

A turn off event takes the PMIC state machine from one of the “System On” states (RUN, STANDBY, or SLEEP) to the REGS_DISABLE state. The power-down sequence is followed during all of the turn off events. The turn off events are: 1. Thermal Shutdown (TJ > TSHDN_rise) 2. PWRON logic low with OTP_PWRON_CFG = 0 3. PWRON low > 4.0 s with OTP_PWRON_CFG = 1 && PWRONRSTEN = 1 4. WDI = 0. This occurs when the processor watchdog expires and pulls the WDI pin low to create a hard reset. 5. ON_KEY pressed low > Tgreset && ON_KEY_RST_EN = 1. This facilitates creating a hard reset when pressing the ON_KEY button without processor intervention. 6. GOTO_SHIP = 1. This is used to initiate the device to go into the SHIP mode. When GOTO_SHIP bit is set to 1, the state machine proceeds from one of the “System On” states to the REGS_DISABLE mode to the SHIP mode.

10.5 State diagram and transition conditions

Table 83. State transition table

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 Transi tion Description PWRON_CFG = 0 (Level sensitive) PWRON_CFG = 1 (Edge sensitive) H REGS_DISABLE to Run (Only if VSYS > UVDET and TJ < TSHDN_fall) (PWRON = 1 ) (PWRON High to Low ) OR (If entered REGS_DISABLE via long press on PWRON && RESTARTEN = 1 && PWRON stays Low > 1.0s) OR (Charger attach) [5] [6] I REGS_DISABLE to CORE_OFF (Only if VBUS_ INVALID = 1) (GOTO_CORE_OFF = 1 && ONKEY = OR (ONKEY High to Low and ONKEY = 0 > Tgreset && ONKEY_RST_EN = 1) [7][8] (GOTO_CORE_OFF = 1 && ONKEY = OR (ONKEY High to Low and ONKEY = 0 > Tgreset && ONKEY_RST_EN = 1) [7][9] J REGS_DISABLE to SHIP GOTO_SHIP = 1 && VBUS_INVALID = 1 [10] GOTO_SHIP = 1 && VBUS_INVALID = 1 [10] K CORE_OFF to REGS_DISABLE (ONKEY High to Low and ONKEY = 0 > 1000 ms) OR (Charger attach) (ONKEY High to Low and ONKEY = 0 > 1000 ms) OR (Charger attach) L SHIP to REGS_ DISABLE (Charger attach) OR (Battery reattach) (Charger attach) OR (Battery reattach) [1] This low period is < 4.0s. If it is longer than 4.0s, it transitions to G [2] PWRON pin is pulled low by processor after WDI = 0. [3] Follows regulator power-down sequence for this transition [4] REGS_DISABLE is a transitionary state when GOTO_SHIP = 1. The state machine does not stay at G when GOTO_SHIP = 1 [5] WDI pin is masked until RESETBMCU is deasserted. [6] Debounce on PWRON programmable via PWRONDBNC[1:0] [7] PWRON pin is pulled low by processor after ONKEY = 0 > Tgreset. [8] GOTO_CORE_OFF is set by user when system is ON. For other products, a secondary processor is used to set this bit while in REGS_DISABLE [9] GOTO_CORE_OFF must be set by user when system is ON [10] VBUSIN pin voltage < 1.0 V

10.6 Regulator power-up sequencer

Start-up sequence of all the switching and linear regulators in the PF1550 is programmable. VSNVS's sequence is not programmable but is always the first regulator to power up when the PF1550 is powered up via a cold start (from no input to valid input). When SYS is first applied to the PF1550 (either by applying a battery, or by plugging in a charger), VSNVS comes up first. The switching and linear regulators power up based on their programmed OTP sequence using the respective OTP_XX_SEQ[2:0] when transitioning from REGS_DISABLE to the RUN state. RESETBMCU is pulled low from VCOREDIG POR until the end of the power-up sequencer. RESETBMCU is pulled high 2.0 ms to 1024 ms after the last regulator powers up. This delay is OTP programmable through the OTP_POR_DLY[2:0] bits.

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 When transitioning from STANDBY mode to RUN mode, the power-up sequencer is activated only if any of the regulators turn back on during this transition. The power-up sequencer ends as soon as the last regulator powers up, rather than waiting for a fixed time. The power-up sequencer is always activated when transitioning from Sleep to Run modes. The sequencer ends as soon as the last regulator powers up, rather than waiting for a fixed time. The PWRUP_I interrupt is set to indicate completion of transition from STANDBY to RUN and SLEEP to RUN. The PWRUP_I interrupt is set while transitioning from STANDBY to RUN even if the sequencers were not used. This is used to indicate that the transition is complete.

10.7 Regulator power-down sequencer

The power-down sequencer performs the functional opposite to the power-up sequencer. Each regulator has an associated register setting (SW1_PWRDN_SEQ[2:0], SW2_PWRDN_SEQ[2:0], SW3_PWRDN_SEQ[2:0], LDO1_PWRDN_SEQ[2:0], LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0], VREFDDR_PWRDN_SEQ[2:0]) that sets its power-down sequence. The default setting of the above registers is equal to the corresponding power-up sequence setting. For example, SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0]. When the power-down sequencer is activated, regulators are turned off one by one in the descending order of the XXX_PWRDN_SEQ[2:0] setting. This way, by default power- down is a mirror of the power-up sequence. In one of the "System On" states, the processor can change the values of the XXX_PWRDN_SEQ[2:0] registers. The power-up sequence is fixed by OTP (or TBB). If all XXX_PWRDN_SEQ[2:0] = 0x00, the power-down sequencer is bypassed and all the regulators are turned off at once. During transition from Run to Standby, the power-down sequencer is activated if any of the regulators are turned off during this transition. If regulators are not turned off during this transition, the power-down sequencer is bypassed and the transition happens at once (any associated DVS transitions still take time). During transition from Run to Sleep, the power-down sequencer is always activated. However, if all XXX_PWRDN_SEQ[2:0] = 0, the transition happens immediately. The PWRDN_I interrupt is set during transition from Run to Sleep and Run to Standby even if regulators are not turned off during these transitions.

11 Device start up

11.1 Startup timing diagram

The startup timing of the regulators is programmable through OTP, Figure 27 shows the startup timing of the regulators as determined by their OTP A4 sequence.

Figure 27. A4 startup and power down sequence Table 84. A4 startup and power down sequence timing

• OTP_SEQ_CLK_SPEED = 0
• OTP_SEQ_CLK_SPEED = 1 [3] 0.5 2.0 ms tR3 Rise time of regulators [4] — 0.2 — ms tD4 Turn-on delay of RESETBMCU — 2.0 — ms tR4 Rise time of RESETBMCU — 0.2 — ms tD5 Power down delay between regulators — 2.0 — ms [1] All regulators avoid drop-out mode at startup [2] Depends on the external signal driving PWRON [3] A4 configuration [4] Rise time is a function of slew rate of regulators and nominal voltage selected.

11.2 Device start up configuration

Table 85. PF1550 start up configuration

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 Pre-programmed OTP configuration Registers A1 A2 A3 A4 A5 A6 A7 A8 A9 OTP_SW3_PWRUP_SEQ[2:0] 3 1 3 2 3 3 3 3 3 OTP_LDO1_PWRUP_SEQ[2:0] 4 1 3 1 3 3 3 3 3 OTP_LDO2_PWRUP_SEQ[2:0] 4 1 2 2 2 2 2 2 3 OTP_LDO3_PWRUP_SEQ[2:0] 5 1 3 1 3 3 3 3 3 OTP_VREFDDR_PWRUP_SEQ[2:0] 5 5 3 3 3 3 3 3 3 OTP_SW1_DVS_SEL Non-DVS mode DVS mode Non-DVS mode OTP_SW2_DVS_SEL DVS mode Non-DVS mode DVS mode Non-DVS mode Non-DVS mode OTP_LDO1_LS_EN LDO Mode OTP_LDO3_LS_EN LS Mode LDO Mode OTP_SW1_RDIS_ENB Enabled OTP_SW2_RDIS_ENB Enabled OTP_SW3_RDIS_ENB Enabled OTP_SW1_DVSSPEED 12.5 mV step each 4.0 µs Non-DVS mode OTP_SW2_DVSSPEED 12.5 mV step each 2.0 µs 12.5 mV step each 4.0 µs Non-DVS mode OTP_SWx_EN_AND_STBY_EN SW1, SW2, SW3 Enabled in RUN and STANDBY OTP_LDOx_EN_AND_STBY_EN LDO1, LDO2, LDO3, VREFDDR Enabled in RUN and STANDBY OTP_PWRON_CFG Level Sensitive Edge Sensitive Level Sensitive OTP_SEQ_CLK_SPEED 0.5 ms Time Slots 2 ms Time Slots OTP_TGRESET[1:0] 4 secs Global Reset Timer OTP_POR_DLY[2:0] 2 ms RESETBMCU Power-Up Delay OTP_UVDET[1:0] Rising 3.0 V; Falling 2.9 V OTP_I2C_DEGLITCH_EN I2C Deglitch Filter Disabled OTP_CHGR_OPER[1:0] Charger = ON, Linear = ON Charger = OFF, Linear = ON Charger = ON, Linear = ON Charger = ON, Linear = ON Charger = ON, Linear = ON Charger = OFF, Linear = ON Charger = ON, Linear = ON Charger = ON, Linear = ON Charger = OFF, Linear = ON OTP_CHGR_TPRECHG Pre-charge timer = 30 minutes OTP_CHGR_EOCTIME[2:0] End-Of-Charge Debounce = 16 secs OTP_CHGR_FCHGTIME[2:0] Fast-Charge Timer Disabled OTP_CHGR_EOC_MODE Linear ON in the DONE state OTP_CHGR_CHG_RESTART[1:0] 100 mV below CHGCV OTP_CHGR_CHG_CC[4:0] CC = 100 mA CC = 500 mA CC = 100 mA OTP_CHGR_VSYSMIN[1:0] VSYSMIN = 4.3 V VSYSMIN = 3.7 V VSYSMIN = 4.3 V VSYSMIN = 3.7 V OTP_CHGR_CHGCV[5:0] CV = 4.2 V OTP_CHGR_VBUS_LIN_ILIM[4:0] VBUS ILIM = 500 mA VBUS ILIM = 1500 mA OTP_CHGR_USBPHYLDO USBPHY LDO Disabled USBPHY LDO Enabled OTP_CHGR_USBPHY USBPHY = 3.3 V OTP_CHGR_ACTDISPHY USBPHY Active Discharge Disabled USBPHY Active Discharge Enabled

12 Register map

12.1 Specific PMIC Registers (Offset is 0x00)

The following pages contain description of the various registers in the PF1550.

Table 86. Register DEVICE_ID - ADDR 0x00 Table 87. Register OTP_FLAVOR - ADDR 0x01 Table 88. Register SILICON_REV - ADDR 0x02 Table 89. Register INT_CATEGORY - ADDR 0x06

LDO_INT 4 R 0 This bit is set high if any of the LDO interrupt status bits are set. This includes LDO1, LDO2, and LDO3. Table 90. Register SW_INT_STAT0 - ADDR 0x08 current limit fault persists for longer than the debounce time. current limit fault persists for longer than the debounce time. current limit fault persists for longer than the debounce time. Table 91. Register SW_INT_MASK0 - ADDR 0x09 interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set.

interrupt status bit is set. interrupt status bit is set. Table 92. Register SW_INT_SENSE0 - ADDR 0x0A as fault persists (post-debounce). as fault persists (post-debounce). Table 93. Register SW_INT_STAT1 - ADDR 0x0B Table 94. Register SW_INT_MASK1 - ADDR 0x0C interrupt status bit is set. interrupt status bit is set.

interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. Table 95. Register SW_INT_SENSE1 - ADDR 0x0D report the sense status within the switching cycle. report the sense status within the switching cycle. report the sense status within the switching cycle. Table 96. Register SW_INT_STAT2 - ADDR 0x0E transitioning states, Run to Standby, for example). transitioning states, Run to Standby, for example).

Table 97. Register SW_INT_MASK2 - ADDR 0x0F interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. Table 98. Register SW_INT_SENSE2 - ADDR 0x10 Table 99. Register LDO_INT_STAT0 - ADDR 0x18 Table 100. Register LDO_INT_MASK0 - ADDR 0x19 interrupt status bit is set. interrupt status bit is set.

interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. Table 101. Register LDO_INT_SENSE0 - ADDR 0x1A Table 102. Register TEMP_INT_STAT0 - ADDR 0x20 THERM110I 0 RW1C[1] 0 Die temperature crosses 110 °C interrupt. Bidirectional interrupt. THERM125I 2 RW1C 0 Die temperature crosses 125 °C interrupt. Bidirectional interrupt. Table 103. Register TEMP_INT_MASK0 - ADDR 0x21 interrupt status bit is set. interrupt status bit is set.

interrupt status bit is set. interrupt status bit is set. Table 104. Register TEMP_INT_SENSE0 - ADDR 0x22 Table 105. Register ONKEY_INT_STAT0 - ADDR 0x24

Table 106. Register ONKEY_INT_MASK0 - ADDR 0x25 interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. Table 107. Register ONKEY_INT_SENSE0 - ADDR 0x26 of the ONKEY button being released. debounce circuit (debounce is programmable).

Table 108. Register MISC_INT_STAT0 - ADDR 0x28

Table 109. Register MISC_INT_MASK0- ADDR 0x29 interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. Table 110. Register MISC_INT_SENSE0 - ADDR 0x2A

Table 111. Register COINCELL_CONTROL - ADDR 0x30 Table 112. Register SW1_VOLT - ADDR 0x32 Table 113. Register SW1_STBY_VOLT - ADDR 0x33 value here should be identical to SW1_VOLT[5:0] register. Table 114. Register SW1_SLP_VOLT - ADDR 0x34 value here should be identical to SW1_VOLT[5:0] register. Table 115. Register SW1_CTRL - ADDR 0x35 sequence settings. User can turn off regulator by clearing this bit.

be equal to the SW1_EN bit (based on OTP). Table 116. Register SW1_SLP_VOLT - ADDR 0x36

Table 117. Register SW2_VOLT - ADDR 0x38 Table 118. Register SW2_STBY_VOLT - ADDR 0x39 value here should be identical to SW2_VOLT[5:0] register. Table 119. Register SW2_SLP_VOLT - ADDR 0x3A value here should be identical to SW2_VOLT[5:0] register. Table 120. Register SW2_CTRL - ADDR 0x3B sequence settings. User can turn off regulator by clearing this bit. be equal to the SW1_EN bit (based on OTP).

1 — Forced in PWM mode irrespective of load current. Table 121. Register SW2_CTRL1 - ADDR 0x3C Table 122. Register SW3_VOLT - ADDR 0x3E SW3_VOLT 3 to 0 RW1S — SW3 voltage setting register (Run mode). Loaded from fuses. Read only because DVS is not supported in this regulator.

Table 123. Register SW3_STBY_VOLT - ADDR 0x3F SW3_STBY_VOLT 3 to 0 RW1S — SW3 voltage setting register (Standby mode). Loaded from fuses. Read only because DVS is not supported in this regulator. Table 124. Register SW3_SLP_VOLT - ADDR 0x40 SW3_SLP_VOLT 3 to 0 RW1S — SW3 voltage setting register (Sleep mode). Loaded from fuses. Read only because DVS is not supported in this regulator. Table 125. Register SW3_CTRL - ADDR 0x41 sequence settings. User can turn off regulator by clearing this bit. be equal to the SW1_EN bit (based on OTP).

Table 126. Register SW3_CTRL1 - ADDR 0x42 Table 127. Register VSNVS_CTRL - ADDR 0x48 VSNVS_VOLT 2 to 0 RW1S 000 Not used in PF1550. Placeholder for future products. Table 128. Register VREFDDR_CTRL - ADDR 0x4A Table 129. Register LDO1_VOLT - ADDR 0x4C LDO1_VOLT 4 to 0 RW1S — LDO1 output voltage setting register. Loaded from OTP.

Table 130. Register LDO1_CTRL - ADDR 0x4D sequence settings. User can turn off regulator by clearing this bit. to 1 on power-up. Changing from 1 to 0 is not allowed. Table 131. Register LDO2_VOLT - ADDR 0x4F LDO2_VOLT 3 to 0 RW1S — LDO2 output voltage setting register. Loaded from OTP. Table 132. Register LDO2_CTRL - ADDR 0x50 sequence settings. User can turn off regulator by clearing this bit.

Table 133. Register LDO3_VOLT - ADDR 0x52 LDO3_VOLT 4 to 0 RW1S — LDO3 output voltage setting register. Loaded from OTP. Table 134. Register LDO3_CTRL - ADDR 0x53 sequence settings. User can turn off regulator by clearing this bit. to 1 on power up. Changing from 1 to 0 is not allowed. Table 135. Register PWRCTRL0 - ADDR 0x58

Table 136. Register PWRCTRL1 - ADDR 0x59 0 — LDO does not shut down in the event of a current limit fault. "PF1550 state machine" for details.

Table 137. Register PWRCTRL2 - ADDR 0x5A Table 138. Register PWRCTRL3 - ADDR 0x5B "PF1550 state machine" for details. Table 139. Register SW1_PWRDN_SEQ - ADDR 0x5F default. Power-up sequence is in mirror registers. LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0]. SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0].

Table 140. Register SW2_PWRDN_SEQ - ADDR 0x60 default. Power-up sequence is in mirror registers. LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0]. SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0]. Table 141. Register SW2_PWRDN_SEQ - ADDR 0x61 default. Power-up sequence is in mirror registers. LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0]. SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0].

Table 142. Register LDO1_PWRDN_SEQ - ADDR 0x62 default. Power-up sequence is in mirror registers. LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0]. SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0]. Table 143. Register LDO2_PWRDN_SEQ - ADDR 0x63 default. Power-up sequence is in mirror registers. SEQ[2:0], LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0]. SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0].

Table 144. Register LDO3_PWRDN_SEQ - ADDR 0x64 default. Power-up sequence is in mirror registers. LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0]. SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0]. Table 145. Register VREFDDR_PWRDN_SEQ - ADDR 0x65 default. Power-up sequence is in mirror registers. LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0]. SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0].

Table 146. Register STATE_INFO - ADDR 0x67 Table 147. Register I2C_ADDR - ADDR 0x68 2 to 0 R 000 Loaded from fuses. But read only in functional space. Table 148. Register RC_16MHZ - ADDR 0x6B Table 149. Register KEY1 - ADDR 0x6B

12.2 Specific Charger Registers (Offset is 0x80)

Table 150. Register CHG_INT - ADDR 0x00 Table 151. Register CHG_INT_MASK - ADDR 0x02

Table 152. Register CHG_INT_OK - ADDR 0x04

Dynamic Power Management threshold. Table 153. Register VBUS_SNS - ADDR 0x06

Table 154. Register CHG_SNS - ADDR 0x07

Table 155. Register BATT_SNS - ADDR 0x08 threshold and charging has suspended and is in timer fault mode. This condition is also reported in the CHG_SNS as 0x06. when there is a valid input. Table 156. Register CHG_OPER- ADDR 0x09 the battery to support the system.

Table 157. Register CHG_TMR - ADDR 0x0A TPRECHG 7 RW1S 0 Precharge timer value. Used for low battery. Table 158. Register CHG_EOC_CNFG - ADDR 0x0D

register. This transition starts the end-of-charge timer (tEOC). Table 159. Register CHG_CURR_CNFG - ADDR 0x0E

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 Name Bit R/W Default Description PRECHGLB_THRS 6 to 5 RW1S 00 Precharge (low battery) charging voltage threshold setting 0 — 2.8 V 1 — 2.7 V (Reserved) 2 — 2.9 V (Reserved) 3 — 3.0 V (Reserved) Reset condition — VCOREDIG_RSTB RSVD7 7 RW 0 Reserved

Table 160. Register BATT_REG - ADDR 0x0F

Table 161. Register BATFET_CNFG - ADDR 0x11 watchdog timer when the watchdog timer is enabled. 1 — BATFET is not turned off when battery overcurrent occurs. Charger operation remains undisturbed by overcurrent event.

Table 162. Register THM_REG_CNFG - ADDR 0x12 THM_CNFG 1 to 0 RW1S 01 Thermistor configuration. 2 bits adjustment. TCOOL/cold, TWARM/hot thresholds are crossed. temperature > THOT or < TCOLD. temperature > TWARM and < TCOOL. current is reduced at battery temperature > TWARM and < TCOOL. Charger voltage is not changed. greater than the REGTEMP set point.

Table 163. Register VBUS_INLIM_CNFG - ADDR 0x14 Table 164. Register VBUS_LIN_DPM - ADDR 0x15

Table 165. Register USB_PHY_LDO_CNFG - ADDR 0x16 Table 166. Register DBNC_DELAY_TIME - ADDR 0x18

Table 167. Register CHG_INT_CNFG - ADDR 0x19 Table 168. Register THM_ADJ_SETTING - ADDR 0x1A

Table 169. Register VBUS2SYS_CNFG - ADDR 0x1B Table 170. Register LED_PWM - ADDR 0x1C

Table 171. Register FAULT_BATFET_CNFG - ADDR 0x1D Table 172. Register LED_CNFG - ADDR 0x1E

Table 173. Register LED_CNFG - ADDR 0x1F

12.3 Register PMIC bitmap

Table 174. Register PMIC bitmap

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 BITS[7:0]Addre ss Register name 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 1 1 1 0x09 SW_INT_MASK0 Reset 0 0 0 0 0 0 0 0 0x0A SW_INT_ SENSE0 Reset 0 0 0 0 0 0 0 0 0x0B SW_INT_STAT1 Type — — — — — RW1C RW1C RW1C Reset 0 0 0 0 0 1 1 1 0x0C SW_INT_MASK1 Reset 0 0 0 0 0 0 0 0 0x0D SW_INT_ SENSE1 DONE_I SW1_DVS_ DONE_I Reset 0 0 0 0 0 0 0 0 0x0E SW_INT_STAT2 DONE_M SW1_DVS_ DONE_M Reset 0 0 0 0 0 0 1 1 0x0F SW_INT_MASK2 Reset 0 0 0 0 0 0 0 0 0x10 SW_INT_ SENSE2 Name — — — — — LDO3_FAULTI LDO2_FAULTI LDO1_FAULTI Reset 0 0 0 0 0 0 0 0 0x18 LDO_INT_ STAT0 Type — — — — — RW1C RW1C RW1C Name — — — — — LDO3_FAULTM LDO2_FAULTM LDO1_FAULTM Reset 0 0 0 0 0 1 1 1 0x19 LDO_INT_ MASK0 Name — — — — — LDO3_FAULTS LDO2_FAULTS LDO1_FAULTS Reset 0 0 0 0 0 0 0 0 0x1A LDO_INT_ SENSE0 Name — — — — — THERM125I — THERM110I Reset 0 0 0 0 0 0 0 0 0x20 TEMP_INT_ STAT0 Name — — — — — THERM125M — THERM110M Reset 0 0 0 0 1 1 1 1 0x21 TEMP_INT_ MASK0 0x22 TEMP_INT_ SENSE0 Name — — — — — THERM125S — THERM110S Reset 0 0 0 0 0 0 0 0 Name — — ONKEY_8SI ONKEY_4SI ONKEY_3SI ONKEY_2SI ONKEY_1SI ONKEY_PUSHI Reset 0 0 0 0 0 0 0 0 0x24 ONKEY_INT_ STAT0 Type — — RW1C RW1C RW1C RW1C RW1C RW1C Name — — ONKEY_8SM ONKEY_4SM ONKEY_3SM ONKEY_2SM ONKEY_1SM ONKEY_PUSHM Reset 0 0 1 1 1 1 1 1 0x25 ONKEY_INT_ MASK0 Type — — RW RW RW RW RW RW Name — — ONKEY_8SS ONKEY_4SS ONKEY_3SS ONKEY_2SS ONKEY_1SS ONKEY_PUSHS Reset 0 0 0 0 0 0 0 0 0x26 ONKEY_INT_ SENSE0 Type — — R R R R R R WARN_I PWRON_I PWRDN_I PWRUP_I Reset 0 0 0 0 0 0 0 0 0x28 MISC_INT_ STAT0 Type — — — RW1C RW1C RW1C RW1C RW1C WARN_M PWRON_M PWRDN_M PWRUP_M0x29 MISC_INT_ MASK0 Reset 0 0 0 1 1 1 1 1

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 BITS[7:0]Addre ss Register name 7 6 5 4 3 2 1 0 Type — — — RW RW RW RW RW WARN_S PWRON_S PWRDN_S PWRUP_S Reset 0 0 0 0 0 0 0 0 0x2A MISC_INT_ SENSE0 Type — — — R R R R R Name COINCHEN VCOIN[3:0] Reset 0 0 0 0 0 0 0 0 0x30 COINCELL_ CONTROL Type — — — RW RW RW RW RW Name — — SW1_VOLT[5:0] Reset 0 0 0 0 0 0 0 0 0x32 SW1_VOLT Type — — RW1S RW1S RW1S RW1S RW1S RW1S Name — — SW1_STBY_VOLT[5:0] Reset 0 0 0 0 0 0 0 0 0x33 SW1_STBY_ VOLT Type — — RW1S RW1S RW1S RW1S RW1S RW1S Name — — SW1_SLP_VOLT[5:0] Reset 0 0 0 0 0 0 0 0 0x34 SW1_SLP_VOLT Type — — RW1S RW1S RW1S RW1S RW1S RW1S Name SW1_RDIS_ENB SW1_FPWM SW1_FPWM_ IN_DVS SW1_ DVSSPEED SW1_LPWR SW1_OMODE SW1_STBY_EN SW1_EN Reset 0 0 0 0 0 0 0 0 0x35 SW1_CTRL Type RW1S RW RW RW1S RW RW RW1S RW1S Name — — — SW1_TMODE_SEL — — SW1_ILIM[1:0] Reset 0 0 0 0 0 0 0 0 0x36 SW1_CTRL1 Type — — — RW — — RW1S RW1S Name — — SW2_VOLT[5:0] Reset 0 0 0 0 0 0 0 0 0x38 SW2_VOLT Type — — RW1S RW1S RW1S RW1S RW1S RW1S Name — — SW2_STBY_VOLT[5:0] Reset 0 0 0 0 0 0 0 0 0x39 SW2_STBY_ VOLT Type — — RW1S RW1S RW1S RW1S RW1S RW1S Name — — SW2_SLP_VOLT[5:0] Reset 0 0 0 0 0 0 0 0 0x3A SW2_SLP_VOLT Type — — RW1S RW1S RW1S RW1S RW1S RW1S Name SW2_RDIS_ENB SW2_FPWM SW2_FPWM_ IN_DVS SW2_ DVSSPEED SW2_LPWR SW2_OMODE SW2_STBY_EN SW2_EN Reset 0 0 0 0 0 0 0 0 0x3B SW2_CTRL Type RW1S RW RW RW1S RW RW RW1S RW1S Name — — — SW2_TMODE_SEL — — SW2_ILIM[1:0] Reset 0 0 0 0 0 0 0 0 0x3C SW2_CTRL1 Type — — — RW — — RW1S RW1S Name — — — — SW3_VOLT[3:0] Reset 0 0 0 0 0 0 0 0 0x3E SW3_VOLT Type — — — — RW1S RW1S RW1S RW1S Name — — — — SW3_STBY_VOLT[3:0] Reset 0 0 0 0 0 0 0 0 0x3F SW3_STBY_ VOLT Type — — — — RW1S RW1S RW1S RW1S Name — — — — SW3_SLP_VOLT[3:0] Reset 0 0 0 0 0 0 0 0 0x40 SW3_SLP_VOLT Type — — — — RW1S RW1S RW1S RW1S Name SW3_RDIS_ENB SW3_FPWM — SW3_ DVSSPEED SW3_LPWR SW3_OMODE SW3_STBY_EN SW3_EN Reset 0 0 0 0 0 0 0 0 0x41 SW3_CTRL Type RW1S RW — RW1S RW RW RW1S RW1S Name — — — SW3_TMODE_SEL — — SW3_ILIM[1:0] Reset 0 0 0 0 0 0 0 0 0x42 SW3_CTRL1 Type — — — RW — — RW1S RW1S Name — — LIBGDIS FORCEBOS CLKPULSE VSNVS_VOLT[2:0] Reset 0 0 0 0 0 0 0 0 0x48 VSNVS_CTRL Type — — RW RW RW RW1S RW1S RW1S 0x4A VREFDDR_ CTRL LPWR VREFDDR_ OMODE VREFDDR_ STBY_EN VREFDDR_EN

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 BITS[7:0]Addre ss Register name 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Type — — — — RW RW RW1S RW1S Name — — — LDO1_VOLT[4:0] Reset 0 0 0 0 0 0 0 0 0x4C LDO1_VOLT Type — — — RW1S RW1S RW1S RW1S RW1S Name — — — LDO1_LS_EN LDO1_LPWR LDO1_OMODE LDO1_STB Y_EN VLDO1_EN Reset 0 0 0 0 0 0 0 0 0x4D LDO1_CTRL Type — — — RW1S RW RW RW1S RW1S Name — — — — LDO2_VOLT[3:0] Reset 0 0 0 0 0 0 0 0 0x4F LDO2_VOLT Type — — — — RW1S RW1S RW1S RW1S Name — — — — LDO2_LPWR LDO2_OMODE LDO2_STB Y_EN VLDO2_EN Reset 0 0 0 0 0 0 0 0 0x50 LDO2_CTRL Type — — — — RW RW RW1S RW1S Name — — — LDO3_VOLT[4:0] Reset 0 0 0 0 0 0 0 0 0x52 LDO3_VOLT Type — — — RW1S RW1S RW1S RW1S RW1S Name — — — LDO3_LS_EN LDO3_LPWR LDO3_OMODE LDO3_STB Y_EN VLDO3_EN Reset 0 0 0 0 0 0 0 0 0x53 LDO3_CTRL Type — — — RW1S RW RW RW1S RW1S Name TGRESET[7:6] POR_DLY[5:3] STANDBYINV STANDBYDLY[1:0] Reset 0 0 0 0 0 0 0 1 0x58 PWRCTRL0 Type RW1S RW1S RW1S RW1S RW1S RW RW RW Name ONKEY_RST_EN REGSCPEN RESTARTEN PWRONRSTEN ONKEYDBNC[3:2] PWRONDBNC[1:0] Reset 1 0 0 0 0 0 0 0 0x59 PWRCTRL1 Type RW RW RW RW RW RW RW RW Name — — — — LOW_SYS_WARN[3:2] UVDET[1:0] Reset 0 0 0 0 0 0 0 0 015A PWRCTRL2 Type — — — — RW RW RW1S RW1S Name — GOTO_CORE_ OFF GOTO_SHIP Reset 0 0 0 0 0 0 0 0 0x5B PWRCTRL3 Type RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0x5F SW1_PWRDN_ SEQ Type — — — — — RW1S RW1S RW1S Reset 0 0 0 0 0 0 0 0 0x60 SW2_PWRDN_ SEQ Type — — — — — RW1S RW1S RW1S Reset 0 0 0 0 0 0 0 0 0x61 SW3_PWRDN_ SEQ Type — — — — — RW1S RW1S RW1S Reset 0 0 0 0 0 0 0 0 0x62 LDO1_PWRDN_ SEQ Type — — — — — RW1S RW1S RW1S Reset 0 0 0 0 0 0 0 0 0x63 LDO2_PWRDN_ SEQ Type — — — — — RW1S RW1S RW1S Reset 0 0 0 0 0 0 0 0 0x64 LDO3_PWRDN_ SEQ Type — — — — — RW1S RW1S RW1S Name — — — — — VREFDDR_PWRDN_SEQ[2:0] Reset 0 0 0 0 0 0 0 0 0x65 VREFDDR_ PWRDN_S EQ Type — — — — — RW1S RW1S RW1S Name — — STATE[5:0] Reset 0 0 0 0 0 0 0 0 0x67 STATE_INFO Type — — R R R R R R Name USE_DEFAULT_ ADDR — — — — I2C_SLAVE_ADDR_LSBS[2:0]0x68 I2C_ADDR Reset 0 0 0 0 0 0 0 0

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 BITS[7:0]Addre ss Register name 7 6 5 4 3 2 1 0 Type RW — — — — R R R Reset 0 0 0 0 0 0 0 0 0x69 IO_DRV0 Type RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0x6A IO_DRV1 HIPWR REQ_ACORE_ON REQ_16MHZ Reset 0 0 0 0 0 0 0 0 0x6B RC_16MHZ Name KEY1[7:0] Reset 0 0 0 0 0 0 0 0 0x6F KEY1 Type RW RW RW RW RW RW RW RW

12.4 Register charger bitmap

Table 175. Register charger bitmap

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 BITS[7:0]Address Register name 7 6 5 4 3 2 1 0 Name RSVD6[7:6] RSVD4[5:4] RSVD3 USBPHYLDO USBPHY ACTDISPHY Reset 0 0 0 0 0 0 0 1 0x16 USB_PHY_LDO_CNFG Type RW RW RW RW RW RW1S RW1S RW1S Name RSVD6[7:6] SYS_WKUP_DLY[5:4] USB_PHY_TDB[3:2] VBUS_OV_TDB[1:0] Reset 0 0 0 0 0 0 0 0 0x18 DBNC_DELAY_TIME Type RW RW RW1S RW1S RW1S RW1S RW1S RW1S Name RSVD2[7:2] EOC_INT CHG_INT_GEN Reset 0 0 0 0 0 0 0 0 0x19 CHG_INT_CNFG Type RW RW RW RW RW RW RW1S RW1S 0x1A THM_ADJ_SETTING Name RSVD6[7:6] CC_ADJ[5:4] CV_ADJ[3:2] THM_COOL THM_WARM Reset 0 0 0 0 0 0 0 0 Type RW RW RW1S RW1S RW1S RW1S RW1S RW1S Name RSVD3[7:3] VBUS2SYS_ THRSH VBUS2SYS_TDB[1:0] Reset 0 0 0 0 0 0 0 0 0x1B VBUS2SYS_CNFG Type RW RW RW RW RW RW1S RW1S RW1S Name LED_EN LED_RAMP LED_PWM[5:0] Reset 0 0 0 0 0 0 0 0 0x1C LED_PWM Type RW RW RW RW RW RW RW RW Name CTRL_CHGR_BETA_SEL[7:6] RSVD5 TMRFLT_BFET_ EN TSHDN_BFET_ EN THMSUS_ BFET_EN WDFLT_ BFEET_EN OVFLT_BFEET_ EN Reset 0 0 0 0 0 0 0 0 0x1D FAULT_BATFET_CNFG Type RW1S RW1S RW1S RW1S RW1S RW1S RW1S RW1S Name RSVD4[7:6] LEDOVRD LED_CFG LED_CURRENT[3:2] LED_FREQ[1:0] Reset 0 0 0 0 0 0 0 0 0x1E LED_CNFG Type RW RW RW RW1S RW1S RW1S RW RW Name CHGR_KEY2[7:0] Reset 0 0 0 0 0 0 0 0 0x1F CHGR_KEY2 Type RW RW RW RW RW RW RW RW

12.5 Register OTP bitmap

Table 176. Register OTP bitmap

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 BIT[7:0]Address Register name Value 7 6 5 4 3 2 1 0 0x21 OTP_VREF_ LDO1 OTP_LDO1_LS_EN OTP_LDO1_VOLT[4:0] OTP_ VREFDDREN_ AND_STBY_EN UNUSED A1 (Default) 0x16 0 0 0 1 0 1 1 0 A2 0x42 0 1 0 0 0 0 1 0 A3 0x42 0 1 0 0 0 0 1 0 A4 0x7E 0 1 1 1 1 1 1 0 A5 0x42 0 1 0 0 0 0 1 0 A6 0x42 0 1 0 0 0 0 1 0 A7 0x7E 0 1 1 1 1 1 1 0 A8 0x42 0 1 0 0 0 0 1 0 A9 0x6A 0 1 1 0 1 0 1 0 0x22 OTP_LDO1_ LDO2 UNUSED OTP_LDO2_EN_ AND_STBY_EN UNUSED OTP_LDO2_VOLT[3:0] OTP_LDO1_ EN_AND_ STBY_EN A1 (Default) 0x4F 0 1 0 0 1 1 1 1 A2 0x5F 0 1 0 1 1 1 1 1 A3 0x5F 0 1 0 1 1 1 1 1 A4 0x5F 0 1 0 1 1 1 1 1 A5 0x5F 0 1 0 1 1 1 1 1 A6 0x5F 0 1 0 1 1 1 1 1 A7 0x5F 0 1 0 1 1 1 1 1 A8 0x5F 0 1 0 1 1 1 1 1 A9 0x5F 0 1 0 1 1 1 1 1 0x23 OTP_LDO3 UNUSED OTP_LDO3_ EN_AND_ STBY_EN OTP_LDO3_ LS_EN OTP_LDO3_VOLT[4:0] A1 (Default) 0x65 0 1 1 0 0 1 0 1 A2 0x50 0 1 0 1 0 0 0 0 A3 0x5F 0 1 0 1 1 1 1 1 A4 0x50 0 1 0 1 0 0 0 0 A5 0x5F 0 1 0 1 1 1 1 1 A6 0x5F 0 1 0 1 1 1 1 1 A7 0x5F 0 1 0 1 1 1 1 1 A8 0x5F 0 1 0 1 1 1 1 1 A9 0x50 0 1 0 1 0 0 0 0 0x24 OTP_PMIC_ CFG1 UNUSED OTP_UVDET[1:0] OTP_POR_DLY[2:0] OTP_TGRESET[1:0] A1 (Default) 0x40 0 1 0 0 0 0 0 0 A2 0x40 0 1 0 0 0 0 0 0 A3 0x40 0 1 0 0 0 0 0 0 A4 0x40 0 1 0 0 0 0 0 0 A5 0x40 0 1 0 0 0 0 0 0 A6 0x40 0 1 0 0 0 0 0 0 A7 0x40 0 1 0 0 0 0 0 0 A8 0x40 0 1 0 0 0 0 0 0 A9 0x40 0 1 0 0 0 0 0 0 0x25 OTP_SW1_ SW2_SEQ UNUSED UNUSED OTP_SW2_PWRUP_SEQ[2:0] OTP_SW1_PWRUP_SEQ[2:0] A1 (Default) 0x11 0 0 0 1 0 0 0 1 A2 0x2D 0 0 1 0 1 1 0 1 A3 0x1B 0 0 0 1 1 0 1 1 A4 0x1C 0 0 0 1 1 1 0 0 A5 0x1B 0 0 0 1 1 0 1 1 A6 0x1B 0 0 0 1 1 0 1 1 A7 0x1B 0 0 0 1 1 0 1 1 A8 0x1B 0 0 0 1 1 0 1 1 A9 0x1B 0 0 0 1 1 0 1 1 0x26 OTP_SW3_ LDO1_SEQ UNUSED UNUSED OTP_LDO1_PWRUP_SEQ[2:0] OTP_SW3_PWRUP_SEQ[2:0] A1 (Default) 0x23 0 0 1 0 0 0 1 1 A2 0x09 0 0 0 0 1 0 0 1

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 BIT[7:0]Address Register name Value 7 6 5 4 3 2 1 0 A3 0x1B 0 0 0 1 1 0 1 1 A4 0x0A 0 0 0 0 1 0 1 0 A5 0x1B 0 0 0 1 1 0 1 1 A6 0x1B 0 0 0 1 1 0 1 1 A7 0x1B 0 0 0 1 1 0 1 1 A8 0x1B 0 0 0 1 1 0 1 1 A9 0x1B 0 0 0 1 1 0 1 1 0x27 OTP_LDO2_ LDO3_SEQ UNUSED UNUSED OTP_LDO3_PWRUP_SEQ[2:0] OTP_LDO2_PWRUP_SEQ[2:0] A1 (Default) 0x2C 0 0 1 0 1 1 0 0 A2 0x09 0 0 0 0 1 0 0 1 A3 0x1A 0 0 0 1 1 0 1 0 A4 0x0A 0 0 0 0 1 0 1 0 A5 0x1A 0 0 0 1 1 0 1 0 A6 0x1A 0 0 0 1 1 0 1 0 A7 0x1A 0 0 0 1 1 0 1 0 A8 0x1A 0 0 0 1 1 0 1 0 A9 0x1B 0 0 0 1 1 0 1 1 0x28 OTP_PMIC_ CFG2 OTP_SHIP_ COREOFF_CYA OTP_I2C_SLV_ADDR[2:0] OTP_I2C_ DEGLITCH_EN[0] OTP_VREFDDR_PWRUP_SEQ[2:0] A1 (Default) 0x05 0 0 0 0 0 1 0 1 A2 0x05 0 0 0 0 0 1 0 1 A3 0x03 0 0 0 0 0 0 1 1 A4 0x03 0 0 0 0 0 0 1 1 A5 0x03 0 0 0 0 0 0 1 1 A6 0x03 0 0 0 0 0 0 1 1 A7 0x03 0 0 0 0 0 0 1 1 A8 0x03 0 0 0 0 0 0 1 1 A9 0x03 0 0 0 0 0 0 1 1 0x29 RSVD UNUSED UNUSED UNUSED UNUSED Reserved (OTP_VSNVS_VOLT[2:0]) Reserved (OTP_FORCE_ LICELL) A1 (Default) 0x00 0 0 0 0 0 0 0 0 A2 0x00 0 0 0 0 0 0 0 0 A3 0x00 0 0 0 0 0 0 0 0 A4 0x00 0 0 0 0 0 0 0 0 A5 0x00 0 0 0 0 0 0 0 0 A6 0x00 0 0 0 0 0 0 0 0 A7 0x00 0 0 0 0 0 0 0 0 A8 0x00 0 0 0 0 0 0 0 0 A9 0x00 0 0 0 0 0 0 0 0 0x2A RSVD OTP_PMIC_SPARE0[7:0] A1 (Default) 0x00 0 0 0 0 0 0 0 0 A2 0x00 0 0 0 0 0 0 0 0 A3 0x00 0 0 0 0 0 0 0 0 A4 0x00 0 0 0 0 0 0 0 0 A5 0x00 0 0 0 0 0 0 0 0 A6 0x00 0 0 0 0 0 0 0 0 A7 0x00 0 0 0 0 0 0 0 0 A8 0x00 0 0 0 0 0 0 0 0 A9 0x00 0 0 0 0 0 0 0 0 0x2B OTP_CHG_CFG0 Reserved (OTP_ CHGR_ THM_WARM) Reserved (OTP_ CHGR_ THM_COOL) OTP_CHGR_EOCTIME[2:0] OTP_CHGR_ TPRECHG OTP_CHGR_OPER[1:0] A1 (Default) 0x02 0 0 0 0 0 0 1 0 A2 0x01 0 0 0 0 0 0 0 1 A3 0x02 0 0 0 0 0 0 1 0 A4 0x02 0 0 0 0 0 0 1 0 A5 0x02 0 0 0 0 0 0 1 0 A6 0x01 0 0 0 0 0 0 0 1 A7 0x02 0 0 0 0 0 0 1 0 A8 0x02 0 0 0 0 0 0 1 0

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 BIT[7:0]Address Register name Value 7 6 5 4 3 2 1 0 A9 0x01 0 0 0 0 0 0 0 1 0x2C OTP_CHG_CFG1 OTP_CHGR_CHG_RESTART[1:0] Reserved (OTP_ CHGR_ FORCE_BATT_ ISO) Reserved (OTP_ CHGR_ EOC_EXIT) Reserved (OTP_ CHGR_ EOC_MODE) OTP_CHGR_FCHGTIME[2:0] A1 (Default) 0x00 0 0 0 0 0 0 0 0 A2 0x00 0 0 0 0 0 0 0 0 A3 0x00 0 0 0 0 0 0 0 0 A4 0x00 0 0 0 0 0 0 0 0 A5 0x00 0 0 0 0 0 0 0 0 A6 0x00 0 0 0 0 0 0 0 0 A7 0x00 0 0 0 0 0 0 0 0 A8 0x00 0 0 0 0 0 0 0 0 A9 0x00 0 0 0 0 0 0 0 0 0x2D OTP_CHG_CFG2 OTP_CHGR_VSYSMIN[1:0] OTP_CHGR_CHG_CC[4:0] OTP_CHGR_ TEMPFB_EN A1 (Default) 0x80 1 0 0 0 0 0 0 0 A2 0x80 1 0 0 0 0 0 0 0 A3 0x80 1 0 0 0 0 0 0 0 A4 0x90 1 0 0 1 0 0 0 0 A5 0x80 1 0 0 0 0 0 0 0 A6 0x40 0 1 0 0 0 0 0 0 A7 0x80 1 0 0 0 0 0 0 0 A8 0x80 1 0 0 0 0 0 0 0 A9 0x40 0 1 0 0 0 0 0 0 0x2E OTP_CHG_CFG3 OTP_CHGR_BATFET_OC[1:0] OTP_CHGR_CHGCV[5:0] A1 (Default) 0x2B 0 0 1 0 1 0 1 1 A2 0x2B 0 0 1 0 1 0 1 1 A3 0x2B 0 0 1 0 1 0 1 1 A4 0x2B 0 0 1 0 1 0 1 1 A5 0x2B 0 0 1 0 1 0 1 1 A6 0x2B 0 0 1 0 1 0 1 1 A7 0x2B 0 0 1 0 1 0 1 1 A8 0x2B 0 0 1 0 1 0 1 1 A9 0x2B 0 0 1 0 1 0 1 1 0x2F OTP_CHG_CFG4 UNUSED OTP_CHGR_THM_CNFG[1:0] OTP_CHGR_REGTEMP[1:0] OTP_CHGR_ THM_COLD OTP_CHGR_ THM_HOT OTP_CHGR_ BOVRC_ DISBATFET A1 (Default) 0x00 0 0 0 0 0 0 0 0 A2 0x00 0 0 0 0 0 0 0 0 A3 0x00 0 0 0 0 0 0 0 0 A4 0x00 0 0 0 0 0 0 0 0 A5 0x00 0 0 0 0 0 0 0 0 A6 0x00 0 0 0 0 0 0 0 0 A7 0x00 0 0 0 0 0 0 0 0 A8 0x00 0 0 0 0 0 0 0 0 A9 0x00 0 0 0 0 0 0 0 0 0x30 OTP_CHG_CFG5 UNUSED UNUSED OTP_CHGR_ VIN_DPM_STOP OTP_CHGR_VBUS_LIN_ILIM[4:0] A1 (Default) 0x0E 0 0 0 0 1 1 1 0 A2 0x14 0 0 0 1 0 1 0 0 A3 0x14 0 0 0 1 0 1 0 0 A4 0x14 0 0 0 1 0 1 0 0 A5 0x14 0 0 0 1 0 1 0 0 A6 0x14 0 0 0 1 0 1 0 0 A7 0x14 0 0 0 1 0 1 0 0 A8 0x14 0 0 0 1 0 1 0 0 A9 0x14 0 0 0 1 0 1 0 0 0x31 OTP_CHG_CFG6 OTP_CHGR_SYS_WKUP_DLY[1:0] OTP_CHGR_ ACTDISPHY OTP_CHGR_ USBPHY OTP_CHGR_ USBPHYLDO OTP_CHGR_VBUS_DPM_REG[2:0] A1 (Default) 0x00 0 0 0 0 0 0 0 0 A2 0x28 0 0 1 0 1 0 0 0

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 BIT[7:0]Address Register name Value 7 6 5 4 3 2 1 0 A3 0x28 0 0 1 0 1 0 0 0 A4 0x2E 0 0 1 0 1 1 1 0 A5 0x28 0 0 1 0 1 0 0 0 A6 0x28 0 0 1 0 1 0 0 0 A7 0x28 0 0 1 0 1 0 0 0 A8 0x28 0 0 1 0 1 0 0 0 A9 0x28 0 0 1 0 1 0 0 0 0x32 OTP_CHG_CFG7 OTP_CHGR_CC_ADJ[1:0] OTP_CHGR_ CHG_INT_EN OTP_CHGR_ EOC_INT OTP_CHGR_VBUS_OV_TDB[1:0] Reserved (OTP_CHGR_USB_PHY_ TDB[1:0]) A1 (Default) 0x04 0 0 0 0 0 1 0 0 A2 0x04 0 0 0 0 0 1 0 0 A3 0x04 0 0 0 0 0 1 0 0 A4 0x14 0 0 0 1 0 1 0 0 A5 0x04 0 0 0 0 0 1 0 0 A6 0x04 0 0 0 0 0 1 0 0 A7 0x04 0 0 0 0 0 1 0 0 A8 0x04 0 0 0 0 0 1 0 0 A9 0x04 0 0 0 0 0 1 0 0 0x33 OTP_CHG_CFG8 UNUSED OTP_CHGR_LED_CURRENT[1:0] OTP_CHGR_VBUS2SYS_TDB[1:0] OTP_CHGR_ VBUS2SYS_ THRSH OTP_CHGR_CV_ADJ[1:0] A1 (Default) 0x28 0 0 1 0 1 0 0 0 A2 0x28 0 0 1 0 1 0 0 0 A3 0x28 0 0 1 0 1 0 0 0 A4 0x28 0 0 1 0 1 0 0 0 A5 0x28 0 0 1 0 1 0 0 0 A6 0x28 0 0 1 0 1 0 0 0 A7 0x28 0 0 1 0 1 0 0 0 A8 0x28 0 0 1 0 1 0 0 0 A9 0x28 0 0 1 0 1 0 0 0 0x34 OTP_CHG_CFG9 OTP_CHGR_LED_ CNFG OTP_CHGR_OVFLT_ BFET_EN OTP_CHGR_ WDFLT_BFET_ EN OTP_CHGR_ THMSUS_BFET_ EN OTP_CHGR_ TSHDN_BFET_ EN OTP_CHGR_ TMRFLT_ BFET_EN Reserved (OTP_CHGR_BETA_SEL[1:0]) A1 (Default) 0x00 0 0 0 0 0 0 0 0 A2 0x00 0 0 0 0 0 0 0 0 A3 0x00 0 0 0 0 0 0 0 0 A4 0x00 0 0 0 0 0 0 0 0 A5 0x00 0 0 0 0 0 0 0 0 A6 0x00 0 0 0 0 0 0 0 0 A7 0x00 0 0 0 0 0 0 0 0 A8 0x00 0 0 0 0 0 0 0 0 A9 0x00 0 0 0 0 0 0 0 0 0x35 OTP_CHG_ CFG10 UNUSED UNUSED UNUSED Reserved (OTP_ CHGR_ FET_SCALE) Reserved (OTP_CHGR_PRECHG_ LOWBATT_THRSH[1:0]) OTP_CHGR_PRECHG_ LOWBATT_THRSH[1:0] A1 (Default) 0x00 0 0 0 0 0 0 0 0 A2 0x00 0 0 0 0 0 0 0 0 A3 0x00 0 0 0 0 0 0 0 0 A4 0x00 0 0 0 0 0 0 0 0 A5 0x00 0 0 0 0 0 0 0 0 A6 0x00 0 0 0 0 0 0 0 0 A7 0x00 0 0 0 0 0 0 0 0 A8 0x00 0 0 0 0 0 0 0 0 A9 0x00 0 0 0 0 0 0 0 0 0x36 RSVD OTP_CHGR_SPARE0[7:0] A1 (Default) 0x00 0 0 0 0 0 0 0 0 A2 0x00 0 0 0 0 0 0 0 0 A3 0x00 0 0 0 0 0 0 0 0 A4 0x00 0 0 0 0 0 0 0 0 A5 0x00 0 0 0 0 0 0 0 0 A6 0x00 0 0 0 0 0 0 0 0

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 BIT[7:0]Address Register name Value 7 6 5 4 3 2 1 0 A7 0x00 0 0 0 0 0 0 0 0 A8 0x00 0 0 0 0 0 0 0 0 A9 0x00 0 0 0 0 0 0 0 0 A1 (Default) 0xB5 1 0 1 1 0 1 0 1 A2 0xB5 1 0 1 1 0 1 0 1 A3 0xB5 1 0 1 1 0 1 0 1 A4 0xB5 1 0 1 1 0 1 0 1 A5 0xB5 1 0 1 1 0 1 0 1 A6 0xB5 1 0 1 1 0 1 0 1 A7 0xB5 1 0 1 1 0 1 0 1 A8 0xB5 1 0 1 1 0 1 0 1 A9 0xB5 1 0 1 1 0 1 0 1

13.1 Example schematic

Figure 28 shows a typical schematic of the PF1550 with key external components.

100 K100 K 100 K

1.0 H 10 F

Figure 28. Typical schematic

13.2 Bill of materials

The following table shows an example bill of materials to be used with the PF1550.

Table 177. Bill of materials

13.3 PF1550 layout guidelines

13.3.1 General board recommendations

• It is recommended to use an eight layer board stack-up arranged as follows: – High current signal – GND – Signal – Power – Power – Signal

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 – GND

• Allocate TOP and BOTTOM PCB layers for POWER ROUTING (high current signals), copper-pour the unused area.
• Use internal layers sandwiched between two GND planes for the SIGNAL routing.

13.3.2 Component placement

It is desirable to keep all component related to the power stage as close to the PMIC as possible, specially decoupling input and output capacitors.

13.3.3 General routing requirements

• Some recommended things to keep in mind for manufacturability: – Via in pads require a 4.5 mil minimum annular ring. Pad must be 9.0 mils larger than the hole – Maximum copper thickness for lines less than 5.0 mils wide is 0.6 oz copper – Minimum allowed spacing between line and hole pad is 3.5 mils – Minimum allowed spacing between line and line is 3.0 mils
• Care must be taken with SWxFB pins traces. These signals are susceptible to noise and must be routed far away from power, clock, or high-power signals, like the ones on the SWxIN, SWxLX. They could be also shielded.
• Shield feedback traces of the regulators and keep them as short as possible (trace them on the bottom so the ground and power planes shield these traces).
• Avoid coupling traces between important signal/low noise supplies (like VCORE, VDIG) from any switching node (for example, SW1LX, SW2LX, SW3LX).
• Make sure that all components related to a specific block are referenced to the corresponding ground.

13.3.4 Parallel routing requirements

• I2C signal routing – CLK is the fastest signal of the system, so it must be given special care. – To avoid contamination of these delicate signals by nearby high power or high frequency signals, it is a good practice to shield them with ground planes placed on adjacent layers. Make sure that the ground plane is uniform throughout the whole signal trace length. – These signals can be placed on an outer layer of the board to reduce their capacitance with respect to the ground plane. – Care must be taken with these signals not to contaminate analog signals, as they are high frequency signals. Another good practice is to trace them perpendicularly on different layers, so there is a minimum area of proximity between signals.

Figure 29. Recommended shielding for critical signals

13.3.5 Switching regulator layout recommendations

• Per design, the switching regulators in PF1550 are designed to operate with only one input bulk capacitor. However, it is recommended to add a high frequency filter input capacitor (CIN_hf), to filter out any noise at the regulator input. This capacitor should be in the range of 100 nF and should be placed right next to or under the IC, closest to the IC pins.
• Make high-current ripple traces low-inductance (short, high W/L ratio).
• Make high-current traces wide or copper islands. COUT CIN_HFCIN VIN SWxIN L SWxLX SWxFBCompensation Driver controller aaa-023892

Figure 30. Generic buck regulator architecture

Figure 31. Layout example for buck regulators

13.4 Thermal information

13.4.1 Rating data

anticipated that the generic name, Theta-JA, continues to be commonly used. The JEDEC standards can be consulted at http://www.jedec.org/.

13.4.2 Estimation of junction temperature

of significant power dissipated by other components placed close to the device.

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 At a known board temperature, the junction temperature TJ is estimated using the following equation TJ= TB+ (RθJBx PD) with TB = Board temperature at the package perimeter in °C RθJB = Junction to board thermal resistance in °C/W PD = Power dissipation in the package in W The PF1550 uses a 40-pin QFN 5.0 mm x 5.0 mm with exposed pad, case number 98ASA00913D. This drawing is available for download at http://www.nxp.com.

Figure 32. Package outline for HVQFN40 (SOT1369-4)

Table 178. Revision history

• Table 1: added MC32PF1550A9EP and MC34PF1550A9EP parts
• Table 77: replaced "0.2 * VSNVS" by "0.4" and "0.8 * VSNVS" by "1.4"
• Section 9.3: added Table 78
• Section 9.4: added Table 79
• Section 11.1: updated Figure 27
• Table 85: added OTP configuration for A9
• Section 8.8.4: updated Figure 23
• Table 165: updated description for USBPHYLDO (replaced 0 by 1)
• Figure 12, Figure 28: replaced "INT_2P7" by "INT2P7" and 1.0 µF by 2.2 µF
• Section 12.5: added A9 OTP
• Global: changed document status from Advance information to Product PF1550 v.4.0 20180928 Advance information — PF1550 v.3.0 Modifications • Added MC32PF1550A0EP, MC32PF1550A8EP, MC34PF1550A0EP, and MC34PF1550A8EP parts to Table 1
• Added OTP configuration for A8 to Table 85 PF1550 v.3.0 20180502 Advance information — PF1550 v.2.0 Modifications • Changed PC parts to MC in Table 1
• Updated programming option for MC32PF1550A7EP and MC34PF1550A7EP (replaced LPDDR3 by LPDDR2) in Table 1
• Updated SDA and SCL pin description in Table 2
• Updated A7 OTP configuration for OTP_SW3_VOLT[5:0] and OTP_LDO1_VOLT[4:0] registers (replaced 3.3 V by 1.8 V and 1.8 V by 3.3 V) in Table 85 and modified Table 176 to reflect A7 OTP option updates
• Updated min. and max. input current values in Table 6 PF1550 v.2.0 20180202 Advance information — PF1550 v.1.0

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 Document ID Release date Data sheet status Change notice Supersedes Modifications • Updated Figure 10

• Updated Figure 28
• Updated description in Section 7.3.6 "LDO2 current limit protection"
• Changed capacitor value from 4.7 µF to 10 µF in Section 7.3.3 "LDO2 external components"
• Updated Figure 15, Figure 17, Figure 28
• Changed the value of LDO2 output capacitor from 4.7 µF to 10 µF in Table 177
• Updated Figure 3 (changed VUSB to VBUSIN
• Updated Figure 4 (changed VDO3IN to VLDO3IN)
• Corrected typos in Table 5, Table 6, Table 7, Table 8, Table 9, Table 10, Table 11, Table 13, Table 14, Table 17, and Table 18
• Updated quiescent current ILDO1Q from 4.0 to 4.5 in Table 21 and added new parameter
• Updated and added new parameters to Table 19 and Table 20
• Updated values for ILDO2LIM in Table 22
• Updated quiescent current ILDO3Q from 4.0 to 4.5 in Table 23
• Updated typical and maximum value for REGS_DISABLE and SHIP MODE in Table 26
• Updated Section 6.3.3 "Output voltage setting in SW3"
• Updated Figure 12, Figure 13, and Figure 14
• Changed OTP_SW2_DVS_SEL to DVS mode for A4 configuration in Table 85
• Changed OTP configuration for SW1 to 1.3875 V in Table 85
• Updated Table 176 and Table 177
• Updated IQ_CHARGER_LQM max. value from 2.5 to 3.0 in Table 6
• Updated values for VSWx in Table 19
• Updated ILDO1Q and ILDO3Q values from 22 to 25 in Table 21 and Table 23
• Added part numbers to Table 1
• Updated typical value for tFC in Table 13
• Updated ISWxLIMH values in Table 19 and Table 20
• Updated Figure 16 and Figure 17
• Added Section 9.7
• Added OTP configuration for A5 to Table 85
• Updated Table 1
• Added A6 and A7 OTP configurations to Table 85
• Updated Figure 3, Figure 16, and Figure 28
• Added Figure 27
• Updated values for ISWxLIMH and ISW3LIMH in Table 19 and Table 20
• Added ripple parameter to Table 20
• Updated values for frequency in Table 72
• Updated Table 116, Table 121, Table 126, Table 167, and Table 174
• Updated Section 12.5
• Replaced MINVSYS by VSYSMIN
• Changed document status from Product preview to Advance information PF1550 v.1.0 20161012 Product preview — —

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019

16 Legal information

16.1 Data sheet status

Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

16.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non- automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. NXP — is a trademark of NXP B.V.

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 Tables Tab. 32. Acceptable inductance and capacitance Tab. 38. Acceptable inductance and capacitance Tab. 106. Register ONKEY_INT_MASK0 - ADDR Tab. 107. Register ONKEY_INT_SENSE0 - ADDR

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 Tab. 111. Register COINCELL_CONTROL - ADDR Tab. 139. Register SW1_PWRDN_SEQ - ADDR 0x5F ..100 Tab. 140. Register SW2_PWRDN_SEQ - ADDR 0x60 .. 101 Tab. 141. Register SW2_PWRDN_SEQ - ADDR 0x61 .. 101 Tab. 142. Register LDO1_PWRDN_SEQ - ADDR Tab. 143. Register LDO2_PWRDN_SEQ - ADDR Tab. 144. Register LDO3_PWRDN_SEQ - ADDR Tab. 145. Register VREFDDR_PWRDN_SEQ - ADDR Tab. 159. Register CHG_CURR_CNFG - ADDR 0x0E .. 111 Tab. 163. Register VBUS_INLIM_CNFG - ADDR 0x14 ..116 Tab. 165. Register USB_PHY_LDO_CNFG - ADDR Tab. 166. Register DBNC_DELAY_TIME - ADDR Tab. 168. Register THM_ADJ_SETTING - ADDR Tab. 171. Register FAULT_BATFET_CNFG - ADDR Figures Fig. 13. Charger low battery (Startup sequence, Fig. 14. Charger healthy battery (Startup sequence, Fig. 19. Thermal regulation (Current versus Temp, example with REGTEMP[1:0] = 00 and Fig. 20. Thermal regulation (Current, Temp versus Time, example with REGTEMP[1:0] = 00 Fig. 21. Response to input voltage droop during

Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 5 — 10 June 2019 Fig. 23. CC charge current and CV charge voltage Fig. 32. Package outline for HVQFN40 (SOT1369-4) . 140 Fig. 33. Package outline detail for HVQFN40 Fig. 34. Package outline notes for HVQFN40

Power management integrated circuit (PMIC) for low power application processors Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2019. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 10 June 2019 Document identifier: PF1550 12.2 Specific Charger Registers (Offset is 0x80) ... 105 13.3.5 Switching regulator layout recommendations . 137