PF1510 NXP | Alldatasheet
Document overview
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- PDF pages: 108
Technical content
Datasheet sections
- 1 General description
- 1.1 Features and benefits
- 1.2 Applications
- 2 Application diagram
- 2.1 Functional block diagram
- 2.2 Internal block diagram
- 3 Orderable parts
- 4 Pinning information
- 4.1 Pinning
- 4.2 Pin definitions
- 5 General product characteristics
- 5.1 Thermal characteristics
- 5.2 Absolute maximum ratings
- 5.3 Electrical characteristics
- 5.3.1 Electrical characteristics – Front-end LDO
- 5.3.2 Electrical characteristics – SW1 and SW2
- 5.3.3 Electrical characteristics – SW3
- 5.3.4 Electrical characteristics – LDO1
- 5.3.5 Electrical characteristics – LDO2
- 5.3.6 Electrical characteristics – LDO3
- 5.3.7 Electrical characteristics – VREFDDR
- 5.3.8 Electrical characteristics – VSNVS
- 5.3.9 Electrical characteristics – IC level bias
- 6 Detailed description
- 6.1 Buck regulators
- 6.2 SW1 and SW2 detailed description
- 6.2.1 SWx dynamic voltage scaling description
- 6.2.2 SWx DVS and non-DVS operation
- 6.2.3 Regulator control
- 6.2.4 Current limit protection
- 6.2.5 Output voltage setting in SWx
- 6.2.6 SWx external components
- 6.3 SW3 detailed description
- 6.3.1 Regulator control
- 6.3.2 Current limit protection
- 6.3.3 Output voltage setting in SW3
- 6.3.4 SW3 external components
- 7 Low dropout linear regulators, VREFDDR
- 7.1 General description
- 7.2 LDO1 and LDO3 detailed description
- 7.2.1 Features summary
- 7.2.2 LDOy block diagram
- 7.2.3 LDOy external components
- 7.2.4 LDOy output voltage setting
- 7.2.5 LDOy low power mode operation
- 7.2.6 LDOy current limit protection
- 7.2.7 LDOy load switch mode
- 7.3 LDO2 detailed description
- 7.3.1 LDO2 features summary
- 7.3.2 LDO2 block diagram
- 7.3.3 LDO2 external components
- 7.3.4 LDO2 output voltage setting
- 7.3.5 LDO2 Low-power mode operation
- 7.3.6 LDO2 current limit protection
- 7.4 VREFDDR reference
- 7.5 VSNVS LDO/Switch
- 8 Front-end LDO description
- 8.1 Operating modes and behavioral description
- 9 Control and interface signals
- 9.1 PWRON
- 9.2 STANDBY
- 9.3 RESETBMCU
- 9.4 INTB
- 9.5 WDI
- 9.6 ONKEY
- 9.7 Control interface I2C block description
- 9.7.1 I2C device ID
- 9.7.2 I2C operation
- 10 PF1510 state machine
- 10.1 System ON states
- 10.1.1 Run state
- 10.1.2 STANDBY state
- 10.1.3 SLEEP state
- 10.2 System OFF states
- 10.2.1 REGS_DISABLE
- 10.2.2 CORE_OFF
- 10.3 Turn on events
- 10.4 Turn off events
- 10.5 State diagram and transition conditions
- 10.6 Regulator power-up sequencer
- 10.7 Regulator power-down sequencer
- 11 Device start up
- 11.1 Startup timing diagram
- 11.2 Device start up configuration
- 12 Register map
- 12.1 Specific PMIC Registers (Offset is 0x00)
- 12.2 Specific Registers (Offset is 0x80)
- 12.3 Register PMIC bitmap
- 12.4 Additional register bitmap
- 13 Application details
- 13.1 Example schematic
- 13.2 Bill of materials
- 13.3 PF1510 layout guidelines
- 13.3.1 General board recommendations
- 13.3.2 Component placement
- 13.3.3 General routing requirements
- 13.3.4 Parallel routing requirements
- 13.3.5 Switching regulator layout recommendations
- 13.4 Thermal information
- 13.4.1 Rating data
- 13.4.2 Estimation of junction temperature
- 14 Packaging information
- 14.1 Packaging description
- 15 Revision history
- 16 Legal information
Power management integrated circuit (PMIC) for low power application processors Rev. 3 — 7 April 2020 Product data sheet
1 General description
The PF1510 is a power management integrated circuit (PMIC) designed specifically for use with i.MX processors on low-power portable, smart wearable and Internet-of-Things (IoT) applications. It is also capable of providing full power solution to i.MX 7ULP, i.MX 6SL, 6UL, 6ULL and 6SX processors. With three high efficiency buck converters, three linear regulators, DDR reference and RTC supply, the PF1510 can provide power for a complete system, including application processors, memory, and system peripherals.
1.1 Features and benefits
This section summarizes the PF1510 features:
- Input voltage VIN from 5V bus, USB, or AC adapter (4.1 V to 6.0 V) – Linear front-end input LDO (1500 mA input limit) – Up to 6.5 V input operating range – VIN can withstand transient and DC inputs from 0 V up to +22 V
- Buck converters: – SW3, 1.0 A; 1.8 V to 3.3 V in 100 mV steps – Internal digital soft start – Quiescent current 1.0 μA in ULP mode with light load – Peak efficiency > 90 % – Dynamic voltage scaling on SW1 and SW2 – Modes: forced PWM quasi-fixed frequency mode, adaptive variable-frequency mode – Programmable output voltage, current limit and soft start
- LDO regulators – LDO1, 0.75 to 1.5 V/1.8 to 3.3 V, 300 mA with load switch mode – LDO2, 1.8 to 3.3 V, 400 mA – LDO3, 0.75 to 1.5 V/1.8 to 3.3 V, 300 mA with load switch mode – Quiescent current < 1.5 μA in Low-power mode – Programmable output voltage – Soft start and ramp – Current limit protection – USB_PHY low dropout linear regulator – LDO2P7 always on regulator output
- LDO/switch supply – RTC supply VSNVS 3.0 V, 2.0 mA – Coin cell charger
Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 3 — 7 April 2020
- DDR memory reference voltage, VREFDDR, 0.5 to 0.9 V, 10 mA
- OTP (One time programmable) memory for device configuration – User programmable start-up sequence, timing, soft-start and power-down sequence – Programmable regulator output voltages
- I2C interface
- User programmable Standby, Sleep/Low-power, and Off (REGS_DISABLE) modes
- Ambient temperature range −40 °C to 105 °C
1.2 Applications
- Low-power IoT applications
- Wireless game controllers
- Embedded monitoring systems
- Home automation
- POS
- E-Reader
- Smart mobile/wearable devices
2 Application diagram
5.0 V FROM ADAPTER OR USB
Figure 1. Application diagram
2.1 Functional block diagram
22 V surge)
Figure 2. Functional block diagram
2.2 Internal block diagram
Figure 3. Internal block diagram
3 Orderable parts
each device can be found in Table 53.
Table 1. Orderable part variations [1] For tape and reel, add an R2 suffix to the part number.
4 Pinning information
4.1 Pinning
Figure 4. Pinout diagram
4.2 Pin definitions
Table 2. Pin description 1 WDI Watchdog input from processor Connect to WDI signal from processor.
2 SDA I2C data line Pull-up to VDDIO Leave floating
3 SCL I2C clock line Pull-up to VDDIO Leave floating
5 VDDOTP Supply to program OTP fuses Connect to ground for the fuse loading N/A
6 PWRON Power On/Off from processor Connect to PMIC_ON_REQ from
7 STANDBY Standby input signal from processor Connect to PMIC_STBY_REQ signal
8 ONKEY ONKEY push button input Connect to push button and pull up via
9 INTB Open drain interrupt signal to processor Pull-up via 68 kΩ - 100 kΩ to VSNVS or
10 RESETBMCU Open drain reset output to processor Pull-up via 68 kΩ - 100 kΩ to VSNVS or
13 SW3LX SW3 switching node Connect to SW3 inductor Leave floating
15 SW3FB Output voltage feedback for SW3 Connect to SW3 output voltage rail near
16 SW2FB Output voltage feedback for SW2 Connect to SW2 output voltage rail near
18 SW2LX SW2 switching node Connect to SW2 inductor Leave floating
19 VLDO2 LDO2 regulator output Bypass with 10 µF capacitor to ground Leave floating
25 SW1LX SW1 switching node Connect to SW1 inductor Leave floating
27 SW1FB Output voltage feedback for SW1 Connect to SW1 output voltage rail near
32 GND Ground Connect to ground Connect to ground
35 VSYS
36 VSYS
40 GND Ground Connect to ground Connect to ground
5 General product characteristics
5.1 Thermal characteristics
Table 3. Thermal ratings Thresholds for thermal protection features. malfunction or permanent damage to the device.
MC33xxxD enter 33xxx), and review parametrics. temperature, air flow, power dissipation of other components on the board, and board thermal resistance. [5] The Board uses the JEDEC specifications for thermal testing (and simulation) JESD51-7 and JESD51-5. [6] Per JEDEC JESD51-6 with the board horizontal. [8] Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). [9] Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
5.2 Absolute maximum ratings
Table 4. Maximum ratings
Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 3 — 7 April 2020 Symbol Description (Rating) Min Max Unit LDO2 VLDO2IN LDO2 input supply −0.3 4.8 V VLDO2 LDO2 output −0.3 3.6 V LDO3 VLDO3IN LDO3 input supply −0.3 4.8 V VLDO3 LDO3 output −0.3 3.6 V VSNVS VSNVS VSNVS regulator output −0.3 3.6 V LICELL Coin cell input −0.3 3.6 V FRONT-END LDO LDO2P7 LDO2P7 regulator output −0.3 3.6 V USBPHY USBPHY regulator output −0.3 5.5 V INPUT/OUTPUT SUPPLY VINREFDDR VREFDDR input supply −0.3 3.6 V VREFDDR VREFDDR output −0.3 3.6 V IC CORE VSYS Main input voltage to PMIC −0.3 4.8 V VDIG VDIG regulator output (used within PF1510) −0.3 1.65 VCORE VCORE regulator output (used within PF1510) −0.3 1.65 V ELECTRICAL RATINGS VESD ESD ratings Human body model Charge device model (corner pins) Charge device model (all other pins) [1] ±2000 ±750 ±500 V [1] Testing is performed in accordance with the human body model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the charge device model (CDM), Robotic (CZAP = 4.0 pF).
5.3 Electrical characteristics
5.3.1 Electrical characteristics – Front-end LDO
VIN = 5.0 V, VSYS = 3.7 V and 25 °C, unless otherwise noted. Table 5. Front-end LDO Table 6. Input currents
Table 7. Switch impedances and leakage currents Table 8. Watchdog timer Table 9. Internal 2.7 V Regulator (LDO2P7) Table 10. USBPHY LDO
5.3.2 Electrical characteristics – SW1 and SW2
1.1 V, ISWx = 100 mA, and 25 °C, unless otherwise noted. Table 11. SW1 and SW2 electrical characteristics
Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 3 — 7 April 2020 Symbol Parameter Min Typ Max Unit VSWx Output voltage accuracy DVS disabled mode (OTP_SWx_DVS_SEL = 1) Low-power mode, 2.5 V < VSWxIN < 4.5 V, 0 < ISWx < 0.1 A 1.8 V ≤ VSWx ≤ 3.3 V −4.0 — 4.0 % ΔVSWx Output ripple — 5.0 — mV SWxEFF Efficiency VSWxIN = 3.6 V, LSWx = 1.0 µH, DCR = 50 mΩ LP/ ULP mode, 1.2 V, 1.0 mA — 88 — % SWxEFF Efficiency VSWxIN = 3.6 V, LSWx = 1.0 µH, DCR = 50 mΩ Normal power mode, 1.2 V, 50 mA — 90 — % SWxEFF Efficiency VSWxIN = 3.6 V, LSWx = 1.0 µH, DCR = 50 mΩ Normal power mode, 1.2 V, 150 mA — 92 — % SWxEFF Efficiency VSWxIN = 3.6 V, LSWx = 1.0 µH, DCR = 50 mΩ Normal power mode, 1.2 V, 400 mA — 89 — % SWxEFF Efficiency VSWxIN = 3.6 V, LSWx = 1.0 µH, DCR = 50 mΩ Normal power mode, 1.2 V, 1000 mA — 83 — % ISWxLIMH Current limiter peak (high-side MOSFET) current detection SWxILIM[1:0] = 00 SWxILIM[1:0] = 01 SWxILIM[1:0] = 10 SWxILIM[1:0] = 11 0.7 0.8 1.0 1.4 1.0 1.2 1.5 2.0 1.3 1.6 2.0 2.6 A ISWxLIML Current limiter low-side MOSFET current detection (sinking current) 0.7 1.0 1.3 A ISWxQ Quiescent current (at 25 °C) Low-power mode with DVS disabled (OTP_SWx_DVS_SEL = 1) 1.0 µA ISWxQ Quiescent current (at 25 °C) Low-power mode with DVS enabled (OTP_SWx_DVS_SEL = 0) 6.0 µA ISWxQ Quiescent current (at 25 °C) Normal power mode with DVS disabled (OTP_SWx_DVS_SEL = 1) 5.5 µA ISWxQ Quiescent current (at 25 °C) Normal power mode with DVS enabled (OTP_SWx_DVS_SEL = 0) µA VSWxOSH Startup overshoot (Normal mode) ISWx = 0 mA DVS speed = 12.5 mV/4 µs, VSYS = VSWxIN = 3.6 V, VSWx = 1.35 V — — 25 mV tONSWx Turn on time 10 % to 90 % of end value DVS speed = 12.5 mV/4 µs, VSYS = VSWxIN = 3.6 V, VSWx = 1.35 V — — 500 µs VSWxLOTR Transient load regulation (Normal power mode) Transient load = 50 mA to 250 mA, di/dt = 200 mA/μs Overshoot Undershoot mV
5.3.3 Electrical characteristics – SW3
1.8 V, ISW3 = 200 mA, and 25 °C, unless otherwise noted. Table 12. SW3 electrical characteristics
5.3.4 Electrical characteristics – LDO1
3.6 V, VLDO1[4:0] = 11111, ILDO1 = 10 mA, typical external component values, unless
VLDO1[4:0] = 11111, ILDO1 = 10 mA, and 25 °C, unless otherwise noted. Table 13. LDO1 electrical characteristics
5.3.5 Electrical characteristics – LDO2
1111, ILDO2 = 10 mA, and 25 °C, unless otherwise noted. Table 14. LDO2 electrical characteristics
5.3.6 Electrical characteristics – LDO3
3.6 V, VLDO3[4:0] = 11111, ILDO3 = 10 mA, typical external component values, unless
VLDO3[4:0] = 11111, ILDO3 = 10 mA, and 25 °C, unless otherwise noted. Table 15. LDO3 electrical characteristics
5.3.7 Electrical characteristics – VREFDDR
Table 16. VREFDDR electrical characteristics
5.3.8 Electrical characteristics – VSNVS
Table 17. VSNVS electrical characteristics
5.3.9 Electrical characteristics – IC level bias currents
3.6 V, VSNVS = 3.0 V, and 25 °C, unless otherwise noted. Table 18. IC level electrical characteristics
6 Detailed description
processor and peripheral devices. supply rail adjustments for the processor cores for power optimization. camera, Bluetooth, Wireless LAN. is powered from VSYS or from a coin cell. Table 19. Voltage regulators
Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 3 — 7 April 2020 Supply Output voltage (V) Programming step size (mV) Load current (mA) USBPHY 3.3 or 4.9 — 60 VSNVS 3.0 N/A 2 VREFDDR 0.5*VINREFDDR N/A 10
6.1 Buck regulators
The PF1510 features three high efficiency buck regulators with internal compensation. Each buck regulator is capable of meeting optimum power efficiency operation using reduced power variable-frequency pulse skip switching scheme at light loads as well as operating in forced PWM quasi-fixed frequency switching mode at higher loads. The switching regulator controller combines the advantages of hysteretic and voltage mode control which provides outstanding load regulation and transient response, low output ripple voltage and seamless transition between pulse-skip mode and Active Quasi-fixed frequency switching mode. The control circuitry includes an AC loop which senses the output voltage (at SWxFB pin) and directly feeds it to a fast comparator stage. This comparator sets the switching frequency, which is almost constant for steady state operating conditions. It also provides immediate response to dynamic load changes. In order to achieve accurate DC load regulation, a voltage feedback loop is used. The internally compensated regulation network achieves fast and stable operation with small external components and low ESR capacitors. The transition into and out of low power pulse-skip switching mode takes place automatically according to the load current to maintain optimum power efficiency. Additionally, further power savings through cutting the buck circuitry quiescent current can be achieved by activating a Low-power mode upon entering either STANDBY or SLEEP PMIC power mode or as commanded via I2C control bits. In SW1 and SW2. An OTP option enables or disables DVS in the regulators. When DVS is disabled and the low-power bit is set, the regulator enters an Ultra Low Power (ULP) mode cuts the operating quiescent current even in order to reach extremely low standby power levels needed for ultra low power processors such as that from Kinetis K and L series. As indicated above, the buck controller supports PWM (Pulse Width Modulation) mode for medium and high load conditions and low-power variable-frequency pulse skip mode at light loads. During high current mode, it operates in continuous conduction and the switching frequency is up to 2.0 MHz with a controlled on-time variation depending on the input voltage and output voltage. If the load current decreases, the converter seamlessly enters the pulse-skip mode to cut the operating quiescent current and maintain high efficiency down to very light loads. In pulse-skip mode the switching frequency varies linearly with the load current. Since the controller supports both power modes within one single building block, the transition from normal power mode to lower power pulse-skip mode and vice versa is seamless without dramatic effects on the output voltage. In the adopted pulse-skip scheme, the device generates a single switching pulse to ramp up the inductor current and recharge the output capacitor, followed by a non-switching (pause) period where most of the internal circuits are shutdown to achieve a lowest quiescent current. During this time, the load current is supported by the output capacitor. The duration of the pause period depends on the load current and the inductor peak current.
6.2 SW1 and SW2 detailed description
6.2.1 SWx dynamic voltage scaling description
mode or activity level of the processor.
- Normal operation: The output voltage is selected by I2C bits SWx_VOLT[5:0]. A voltage transition initiated by I2C is governed by the SWx_DVSSPEED I2C bit as shown in Table 20.
- Standby mode: The output voltage can be selected by I2C bits SWx_STBY_VOLT[5:0]. Voltage transitions initiated by a Standby event are governed by the SWx_DVSSPEED I2C bit as shown in Table 20. This applies only when DVS is enabled.
- Sleep mode: The output voltage can be higher or lower than in normal operation, but is typically selected to be the lowest state retention voltage of a given processor; it is selected by I2C bits SWx_SLP_VOLT[5:0]. Voltage transitions initiated by a turn off event are governed by the SWx_DVSSPEED I2C bit for SWx as shown in Table 20. This applies only when DVS is enabled. As shown in Figure 5, during a falling DVS transition, dv/dt of the output voltage depends on the load current. Setting the SWx_FPWM_IN_DVS bit forces the regulator in the FPWM mode during the falling transition allowing it to accurately track the DVS reference removing the load dependency. The SWx_FPWM_IN_DVS bit is active only when OTP_SWx_DVS_SEL = 0.
Table 20. SWx DVS setting selection Figure 5. SWx DVS transitions
6.2.2 SWx DVS and non-DVS operation
- DVS enabled: a DVS reference is activated and output accuracy of the regulator is tight at the cost of slightly higher quiescent current. See Section 5.3 "Electrical characteristics" for details. In Figure 6, DVS FB and DVS REF are enabled via OTP for this mode of operation.
- DVS disabled: the regulator operates as a traditional buck converter with a fixed reference and soft-start. The quiescent current in this mode is lower at the cost of output accuracy and transient response. See Section 5.3 "Electrical characteristics" for details. In Figure 6, VREF FB and VREF are enabled via OTP for this mode of operation. ibias Fixed DVS feedback and compensation Programmable DVS feedback and compensation Fixed bandgap reference with soft-start function Reduced accuracy and transient capabilities OR VREF FB VREF DVS FB DVS REF Bias control VOUT DVS FB VREF FB sel COMP DVS REF VREF sel LowPWR LowPWR VIN VOUT TON iLim CTRLlogic Driver TOFF ZCDiLim aaa-023877
Figure 6. SWx DVS and non-DVS selection
6.2.3 Regulator control
entering the Standby mode, exiting/entering Sleep/Low-power mode. Table 21. Buck regulator operating modes OFF The regulator is switched off and the output voltage is discharged using an internal resistor.
scheme at light load for optimized efficiency. F-PWM In this mode, the regulator is always in PWM mode operation regardless of load conditions. (Standby and/or Sleep) with the proper I2C setting. See Table 22. The following table shows actions to control different bits for SW1 and SW2. Table 22. Buck mode control
0 X X X X SW disabled
Standby 1 1 X 0 0 SW enabled. Operates in DCM at light loads. Standby 1 1 X 0 1 SW enabled. Forced PWM mode. Standby 1 1 X 1 0 SW enabled. Operates in Low-power mode. Sleep 1 X 1 0 0 SW enabled. Operates in DCM at light loads. Sleep 1 X 1 0 1 SW enabled. Forced PWM mode. Sleep 1 X 1 1 0 SW enabled. Operates in Low-power mode.
6.2.4 Current limit protection
debounce time, the interrupt status bit is set.
6.2.5 Output voltage setting in SWx
the regulator output voltage during Run, Standby and Sleep modes respectively.
starts up (RESETBMCU is released). Table 23. SW1 and SW2 output voltage setting
Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 3 — 7 April 2020 Set point SWx_VOLT[5:0] SWx_STBY_VOLT[5:0] SWx_SLP_VOLT[5:0] Output voltage with DVS enabled OTP_SWx_DVS_SEL = 0 Output voltage with DVS disabled OTP_SWx_DVS_SEL = 1 29 011101 0.9625 3.30 30 011110 0.9750 3.30 31 011111 0.9875 3.30 32 100000 1.0000 3.30 33 100001 1.0125 3.30 34 100010 1.0250 3.30 35 100011 1.0375 3.30 36 100100 1.0500 3.30 37 100101 1.0625 3.30 38 100110 1.0750 3.30 39 100111 1.0875 3.30 40 101000 1.1000 3.30 41 101001 1.1125 3.30 42 101010 1.125 3.30 43 101011 1.1375 3.30 44 101100 1.1500 3.30 45 101101 1.1625 3.30 46 101110 1.1750 3.30 47 101111 1.1875 3.30 48 110000 1.2000 3.30 49 110001 1.2125 3.30 50 110010 1.2250 3.30 51 110011 1.2375 3.30 52 110100 1.2500 3.30 53 110101 1.2625 3.30 54 110110 1.2750 3.30 55 110111 1.2875 3.30 56 111000 1.3000 3.30 57 111001 1.3125 3.3 58 111010 1.3250 3.30 59 111011 1.3375 3.30 60 111100 1.3500 3.30 61 111101 1.3625 3.30 62 111110 1.3750 3.30 63 111111 1.3875 3.30
6.2.6 SWx external components
The design is optimized for a 1.0 µH inductor. Table 24. Acceptable inductance and capacitance values Table 25 and Table 26 show example inductor and capacitor part numbers respectively. Table 25. Example inductor part numbers Table 26. Example capacitor part numbers
6.3 SW3 detailed description
not supported in this regulator. Figure 7. SW3 block diagram
6.3.1 Regulator control
Available modes for buck regulators are presented in Table 27 . on the PMIC operating state. Table 27. SW3 buck regulator operating modes the quiescent current of the buck converter by reducing the bias to the comparator. proper I2C setting. See Table 28. Table 28. SW3 buck mode control
6.3.2 Current limit protection
debounce time, the interrupt status bit is set.
6.3.3 Output voltage setting in SW3
the regulator output voltage during Run, Standby and Sleep modes respectively. only and cannot be written to. Table 29. SW3 output voltage setting
6.3.4 SW3 external components
Table 30. Acceptable inductance and capacitance values Table 31 and Table 32 show example inductor and capacitor part numbers respectively. Table 31. Example inductor part numbers Table 32. Example capacitor part numbers
Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 3 — 7 April 2020
7 Low dropout linear regulators, VREFDDR and VSNVS
7.1 General description
This section describes the LDO regulators provided by the PF1510. All regulators use the main bandgap as reference. When a regulator is disabled, the output is discharged by an internal pull-down. VLDO1 and VLDO3 can be used as load switches by setting the corresponding load switch enable bit OTP_VLDOx_LS. All general purpose LDOs have short-circuit protection capability. The Short-circuit Protection (SCP) system includes debounced fault condition detection, regulator shutdown, and processor interrupt generation, to contain failures and minimize the chance of product damage. If a short-circuit condition is detected and REGSCPEN bit is set, the LDO is disabled by resetting its VLDOxEN bit, while at the same time, an interrupt VLDOxFAULTI is generated to flag the fault to the system processor. The VLDOxFAULTI interrupt is maskable through the VLDOxFAULTM mask bit. The SCP feature is enabled by setting the REGSCPEN bit. If this bit is not set, the regulators are not automatically disabled upon a short-circuit detection. However, the current limiter continues to limit the output current of the regulator. By default, the REGSCPEN is not set; therefore, at start up none of the regulators are disabled if an overloaded condition occurs. A fault interrupt, VLDOxFAULTI is generated in an overload condition regardless of the state of the REGSCPEN bit. Each LDO features a Low-power mode where the quiescent current consumed is significantly lower than in regulator operation. In the Low-power mode, load current of each regulator is limited to 10 mA.
7.2 LDO1 and LDO3 detailed description
LDO1 and LDO3 are identical 300 mA low dropout (LDO) regulators that provide output voltage with high accuracy and are programmable through I2C interface bits. Being identical, reference is made to these LDOs as LDOy. To support this wide input range, LDOy circuit incorporates a PMOS pass FET as well as an NMOS pass FET. The LDO uses the main bandgap as its reference. The regulator incorporates a soft-start circuit that ramps the internal reference in order to provide smooth output waveform with minimal overshooting during power up. When the regulator is disabled, the output is discharged by an internal pull-down resistor. Additionally, the LDO can be used as a load switch by setting the corresponding Load Switch enable bit OTP_LDOy_LS. Moreover, LDOy includes current limit protection with the option to turn off the LDO when an overcurrent is detected.
7.2.1 Features summary
- Input range LDO from 1.0 V to 4.5 V
- Programmable output voltage between 0.75 V to 1.5 V (uses NMOS) or 1.8 V and
3.3 V (uses PMOS) with 2 % accuracy
- Soft-start ramp control during power up and discharge mechanism during power down
- Low quiescent current (~ 2.5 µA) at Low-power mode
- Current limit protection
- Configurable into load switch via OTP bit
7.2.2 LDOy block diagram
Figure 8. LDOy Block Diagram
7.2.3 LDOy external components
times the nominal output voltage.
7.2.4 LDOy output voltage setting
LDOy output voltage is programmed by setting the LDOy[4:0] bits as shown in Table 33. Table 33. LDOy output voltage setting
7.2.5 LDOy low power mode operation
Table 34. LDOy control bits
7.2.6 LDOy current limit protection
mode that limits the available output current.
Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 3 — 7 April 2020 By setting the REGSCPEN bit, LDOy can be automatically disabled in the event of an over current situation. In the event of an over current, the LDO will be disabled by resetting its LDOy_EN bit, while at the same time an interrupt LDOy_FAULTI is generated to flag the fault to the system processor. The LDOy_FAULTI interrupt is maskable through the LDOy_FAULTM mask bit. If REGSCPEN is not set, the regulator will not be automatically disabled, but will instead enter the current limit mode. By default, the REGSCPEN is not set; therefore, at start- up none of the regulators will be disabled if an overloaded condition occurs. A fault interrupt, LDOy_FAULTI, is generated in an overload condition regardless of the state of the REGSCPEN bit. Current limit is not active when LDOy is operated in the load switch mode.
7.2.7 LDOy load switch mode
The LDOy path can be turned into a switch by setting the OTP_LDOy_LS bit. Setting this bit fully turns on the LDO pass FET. This could be useful if power domain partitioning or additional isolation is needed on the system application. Soft-start is engaged during start up of the load switch to reduce inrush currents.
7.3 LDO2 detailed description
LDO2 is a 400 mA low dropout (LDO) regulator that provides output voltage with high accuracy and programmable through I2C/ interface bits. To support this wide input range the LDO circuit incorporates a PMOS pass FET. The LDO uses the main bandgap as its reference. The regulator incorporates a soft-start circuit that ramps the internal reference in order to provide smooth output waveform with minimal overshooting during power up. When the regulator is disabled, the output is discharged by an internal pull-down resistor. The pull- down is also activated when RESETBMCU is low. Moreover, LDO2 includes current limit protection with option to turn off the LDO when an overcurrent is detected.
7.3.1 LDO2 features summary
- Input range LDO from 2.8 V to 4.5 V
- Programmable output voltage between 1.8 V and 3.3 V with 2 % accuracy
- Soft-start ramp control during power up and discharge mechanism during power down
- Low quiescent current (~ 1.5 µA) at Low-power mode
- Current limit protection
7.3.2 LDO2 block diagram
Figure 9. LDO2 block diagram
7.3.3 LDO2 external components
times the nominal output voltage.
7.3.4 LDO2 output voltage setting
Table 35. LDO2 output voltage setting
7.3.5 LDO2 Low-power mode operation
Table 36. LDO2 control bits
7.3.6 LDO2 current limit protection
mode limiting the available output current.
7.4 VREFDDR reference
reference voltage for DDR memories. utilizes a voltage follower to drive the load.
Figure 10. VREFDDR block diagram
7.5 VSNVS LDO/Switch
voltage is simply the coin cell voltage minus the voltage drop across the switch. configuration from an LDO to a switch. Figure 11. VSNVS block diagram
Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 3 — 7 April 2020
8 Front-end LDO description
The VIN operates from 4.0 V to 6.5 V with up to 22 V overvoltage protection. The VIN current limit works by monitoring the current being drawn from the VIN and comparing it to the programmed current limit. The current limit should be set based on the current-handling capability of the input adaptor. Generally, this limit is chosen to optimally fulfill the system-power requirements. See Table 40. The PMIC is powered from the VSYS node in the PF1510.
8.1 Operating modes and behavioral description
Figure 12. Startup sequence Table 37. Front-end regulator register
The VSYSMIN value is programmable via OTP as per the table below. Table 38. VSYSMIN setting
11 Reserved
(PMIC undervoltage detection, 2.9 V typ.). Typically, the VSYS output range can go as low as 300 mV below the VSYSMIN setting. Table 39. VIN current limit register The table below shows valid VIN limit settings. Table 40. VIN limit settings
11110 Reserved
11111 Reserved
9 Control and interface signals
9.1 PWRON
= 0), or as an edge sensitive input (OTP_PWRON_CFG = 1). turns off the part, or puts it into Sleep mode. seconds, the part turns off or enters Sleep mode. Table 41. PWRON pin OTP configuration options
0 PWRON pin HIGH = ON
1 PWRON pin pulled LOW momentarily = ON
Table 42. PWRON pin logic level
momentarily while in RUN or STANDBY modes. Only an interrupt is generated. See Section 10 "PF1510 state machine" for detailed description. interrupt is cleared by software, or when cycling through the REGS_DISABLE mode. Table 43. PWRONDBNC settings
9.2 STANDBY
active high or active low using the STANDBYINV bit. Table 44. Standby pin polarity control Table 45. STANDBY pin logic level
made for three additional 32 kHz cycles required to synchronize the Standby event.
9.3 RESETBMCU
supplies have been enabled; it is only asserted during a turn off event. occurs and persists for 1.8 ms typically, RESETBMCU is asserted low. repeated. To enter the fault mode, set bit OTP_PWRGD_EN to 1. deasserted is programmable between 2.0 ms and 1024 ms via OTP_POR_DLY[2:0] bits. Table 46. RESETBMCU pin logic level
9.4 INTB
cleared by software, which requires writing a “1” to the interrupt bit. polling for status from the IC. Table 47. INTB pin logic level
9.5 WDI
Table 48. WDI pin logic level
9.6 ONKEY
Table 49. ONKEY pin logic level Table 50. ONKEYDBNC settings press. The interrupt is generated during the rising edge of the ONKEY pin. See Section 12 "Register map" for detailed description of the ONKEY interrupt registers.
9.7 Control interface I2C block description
controlled. The registers also provide status information about how the IC is operating.
9.7.1 I2C device ID
bus. The PF1510 I2C device address is 0x08.
9.7.2 I2C operation
or NACK is received prior to completion. Figure 13. I2C sequence
10 PF1510 state machine
The PMIC part of the PF1510 can operate in a number of states as shown in Figure 14.
- “System On” that includes the RUN, STANDBY and SLEEP modes
- “System Off” that includes the REGS_DISABLE and CORE_OFF modes
Figure 14. PMIC state machine general the system processor is powered. the Run mode requires a Turn On event. See Section 10.3 "Turn on events". Transition from any of the “System On” modes to the REGS_DISABLE state is allowed. This transition is referred to as a Turn Off event. See Section 10.4 "Turn off events".
10.1 System ON states
10.1.1 Run state
In this state, the PMIC regulators are enabled and the system is powered up. RESETBMCU is de-asserted in this state.
- From REGS_DISABLE through a Turn On Event: During this transition, the PMIC
regulators are powered, the RESETBMCU pin is de-asserted.
- From STANDBY by using the STANDBY pin
- From SLEEP mode by using the PWRON pin: Typically, some of the regulators are
Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 3 — 7 April 2020 mode. While transitioning from the SLEEP to the RUN mode, regulators that were turned off in the SLEEP mode are turned back on in the RUN mode following the same sequence as the programmed OTP sequence. Output voltage transitions during transition from the SLEEP to the RUN mode also occurs at the same OTP sequence time slot. RESETBMCU is de-asserted through this state transition.
10.1.2 STANDBY state
This state is entered by controlling the logic level of the STANDBY pin. It can be entered only from the RUN mode. The STANDBY pin polarity is programmable through the STANDBYINV I2C bit. By default, STANDBYINV = 0 and a logic high on the STANDBY pin moves the state machine from the RUN state to the STANDBY state. When STANDBYINV = 1, a logic low moves the state machine from the RUN state to the STANDBY state. Regulator output voltage may be changed, or regulator outputs could be disabled while entering the STANDBY state and vice versa. For details on the power-down sequence, see Section 10.7 "Regulator power-down sequencer". While exiting STANDBY state into the RUN mode, regulator output voltage changes and regulator enables follow the power-up sequence. It is possible to exit STANDBY state and enter the SLEEP state. SLEEP state is generally a lower power system state compared to the STANDBY state. Exiting STANDBY into the SLEEP state follows the power-down sequence. RESETBMCU is de-asserted in the STANDBY state.
10.1.3 SLEEP state
This state is entered from either the RUN state or the STANDBY state by controlling the PWRON pin. The exact condition required for this transition depends on the OTP configuration of the PWRON pin. For details see Section 9.1 "PWRON". The power-down sequence is followed while entering this state and the power-up sequence is followed while exiting this state into the RUN state. RESETBMCU is de-asserted in the SLEEP state.
10.2 System OFF states
RESETBMCU is asserted (low) in all the System Off states.
10.2.1 REGS_DISABLE
This state can be considered the ‘home state’ for the state machine. In this state, the state machine waits for appropriate commands to proceed to other states. REGS_DISABLE can be entered from one of the “System On” state through a turn off event. REGS_DISABLE can be entered from the CORE_OFF by pressing the ONKEY button for more than 1000 ms or by applying the Vin. In the REGS_DISABLE state, the PMIC core circuitry is active. VSNVS is a best-of- supply output of VSYS and LICELL.
10.2.2 CORE_OFF
- From the REGS_DISABLE mode by pressing and holding the ONKEY button low >
- From the REGS_DISABLE mode if the GOTO_CORE_OFF bit is set
This state cannot be entered if Vin is applied. In this state, the internal core of the PMIC is turned off to reduce quiescent current. VSNVS is the only regulator that is supplied to external loads.
10.3 Turn on events
(transition H in Figure 14 ).
- PWRON logic high with PWRON_CFG = 0
- PWRON H -> L with PWRON_CFG = 1
VSYS > UVDETrising and TJ < TSHDN_fall are preconditions for a turn on event to occur. is masked till the RESETBMCU pin is deasserted.
10.4 Turn off events
followed during all of the turn off events.
- Thermal Shutdown (TJ > TSHDN_rise)
- PWRON logic low with OTP_PWRON_CFG = 0
- PWRON low > 4.0 s with OTP_PWRON_CFG = 1 && PWRONRSTEN = 1
- WDI = 0. This occurs when the processor watchdog expires and pulls the WDI pin low
- ONKEY pressed low > Tgreset && ONKEYRST_EN = 1. This facilitates creating a hard
reset when pressing the ONKEY button without processor intervention.
10.5 State diagram and transition conditions
Table 51. State transition table
Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 3 — 7 April 2020 Transition Description PWRON_CFG = 0 (Level sensitive) PWRON_CFG = 1 (Edge sensitive) E Sleep to Run PWRON = 1 PWRON High to Low to High [1] F Run to Sleep (PWRON = 0) && (Any SWxOMODE = 1 || Any LDOxOMODE = 1) (PWRON High to Low and PWRON = 0 > 4s) && (PWRONRSTEN = 1) && (Any SWxOMODE = 1 || Any LDOxOMODE = 1) G Run/Standby/Sleep to REGS_DISABLE (Thermal shutdown) OR (PWRON = 0 && All SWxOMODE = 0 && All LDOxOMODE = 0) OR (WDI = 0) [2] OR (ONKEY High to Low and ONKEY = 0 > Tgreset && ONKEY_RST_EN = 1) OR (VSYS < UVDET_Fall) [3] (Thermal shutdown) OR (PWRON = 0 > 4s && PWRONRSTEN = 1 && All SWxOMODE = 0 && All LDOxOMODE = 0) OR (PWRON High to Low and PWRON = 0 > 4s when in Sleep state) OR (WDI = 0) [2] OR (ONKEY High to Low and ONKEY = 0 > Tgreset and ONKEY_RST_EN = 1) OR (VSYS < UVDET_Fall) [3] H REGS_DISABLE to Run (Only if VSYS > UVDET and TJ < TSHDN_fall) PWRON = 1 (PWRON High to Low ) OR (If entered REGS_DISABLE via long press on PWRON && RESTARTEN = 1 && PWRON stays Low > 1.0 s) OR (Vin applied) [4] [5] I REGS_DISABLE to CORE_OFF (Only if VIN_INVALID = 1) (GOTO_CORE_OFF = 1 && ONKEY = 1) OR (ONKEY High to Low and ONKEY = 0 > Tgreset && ONKEY_RST_EN = 1) [6][7] (GOTO_CORE_OFF = 1 && ONKEY = 1) OR (ONKEY High to Low and ONKEY = 0 > Tgreset && ONKEY_RST_EN = 1) [6][8] K CORE_OFF to REGS_ DISABLE (ONKEY High to Low and ONKEY = 0 > 1000 ms) OR (Vin applied) (ONKEY High to Low and ONKEY = 0 > 1000 ms) OR (Vin applied) [1] This low period is < 4.0 s. If it is longer than 4.0 s, it transitions to G [2] PWRON pin is pulled low by processor after WDI = 0. [3] Follows regulator power-down sequence for this transition [4] WDI pin is masked till RESETBMCU is deasserted. [5] Debounce on PWRON programmable via PWRONDBNC[1:0] [6] PWRON pin is pulled low by processor after ONKEY = 0 > Tgreset. [7] GOTO_CORE_OFF is set by user when system is ON. For other products, a secondary processor is used to set this bit while in REGS_DISABLE [8] GOTO_CORE_OFF must be set by user when system is ON
10.6 Regulator power-up sequencer
Start-up sequence of all the switching and linear regulators in the PF1510 is programmable. VSNVS's sequence is not programmable but is always the first regulator to power up when the PF1510 is powered up via a cold start (from no input to valid input). When SYS is first applied to the PF1510, VSNVS comes up first. The switching and linear regulators power up based on their programmed OTP sequence using the respective OTP_XX_SEQ[2:0] when transitioning from REGS_DISABLE to the RUN state. RESETBMCU is pulled low from VCOREDIG POR till the end of the power-up sequencer. RESETBMCU is pulled high 2.0 ms to 1024 ms after the last regulator powers up. This delay is OTP programmable through the OTP_POR_DLY[2:0] bits. When transitioning from STANDBY mode to RUN mode, the power-up sequencer is activated only if any of the regulators turn back on during this transition.
Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 3 — 7 April 2020 The power-up sequencer ends as soon as the last regulator powers up, rather than waiting for a fixed time. The power-up sequencer is always activated when transitioning from Sleep to Run modes. The sequencer ends as soon as the last regulator powers up, rather than waiting for a fixed time. The PWRUP_I interrupt is set to indicate completion of transition from STANDBY to RUN and SLEEP to RUN. The PWRUP_I interrupt is set while transitioning from STANDBY to RUN even if the sequencers were not used. This is used to indicate that the transition is complete.
10.7 Regulator power-down sequencer
The power-down sequencer performs the functional opposite to the power-up sequencer. Each regulator has an associated register setting (SW1_PWRDN_SEQ[2:0], SW2_PWRDN_SEQ[2:0], SW3_PWRDN_SEQ[2:0], LDO1_PWRDN_SEQ[2:0], LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0], VREFDDR_PWRDN_SEQ[2:0]) that sets its power-down sequence. The default setting of the above registers is equal to the corresponding power-up sequence setting. For example, SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0]. When the power-down sequencer is activated, regulators are turned off one by one in the descending order of the XXX_PWRDN_SEQ[2:0] setting. This way, by default power- down is a mirror of the power-up sequence. In one of the "System On" states, the processor can change the values of the XXX_PWRDN_SEQ[2:0] registers. The power-up sequence is fixed by OTP (or TBB). If all XXX_PWRDN_SEQ[2:0] = 0x00, the power-down sequencer is bypassed and all the regulators are turned off at once. During transition from Run to Standby, the power-down sequencer is activated if any of the regulators are turned off during this transition. If regulators are not turned off during this transition, the power-down sequencer is bypassed and the transition happens at once (any associated DVS transitions still take time). During transition from Run to Sleep, the power-down sequencer is always activated. However, if all XXX_PWRDN_SEQ[2:0] = 0, the transition happens immediately. The PWRDN_I interrupt is set during transition from Run to Sleep and Run to Standby even if regulators are not turned off during these transitions.
11 Device start up
11.1 Startup timing diagram
The startup timing of the regulators is programmable through OTP, Figure 15 shows the startup timing of the regulators as determined by their OTP A4 sequence.
Figure 15. A4 startup and power down sequence Table 52. A4 startup and power down sequence timing
- OTP_SEQ_CLK_SPEED = 0
- OTP_SEQ_CLK_SPEED = 1 [3] 0.5 2.0 ms tR3 Rise time of regulators [4] — 0.2 — ms tD4 Turn-on delay of RESETBMCU — 2.0 — ms tR4 Rise time of RESETBMCU — 0.2 — ms tD5 Power down delay between regulators — 2.0 — ms [1] All regulators avoid drop-out mode at startup [2] Depends on the external signal driving PWRON [3] A4 configuration [4] Rise time is a function of slew rate of regulators and nominal voltage selected.
11.2 Device start up configuration
Table 53. PF1510 start up configuration
Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 3 — 7 April 2020 Pre-programmed OTP configuration Registers A1 A2 A3 A4 A5 A6 A7 OTP_SW1_PWRUP_SEQ[2:0] 1 5 3 4 3 3 3 OTP_SW2_PWRUP_SEQ[2:0] 2 5 3 3 3 3 3 OTP_SW3_PWRUP_SEQ[2:0] 3 1 3 2 3 3 3 OTP_LDO1_PWRUP_SEQ[2:0] 4 1 3 1 3 3 3 OTP_LDO2_PWRUP_SEQ[2:0] 4 1 2 2 2 2 2 OTP_LDO3_PWRUP_SEQ[2:0] 5 1 3 1 3 3 3 OTP_VREFDDR_PWRUP_ SEQ[2:0] 5 5 3 3 3 3 3 OTP_SW1_DVS_SEL Non-DVS mode DVS mode OTP_SW2_DVS_SEL DVS mode Non-DVS mode DVS mode Non-DVS mode OTP_LDO1_LS_EN LDO mode OTP_LDO3_LS_EN LS mode LDO mode OTP_SW1_RDIS_ENB Enabled OTP_SW2_RDIS_ENB Enabled OTP_SW3_RDIS_ENB Enabled OTP_SW1_DVSSPEED 12.5 mV step each 4.0 µs OTP_SW2_DVSSPEED 12.5 mV step each 2.0 µs 12.5 mV step each 4.0 µs OTP_SWx_EN_AND_STBY_EN SW1, SW2, SW3 enabled in RUN and STANDBY OTP_LDOx_EN_AND_STBY_EN LDO1, LDO2, LDO3, VREFDDR enabled in RUN and STANDBY OTP_PWRON_CFG Level sensitive OTP_SEQ_CLK_SPEED 0.5 ms time slots 2 ms time slots OTP_TGRESET[1:0] 4 secs global reset timer OTP_POR_DLY[2:0] 2 ms RESETBMCU power-up delay OTP_UVDET[1:0] Rising 3.0 V; falling 2.9 V OTP_I2C_DEGLITCH_EN I2C deglitch filter disabled OTP_VSYSMIN[1:0] VSYSMIN = 4.3 V VSYSMIN = 3.7 V VSYSMIN = 4.3 V OTP_VIN_ILIM[4:0] VIN ILIM = 500 mA VIN ILIM = 1500 mA
12 Register map
12.1 Specific PMIC Registers (Offset is 0x00)
The following pages contain description of the various registers in the PF1510. Table 54. Register DEVICE_ID - ADDR 0x00 Table 55. Register OTP_FLAVOR - ADDR 0x01 Table 56. Register SILICON_REV - ADDR 0x02
Table 57. Register INT_CATEGORY - ADDR 0x06 LDO_INT 4 R 0 This bit is set high if any of the LDO interrupt status bits are set. This includes LDO1, LDO2 and LDO3. Table 58. Register SW_INT_STAT0 - ADDR 0x08 current limit fault persists for longer than the debounce time.
current limit fault persists for longer than the debounce time. current limit fault persists for longer than the debounce time. Table 59. Register SW_INT_MASK0 - ADDR 0x09 interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. Table 60. Register SW_INT_SENSE0 - ADDR 0x0A as fault persists (post-debounce). as fault persists (post-debounce).
Table 61. Register SW_INT_STAT1 - ADDR 0x0B Table 62. Register SW_INT_MASK1 - ADDR 0x0C interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. Table 63. Register SW_INT_SENSE1 - ADDR 0x0D report the sense status within the switching cycle.
report the sense status within the switching cycle. report the sense status within the switching cycle. Table 64. Register SW_INT_STAT2 - ADDR 0x0E transitioning states, Run to Standby, for example). transitioning states, Run to Standby, for example). Table 65. Register SW_INT_MASK2 - ADDR 0x0F interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set.
Table 66. Register SW_INT_SENSE2 - ADDR 0x10 Table 67. Register LDO_INT_STAT0 - ADDR 0x18 Table 68. Register LDO_INT_MASK0 - ADDR 0x19 interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set.
Table 69. Register LDO_INT_SENSE0 - ADDR 0x1A Table 70. Register TEMP_INT_STAT0 - ADDR 0x20 THERM110I 0 RW1C[1] 0 Die temperature crosses 110 °C interrupt. Bidirectional interrupt. THERM125I 2 RW1C 0 Die temperature crosses 125 °C interrupt. Bidirectional interrupt. Table 71. Register TEMP_INT_MASK0 - ADDR 0x21 interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set.
Table 72. Register TEMP_INT_SENSE0 - ADDR 0x22 Table 73. Register ONKEY_INT_STAT0 - ADDR 0x24
Table 74. Register ONKEY_INT_MASK0 - ADDR 0x25 interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. Table 75. Register ONKEY_INT_SENSE0 - ADDR 0x26 of the ONKEY button being released. the debounce circuit (debounce is programmable).
Table 76. Register MISC_INT_STAT0 - ADDR 0x28
Table 77. Register MISC_INT_MASK0- ADDR 0x29 interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. interrupt status bit is set. Table 78. Register MISC_INT_SENSE0 - ADDR 0x2A
Table 79. Register COINCELL_CONTROL - ADDR 0x30 Table 80. Register SW1_VOLT - ADDR 0x32 Table 81. Register SW1_STBY_VOLT - ADDR 0x33 value here should be identical to SW1_VOLT[5:0] register.
Table 82. Register SW1_SLP_VOLT - ADDR 0x34 value here should be identical to SW1_VOLT[5:0] register. Table 83. Register SW1_CTRL - ADDR 0x35 sequence settings. User can turn regulator off by clearing this bit. equal to the SW1_EN bit (based on OTP).
Table 84. Register SW1_SLP_VOLT - ADDR 0x36 Table 85. Register SW2_VOLT - ADDR 0x38 Table 86. Register SW2_STBY_VOLT - ADDR 0x39 value here should be identical to SW2_VOLT[5:0] register.
Table 87. Register SW2_SLP_VOLT - ADDR 0x3A value here should be identical to SW2_VOLT[5:0] register. Table 88. Register SW2_CTRL - ADDR 0x3B sequence settings. User can turn regulator off by clearing this bit. equal to the SW1_EN bit (based on OTP). 1 — Forced in PWM mode irrespective of load current.
Table 89. Register SW2_CTRL1 - ADDR 0x3C Table 90. Register SW3_VOLT - ADDR 0x3E SW3_VOLT 3 to 0 RW1S — SW3 voltage setting register (Run mode). Loaded from fuses. Read only because DVS is not supported in this regulator. Table 91. Register SW3_STBY_VOLT - ADDR 0x3F SW3_STBY_VOLT 3 to 0 RW1S — SW3 voltage setting register (Standby mode). Loaded from fuses. Read only because DVS is not supported in this regulator.
Table 92. Register SW3_SLP_VOLT - ADDR 0x40 SW3_SLP_VOLT 3 to 0 RW1S — SW3 voltage setting register (Sleep mode). Loaded from fuses. Read only because DVS is not supported in this regulator. Table 93. Register SW3_CTRL - ADDR 0x41 sequence settings. User can turn regulator off by clearing this bit. equal to the SW1_EN bit (based on OTP).
Table 94. Register SW3_CTRL1 - ADDR 0x42 Table 95. Register VSNVS_CTRL - ADDR 0x48 VSNVS_VOLT 2 to 0 RW1S 000 Not used in PF1510. Placeholder for future products. Table 96. Register VREFDDR_CTRL - ADDR 0x4A
Table 97. Register LDO1_VOLT - ADDR 0x4C LDO1_VOLT 4 to 0 RW1S — LDO1 output voltage setting register. Loaded from OTP. Table 98. Register LDO1_CTRL - ADDR 0x4D sequence settings. User can turn regulator off by clearing this bit. to 1 on power up. Changing from 1 to 0 is not allowed. Table 99. Register LDO2_VOLT - ADDR 0x4F LDO2_VOLT 3 to 0 RW1S — LDO2 output voltage setting register. Loaded from OTP. Table 100. Register LDO2_CTRL - ADDR 0x50 sequence settings. User can turn regulator off by clearing this bit.
Table 101. Register LDO3_VOLT - ADDR 0x52 LDO3_VOLT 4 to 0 RW1S — LDO3 output voltage setting register. Loaded from OTP. Table 102. Register LDO3_CTRL - ADDR 0x53 sequence settings. User can turn regulator off by clearing this bit. to 1 on power up. Changing from 1 to 0 is not allowed.
Table 103. Register PWRCTRL0 - ADDR 0x58 Table 104. Register PWRCTRL1 - ADDR 0x59
0 — LDO does not shutdown in the event of a current limit fault. "PF1510 state machine" for details. Table 105. Register PWRCTRL2 - ADDR 0x5A Table 106. Register PWRCTRL3 - ADDR 0x5B
Table 107. Register SW1_PWRDN_SEQ - ADDR 0x5F default. Power-up sequence is in mirror registers. SEQ[2:0], LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0]. SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0]. Table 108. Register SW2_PWRDN_SEQ - ADDR 0x60 default. Power-up sequence is in mirror registers. SEQ[2:0], LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0]. SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0].
Table 109. Register SW2_PWRDN_SEQ - ADDR 0x61 default. Power-up sequence is in mirror registers. SEQ[2:0], LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0]. SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0]. Table 110. Register LDO1_PWRDN_SEQ - ADDR 0x62 default. Power-up sequence is in mirror registers. SEQ[2:0], LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0]. SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0].
Table 111. Register LDO2_PWRDN_SEQ - ADDR 0x63 default. Power-up sequence is in mirror registers. SEQ[2:0], LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0]. SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0]. Table 112. Register LDO3_PWRDN_SEQ - ADDR 0x64 default. Power-up sequence is in mirror registers. SEQ[2:0], LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0]. SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0].
Table 113. Register VREFDDR_PWRDN_SEQ - ADDR 0x65 default. Power-up sequence is in mirror registers. SEQ[2:0], LDO2_PWRDN_SEQ[2:0], LDO3_PWRDN_SEQ[2:0]. SW1_PWRDN_SEQ[2:0] = OTP_SW1_PWRUP_SEQ[2:0]. Table 114. Register STATE_INFO - ADDR 0x67 Table 115. Register I2C_ADDR - ADDR 0x68 2 to 0 R 000 Loaded from fuses. But read only in functional space.
7 RW 0 DEFAULT ADDR
Table 116. Register RC_16MHZ - ADDR 0x6B Table 117. Register KEY1 - ADDR 0x6B
12.2 Specific Registers (Offset is 0x80)
Table 118. Register INT - ADDR 0x00 Table 119. Register INT_MASK - ADDR 0x02
Table 120. Register INT_OK - ADDR 0x04 0 — The VIN input is invalid. For example, VIN_VALID = 0. 1 — The VIN input is valid. For example, VIN_VALID = 1. Table 121. Register VIN_SNS - ADDR 0x06
Table 122. Register FRONT_END_OPER- ADDR 0x09 Table 123. Register FRONT_END_REG - ADDR 0x0F Table 124. Register VIN_INLIM_CNFG - ADDR 0x14
Table 125. Register USB_PHY_LDO_CNFG - ADDR 0x16
Table 126. Register DBNC_DELAY_TIME - ADDR 0x18 Table 127. Register VIN2SYS_CNFG - ADDR 0x1B
12.3 Register PMIC bitmap
Table 128. Register PMIC bitmap
Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 3 — 7 April 2020 BITS[7:0]Address Register name 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 0x10 SW_INT_SENSE2 Name — — — — — LDO3_FAULTI LDO2_FAULTI LDO1_FAULTI Reset 0 0 0 0 0 0 0 0 0x18 LDO_INT_STAT0 Type — — — — — RW1C RW1C RW1C Name — — — — — LDO3_FAULTM LDO2_FAULTM LDO1_FAULTM Reset 0 0 0 0 0 1 1 1 0x19 LDO_INT_MASK0 Name — — — — — LDO3_FAULTS LDO2_FAULTS LDO1_FAULTS Reset 0 0 0 0 0 0 0 0 0x1A LDO_INT_SENSE0 Name — — — — — THERM125I — THERM110I Reset 0 0 0 0 0 0 0 0 0x20 TEMP_INT_STAT0 Name — — — — — THERM125M — THERM110M Reset 0 0 0 0 1 1 1 1 0x21 TEMP_INT_MASK0 0x22 TEMP_INT_SENSE0 Name — — — — — THERM125S — THERM110S Reset 0 0 0 0 0 0 0 0 Name — — ONKEY_8SI ONKEY_4SI ONKEY_3SI ONKEY_2SI ONKEY_1SI ONKEY_PUSHI Reset 0 0 0 0 0 0 0 0 0x24 ONKEY_INT_STAT0 Type — — RW1C RW1C RW1C RW1C RW1C RW1C Name — — ONKEY_8SM ONKEY_4SM ONKEY_3SM ONKEY_2SM ONKEY_1SM ONKEY_ PUSHM Reset 0 0 1 1 1 1 1 1 0x25 ONKEY_INT_MASK0 Type — — RW RW RW RW RW RW Name — — ONKEY_8SS ONKEY_4SS ONKEY_3SS ONKEY_2SS ONKEY_1SS ONKEY_ PUSHS Reset 0 0 0 0 0 0 0 0 0x26 ONKEY_INT_SENSE0 Type — — R R R R R R WARN_I PWRON_I PWRDN_I PWRUP_I Reset 0 0 0 0 0 0 0 0 0x28 MISC_INT_STAT0 Type — — — RW1C RW1C RW1C RW1C RW1C WARN_M PWRON_M PWRDN_M PWRUP_M Reset 0 0 0 1 1 1 1 1 0x29 MISC_INT_MASK0 Type — — — RW RW RW RW RW WARN_S PWRON_S PWRDN_S PWRUP_S Reset 0 0 0 0 0 0 0 0 0x2A MISC_INT_SENSE0 Type — — — R R R R R Name COINCHEN VCOIN[3:0] Reset 0 0 0 0 0 0 0 0 0x30 COINCELL_CONTROL Type — — — RW RW RW RW RW Name — — SW1_VOLT[5:0] Reset 0 0 0 0 0 0 0 0 0x32 SW1_VOLT Type — — RW1S RW1S RW1S RW1S RW1S RW1S Name — — SW1_STBY_VOLT[5:0] Reset 0 0 0 0 0 0 0 0 0x33 SW1_STBY_VOLT Type — — RW1S RW1S RW1S RW1S RW1S RW1S
Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 3 — 7 April 2020 BITS[7:0]Address Register name 7 6 5 4 3 2 1 0 Name — — SW1_SLP_VOLT[5:0] Reset 0 0 0 0 0 0 0 0 0x34 SW1_SLP_VOLT Type — — RW1S RW1S RW1S RW1S RW1S RW1S Name SW1_ RDIS_ENB SW1_FPWM SW1_FPWM_ IN_DVS SW1_ DVSSPEED SW1_LPWR SW1_OMODE SW1_STBY_EN SW1_EN Reset 0 0 0 0 0 0 0 0 0x35 SW1_CTRL Type RW1S RW RW RW1S RW RW RW1S RW1S SEL — — SW1_ILIM[1:0] Reset 0 0 0 0 0 0 0 0 0x36 SW1_CTRL1 Type — — — RW — — RW1S RW1S Name — — SW2_VOLT[5:0] Reset 0 0 0 0 0 0 0 0 0x38 SW2_VOLT Type — — RW1S RW1S RW1S RW1S RW1S RW1S Name — — SW2_STBY_VOLT[5:0] Reset 0 0 0 0 0 0 0 0 0x39 SW2_STBY_VOLT Type — — RW1S RW1S RW1S RW1S RW1S RW1S Name — — SW2_SLP_VOLT[5:0] Reset 0 0 0 0 0 0 0 0 0x3A SW2_SLP_VOLT Type — — RW1S RW1S RW1S RW1S RW1S RW1S Name SW2_ RDIS_ENB SW2_FPWM SW2_FPWM_ IN_DVS SW2_ DVSSPEED SW2_LPWR SW2_OMODE SW2_STBY_EN SW2_EN Reset 0 0 0 0 0 0 0 0 0x3B SW2_CTRL Type RW1S RW RW RW1S RW RW RW1S RW1S SEL — — SW2_ILIM[1:0] Reset 0 0 0 0 0 0 0 0 0x3C SW2_CTRL1 Type — — — RW — — RW1S RW1S Name — — — — SW3_VOLT[3:0] Reset 0 0 0 0 0 0 0 0 0x3E SW3_VOLT Type — — — — RW1S RW1S RW1S RW1S Name — — — — SW3_STBY_VOLT[3:0] Reset 0 0 0 0 0 0 0 0 0x3F SW3_STBY_VOLT Type — — — — RW1S RW1S RW1S RW1S Name — — — — SW3_SLP_VOLT[3:0] Reset 0 0 0 0 0 0 0 0 0x40 SW3_SLP_VOLT Type — — — — RW1S RW1S RW1S RW1S Name SW3_ RDIS_ENB SW3_FPWM — SW3_ DVSSPEED SW3_LPWR SW3_OMODE SW3_STBY_EN SW3_EN Reset 0 0 0 0 0 0 0 0 0x41 SW3_CTRL Type RW1S RW — RW1S RW RW RW1S RW1S SEL — — SW3_ILIM[1:0] Reset 0 0 0 0 0 0 0 0 0x42 SW3_CTRL1 Type — — — RW — — RW1S RW1S Name — — LIBGDIS FORCEBOS CLKPULSE VSNVS_VOLT[2:0] Reset 0 0 0 0 0 0 0 0 0x48 VSNVS_CTRL Type — — RW RW RW RW1S RW1S RW1S LPWR VREFDDR_ OMODE VREFDDR_ STBY_EN VREFDDR_EN Reset 0 0 0 0 0 0 0 0 0x4A VREFDDR_CTRL Type — — — — RW RW RW1S RW1S Name — — — LDO1_VOLT[4:0]0x4C LDO1_VOLT Reset 0 0 0 0 0 0 0 0
Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 3 — 7 April 2020 BITS[7:0]Address Register name 7 6 5 4 3 2 1 0 Type — — — RW1S RW1S RW1S RW1S RW1S Name — — — LDO1_LS_EN LDO1_LPWR LDO1_OMODE LDO1_STB Y_ EN VLDO1_EN Reset 0 0 0 0 0 0 0 0 0x4D LDO1_CTRL Type — — — RW1S RW RW RW1S RW1S Name — — — — LDO2_VOLT[3:0] Reset 0 0 0 0 0 0 0 0 0x4F LDO2_VOLT Type — — — — RW1S RW1S RW1S RW1S Name — — — — LDO2_LPWR LDO2_OMODE LDO2_STB Y_ EN VLDO2_EN Reset 0 0 0 0 0 0 0 0 0x50 LDO2_CTRL Type — — — — RW RW RW1S RW1S Name — — — LDO3_VOLT[4:0] Reset 0 0 0 0 0 0 0 0 0x52 LDO3_VOLT Type — — — RW1S RW1S RW1S RW1S RW1S Name — — — LDO3_LS_EN LDO3_LPWR LDO3_OMODE LDO3_STB Y_ EN VLDO3_EN Reset 0 0 0 0 0 0 0 0 0x53 LDO3_CTRL Type — — — RW1S RW RW RW1S RW1S Name TGRESET[7:6] POR_DLY[5:3] STANDBYINV STANDBYDLY[1:0] Reset 0 0 0 0 0 0 0 1 0x58 PWRCTRL0 Type RW1S RW1S RW1S RW1S RW1S RW RW RW Name ONKEY_ RST_EN REGSCPEN RESTARTEN PWRONRSTEN ONKEYDBNC[3:2] PWRONDBNC[1:0] Reset 1 0 0 0 0 0 0 0 0x59 PWRCTRL1 Type RW RW RW RW RW RW RW RW Name — — — — LOW_SYS_WARN[3:2] UVDET[1:0] Reset 0 0 0 0 0 0 0 0 015A PWRCTRL2 Type — — — — RW RW RW1S RW1S Name — GOTO_CORE_ OFF Reset 0 0 0 0 0 0 0 0 0x5B PWRCTRL3 Type RW RW RW RW RW RW RW RW Reset 0 0 0 0 0 0 0 0 0x5F SW1_PWRDN_SEQ Type — — — — — RW1S RW1S RW1S Reset 0 0 0 0 0 0 0 0 0x60 SW2_PWRDN_SEQ Type — — — — — RW1S RW1S RW1S Reset 0 0 0 0 0 0 0 0 0x61 SW3_PWRDN_SEQ Type — — — — — RW1S RW1S RW1S Reset 0 0 0 0 0 0 0 0 0x62 LDO1_PWRDN_SEQ Type — — — — — RW1S RW1S RW1S Reset 0 0 0 0 0 0 0 0 0x63 LDO2_PWRDN_SEQ Type — — — — — RW1S RW1S RW1S Reset 0 0 0 0 0 0 0 0 0x64 LDO3_PWRDN_SEQ Type — — — — — RW1S RW1S RW1S Name — — — — — VREFDDR_PWRDN_SEQ[2:0]0x65 VREFDDR_PWRDN_ S EQ Reset 0 0 0 0 0 0 0 0
Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 3 — 7 April 2020 BITS[7:0]Address Register name 7 6 5 4 3 2 1 0 Type — — — — — RW1S RW1S RW1S Name — — STATE[5:0] Reset 0 0 0 0 0 0 0 0 0x67 STATE_INFO Type — — R R R R R R Name USE_ DEFAULT_ ADDR Reset 0 0 0 0 0 0 0 0 0x68 I2C_ADDR Type RW — — — — R R R Reset 0 0 0 0 0 0 0 0 0x69 IO_DRV0 Reset 0 0 0 0 0 0 0 0 0x6A IO_DRV1 HIPWR REQ_ACORE_ ON REQ_16MHZ Reset 0 0 0 0 0 0 0 0 0x6B RC_16MHZ Name KEY1[7:0] Reset 0 0 0 0 0 0 0 0 0x6F KEY1 Type RW RW RW RW RW RW RW RW
12.4 Additional register bitmap
Table 129. Additional register bitmap
Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 3 — 7 April 2020
13.1 Example schematic
Figure 16 shows a typical schematic of the PF1510 with key external components.
1 VIN
6.3 V 27
30 VSNVS
6.3 V100 kΩ100 kΩ
5 VDDOTP
24 VCORE
23 VDIG
Figure 16. Typical schematic
13.2 Bill of materials
The table below shows an example bill of materials to be used with the PF1510.
Table 130. Bill of materials
13.3 PF1510 layout guidelines
13.3.1 General board recommendations
- It is recommended to use an eight layer board stack-up arranged as follows: – High current signal – GND – Signal – Power – Power – Signal – GND
Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 3 — 7 April 2020
- Allocate TOP and BOTTOM PCB layers for POWER ROUTING (high current signals), copper-pour the unused area.
- Use internal layers sandwiched between two GND planes for the SIGNAL routing.
13.3.2 Component placement
It is desirable to keep all component related to the power stage as close to the PMIC as possible, specially decoupling input and output capacitors.
13.3.3 General routing requirements
- Some recommended things to keep in mind for manufacturability: – Via in pads require a 4.5 mil minimum annular ring. Pad must be 9.0 mils larger than the hole – Maximum copper thickness for lines less than 5.0 mils wide is 0.6 oz copper – Minimum allowed spacing between line and hole pad is 3.5 mils – Minimum allowed spacing between line and line is 3.0 mils
- Care must be taken with SWxFB pins traces. These signals are susceptible to noise and must be routed far away from power, clock, or high power signals, like the ones on the SWxIN, SWxLX. They could be also shielded.
- Shield feedback traces of the regulators and keep them as short as possible (trace them on the bottom so the ground and power planes shield these traces).
- Avoid coupling traces between important signal/low noise supplies (like VCORE, VDIG) from any switching node (for example, SW1LX, SW2LX, SW3LX).
- Make sure that all components related to a specific block are referenced to the corresponding ground.
13.3.4 Parallel routing requirements
- I2C signal routing – CLK is the fastest signal of the system, so it must be given special care. – To avoid contamination of these delicate signals by nearby high power or high frequency signals, it is a good practice to shield them with ground planes placed on adjacent layers. Make sure the ground plane is uniform throughout the whole signal trace length. – These signals can be placed on an outer layer of the board to reduce their capacitance with respect to the ground plane. – Care must be taken with these signals not to contaminate analog signals, as they are high frequency signals. Another good practice is to trace them perpendicularly on different layers, so there is a minimum area of proximity between signals.
Figure 17. Recommended shielding for critical signals
13.3.5 Switching regulator layout recommendations
- Per design, the switching regulators in PF1510 are designed to operate with only one input bulk capacitor. However, it is recommended to add a high frequency filter input capacitor (CIN_hf), to filter out any noise at the regulator input. This capacitor should be in the range of 100 nF and should be placed right next to or under the IC, closest to the IC pins.
- Make high-current ripple traces low-inductance (short, high W/L ratio).
- Make high-current traces wide or copper islands. COUT CIN_HFCIN VIN SWxIN L SWxLX SWxFBCompensation Driver controller aaa-023892
Figure 18. Generic buck regulator architecture
Figure 19. Layout example for buck regulators
13.4 Thermal information
13.4.1 Rating data
anticipated that the generic name, Theta-JA, continues to be commonly used. The JEDEC standards can be consulted at http://www.jedec.org/.
13.4.2 Estimation of junction temperature
of significant power dissipated by other components placed close to the device.
Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 3 — 7 April 2020 At a known board temperature, the junction temperature TJ is estimated using the following equation TJ= TB+ (RθJBx PD) with TB = Board temperature at the package perimeter in °C RθJB = Junction to board thermal resistance in °C/W PD = Power dissipation in the package in W
14 Packaging information
The PF1510 uses a 40 QFN 5.0 mm x 5.0 mm with exposed pad, case number 98ASA00913D.
14.1 Packaging description
This drawing is available for download at http://www.nxp.com. Consult the most recently issued drawing before initiating or completing a design.
Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 3 — 7 April 2020
Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 3 — 7 April 2020
Figure 20. PF1510 Package dimensions
Table 131. Revision history
- Table 2, pin 38 – Changed Recommended connection from "Bypass with 1.0 capacitor to ground" to "Bypass with 2.2 μF capacitor to ground mandatory" – Changed Recommended connection when not used from "Leave floating" to "Bypass with 2.2 μF capacitor to ground mandatory"
- Section 7.5 – Changed "It derives its power from either VSYS or a coin cell (only if the COIN_CELL bit is set)." to "It derives its power from either VSYS or a coin cell." – Changed "Upon subsequent removal of VSYS, with the coin cell attached and COIN_ CELL set, VSNVS..." to "Upon subsequent removal of VSYS, with the coin cell attached, VSNVS..."
- Table 45 – Changed VIL max from "0.2 * VSNVS" to "0.4" – Changed VIH min from "0.8 * VSNVS" to "1.4"
- Added Table 46
- Added Table 47
- Table 49 – Changed VIL max from "0.2 * VSYS" to "0.4" – Changed VIH min from "0.8 * VSYS" to "1.4"
- Figure 15 – Removed step-down from VSYS and VSNVS lines
- Figure 16 – Terminal 38, changed capacitor value from 1.0 μF to 2.2 μF
- Table 125 – Changed USBPHYLDO description from "0 — Enabled" to "1 — Enabled" PF1510 v.1.0 20180523 Data sheet: advance information — —
Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 3 — 7 April 2020
16 Legal information
16.1 Data sheet status
Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.
Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 3 — 7 April 2020 No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non- automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. NXP — is a trademark of NXP B.V.
Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 3 — 7 April 2020 Tables Tab. 24. Acceptable inductance and capacitance Tab. 30. Acceptable inductance and capacitance Tab. 74. Register ONKEY_INT_MASK0 - ADDR Tab. 75. Register ONKEY_INT_SENSE0 - ADDR Tab. 79. Register COINCELL_CONTROL - ADDR
Power management integrated circuit (PMIC) for low power application processors Product data sheet Rev. 3 — 7 April 2020 Tab. 110. Register LDO1_PWRDN_SEQ - ADDR Tab. 111. Register LDO2_PWRDN_SEQ - ADDR Tab. 112. Register LDO3_PWRDN_SEQ - ADDR Tab. 113. Register VREFDDR_PWRDN_SEQ - ADDR Tab. 125. Register USB_PHY_LDO_CNFG - ADDR Tab. 126. Register DBNC_DELAY_TIME - ADDR Figures
Power management integrated circuit (PMIC) for low power application processors Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2020. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 7 April 2020 Document identifier: PF1510