BC3770 FREESCALE | Alldatasheet
Document overview
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Technical content
Features
- Dual-path output to power-up system in dead battery
- Single input for USB/TA
- High-efficiency synchronous switching regulator
- 2 0 V maximum withstanding input voltage
- Minimize the charging time with remote sense
- Up to 2.0 A load current for system or battery
- Programmable charge parameters via I 2C compatible interface
- 4 0 0 kHz full-speed I2C interface
- 1 . 5 MHz switching frequency
- Charge reduction mode for maximizing charging efficiency
Figure 1. BC3770 Simplified Application Diagram
25 WLCSP
Applications
- Internet of Things (IoT)
- Handheld consumer devices
- Wearable application
- mPOS terminals
- Medical portable equipment
- Consumer tablets LX PGND System I/O GND System Load PMID BOOT VBUS ID GND USB/TA NOBAT SDA SCL INTBINT SDA SCL MCU CHGENB VSYS GPIO BATSNSN VL SHDNB CHGOUT BATREG GPIO VIO connected on the PCB ADC Optional BC3770 Charge Detector VF 1-Cell Li-Ion Battery VBUS
1 Orderable Parts
Table 1. Orderable Part Variations
3 Freescale Semiconductor
2 Internal Block Diagram
Figure 2. BC3770 Simplified Internal Block Diagram
1.5 MHz
3 Pin Connections
Figure 3. BC3770 Pin Connections (Transparent Top View) Functional descriptions of many of these pins can be found in the Functional Pin Description section beginning on page 13. Table 2. BC3770 Pin Definitions mode. An embedded 100 kdischarge resistance is enabled in Charge mode. It is disconnected in the Boost mode. A3 VL Output Internal Regulator Output The analog output for internal reference, bandgap and so on. DO NOT LOAD. Use a pull-up resistor, 1.5 k to 2.2 k, to the VIO. Interface with the Processor Use a pull-up resistor, 1.5 k to 2.2 k, to the VIO. Supply Bypass BOOT to LX with a 22 nF/10 V ceramic capacitor. B4 VIO Supply for Internal Buffer Connect to the system I/O supply voltage rail.
5 Freescale Semiconductor
supply. Active-low when status change on interrupt registers occurs. C3 GND Ground Device Ground Must be connected to the system ground. C4 BATREG Battery + Terminal Sensing Connect to positive terminal of battery cell as close as possible. Converter The two PGND pins must be connected together externally. Table 2. BC3770 Pin Definitions (continued)
4 Electrical Characteristics
4.1 Maximum Ratings
of the specifications is not implied. Exposure to absolute maximum rating condition(s) for extended periods may affect device reliability. Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted.
- Human Body Model (HBM)
- Machine Model 2000 200 V (2) (3) THERMAL RATINGS Continuous Power Dissipation
- T A 25 °C
- T A 70 °C
- T A 85 °C 2.08 1.14 0.832 W TA Operating Temperature
- Ambient - 40 85 C TJ Maximum Temperature
- Junction — 150 C TSTG Storage Ambient Temperature -65 150 C TSOLDER Lead Soldering Temperature (within 10 s) — 300 °C TJA Thermal Resistance Junction to Ambient — 48 °C/W (4), (5) Notes 1. GND: all of the PGND and GND should be within the limit. 2. Human Body Model (HBM) per JESD22-A114 for all pins 3. Highly depends on the PCB heat dissipation. Tested with the Thermal Characteristics test condition below. 4. T A = 70 °C 5. Measured in still air, free convection c ondition (conforms to EIA/JESD51-2) on high effective thermal conductivity JESD51-7 test board.
7 Freescale Semiconductor
4.2 Electrical Characteristics
Table 4. BC3770 Electrical Characteristics
- On VBUS
- O n V I O 4.0 1.6 6.2 3.3 V VBUS_UVLO UVLO Threshold
- VBUS rising, 200 mV Hysteresis, VBUSOK bit set to 1 3.6 3.8 4.0 V VBUS_OVP OVP Threshold
- VBUS rising to turn off converter, 200 mV Hysteresis 6.3 6.5 6.7 V (7) VAICL_TH Adaptive-Input Current Limit (AICL) Threshold Range
- VBUS falling, Programmable in 100 mV steps, 4.5 V Default 4.3 — 4.9 V IVBUS_OP Adaptive-Input Current Limit (AICL) Threshold Range
- In charger enabled, I FAST_CHG = ISYS = 0 mA, SHDNB = H, SUSPEN = 0 LX No switching, VVSYS = VBATREG = 4.4 V override LX switching w/VSYS = 3.7 V in PWM
- USB suspended mode in SUSPEN=1 2.0 1.0 mA IIN_LIM Input Current Limit Programmable Range
- 5 0 0 mA default, test 100 mA, 500 mA, 900 mA and 1.9 A only in production 100 — 2050 mA IIN_LIM Accuracy
- With respect to I IN_LIM = 100 mA
- With respect to I IN_LIM = 500 mA
- With respect to I IN_LIM = 900 mA
- With respect to I IN_LIM = 2000 mA 100 100 100 100 107 % (7) VBUS Pull-down Resistance
- Off in BOOST Mode — 100 — k VL LDO Regulator VOUT_VLLDO Output Voltage
- V PMID = 5.0 V, ILOAD = 30 mA 4.65 4.8 — V ILOAD_LIM Current Limit
- V VLLDO = 3.8 V 50 — — mA (7) Switching Regulator fSW Switching Frequency
- In PWM mode 1.35 1.5 1.65 MHz (7) DMAX Maximum Duty Cycle — — 99 % DMIN Minimum Duty Cycle 0.0 — — % ILIM_CHG Cycle-by-cycle Current Limit for Charger Mode
- For high-side MOSFET in charger mode — 3.5 4.7 A (7) Minimum Output Capacitance
- For stability -30% 10 — F (7) Notes 6. Specifications over the T A range are assured by design, characterized, and correlated with process control. 7. Guaranteed by design, characterizati on, and correlation with process controls. Not fully tested in production.
- Q 1 F E T — 50 — m RDS(on)_Q2 Internal High-side MOSFET On-resistance
- Q 2 F E T — 50 — m RDS(on)_Q3 Internal Low-side MOSFET On-resistance
- Q 3 F E T — 70 — m RDS(on)_Q4 CHGOUT to VSYS MOSFET On-resistance
- Q 4 F E T — 30 — m VSYS Output VVSYS_MIN VSYS Min. Regulation Voltage in IIN_LIM IVSYS
- In both Trickle and pre-charge mode (V BATREG < VVSYS_MIN), ISYS = 500 mA 3.5 3.6 3.71 V VVSYS_MIN_OLP VSYS Min Regulation Voltage in IIN_LIM < IVSYS (VSYS overloaded)
- VSYS falling in VSYS overloaded in VBUSOK = 1 3.3 3.4 — V VVSYS_MAX SYS Max Regulation Voltage
- In VBUSOK = 1, ISYS_LOAD = 0 mA, ICHG = 1.5 A — VBATREG + ICHG * RDSON_Q4 VBATREG +
0.1 V V
- VSYS rising in VBUSOK = 1, VSYSOK bit set to 1 3.4 3.5 3.61 V (8) VSYSNG Threshold
- VSYS falling, VSYSNG bit set to 1 3.2 3.3 — V (8) VSYS_REVERSE Ideal Diode Regulation Voltage
- VSYS falling below BATREG, I SYS_LOAD = 3.0 A — VBATREG - 50 mV VBATREG - 75 mV V (8) VSYSLOAD Load Regulation in Transition
- I SYS = 1.0 mA to 1.0 A in tR = 20 s VBATREG - 0.2 VBATREG - 0.1 — V (8) VSYS_UVLO VSYS Undervoltage Lockout Threshold
- VSYS falling, 200 mV Hysteresis 2.3 2.4 2.5 V tDIODE-ON Ideal Diode Turn-on Time — 10 — s tDIODE_OFF Ideal Diode Turn-off Time — 10 — s Battery Charger VBATREG_RNG BATREG Programmable Voltage Range
- Programmable in 25 mV steps 4.1 — 4.475 V VBAT_REG Voltage Accuracy
- I FAST_CHG = 0 mA, set to 4.2 V and 4.35 V at VBATREG TA = 25 °C TA = -40 to 85 -0.5 -1.0 0.5 1.0 VRCH Recharge Threshold
- V BATREG - VBAT_REG — -100 — mV Notes 8. Guaranteed by design, characterization, and correlation with process controls. Not fully tested in production. 9. Designed and simulated according to I 2C specifications except general call support. 10. The regulation in boost is only guaranteed in the operation range.
Table 4. BC3770 Electrical Characteristics (continued)
9 Freescale Semiconductor
- No VBUS, V BATREG = 4.2 V, ISYS = 0 mA, SHDNB = H(I2C active), Q4 = On with OCP enabled, ENCOMPARATOR bit reset to 0, others with default — 60 — A IBAT_SHDN Shutdown Current
- No VBUS, V BATREG = 4.2 V, charger disabled, Q4 = On with OCP disabled, SHDNB = L (I2C inactive), ENCOMPARATOR bit reset to 0, others with default — — 20 A VCHGEN_ON VCHGEN_OFF Charger Enable Threshold
- V BUS - VBATREG, rising, valid VBUS detected to enable buck & charging
- V BUS - VBATREG, falling, invalid VBUS detection to disable buck & charging 100 0.0 150 200 mV (11) VTRICKLE Trickle to Pre-charge Mode Change Threshold
- V BATREG rising, 100 mV Hysteresis 2.4 2.5 2.7 V (11) ITRICKLE Trickle Charge Current
- Fixed, V BATREG = 2.3 V, VSYS = 3.6 V — 90 — mA IPRECHG Pre-charge Current Programmable Range
- 4 5 0 mA default and test in production 150 — 450 mA IFAST_CHG Fast-charge Current Programmable Range
- 5 0 0 mA default, test 500 mA, 1.0 A only in production 100 — 2000 mA ITOPOFF Top-off Current Programmable Range
- I FAST_CHG falling, 100 mA default, in 50 mA steps, test 100 mA and 300 mA only in production 100 — 65 mA VBAT_OVP Overvoltage Protection Threshold
- BATREG rising — VBAT_REG + 0.1 — V Soft-start Slope Time
- In fast charge mode — 1.17 — mA/s Minimum Output Capacitance
- On CHGOUT, For stability -30% 4.7 — F (11) Charge Current Accuracy
- Pre-charge current at 150 mA
- Top-off current at 100 mA
- I FAST_CHG = 1000mA
- I FAST_CHG = 2000mA -20 -20 -7.0 -7.0 7.0 7.0 % (11) Thermal Protection TSD Thermal Shutdown Temperature
- Temperature rising to shutdown with 20 °C hysteresis — 150 — °C (11) TCF Thermal Regulation Threshold
- Rising, charge current starts to reduce and the Interrupt triggered — 100 — °C Thermal Regulation Gain
- To have no charge current with respect to I FAST_CHG, TJ 100 °C — 3.33 — %/°C Notes 11. Guaranteed by design, characterizati on, and correlation with process controls. Not fully tested in production.
- Time for BAT from V TRICKLE to VSYS_MIN — 45 — min. Timer Accuracy -10 — 10 % (12) tTOPOFF_TMR Top-off Timer
- Programmable 10 — 45 min. tFAST_TMR Fast Charge Timer
- This timer is automatically disa bled when the input current limit is set to 100 mA FASTTIME = 00 FASTTIME = 01 FASTTIME = 10 FASTTIME = 11 (default) 3.5 4.5 5.5 disabled hrs. Deglitch Timer (12) tVBUS_OVP VBUS Supply OVP Release Deglitch Time
- Duration VBUS stays below falling OVP before VSYS/Charger/ OTG is enabled — 0.426 — ms tNOBAT NOBAT Release Deglitch Time
- Duration V NOBAT stays logic low to enable the charger — 1.0 — ms tBATOVP BATREG OVP Release Deglitch Time
- Duration BATREG stays below falling OVP level to enable charger/OTG — 7.0 — ms tTRICKLE Trickle to Pre-charge Release Deglitch Time
- Duration BATREG stays above trickle charge level to enable pre-charge — 7.0 — ms tPRCHG Pre-charge to Fast Charge Release Deglitch Time
- Duration BATREG stays above pre-charge level to enable fast charge — 7.0 — ms tITOPOFF Top-Off Deglitch Time
- Duration I FAST_CHG stays below Top-off level to generate an interrupt — 7.0 — ms tBAT_RECHG Recharge Deglitch Time
- Duration V BATREG stays below the VRCH Threshold — 27 — ms tWAIT Waiting Time to Initiate Trickle Charge Mode
- F r o m tSTART_VSYS expire to initiate trickle charge — 27 — ms (12) tWEAK_DEB Weak Battery Deglitch Time
- Duration V BATREG stays below VWEAK_HYS in ENCOMPARATOR bit = 1 — 27 — ms tSTART_VSYS VSYS Start-up Time
- From VBUS stays above UVLO to VSYS start-up — 220 — ms tINT_MASK Interrupt Mask Time — 10 — s tITOPOFF Overcurrent Discharge Deglitch Time
- Duration I FAST_DISCHG stays above the overcurrent threshold in Discharge mode to generate an interrupt — 7.0 — ms Notes 12. Guaranteed by design, characterization, and correlation with process controls. Not fully tested in production.
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- Duration VSYS stays above 3.6 V to set the VSYSOK interrupt bit = 1 and pull the INTB pin Low in VBUSOK = ENCOMPARATOR = 1 — 27 — ms tVSYSNG_DEB VSYSNG Deglitch Time
- Duration VSYS stays at/below the V VSYS_MIN_OLP threshold to set the VSYSNG interrupt bit = 1 and pull the INTB pin Low in Discharge mode and ENCOMPARATOR = 1 — 27 — ms tVSYSOLP_DEB VSYSOLP Deglitch Time
- Duration VSYS stays at/below the V VSYS_MIN_OLP threshold to set the VSYSOLP interrupt bit = 1 and pull the INTB pin Low in Overload mode and VBUSOK = 1 — 27 — ms Boost Converter IS_OTG Boost Supply Current
- In OTG enabled with no load — 3.0 — mA Output Regulation Voltage Range
- Programmable at PMID 5.0 — 5.2 V ILIM_OTG Cycle-by-Cycle Current Limit — 2.4 — A VBO_REG Boost Output Regulation Voltage at VBUS
- 3 . 0 V VBATREG 4.45 V, set to 5.1 V at PMID, 0 mA ILOAD 900 mA IBO_MAX Maximum Continuous Output Current at VBUS VBAT_MAX_BO Battery Operation Voltage Range
- For the regulated output 3.0 — 4.45 V (13) VSTART_BO BATREG Start Threshold Voltage for Boost
- V BATREG rising — 2.9 — V VSTOP_BO BATREG Stop Threshold Voltage for Boost
- V BATREG falling — 2.5 — V VBUS_OVP_H Overvoltage Protection at VBUS
- VBUS rising, 400 mV Hysteresis — 5.4 — V INTB Output Low Voltage
- I SINK = 5.0 mA — — 0.4 V Logic Inputs (CHGENB, SHDNB, and NOBAT) VIH Logic Input High Voltage 1.2 — — V VIL Logic Input Low Voltage — — 0.4 V RPD Pull-down Resistance to GND
- On CHGENB & SHDNB pin — 300 — k RPU Pull-up Resistance to VL
- On NOBAT pin — 300 — k Notes 13. Guaranteed by design, characterizati on, and correlation with process controls. Not fully tested in production. 14. The regulation in boost is only guaranteed in the operation range.
- BATREG falling, programmable in 50 mV steps 3.0 — 3.75 V Weak Battery Threshold Accuracy -5.0 — 0.4 % (15) VWEAK_HYS Weak Battery Voltage Hysteresis
- BATREG rising — 100 — mV I2C Interface (15), (16) VIH_I2C I2C Logic Input High Threshold Voltage
- S D A , S C L 1.2 — — V VIL_I2C I2C Logic Input Low Threshold Voltage
- S D A , S C L — — 0.4 V VOL_I2C I2C Logic Output Low Voltage
- S D A a t 3 . 0 mA sink current — — 0.4 V fSCL SCL Clock Frequency 0.0 — 400 kHz Notes 15. Guaranteed by design, characterization, and correlation with process controls. Not fully tested in production. 16. The regulation in boost is only guaranteed in the operation range.
Analog Integrated Circuit Device Data
13 Freescale Semiconductor
5 Functional Device Operation
5.1 Introduction
The BC3770 is a fully programmable switching charger with a single-input for USB/DCP adapter and a dual-path output for single-cell Li- Ion and Li-Polymer batteries. The dual-path output allows mobile applications with a fully discharged or dead battery to boot up the system through the VSYS output. High-efficiency and switch-mode operation of the BC3770 reduce thermal dissipation and allows the battery to charge faster with a higher current capability. The BC3770 supports single input up to 20 V max. absolute voltage and charges the battery with the current up to 2.0 A. Owing to a high-efficiency in a wide range of input voltages and charging currents, the switch mode charger is a good choice for fast charging with less power loss and better thermal management than a linear charger. The charging parameters and operating modes are fully programmable over an I2C interface that operates up to 400 kHz in full speed. The BC3770 features a highly integrated synchronous switch-mode charger, intelligent power-path, VSYS stable control scheme in overload condition, and an automatic battery detection function. The charger and boost regulator circuit switches at 1.5 MHz, to minimize the size of external passive components. To ensure USB compliance and minimize charging time, the input current is able to be limited to the value set through the I2C. The setting of charge top-off current is also programmable over I2C. The BC3770 provides battery charging in four modes: trickle, pre-charge, fast charge (constant current), and full-charge (constant voltage). The charging restart circuit automatically restarts the fast-charge cycle in full-charge mode when the battery falls below an internal threshold over the deglitch time and detected top-off threshold. Input and charge status are reported to the processors through the interrupt pin, INTB. Charge current is reduced when the die temperature reaches 100 °C, while the system current is maintained. The BC3770 is able to operate as a boost regulator for USB-OTG devices over I2C.
5.2 Features
- Dual-path output to power-up system in dead battery
- Single Input for USB/TA
- High-efficiency synchronous switching regulator
- 2 0 V maximum withstanding input voltage
- Minimize the charging time with remote sense
- Up to 2.0 A load current for system or battery
- Programmable charge parameters via I 2C compatible interface
- Fast charge current
- Charge termination current
- Battery regulation voltage
- Pre-charge current
- Fast charge threshold voltage
- Charge reduction threshold voltage
- 400 kHz full-speed I2C interface
- 1 . 5 MHz switching frequency
- Charge reduction mode for maximizing charging efficiency
- Protection
- Thermal protection
- Thermal regulation
- Input/output over voltage protection
- Adaptive input current limit protection (AICL)
- Reverse leakage protection
- No battery detection over pin detection
- Battery OVP protection
- Overcurrent protection in discharge mode
- Boost mode operation for USB OTG
- Output voltage: 5.0 V to 5.2 V, programmable at 900 mA
Analog Integrated Circuit Device Data Freescale Semiconductor 14 BC3770
5.3 Operational Modes
5.3.1 Undervoltage Lockout (UVLO)
The BC3770 has a typical undervoltage lockout threshold of 3.8 V, with a 200 mV hysteresis, rising on VBUS. VSYS also has a falling 2.5 V typical with 200 mV hysteresis. When the input supply voltage is below the 3.6 V typical UVLO falling level, the PWM buck converter turns off.
5.3.2 Registers Reset
All programmable registers in the device are reset to the default values when the following condition is met.
- Reset Condition: VSYS VSYS_UVLO
5.3.3 Q4 FET On in NO VALID VBUS
If the battery is connected with the voltage above a typical of 2.4 V and no any valid input power source is attached, the Q4 FET between VSYS and CHGOUT turns On and connects the Battery to the system, regardless of status of SHDNB. The VL regulator stays off.
5.3.4 Charge Mode
The BC3770 performs the following pre-qualification process before initiating the Charging mode: 1. Input Voltage: Detect the validation of VBUS power source, c harger enable threshold, and Adaptive-Input Current Limit (AICL) threshold. If the falling VBUS hits the AICL threshold, the charging current is reduced to limit the amount of drop on VBUS power source. In addition, the device senses the input voltage is at least above BATREG + 150 mV. 2. Battery Presence Detection: Detect the status of battery presence through the NOBAT pin. If the voltage on the NOBAT pin is above the logic high threshold, the charging is suspended (Internal Q4 FET is open). However, VSYS is regulated at VVSYS_MAX as long as a valid input source is attached. 3. Battery Voltage: Sense the battery volta ge if it is less than the BAT OVP threshold. 4. Die Temperature: If the die temperature is above 130 °C or less than 150 °C, charging is suspended. 5. Overvoltage Detection (OVP): Sense if the VBUS is less than the OVP threshold. If the OVP condition is detected, the PWM converter is immediately shut off. 6. Validation of Software and Hardware Enable signals: Detect the status of software enable bit, CHGEN=1, SUSPEN=0, and hardware pin of CHGENB=LOW. This pre-qualification process is continuously monitored and charging is suspended until all conditions are met.
5.3.5 CHARGING PROFILE
5.3.5.1 Trickle-charge Mode
Trickle-charge mode is automatically enabled in 27 ms after the VSYS start-up time expires. The battery is charged with a fixed 90 mA charge current until the battery voltage reaches the threshold, 2.5 V typical in rising. This threshold is not programmable over I2C. As soon as the battery voltage crosses over the threshold, a pre-charge mode is activated automatically after the fixed deglitch time. This allows the protection circuit in the battery pack to be reset with no damage, and brings the battery voltage to a higher level.
5.3.5.2 Pre-charge Mode
The Pre-charge mode is enabled in tTRICKLE when the battery voltage crosses over a typical 2.5 V. The safety timer called pre-charge timer, tPRECHG_TMR, 45-minute counts at the same time as well. This timer is reset as soon as the Fast-charge mode is initiated. This allows a deeply discharged battery to charge safely. The pre-charge current is programmable from 150 mA to 450 mA in 100 mA steps over I2C. If the battery voltage does not exceed the VVSYS_MIN threshold before the timer expires, charging is suspended and a fault signal is asserted via the INTB pin. If the VSYS voltage drops due to the limited input power source during the mode, the charge current is automatically reduce to maintain the VSYS as low as at 3.4 V. If the load is still overloaded, even in no charge current and limited input current, the VSYS can't help the collapse.
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5.3.5.3 Fast-charge Mode (Constant-current Mode)
The Fast-charge mode is entered in tPRECHG when the battery voltage exceeds the VVSYS_MIN threshold of a typical 3.6 V. During this mode, the battery is charged with a programmable fast-charge current. The fast-charge current is programmable from 100 mA to 2000 mA with a 500 mA default. Fast-charge current is always limited by the input current limit setting. As soon as the battery voltage reaches the VVSYS_MIN threshold, VSYS tracks the battery voltage through the Q4. This is called 'tracking mode”. In tracking mode, power dissipation is minimized by RDSON_Q4 x IFAST_CHG. However, if the VSYS voltage drops during the fast-charge mode, the charge current is automatically reduce to keep the dropout voltage, to ensure proper operation of charging circuitry. During this fast-charge mode, the safety timer called fast charge timer, tFAST_TMR, counts. If the battery voltage does not reach the VBAT_REG threshold before the timer expires, charging is suspended and a fault signal is asserted via the INTB pin. This timer is programmable and is disabled by default. This timer is automatically disabled when the input current limit is set to 100 mA.
5.3.5.4 Full-charge Mode (Constant-Voltage Mode)
As soon as the BATREG voltage reaches the VBAT_REG threshold, the fast-charge current is reduced to a programmable top-off current. The VBAT_REG regulation threshold is programmable from 4.1 V to 4.475 V in 25 mV steps.
5.3.5.5 Top-off Mode (Con stant-voltage Mode)
If the charge current down to a pre-programmed top-off current threshold is sensed over tITOPOFF, the safety timer called top-off timer, tTOPOFF_TMR, 45-minute by default, automatically counts. The top-off interrupt event is reported to the processor via the INTB. As soon as the processor reads the interrupt registers, the processor is able to turn off the charger by either CHGENB = H, CHGEN = 0, or wait until the timer expires in AUTOSTOP=1. The top-off current is programmable from 100 mA to 650 mA in 50 mA steps. 100 mA is the default.
5.3.5.6 Done Mode (Constant-voltage Mode)
After the top-off timer expires, the charger is Off automatically in AUTOSTOP=1. However, the charger stays at CV (Constant-voltage mode) in AUTOSTOP=0 even though the top-off timer expires. The interrupt signal of Done is reported to the processors via the INTB pin, regardless of the AUTOSTOP status.
5.3.6 Boost (OTG) Mode
Similar to Charge mode operation, in OTG mode enabled by I2C control bit, ENBOOST = 1, the device provides a regulated output voltage to VBUS from the battery. In Boost mode, the device first converts the battery voltage to a target voltage at PMID, then bypasses it to the VBUS pin with load current up to 900 mA to support USB OTG devices. In order to have a final regulated output at VBUS, the minimum input at BATREG should be at least or above 3.0 V. To activate Boost mode, all of the following conditions should be met in advance. 1. Either the CHGEN bit resets to “0” or CHGENB = HIGH (meaning for “charger disabled”) 2. The VBUS voltage must be less than the UVLO falling threshold 3. No Fault Conditions 4. SUSPEN bit reset to “0” Then set the ENBOOST bit to “1”. In this Boost mode, the following functions are consequently disabled.
- A I C L
- Charging
5.3.6.1 Soft -start in BOOST Mode
When Boost mode is enabled, the PMID is regulated to a pre-programmed voltage. After PMID reaches a preset target regulation voltage, the FET between PMID and VBUS turns On slowly to minimize the inrush current. The output current limit is ramped up to the boost output current limit. This soft-start counter is not initialized when one of next conditions occur. 1. Die temperature exceeds T SD 2. No battery detection (NOBAT = H) on NOBAT 3. Voltage on VBUS rises over V BUS_OVP 4. Voltage on the BATREG pin rises over VBAT_MAX_BO 5. Voltage on the BATREG pin falls below VSTOP_BO
5.3.7 Battery Recharge
Regardless of the AUTOSTOP bit status, the re-charge of the battery is able to be performed in two ways. interrupt event is not reported. The threshold is a fixed value of -100 mV. Figure 4. Re-charge Enabled in the Automatic Way the processor and if the recharge conditions are met, the charger automatically charges the battery.
5.3.8 Soft-start
charging profile where the following conditions are met in advance.
- A valid input is detected
- No AICL threshold detected
- All timers reset
- Input current limit > fast-charge current
- No SYS current
- Input current limit not detected
- No status changes on CHGEN = 1, CHGENB = LOW, SUSPEND = 0 and AUTOSTOP = 1
- V RCH = -100 mV
- Related interrupt bits not masked
- Deep battery with 2.0 V attached in advance
- Deglitch time excluded Top-Off detected Re- Charge enabled VRCH detected DONE detected 27 m s de glitch time
17 Freescale Semiconductor
Figure 5. Typical Charging Profile in No Fault Condition Note 2: The time of Read & Clear depends on the p rocessor. Note 3: Each deglitch time is not included. Note 4; Charger re st art co ndition is made on pu rp ose to sho w the beh avior.
Figure 6. Charger State Diagram
19 Freescale Semiconductor
5.3.9 Safety Timer
- Pre-charge timer is reset in one or more of the following ways:
- BATREG crosses over the VSYS minimum threshold of 3.6 V
- Falling VBUS UVLO detected
- CHGENB = HIGH 2. Fast-charge timer is reset in one or more of the following ways:
- BATREG hits the regulation voltage V BAT_REG and the charge current hits the top-off current threshold
- Falling VBUS UVLO detected
- CHGENB=HIGH or CHGEN reset to “0” before expiration 3. Top-off timer is reset in one or more of the following ways:
- BATREG hits the regulation voltage V BAT_REG, the charge current hits the top-off current threshold, and the timer expires in AUTOSTOP = 1
- Falling VBUS UVLO detected
- CHGENB = HIGH or CHGEN reset to “0” before expiration However, all safety timers are reset commonly in the following fault conditions:
- BAT OVP detected
- VBUS OVP detected
- Thermal shutdown If all fault conditions are released, the timer resumes to start.
5.3.10 VSYS
maximum input limit programmed value. Figure 7. VSYS Tracking BATTEG
5.3.10.1 Charger Enable Control
The CHGEN bit in the control register and CHGENB pin are used to enable or disable the charging process. Figure 8. Charger Enable If the CHGENB pin is not used in the application, leave the pin float since CHGENB has an internal 300 k pull-down resistance to ground.
5.3.10.2 Battery Presence Detection
configuration in fig should be done to lower the voltage rating to 1.8 V. Figure 9. Resister Divided Network If NOBAT is not used as a battery presence indicator, the following configuration is also possible. Figure 10. Resister Divided Network Option
21 Freescale Semiconductor
5.3.10.3 Battery Remote Sensing
on the battery pack as possible.
5.3.10.4 Adaptive-Input Current Limit (AICL)
The AICL function prevents the current limited input supply voltage from sagging below a certain preset AICL threshold voltage (VAICL_TH). supply can possibly provide without severely collapsing. Figure 11. AICL Operation
Analog Integrated Circuit Device Data Freescale Semiconductor 22 BC3770
5.3.10.5 Supplement Mode
When the VSYS voltage falls below the battery voltage while a valid input is attached, the Q4 FET turns On and the Q4 FET gate regulates the gate drive of Q4 so the minimum VSYS stays at 50 mV below BATREG in the Supplement mode. This prevents oscillation from entering and exiting Supplement mode. As the discharge current increases, the Q4 gate is regulated with a higher voltage, to reduce RDS(on) until Q4 is full conduction.
5.3.10.6 Charging Current Reduction in VSYS Overload
When the input current limit is detected in Charge mode by either a system overload or a programmed value is lower than the sum of load current and charge current, the device reduces the charge current until the limited input current falls below the preset current limit threshold, and the input voltage rises above the input voltage limit while maintaining the VSYS voltage at 3.4 V. Although the charge current is reduced to 0 mA, the input power source is still overloaded, and the system voltage starts to drop. Once the system voltage falls 50 mV below the battery voltage, the device automatically enters the Supplement mode and the battery starts discharging so the system is supported from the both the input supply and battery. An corresponding interrupt for VSYS overload triggers via the INTB pin.
5.4 Protection And Diagnosis Features
5.4.1 Input Overvoltage Protection
When the input voltage exceeds the overvoltage protection (OVP) threshold, internal switches immediately turn off and disconnect the load and the charger from the power source, preventing damage to any downstream components. Simultaneously, the fault flag is triggered, alerting the system. As soon as the OVP event stays over the deglitch time, tINPUT_OVP, the converter resumes.
5.4.2 Battery (BAT) Overvoltage Protection
When the BATREG voltage exceeds the battery overvoltage protection threshold, VBAT_OVP (typ. VBAT_REG+ 0.1 V), the device turns off the PWM converter and sets the fault status bit. Simultaneously, the fault flag is asserted, alerting the system. There is a 0.1 V hysteresis in the internal threshold voltage. If the OVP event over the deglitch time is released, the converter and charging resume.
5.4.3 Reverse Blocking
In the reverse blocking mode (VBUS - VBATREG) 50 mV (typ.), charging is disabled and the device is entered into Charger-suspended mode to minimize current drain from BATREG.
5.4.4 Thermal Regulation and Protection
When the device’s die temperature reaches TCF (around 100 °C), the device reduces the charge current by around 3.33% of the fast- charge current per °C. This drives the charge current down to 0 mA at 130 °C. Since the system load has priority over the battery charging, the battery charge current is reduced to 0 mA before the input limiter drops the system load current. If the junction temperature rises beyond 130 °C and then hits 150 °C, the PWM switcher shuts down to allow no input current from the input source. This prevents further die heating. In this condition, the system output voltage is regulated at BATREG. This internal thermal protection helps to improve device reliability. The device automatically goes back to normal operation when the die temperature cools down below 130 °C. In these thermal regulation and shutdown modes, I2C access is still active.
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Figure 12. Thermal Regulation
5.4.5 Weak Battery Detection
is generated. If the battery voltage goes back in range before the deglitch time, no corresponding interrupt is generated.
5.4.6 DC-DC PWM Converter
5.4.7 INTERRUPT
more interrupt events are detected in its operation. The processor reads the interrupt registers to see the source of interrupt event(s). processor reads a corresponding interrupt bit, the corresponding interrupt bit is no longer set to “1”.
5.4.7.1 Comparators for Interrupt Events
“ENCOMPARATOR” bit 6 to 0 in the 07h register. The comparators are enabled by default. INT1: Thermal regulation of interrupt is asserted. INT2: Thermal shutdown , detected by TDIE=150°C.
5.5 Logic Commands And Registers
5.5.1 Serial Interface
which means that it runs off of SCL.The data transfer protocol for Standard and Fast modes is exactly the same.
5.5.1.1 Bus Speed
spike suppression and Schmitt triggers to reject short glitches, as required by the I2C specifications.
5.5.1.2 Data Validity
(see Figure 1). One clock pulse is generated for each data bit transferred. Figure 13. Bit Transfer on the I2C Bus
5.5.1.3 Start and Stop Condition
while SCL is High defines a START condition. A Low to High transition on the SDA line while SCL is High defines a STOP condition. Figure 14. START and STOP Conditions is considered to be free again a certain time after the STOP condition.
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5.5.1.4 Byte Format
the slave is ready for another byte of data and releases clock line SCL.
5.5.1.5 Acknowledge (ACK) an d Not Acknowledge (NACK)
from, device only acknowledges its read address.
- No receiver is present on the bus with the transmitted address, so there is no device to respond with an acknowledge.
- The receiver is unable to receive or transmit, because it is performing some real-time function and is not ready to start
communication with the master.
- During the transfer the receiver gets dat a or commands it does not understand.
- During the transfer, the receiver cannot receive any more data bytes.
- A master-receiver needs to signal the end of the transfer to the slave transmitter.
Figure 15. BUS Acknowledge Cycle
5.5.2 Writing to Control Registers
format in single packet is shown in Figure 16 and Figure 17. Figure 16. Repeated Data Write to a Single Register Figure 17. Burst Data Write to Multiple Registers Note: A single byte read is initiated by the master with P immediately following the first data byte.
5.5.3 Reading to Control Registers
cycle is terminated. The device supports combined mode and split mode as shown in Figures 18 to 21. Figure 18. Repeated Data Read from a Single Register- Combined Mode Note: A single byte read is initiated by the master with P immediately following first data byte. Figure 19. Burst Data Read from Multiple Registers- Combined Mode Note: A single byte read is initiated by the master with P immediately following first data byte.
27 Freescale Semiconductor
Figure 20. Repeated Data Read from a Single Register- Split Mode Note: A single byte read is initiated by the master with P immediately following first data byte. Figure 21. Burst Data Read from Multiple Registers- Split Mode Note: A single byte read is initiated by Master with P immediately following first data byte.
5.5.4 I 2C Control Registers
The BC3770 has one Full-speed I2C control for the application processor (AP). Register Reset Condition: All registers in the I2C block are reset each time the VSYS falls below its falling UVLO threshold (typ. 2.5 V).
5.5.4.1 Slave Address
The device supports 7-bit addressing only.
Analog Integrated Circuit Device Data Freescale Semiconductor 28 BC3770
5.5.5 Control Register Map
5.5.5.1 INT1: Interrupt Regist er 1 for Abnormal Conditions
(hex) Register Name Reset (hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00 INT1 00 VBUSOVP VBUSUVLO VBUSINOK AICL VBUSLIMIT BATOVP THEMSHDN THEMREG
01 INT2 00 FASTTMROFF NOBAT WEAKBAT OTGFAIL PRETMROFF CHGRSTF DONE TOPOFF
02 INT3 00 Reserved Reserved Reserved Reserved VSYSOK VSYSNG VSYSOLP DISLIMIT
03 INTMSK1 03 VBUSOVPM VBUSUVLOM VBUSINOKM AICLM VBUSINLIMIT
M BATOVPM THEMSHDNM THEMREGM
04 INTMSK2 B8 FASTTMROFF
M NOBATM WEAKBATM OTGFAILM PRETMROFF M CHGRSTFM DONEM TOPOFFM
05 INTMSK3 FF Reserved Reserved Reserved Reserved VSYSOKM VSYSNGM VSYSOLPM DISLIMITM
06 STATUS N/A Reserved Reserved Reserved VSYSOLP DISLIMIT THEMSHDN BATDET SUSPEND
07 CTRL 42 Reserved ENCOMPARA
TOR Reserved Reserved RESET SUSPEN CHGEN ENBOOST
08 VBUSCTRL 08 Reserved Reserved VBUSLIMIT
09 CHGCTRL1 2F Reserved AICLTH AUTOSTOP AICLEN PRECHG
0A CHGCTRL2 08 Reserved Reserved FASTCHG 0B CHGCTRL3 4C BATREG WEAKBAT 0C CHGCTRL4 05 Reserved TOPOFF DISLIMIT 0D CHGCTRL5 0F Reserved Reserved VOTG FASTTIMER TOPOFFTIMER Address (hex) Mode Reset Condition: VSYS VSYS_UVLO Reset: 0x00
00 R/C
Bit Name Reset Description
7 VBUSOVP 0 1: VBUS OVP event detected
6 VBUSUVLO 0 1: VBUS falling UVLO detected
5 VBUSINOK 0 1: Valid VBUS detected
4 AICL 0 1: AICL threshold detected
3 VBUSLIMIT 0 1: VBUS input current limit detected
2 BATOVP (17), (18) 0 1: BAT OVP detected
1 THEMSHDN 0 1: Thermal shutdown detected
0 THEMREG 0 1: Thermal regulation threshold detected
- These interrupts are to be set to 1 when “ENCOMPARATOR” bit 7 in the 07h register set to “1” AND no valid VBUS supply is at preset. If “ENCOMPARATOR” bit 7 is reset to “0” in no valid VBUS supply, these interrupt events are in no response. 18. These interrupts are to be forcibly overridden to alert the interrupt events in a valid VBUS attached.
Analog Integrated Circuit Device Data
29 Freescale Semiconductor
5.5.5.2 INT2: Interrupt Register 2
5.5.5.3 INT3: Interrupt Register 3
Address (hex) Mode Reset Condition: VSYS VSYS_UVLO Reset: 0x00
01 R/C
Bit Name Reset Description
7 FASTTMROFF 0 1: Fast charger timer expired
6 NOBAT 0 1: No battery threshold detected
5 WEAKBAT (19), (20) 0 1: Weak battery threshold detected
4 OTGFAIL 0 1: Boost failed detected due to overload
3 PRETMROFF 0 1: Pre-charge timer expired
2 CHGRSTF 0 1: Charger restart detected
1 DONE 0 1: Top-off charge timer expired
0 TOPOFF 0 1: Top-off threshold is detected
- These interrupts are to be set to 1 when “ENCOMPARATOR” bit 7 in the 07h register set to “1” AND no valid VBUS supply is at preset. If “ENCOMPARATOR” bit 7 is reset to “0” in no valid VBUS supply, these interrupt events are in no response. 20. These interrupts are to be forcibly overridden to al ert the interrupt events in a valid VBUS attached. Address (hex) Mode Reset Condition: VSYS VSYS_UVLO Reset: 0x00
02 R/C
Bit Name Reset Description 7:4 Reserved 0000 Write “0000” 3 VSYSOK (21), (22) 0 1: VSYS rising 3.6 V detected in a valid VBUS attached 2 VSYSNG (21), (22) 0 1: VSYS falling 3.4 V detected in a valid VBUS attached 1 VSYSOLP 0 1: VSYS overload condition debounced is detected (VSYS 3.4 V) in a valid VBUS attached
0 DISLIMIT (21) 0 1: Current limit threshold detected in discharge mode
- These interrupts are to be set to 1 when “ENCOMPARATOR” bit 7 in the 07h register set to “1” AND no valid VBUS supply is at preset. If “ENCOMPARATOR” bit 7 is reset to “0” in no valid VBUS supply, these interrupt events are in no response. 22. These interrupts are to be forcibly overridden to al ert the interrupt events in a valid VBUS attached.
Analog Integrated Circuit Device Data Freescale Semiconductor 30 BC3770
5.5.5.4 INTMSK1: Interrupt Mask Register 1
5.5.5.5 INTMSK2: Interrupt Mask Register 2
Address (hex) MODE Reset Condition: VSYS VSYS_UVLO Reset: 0x03
03 R/W
Bit Name Reset Description
7 VBUSOVPM 0 0: Interrupt is enabled
1: VBUS OVP interrupt masked
6 VBUSUVLOM 0 0: Interrupt is enabled
1: VBUS falling UVLO interrupt masked
5 VBUSINOKM 0 0: Interrupt is enabled
1: Valid VBUS interrupt masked
4 AICLM 0 0: Interrupt is enabled
1: AICL interrupt masked
3 VBUSINLIMITM 0 0: Interrupt is enabled
1: VBUS Input Current Limit interrupt masked
2 BATOVPM 0 0: Interrupt is enabled
1: BAT OVP interrupt masked
1 THEMSHDNM 1 0: Interrupt is enabled
1: Thermal shutdown interrupt masked
0 THEMREGM 1 0: Interrupt is enabled
1: Thermal regulation interrupt masked Address (hex) Mode Reset Condition: VSYS ≤ VSYS_UVLO Reset: 0xB8
04 R/W
Bit Name Reset Description
7 FASTTMROFFM 1 0: Interrupt is enabled
1: Fast charger timer expired interrupt masked
6 NOBATM 0 0: Interrupt is enabled
1: No Battery interrupt masked
5 WEAKBATM 1 0: Interrupt is enabled
1: Weak battery interrupt masked
4 OTGFAILM 1 0: Interrupt is enabled
1: Boost failed interrupt masked
3 PRETMROFFM 1 0: Interrupt is enabled
1: Pre-charge timer expired interrupt masked
2 CHGRSTFM 0 0: Interrupt is enabled
1: Charger restart interrupt masked
1 DONEM 0 0: Interrupt is enabled
1: Done interrupt masked
0 TOPOFFM 0 0: Interrupt is enabled
1: Top-Off threshold interrupt masked
Analog Integrated Circuit Device Data
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5.5.5.6 INTMSK3: Interrupt Mask Register 3
5.5.5.7 STATUS –Status Register
Address (hex) Mode Reset Condition: VSYS VSYS_UVLO Reset: 0xFF
05 R/W
Bit Name Reset Description 7:4 Reserved 1111 Write “1111”
3 VSYSOKM 1 0: Interrupt is enabled
1: VSYS rising 3.6 V detection masked
2 VSYSNGM 1 0: Interrupt is enabled
1: VSYS falling 3.4 V detection masked
1 VSYSOLPM 1 0: Interrupt is enabled
1: VSYS overload condition detection masked
0 DISLIMITM 1 0: Interrupt is enabled
1: Current limit threshold detection masked Address (hex) Mode Reset Condition: VSYS VSYS_UVLO Reset: N/A 06 R Bit Name Reset Description 7:5 Reserved Reserved for future use 4 VSYSOLP 0: VSYS output is healthy (3.6 V VSYS VBAT_REG) 1: VSYS overloaded with a valid VBUS (VSYS 3.4 V)
3 DISLIMIT 0: Current limit threshold not detected in discharge mode
1: Current limit threshold detected in discharge mode 2 THEMSHDN 0: The die temperature is less than 130 °C. 1: The die temperature is between 150 °C and 130 °C
1 BATDET 0: Battery detached (No Battery)
1: Battery attached (Battery at present)
0 SUSPEND 0: Suspend mode is disabled
1: Suspend mode is enabled
Analog Integrated Circuit Device Data Freescale Semiconductor 32 BC3770
5.5.5.8 CTRL: ON/OFF Control Register
5.5.5.9 VBUSCTRL: VBUS Input Current Limit
(hex) Mode Reset Condition: VSYS VSYS_UVLO reset: 0x42
07 R/W
Bit Name Reset Description
7 Reserved 0 Write “0”
6 ENCOMPARATOR 1
Enable/Disable the comparators to detect “BATOVP”, WEAKBAT”, “VSYSOK”, “VSYSNG” and “DISLIMIT” interrupt events in the registers from 00h to 02h. 0: Turn Off the comparators 1: Turn On the comparators
5 Reserved 0 Do Not write “1”
4 Reserved 0 Do Not write “1”
3 RESET 0
0: No Reset 1: Reset all charge parameters on all registers (except interrupt, interrupt mask registers and status register) (return to 0 after writing 1)
2 SUSPEN 0
Enable/Disable Suspend mode (Turn off the FET between VBUS and PMID) 0: Disable Suspend mode (Q1 FET ON) 1: Enable Suspend mode (Q1 FET in Hi-Z Mode)
1 CHGEN 1
Enable/Disable Battery Charger 0: Disabled 1: Enabled
0 ENBOOST 0
Enable/Disable OTG mode in Boost 0: Disable OTG mode 1: Enable OTG mode Address (hex) Mode Reset Condition: VSYS VSYS_UVLO Reset: 0x08
08 R/W
Bit Name Reset Description 7:6 Reserved 00 Write “00” 5:0 VBUSLIMIT 00 1000 Program the Input Current Limit, IIN_LIM, on VBUS in mA Max current is limited to 2050 mA (All above 10 0111 set to 2.05 A) 500 mA Default IIN_LIM = [100 mA + Dec. (bit 5:0) * 50 mA] (mA) i.g: 500 mA = 100 mA + Dec. 8 (Bin 00 1000) * 50 mA
Analog Integrated Circuit Device Data
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5.5.5.10 CHGCTRL1: Charger Control Register 1
5.5.5.11 CHGCTRL2: Charger Control Register 2
Address (hex) Mode Reset Condition: VSYS VSYS_UVLO Reset: 0x2F
09 R/W
Bit Name Reset Description 6:4 AICLTH 010 Program the AICL Threshold on VBUS 0x0: 4.3 V 0x1: 4.4 V 0x2: 4.5 V 0x3: 4.6 V 0x4: 4.7 V 0x5: 4.8 V 0x6: 4.9 V 0x7: 4.9 V
3 AUTOSTOP 1
0: Charger is on continuously and stays in CV mode after top-off timer is expired. 1: Automatic stop is enabled. After top-off timer is expired, the charger turns off and goes into DONE state.
2 AICLEN 1
Enable/Disable the function of Adaptive-Input Current Limit on VBUS 0: Disable 1: Enable 1:0 PRECHG 11 Program the Pre-charge current in Pre-charge mode 00: 150 mA 01: 250 mA 10: 350 mA 11: 450 mA Address (hex) mOde Reset Condition: VSYS VSYS_UVLO Reset: 0x08 0A R/W Bit Name Reset Description 7:6 Reserved 00 Write “00” 5:0 FASTCHG 00 1000 Program the fast-charge current IFAST_CHG, in mA Max current is limited to 2.0 A (all bits above 10 0110 set to 2.0 A) 500 mA Default IFAST_CHG = [100 mA + Dec. (bit 5:0) * 50 mA] (mA) i.g: 500 mA= 100 mA + Dec. 8 (Bin 001000) * 50 mA
Analog Integrated Circuit Device Data Freescale Semiconductor 34 BC3770
5.5.5.12 CHGCTRL3: Charge r Control Register 3
Address (hex) Mode Reset Condition: VSYS VSYS_UVLO Reset: 0x4C 0B R/W Bit Name Reset Description 7:4 BATREG 0100 Program the battery regulation voltage on BATREG in 25 mV steps 0x0: 4.100 V 0x1: 4.125 V 0x2: 4.150 V 0x3: 4.175 V 0x4: 4.200 V 0x5: 4.225 V 0x6: 4.250 V 0x7: 4.275 V 0x8: 4.300 V 0x9: 4.325 V 0xA: 4.350 V 0xB: 4.375 V 0xC: 4.400 V 0xD: 4.425 V 0xE: 4.450 V 0xF: 4.475 V 3:0 WEAKBAT 1100 Program the weak battery voltage threshold in 50 mV steps 0x0: 3.00 V 0x1: 3.05V 0x2: 3.10 V 0x3: 3.15 V 0x4: 3.20 V 0x5: 3.25 V 0x6: 3.30 V 0x7: 3.35 V 0x8: 3.40 V 0x9: 3.45 V 0xA: 3.50 V 0xB: 3.55 V 0xC: 3.60 V 0xD: 3.65 V 0xE: 3.70 V 0xF: 3.75 V
Analog Integrated Circuit Device Data
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5.5.5.13 CHGCTRL4: Charger Control Register 4
Address (hex) Mode Reset Condition: VSYS VSYS_UVLO Reset: 0x05 0C R/W Bit Name Reset Description
7 Reserved 0
6:3 TOPOFF 0000 Program the top-off charge current in 50 mA steps 0x0: 100 mA 0x1: 150 mA 0x2: 200 mA 0x3: 250 mA 0x4: 300 mA 0x5: 350 mA 0x6: 400 mA 0x7: 450 mA 0x8: 500 mA 0x9: 550 mA 0xA: 600 mA 0xB: 650 mA 0xC: 650 mA 0xD: 650 mA 0xE: 650 mA 0xF: 650 mA 2:0 DISLIMIT 101 Program the discharge current limit in discharge mode 0x0: disabled 0x1: 2.0 A 0x2: 2.5 A 0x3: 3.0 A 0x4: 3.5 A 0x5: 4.0 A 0x6: 4.5 A 0x7: 5.0 A
Analog Integrated Circuit Device Data Freescale Semiconductor 36 BC3770
5.5.5.14 CHGCTRL5: Charge r Control Register 5
Address (hex) Mode Reset Condition: VSYS VSYS_UVLO Reset: 0x0F 0D R/W Bit Name Reset Description 7:6 Reserved 00 Write “00” 5:4 VOTG 00 Program the OTG voltage in boost mode on PMID 00: 5.0 V 01: 5.1 V 10: 5.2 V 11: 5.2 V 3:2 FASTTIMER 11 Program the timer for Fast-charge current 00: 3.5 hours 01: 4.5 hours 10: 5.5 hours 11: Disabled 1: 0 TOPOFFTIMER 11 Program the timer for Top-Off in AUTOSTOP=1 00: 10 min 01: 20 min 10: 30 min 11: 45 min
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6 Typical Applications
6.1 Introduction
The BC3770 can be configured in several applications. Figure 22 shows the BC3770 in a typical application.
6.1.1 Application Diagram
Figure 22. Typical Applications
6.1.2 Application Instructions
6.1.2.1 Determine the Inductor, L
Selecting the proper inductor value is a critical design step for a DC-DC converter. temperature of both the inductor and the switching MOSFETs. Select the inductor to a standard 1.0 H. The peak current on the inductor is 2.3 A. Therefore, select an inductor that has a higher rated current than the peak current and 1.0 H. lower DC resistance should be considered to achieve higher efficiency. Table 5. Recommended Inductors
39 Freescale Semiconductor
6.1.2.2 Output Capacitors Characteristics
capacitance value that falls below the minimum valve given in the recommended capacitance. capacitors are not recommended due to a higher ESR values. Figure 23. Capacitor DC Bias
6.1.2.3 Output Capacitor Selection
6.1.2.4 Input and Output Capacitors
and a 4.7 F on CHGOUT with X5R or X7R rated with an appropriate thickness, low ESR is able to make stable operations.
6.1.2.5 PMID Output Capacitor
capacitor, X5R or X7R rated, low ESR. The voltage rating for a capacitor depends on the maximum input voltage protection rating.
6.1.2.6 PCB Layout Considerations
satisfactory performance. The following provides some guidelines.
- The power loop is composed of the inductor, the input and out put capacitor, the LX pin and the PGND pin. It is important to make
placed as close as possible to their respective the IC pins.
- The switching node of the converter, the LX pin, and the traces connected to this node are very noisy. This trace keeps other noise
- The GND and PGND should connect to the power ground plane at only one point, to minimize the effects of power ground currents.
Also, battery ground should connect directly to the power ground plane.
- Connect the BATREG pin directly to the + terminal on the batte ry cell and connect the BATSNSN pin directly to the – terminal on
the battery cell, to regulate the VBAT_REG battery regulation voltage as close to the target as possible.
- One bypass capacitor for PMID should be placed as close to the pin and power ground as possible.
Figure 24 is an example layout for some key components. Figure 24. Key Component Layout Example
41 Freescale Semiconductor
6.1.2.7 Bill of Materials
components for this diagram. Table 6. Bill of Materials (23)
- Freescale does not assume liability, endorse, or warrant com ponents from external manufacturers are referenced in circuit drawings or tables.
While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their application.
- Critical components. For critical components, it is vital to use the manufacturer listed.
Analog Integrated Circuit Device Data Freescale Semiconductor 42 BC3770
7 Packaging
7.1 Package Mechanical Dimensions
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.freescale.com and perform a keyword search for the drawing’s document number. Table 7. Package Suffix Package Outline Drawing Number 25-Pin WLCSP CS 98ASA00848D
Analog Integrated Circuit Device Data
43 Freescale Semiconductor
Analog Integrated Circuit Device Data Freescale Semiconductor 44 BC3770
8 Revision History
REVISION DATE DESCRIPTION OF CHANGES 1.0 12/2014 • Initial release
- Corrected Figure 1
- Updated Applications on page 1
- Corrected typo in Table 2, BC3770 Pin Definitions 10/2015 • Corrected part number in Table 1, Orderable Part Variations
Document Number: MC32BC3770 Rev. 1.0 Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. product or service names are the property of their respective owners. © 2015 Freescale Semiconductor, Inc. How to Reach Us: Home Page: freescale.com Web Support: freescale.com/support