MC100EP16VS ONSEMI | Alldatasheet
Document overview
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- PDF pages: 12
Technical content
Features
- 220 ps Propagation Delay
- Maximum Frequency > 4 GHz Typical (See Graph)
- The 100 Series Contains Temperature Compensation
- PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
- NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V
- Open Input Default State
- Q Output Will Default LOW with Inputs Open or at VEE
- Pb−Free Packages are Available *For additional marking information, refer to A = Assembly Location L = Wafer Lot Y = Year W = Work Week M = Date Code /C0071= Pb−Free Package ALYW/C0071 /C0071 KP62 MARKING DIAGRAMS* SOIC−8 D SUFFIX CASE 751 TSSOP−8 DT SUFFIX CASE 948R See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
http://onsemi.com KEP62 ALYW /C0071 DFN8 MN SUFFIX CASE 506AA 3H M/C0071 /C0071 (Note: Microdot may be in either location)
Figure 1. 8−Lead Pinout (Top View) and Logic Diagram Table 1. PIN DESCRIPTION
- Pins will default LOW when left open.
** Pins will default to V CC/2 when left open. a sufficient thermal conduit. Table 2. ATTRIBUTES
- For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
8 SOIC
8 TSSOP
Table 4. DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2) values are applied individually under normal operating conditions and not valid simultaneously.
- V IHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
Table 5. DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5) values are applied individually under normal operating conditions and not valid simultaneously.
- Input and output parameters vary 1:1 with V
CC. VEE can vary +2.0 V to −0.5 V.
- V IHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
Table 6. DC CHARACTERISTICS, NECL VCC = 0 V; VEE = −5.5 V to −3.0 V (Note 8) values are applied individually under normal operating conditions and not valid simultaneously.
- Input and output parameters vary 1:1 with V CC.
values are applied individually under normal operating conditions and not valid simultaneously.
- Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 /C0087 to VCC − 2.0 V.
are measured from the cross point of the inputs to the cross point of the outputs. 13.VPP(min) is minimum input swing for which AC parameters are guaranteed.
Figure 5. Alternative Implementation Figure 6. Fmax/Jitter
0.25 V Below VCC
0.75 V Below VCC
1.00 V Below VCC
1.25 V Below VCC
2.00 V Below VCC
Figure 7. Typical Termination for Output Driver and Device Evaluation
http://onsemi.com Device Package Shipping† MC100EP16VSD SOIC−8 98 Units / Rail MC100EP16VSDG SOIC−8 (Pb−Free)
98 Units / Rail
MC100EP16VSDR2 SOIC−8 2500 / Tape & Reel MC100EP16VSDR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel MC3100EP16VSDT TSSOP−8 100 Units / Rail MC3100EP16VSDTG TSSOP−8 (Pb−Free)
100 Units / Rail
MC100EP16VSDTR2 TSSOP−8 2500 / Tape & Reel MC100EP16VSDTR2G TSSOP−8 (Pb−Free) 2500 / Tape & Reel MC100EP16VSMNR4 DFN8 1000 / Tape & Reel MC100EP16VSMNR4G DFN8 (Pb−Free) 1000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPS/C0116 I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices
http://onsemi.com PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AH SEATING PLANE N J X 45/C0095 K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751 −01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A B S DH C 0.10 (0.004) DIM A MIN MAX MIN MAX INCHES 4.80 5.00 0.189 0.197 MILLIMETERS B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8 N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244 −X− −Y− G MYM0.25 (0.010) −Z− YM0.25 (0.010) Z S X S M /C0095/C0095/C0095/C0095 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 /C0466mm inches/C0467SCALE 6:1 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT*
http://onsemi.com PACKAGE DIMENSIONS TSSOP−8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R−02 ISSUE A DIM MIN MAX MIN MAX INCHESMILLIMETERS A 2.90 3.10 0.114 0.122 B 2.90 3.10 0.114 0.122 C 0.80 1.10 0.031 0.043 D 0.05 0.15 0.002 0.006 F 0.40 0.70 0.016 0.028 G 0.65 BSC 0.026 BSC L 4.90 BSC 0.193 BSC M 0 6 0 6 /C0095/C0095/C0095/C0095 SEATING PLANE PIN 1 1 4 DETAIL E B C D A G DETAIL E F M L 2X L/2 −U− SU0.15 (0.006) T SU0.15 (0.006) T SUM0.10 (0.004) V ST 0.10 (0.004) −T− −V− −W− 0.25 (0.010) 8x REFK IDENT K 0.25 0.40 0.010 0.016 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−.
http://onsemi.com PACKAGE DIMENSIONS DFN8 CASE 506AA−01 ISSUE D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ AD E B C0.10 PIN ONE 2 X REFERENCE 2 X TOP VIEW SIDE VIEW BOTTOM VIEW A L (A3) C C0.10 C0.10 C0.088 X A1SEATING PLANE e/2 e 8 X K NOTE 3 b8 X 0.10 C 0.05 C A BB DIM MIN MAX MILLIMETERS A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF b 0.20 0.30 D 2.00 BSC D2 1.10 1.30 E 2.00 BSC E2 0.70 0.90 e 0.50 BSC K 0.20 −−− L 0.25 0.35 1 4 8 5 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 MC100EP16VS/D ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative