MC26LS30 ONSEMI | Alldatasheet
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Semiconductor Components Industries, LLC, 2000 July, 2000 – Rev. 1
1 Publication Order Number:
(EIA-422-A)/ Quad Single-Ended (EIA-423-A) Line Drivers The MC26LS30 is a low power Schottky set of line drivers which can be configured as two differential drivers which comply with EIA–422–A standards, or as four single–ended drivers which comply with EIA–423–A standards. A mode select pin and appropriate choice of power supplies determine the mode. Each driver can source and sink currents in excess of 50 mA. In the differential mode (EIA–422–A), the drivers can be used up to 10 Mbaud. A disable pin for each driver permits setting the outputs into a high impedance mode within a +10 V common mode range. In the single–ended mode (EIA–423–A), each driver has a slew rate control pin which permits setting the slew rate of the output signal so as to comply with EIA–423–A and FCC requirements and to reduce crosstalk. When operated from symmetrical supplies (+5.0 V), the outputs exhibit zero imbalance The MC26LS30 is available in a 16–pin surface mount package. Operating temperature range is –40° to +85°C.
- Operates as Two Differential EIA–422–A Drivers, or Four Single–Ended EIA–423–A Drivers
- High Impedance Outputs in Differential Mode
- Short Circuit Current Limit In Both Source and Sink Modes
- ±10 V Common Mode Range on High Impedance Outputs
- ±15 V Range on Inputs
- Low Current PNP Inputs Compatible with TTL, CMOS, and MOS Outputs
- Individual Output Slew Rate Control in Single–Ended Mode
- Replacement for the AMD AM26LS30 and National Semiconductor DS3691 Representative Block Diagrams Single–Ended Mode EIA–423–A Differential Mode EIA–422–A Enable CD Enable AB Out D Out C Out B Out A VCC-1 VEE-8 Input D Input A Input A SR-A Out A Gnd-5 Mode-4 SR-B SR-C Out D SR-D Out C Out BInput B Input C Input D http://onsemi.com Device Package Shipping
ORDERING INFORMATION
MC26LS30D 48 Units/RailSO–16 PIN CONNECTIONS 161 8 9 Input C/ Enable CD (Top View) SR-A Output A Output B Input D VEE SR-D Output D Output C SR-C SR-B Gnd VCC Input A Mode Input B/ Enable AB SO–16 D SUFFIX CASE 751B 1 1 MC26LS30D AWLYWW MARKING DIAGRAM A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week MC26LS30DR2 2500 Tape & ReelSO–16
http://onsemi.com MAXIMUM OPERATING CONDITIONS (Pin numbers refer to SO–16 package only.) Rating Symbol Value Unit Power Supply Voltage VCC VEE –0.5, +7.0 –7.0, +0.5 Vdc Input Voltage (All Inputs) Vin –0.5, +20 Vdc Applied Output Voltage when in High Impedance Mode CC = 5.0 V, Pin 4 = Logic 0, Pins 3, 6 = Logic 1) Vza ±15 Vdc Output Voltage with VCC , VEE = 0 V Vzb ±15 Output Current IO Self limiting – Junction Temperature TJ –65, +150 °C Devices should not be operated at these limits. The “Recommended Operating Conditions” table provides conditions for actual device operation. RECOMMENDED OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Power Supply Voltage (Differential Mode) VCC VEE +4.75 –0.5 5.0 +5.25 +0.3 Vdc Power Supply Voltage (Single–Ended Mode) VCC VEE +4.75 –5.25 +5.0 –5.0 +5.25 –4.75 Input Voltage (All Inputs) Vin 0 – +15 Vdc Applied Output Voltage (when in High Impedance Mode) Vza –10 – +10 Applied Output Voltage, VCC = 0 Vzb –10 – +10 Output Current IO –65 – +65 mA Operating Ambient Temperature (See text) TA –40 – +85 °C All limits are not necessarily functional concurrently.
http://onsemi.com ELECTRICAL CHARACTERISTICS (EIA–422–A differential mode, Pin 4 0.8 V, –40°C TA 85°C, 4.75 V VCC 5.25 V, VEE = Gnd, unless otherwise noted. Pin numbers refer to SO–16 package only.) Characteristic Symbol Min Typ Max Unit Output Voltage (see Figure 1) Differential, RL = ∞ , VCC = 5.25 V Differential, RL = 100 Ω , VCC = 4.75 V Change in Differential Voltage, RL = 100 Ω (Note 4.) Offset Voltage, RL = 100 Ω Change in Offset Voltage*, RL = 100 Ω VOD1 VOD2 ΔVOD2 VOS ΔVOS 2.0 4.2 2.6 2.5 6.0 400 3.0 400 Vdc Vdc mVdc Vdc mVdc Output Current (each output) Power Off Leakage, VCC = 0, –10 V VO +10 V High Impedance Mode, VCC = 5.25 V, –10 V VO +10 V Short Circuit Current (Note 2.) High Output Shorted to Pin 5 (TA = 25°C) High Output Shorted to Pin 5 (–40°C TA +85°C) Low Output Shorted to +6.0 V (TA = 25°C) Low Output Shorted to +6.0 V (–40°C TA +85°C) IOLK IOZ ISC– ISC– ISC+ ISC+ –100 –100 –150 –150 –95 +100 +100 –60 –50 150 150 µA mA Inputs Low Level Voltage High Level Voltage Current @ Vin = 2.4 V Current @ Vin = 15 V Current @ Vin = 0.4 V Current, 0 Vin 15 V, VCC = 0 Clamp Voltage (Iin = –12 mA) VIL VIH IIH IIHH IIL IIX VIK 2.0 –200 –1.5 –8.0 0.8 100 Vdc Vdc µA Vdc Power Supply Current (VCC = +5.25 V, Outputs Open) (0 Enable VCC ) ICC – 16 30 mA TIMING CHARACTERISTICS (EIA–422–A differential mode, Pin 4 0.8 V, TA = 25°C, VCC = 5.0 V, VEE = Gnd, (Notes 1. and 3.) unless otherwise noted.) Characteristic Symbol Min Typ Max Unit Differential Output Rise Time (Figure 3) tr – 70 200 ns Differential Output Fall Time (Figure 3) tf – 70 200 ns Propagation Delay Time – Input to Differential Output Input Low to High (Figure 3) Input High to Low (Figure 3) tPDH tPDL 200 200 ns Skew Timing (Figure 3) tPDH to tPDL for Each Driver Max to Min tPDH Within a Package Max to Min tPDL Within a Package tSK1 tSK2 tSK3 9.0 2.0 2.0 ns Enable Timing (Figure 4) Enable to Active High Differential Output Enable to Active Low Differential Output Enable to 3–State Output From Active High Enable to 3–State Output From Active Low tPZH tPZL tPHZ tPLZ 150 190 110 300 350 350 300 ns 1. All voltages measured with respect to Pin 5. 2. Only one output shorted at a time, for not more than 1 second. 3. Typical values established at +25°C, VCC = +5.0 V, VEE = –5.0 V. 4. Vin switched from 0.8 to 2.0 V. 5. Imbalance is the difference between VO2 with Vin 0.8 V and VO2 with Vin 2.0 V.
http://onsemi.com ELECTRICAL CHARACTERISTICS (EIA–423–A single–ended mode, Pin 4 2.0 V, –40°C TA 85°C, 4.75 V VCC , |VEE 5.25 V, (Notes 1. and 3.) unless otherwise noted). Characteristic Symbol Min Typ Max Unit Output Voltage (VCC = VEE = 4.75 V) Single–Ended Voltage, RL = ∞ (Figure 2) Single–Ended Voltage, RL = 450 Ω , (Figure 2) Voltage Imbalance (Note 5.), RL = 450 Ω VO1 VO2 ΔVO2 4.0 3.6 4.2 3.95 0.05 6.0 6.0 0.4 Vdc Slew Control Current (Pins 16, 13, 12, 9) ISLEW – ±120 – µA Output Current (Each Output) Power Off Leakage, VCC = VEE = 0, –6.0 V VO +6.0 V Short Circuit Current (Output Short to Ground, Note 2.) Vin 0.8 V (TA = 25°C) Vin 0.8 V (–40°C TA +85°C) Vin /C0119 2.0 V (TA = 25°C) Vin /C0119 2.0 V (–40°C TA +85°C) IOLK ISC+ ISC+ ISC– ISC– –100 –150 –150 –95 +100 150 150 –60 –50 µA mA Inputs Low Level Voltage High Level Voltage Current @ Vin = 2.4 V Current @ Vin = 15 V Current @ Vin = 0.4 V Current, 0 Vin 15 V, VCC = 0 Clamp Voltage (Iin = –12 mA) VIL VIH IIH IIHH IIL IIX VIK 2.0 –200 –1.5 –8.0 0.8 100 Vdc Vdc µA Vdc Power Supply Current (Outputs Open) VCC = +5.25 V, VEE = –5.25 V, Vin = 0.4 V ICC IEE –22 –8.0 mA TIMING CHARACTERISTICS (EIA–423–A single–ended mode, Pin 4 2.0 V, TA = 25°C, VCC = 5.0 V, VEE = –5.0 V, (Notes 1. and 3.) unless otherwise noted.) Characteristic Symbol Min Typ Max Unit Output Timing (Figure 5) Output Rise Time, CC = 0 Output Fall Time, CC = 0 Output Rise Time, CC = 50 pF Output Fall Time, CC = 50 pF tr tf tr tf 3.0 3.0 300 300 ns µs Rise Time Coefficient (Figure 16) C rt – 0.06 – µs/pF Propagation Delay Time, Input to Single Ended Output (Figure 5) Input Low to High, CC = 0 Input High to Low, CC = 0 tPDH tPDL 100 100 300 300 ns Skew Timing, CC = 0 (Figure 5) tPDH to tPDL for Each Driver Max to Min tPDH Within a Package Max to Min tPDL Within a Package tSK4 tSK5 tSK6 2.0 5.0 ns 1. All voltages measured with respect to Pin 5. 2. Only one output shorted at a time, for not more than 1 second. 3. Typical values established at +25°C, VCC = +5.0 V, VEE = –5.0 V. 4. Vin switched from 0.8 to 2.0 V. 5. Imbalance is the difference between VO2 with Vin 0.8 V and VO2 with Vin 2.0 V.
Figure 1. Differential Output Test Figure 2. Single–Ended Output Test Figure 3. Differential Mode Rise/Fall Time and Data Propagation Delay
- tSK1 = tPDH –tPDL for each driver.
- tSK2 computed by subtracting the shortest tPDH from the longest tPDH of the 2 drivers within a package.
- tSK3 computed by subtracting the shortest tPDL from the longest tPDL of the 2 drivers within a package.
1.5 VVin 0 V
Figure 4. Differential Mode Enable Timing
- Above tests conducted by monitoring output current levels.
Figure 5. Single–Ended Mode Rise/Fall Time and Data Propagation Delay
- tSK4 = tPDH –tPDL for each driver.
- tSK5 computed by subtracting the shortest tPDH from the longest tPDH of the 4 drivers within a package.
- tSK6 computed by subtracting the shortest tPDL from the longest tPDL of the 4 drivers within a package.
0.1 VSS/RL
0.5 VSS/RL
TA = ambient air temperature near the IC package. suitability of the package types is calculated as follows. Figure 10. Note that the term (VCC – VOH ) is constant for a
http://onsemi.com PACKAGE DIMENSIONS NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 16 9 SEATING PLANE F JM R X 45 G
8 PLP–B–
–A– M0.25 (0.010) B S –T– D K C 16 PL SBM0.25 (0.010) A ST DIM MIN MAX MIN MAX INCHESMILLIMETERS A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7 P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019 SO–16 D SUFFIX CASE 751B–05 ISSUE J
http://onsemi.com Notes
http://onsemi.com Notes
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